+1 -2

drivers/gpu/Makefile

reviewed

··· 2 2 # drm/tegra depends on host1x, so if both drivers are built-in care must be 3 3 # taken to initialize them in the correct order. Link order is the only way 4 4 # to ensure this currently. 5 5 - obj-$(CONFIG_TEGRA_HOST1X) += host1x/ 6 6 - obj-y += drm/ vga/ 5 5 + obj-y += host1x/ drm/ vga/ 7 6 obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/ 8 7 obj-$(CONFIG_TRACE_GPU_MEM) += trace/

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

reviewed

··· 1621 1621 1622 1622 mutex_lock(&mem->lock); 1623 1623 1624 1624 - /* Unpin MMIO/DOORBELL BO's that were pinnned during allocation */ 1624 1624 + /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */ 1625 1625 if (mem->alloc_flags & 1626 1626 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1627 1627 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {

+6 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

reviewed

··· 188 188 vram_type = AMDGPU_VRAM_TYPE_DDR3; 189 189 break; 190 190 case Ddr4MemType: 191 191 - case LpDdr4MemType: 192 191 vram_type = AMDGPU_VRAM_TYPE_DDR4; 193 192 break; 193 193 + case LpDdr4MemType: 194 194 + vram_type = AMDGPU_VRAM_TYPE_LPDDR4; 195 195 + break; 194 196 case Ddr5MemType: 195 195 - case LpDdr5MemType: 196 197 vram_type = AMDGPU_VRAM_TYPE_DDR5; 198 198 + break; 199 199 + case LpDdr5MemType: 200 200 + vram_type = AMDGPU_VRAM_TYPE_LPDDR5; 197 201 break; 198 202 default: 199 203 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

reviewed

··· 116 116 int ret; 117 117 118 118 if (cs->in.num_chunks == 0) 119 119 - return 0; 119 119 + return -EINVAL; 120 120 121 121 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); 122 122 if (!chunk_array) ··· 1252 1252 1253 1253 p->fence = dma_fence_get(&job->base.s_fence->finished); 1254 1254 1255 1255 - amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq); 1255 1255 + seq = amdgpu_ctx_add_fence(p->ctx, entity, p->fence); 1256 1256 amdgpu_cs_post_dependencies(p); 1257 1257 1258 1258 if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&

+114 -111

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

reviewed

··· 135 135 136 136 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 137 137 { 138 138 - struct amdgpu_device *adev = ctx->adev; 139 139 - int32_t ctx_prio; 138 138 + struct amdgpu_device *adev = ctx->mgr->adev; 140 139 unsigned int hw_prio; 140 140 + int32_t ctx_prio; 141 141 142 142 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 143 143 ctx->init_priority : ctx->override_priority; ··· 162 162 return hw_prio; 163 163 } 164 164 165 165 + /* Calculate the time spend on the hw */ 166 166 + static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 167 167 + { 168 168 + struct drm_sched_fence *s_fence; 169 169 + 170 170 + if (!fence) 171 171 + return ns_to_ktime(0); 172 172 + 173 173 + /* When the fence is not even scheduled it can't have spend time */ 174 174 + s_fence = to_drm_sched_fence(fence); 175 175 + if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 176 176 + return ns_to_ktime(0); 177 177 + 178 178 + /* When it is still running account how much already spend */ 179 179 + if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 180 180 + return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 181 181 + 182 182 + return ktime_sub(s_fence->finished.timestamp, 183 183 + s_fence->scheduled.timestamp); 184 184 + } 185 185 + 186 186 + static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 187 187 + struct amdgpu_ctx_entity *centity) 188 188 + { 189 189 + ktime_t res = ns_to_ktime(0); 190 190 + uint32_t i; 191 191 + 192 192 + spin_lock(&ctx->ring_lock); 193 193 + for (i = 0; i < amdgpu_sched_jobs; i++) { 194 194 + res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 195 195 + } 196 196 + spin_unlock(&ctx->ring_lock); 197 197 + return res; 198 198 + } 165 199 166 200 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 167 201 const u32 ring) 168 202 { 169 169 - struct amdgpu_device *adev = ctx->adev; 170 170 - struct amdgpu_ctx_entity *entity; 171 203 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 172 172 - unsigned num_scheds = 0; 173 173 - int32_t ctx_prio; 174 174 - unsigned int hw_prio; 204 204 + struct amdgpu_device *adev = ctx->mgr->adev; 205 205 + struct amdgpu_ctx_entity *entity; 175 206 enum drm_sched_priority drm_prio; 207 207 + unsigned int hw_prio, num_scheds; 208 208 + int32_t ctx_prio; 176 209 int r; 177 210 178 211 entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs), ··· 215 182 216 183 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 217 184 ctx->init_priority : ctx->override_priority; 185 185 + entity->hw_ip = hw_ip; 218 186 entity->sequence = 1; 219 187 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 220 188 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); ··· 254 220 return r; 255 221 } 256 222 257 257 - static int amdgpu_ctx_init(struct amdgpu_device *adev, 258 258 - int32_t priority, 259 259 - struct drm_file *filp, 260 260 - struct amdgpu_ctx *ctx) 223 223 + static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) 224 224 + { 225 225 + ktime_t res = ns_to_ktime(0); 226 226 + int i; 227 227 + 228 228 + if (!entity) 229 229 + return res; 230 230 + 231 231 + for (i = 0; i < amdgpu_sched_jobs; ++i) { 232 232 + res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 233 233 + dma_fence_put(entity->fences[i]); 234 234 + } 235 235 + 236 236 + kfree(entity); 237 237 + return res; 238 238 + } 239 239 + 240 240 + static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 241 241 + struct drm_file *filp, struct amdgpu_ctx *ctx) 261 242 { 262 243 int r; 263 244 ··· 282 233 283 234 memset(ctx, 0, sizeof(*ctx)); 284 235 285 285 - ctx->adev = adev; 286 286 - 287 236 kref_init(&ctx->refcount); 237 237 + ctx->mgr = mgr; 288 238 spin_lock_init(&ctx->ring_lock); 289 239 mutex_init(&ctx->lock); 290 240 291 291 - ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); 241 241 + ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 292 242 ctx->reset_counter_query = ctx->reset_counter; 293 293 - ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 243 243 + ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter); 294 244 ctx->init_priority = priority; 295 245 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 296 246 ctx->stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; ··· 297 249 return 0; 298 250 } 299 251 300 300 - static void amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) 301 301 - { 302 302 - 303 303 - int i; 304 304 - 305 305 - if (!entity) 306 306 - return; 307 307 - 308 308 - for (i = 0; i < amdgpu_sched_jobs; ++i) 309 309 - dma_fence_put(entity->fences[i]); 310 310 - 311 311 - kfree(entity); 312 312 - } 313 313 - 314 252 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 315 253 u32 *stable_pstate) 316 254 { 317 317 - struct amdgpu_device *adev = ctx->adev; 255 255 + struct amdgpu_device *adev = ctx->mgr->adev; 318 256 enum amd_dpm_forced_level current_level; 319 257 320 258 current_level = amdgpu_dpm_get_performance_level(adev); ··· 328 294 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 329 295 u32 stable_pstate) 330 296 { 331 331 - struct amdgpu_device *adev = ctx->adev; 297 297 + struct amdgpu_device *adev = ctx->mgr->adev; 332 298 enum amd_dpm_forced_level level; 333 299 u32 current_stable_pstate; 334 300 int r; ··· 379 345 static void amdgpu_ctx_fini(struct kref *ref) 380 346 { 381 347 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 382 382 - struct amdgpu_device *adev = ctx->adev; 348 348 + struct amdgpu_ctx_mgr *mgr = ctx->mgr; 349 349 + struct amdgpu_device *adev = mgr->adev; 383 350 unsigned i, j, idx; 384 351 385 352 if (!adev) ··· 388 353 389 354 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 390 355 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 391 391 - amdgpu_ctx_fini_entity(ctx->entities[i][j]); 392 392 - ctx->entities[i][j] = NULL; 356 356 + ktime_t spend; 357 357 + 358 358 + spend = amdgpu_ctx_fini_entity(ctx->entities[i][j]); 359 359 + atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 393 360 } 394 361 } 395 362 ··· 458 421 } 459 422 460 423 *id = (uint32_t)r; 461 461 - r = amdgpu_ctx_init(adev, priority, filp, ctx); 424 424 + r = amdgpu_ctx_init(mgr, priority, filp, ctx); 462 425 if (r) { 463 426 idr_remove(&mgr->ctx_handles, *id); 464 427 *id = 0; ··· 708 671 return 0; 709 672 } 710 673 711 711 - void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 712 712 - struct drm_sched_entity *entity, 713 713 - struct dma_fence *fence, uint64_t *handle) 674 674 + uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 675 675 + struct drm_sched_entity *entity, 676 676 + struct dma_fence *fence) 714 677 { 715 678 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 716 679 uint64_t seq = centity->sequence; ··· 719 682 720 683 idx = seq & (amdgpu_sched_jobs - 1); 721 684 other = centity->fences[idx]; 722 722 - if (other) 723 723 - BUG_ON(!dma_fence_is_signaled(other)); 685 685 + WARN_ON(other && !dma_fence_is_signaled(other)); 724 686 725 687 dma_fence_get(fence); 726 688 ··· 728 692 centity->sequence++; 729 693 spin_unlock(&ctx->ring_lock); 730 694 695 695 + atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 696 696 + &ctx->mgr->time_spend[centity->hw_ip]); 697 697 + 731 698 dma_fence_put(other); 732 732 - if (handle) 733 733 - *handle = seq; 699 699 + return seq; 734 700 } 735 701 736 702 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, ··· 769 731 int hw_ip, 770 732 int32_t priority) 771 733 { 772 772 - struct amdgpu_device *adev = ctx->adev; 734 734 + struct amdgpu_device *adev = ctx->mgr->adev; 773 735 unsigned int hw_prio; 774 736 struct drm_gpu_scheduler **scheds = NULL; 775 737 unsigned num_scheds; ··· 834 796 return r; 835 797 } 836 798 837 837 - void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 799 799 + void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 800 800 + struct amdgpu_device *adev) 838 801 { 802 802 + unsigned int i; 803 803 + 804 804 + mgr->adev = adev; 839 805 mutex_init(&mgr->lock); 840 806 idr_init(&mgr->ctx_handles); 807 807 + 808 808 + for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 809 809 + atomic64_set(&mgr->time_spend[i], 0); 841 810 } 842 811 843 812 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) ··· 920 875 mutex_destroy(&mgr->lock); 921 876 } 922 877 923 923 - static void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, 924 924 - struct amdgpu_ctx_entity *centity, ktime_t *total, ktime_t *max) 878 878 + void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 879 879 + ktime_t usage[AMDGPU_HW_IP_NUM]) 925 880 { 926 926 - ktime_t now, t1; 927 927 - uint32_t i; 928 928 - 929 929 - *total = *max = 0; 930 930 - 931 931 - now = ktime_get(); 932 932 - for (i = 0; i < amdgpu_sched_jobs; i++) { 933 933 - struct dma_fence *fence; 934 934 - struct drm_sched_fence *s_fence; 935 935 - 936 936 - spin_lock(&ctx->ring_lock); 937 937 - fence = dma_fence_get(centity->fences[i]); 938 938 - spin_unlock(&ctx->ring_lock); 939 939 - if (!fence) 940 940 - continue; 941 941 - s_fence = to_drm_sched_fence(fence); 942 942 - if (!dma_fence_is_signaled(&s_fence->scheduled)) { 943 943 - dma_fence_put(fence); 944 944 - continue; 945 945 - } 946 946 - t1 = s_fence->scheduled.timestamp; 947 947 - if (!ktime_before(t1, now)) { 948 948 - dma_fence_put(fence); 949 949 - continue; 950 950 - } 951 951 - if (dma_fence_is_signaled(&s_fence->finished) && 952 952 - s_fence->finished.timestamp < now) 953 953 - *total += ktime_sub(s_fence->finished.timestamp, t1); 954 954 - else 955 955 - *total += ktime_sub(now, t1); 956 956 - t1 = ktime_sub(now, t1); 957 957 - dma_fence_put(fence); 958 958 - *max = max(t1, *max); 959 959 - } 960 960 - } 961 961 - 962 962 - ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip, 963 963 - uint32_t idx, uint64_t *elapsed) 964 964 - { 965 965 - struct idr *idp; 966 881 struct amdgpu_ctx *ctx; 882 882 + unsigned int hw_ip, i; 967 883 uint32_t id; 968 968 - struct amdgpu_ctx_entity *centity; 969 969 - ktime_t total = 0, max = 0; 970 884 971 971 - if (idx >= AMDGPU_MAX_ENTITY_NUM) 972 972 - return 0; 973 973 - idp = &mgr->ctx_handles; 885 885 + /* 886 886 + * This is a little bit racy because it can be that a ctx or a fence are 887 887 + * destroyed just in the moment we try to account them. But that is ok 888 888 + * since exactly that case is explicitely allowed by the interface. 889 889 + */ 974 890 mutex_lock(&mgr->lock); 975 975 - idr_for_each_entry(idp, ctx, id) { 976 976 - ktime_t ttotal, tmax; 891 891 + for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 892 892 + uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 977 893 978 978 - if (!ctx->entities[hwip][idx]) 979 979 - continue; 980 980 - 981 981 - centity = ctx->entities[hwip][idx]; 982 982 - amdgpu_ctx_fence_time(ctx, centity, &ttotal, &tmax); 983 983 - 984 984 - /* Harmonic mean approximation diverges for very small 985 985 - * values. If ratio < 0.01% ignore 986 986 - */ 987 987 - if (AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(tmax, ttotal)) 988 988 - continue; 989 989 - 990 990 - total = ktime_add(total, ttotal); 991 991 - max = ktime_after(tmax, max) ? tmax : max; 894 894 + usage[hw_ip] = ns_to_ktime(ns); 992 895 } 993 896 994 994 - mutex_unlock(&mgr->lock); 995 995 - if (elapsed) 996 996 - *elapsed = max; 897 897 + idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 898 898 + for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 899 899 + for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 900 900 + struct amdgpu_ctx_entity *centity; 901 901 + ktime_t spend; 997 902 998 998 - return total; 903 903 + centity = ctx->entities[hw_ip][i]; 904 904 + if (!centity) 905 905 + continue; 906 906 + spend = amdgpu_ctx_entity_time(ctx, centity); 907 907 + usage[hw_ip] = ktime_add(usage[hw_ip], spend); 908 908 + } 909 909 + } 910 910 + } 911 911 + mutex_unlock(&mgr->lock); 999 912 }

+15 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h

reviewed

··· 23 23 #ifndef __AMDGPU_CTX_H__ 24 24 #define __AMDGPU_CTX_H__ 25 25 26 26 + #include <linux/ktime.h> 27 27 + #include <linux/types.h> 28 28 + 26 29 #include "amdgpu_ring.h" 27 30 28 31 struct drm_device; 29 32 struct drm_file; 30 33 struct amdgpu_fpriv; 34 34 + struct amdgpu_ctx_mgr; 31 35 32 36 #define AMDGPU_MAX_ENTITY_NUM 4 33 33 - #define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total)) 34 37 35 38 struct amdgpu_ctx_entity { 39 39 + uint32_t hw_ip; 36 40 uint64_t sequence; 37 41 struct drm_sched_entity entity; 38 42 struct dma_fence *fences[]; ··· 44 40 45 41 struct amdgpu_ctx { 46 42 struct kref refcount; 47 47 - struct amdgpu_device *adev; 43 43 + struct amdgpu_ctx_mgr *mgr; 48 44 unsigned reset_counter; 49 45 unsigned reset_counter_query; 50 46 uint32_t vram_lost_counter; ··· 65 61 struct mutex lock; 66 62 /* protected by lock */ 67 63 struct idr ctx_handles; 64 64 + atomic64_t time_spend[AMDGPU_HW_IP_NUM]; 68 65 }; 69 66 70 67 extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM]; ··· 75 70 76 71 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 77 72 u32 ring, struct drm_sched_entity **entity); 78 78 - void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 79 79 - struct drm_sched_entity *entity, 80 80 - struct dma_fence *fence, uint64_t *seq); 73 73 + uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 74 74 + struct drm_sched_entity *entity, 75 75 + struct dma_fence *fence); 81 76 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 82 77 struct drm_sched_entity *entity, 83 78 uint64_t seq); ··· 90 85 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 91 86 struct drm_sched_entity *entity); 92 87 93 93 - void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 88 88 + void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 89 89 + struct amdgpu_device *adev); 94 90 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr); 95 91 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout); 96 92 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 97 97 - ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip, 98 98 - uint32_t idx, uint64_t *elapsed); 93 93 + void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 94 94 + ktime_t usage[AMDGPU_HW_IP_NUM]); 95 95 + 99 96 #endif

+7 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 1556 1556 1557 1557 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); 1558 1558 1559 1559 - amdgpu_gmc_tmz_set(adev); 1560 1560 - 1561 1561 - 1562 1559 return 0; 1563 1560 } 1564 1561 ··· 3698 3701 if (r) 3699 3702 return r; 3700 3703 3704 3704 + /* Enable TMZ based on IP_VERSION */ 3705 3705 + amdgpu_gmc_tmz_set(adev); 3706 3706 + 3701 3707 amdgpu_gmc_noretry_set(adev); 3702 3708 /* Need to get xgmi info early to decide the reset behavior*/ 3703 3709 if (adev->gmc.xgmi.supported) { ··· 5219 5219 r = amdgpu_device_reset_sriov(adev, job ? false : true); 5220 5220 if (r) 5221 5221 adev->asic_reset_res = r; 5222 5222 + 5223 5223 + /* Aldebaran supports ras in SRIOV, so need resume ras during reset */ 5224 5224 + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 5225 5225 + amdgpu_ras_resume(adev); 5222 5226 } else { 5223 5227 r = amdgpu_do_asic_reset(device_list_handle, &reset_context); 5224 5228 if (r && r == -EAGAIN)

+15 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

reviewed

··· 1130 1130 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1131 1131 ip->revision & 0xc0; 1132 1132 ip->revision &= ~0xc0; 1133 1133 - adev->vcn.num_vcn_inst++; 1133 1133 + if (adev->vcn.num_vcn_inst < AMDGPU_MAX_VCN_INSTANCES) 1134 1134 + adev->vcn.num_vcn_inst++; 1135 1135 + else 1136 1136 + dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1137 1137 + adev->vcn.num_vcn_inst + 1, 1138 1138 + AMDGPU_MAX_VCN_INSTANCES); 1134 1139 } 1135 1140 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1136 1141 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1137 1142 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1138 1138 - le16_to_cpu(ip->hw_id) == SDMA3_HWID) 1139 1139 - adev->sdma.num_instances++; 1143 1143 + le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1144 1144 + if (adev->sdma.num_instances < AMDGPU_MAX_SDMA_INSTANCES) 1145 1145 + adev->sdma.num_instances++; 1146 1146 + else 1147 1147 + dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1148 1148 + adev->sdma.num_instances + 1, 1149 1149 + AMDGPU_MAX_SDMA_INSTANCES); 1150 1150 + } 1140 1151 1141 1152 if (le16_to_cpu(ip->hw_id) == UMC_HWID) 1142 1153 adev->gmc.num_umc++; ··· 1372 1361 struct mall_info_v1_0 v1; 1373 1362 }; 1374 1363 1375 1375 - int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1364 1364 + static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1376 1365 { 1377 1366 struct binary_header *bhdr; 1378 1367 union mall_info *mall_info;

+4 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

reviewed

··· 99 99 * - 3.43.0 - Add device hot plug/unplug support 100 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 101 101 * - 3.45.0 - Add context ioctl stable pstate interface 102 102 - * * 3.46.0 - To enable hot plug amdgpu tests in libdrm 102 102 + * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 103 103 + * * 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 103 104 */ 104 105 #define KMS_DRIVER_MAJOR 3 105 105 - #define KMS_DRIVER_MINOR 46 106 106 + #define KMS_DRIVER_MINOR 47 106 107 #define KMS_DRIVER_PATCHLEVEL 0 107 108 108 109 int amdgpu_vram_limit; ··· 1941 1940 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1942 1941 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1943 1942 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1943 1943 + {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1944 1944 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1945 1945 1946 1946 { PCI_DEVICE(0x1002, PCI_ANY_ID),

+30 -38

drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c

reviewed

··· 32 32 33 33 #include <drm/amdgpu_drm.h> 34 34 #include <drm/drm_debugfs.h> 35 35 + #include <drm/drm_drv.h> 35 36 36 37 #include "amdgpu.h" 37 38 #include "amdgpu_vm.h" ··· 55 54 56 55 void amdgpu_show_fdinfo(struct seq_file *m, struct file *f) 57 56 { 58 58 - struct amdgpu_fpriv *fpriv; 59 59 - uint32_t bus, dev, fn, i, domain; 60 60 - uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0; 61 57 struct drm_file *file = f->private_data; 62 58 struct amdgpu_device *adev = drm_to_adev(file->minor->dev); 63 63 - struct amdgpu_bo *root; 59 59 + struct amdgpu_fpriv *fpriv = file->driver_priv; 60 60 + struct amdgpu_vm *vm = &fpriv->vm; 61 61 + 62 62 + uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0; 63 63 + ktime_t usage[AMDGPU_HW_IP_NUM]; 64 64 + uint32_t bus, dev, fn, domain; 65 65 + unsigned int hw_ip; 64 66 int ret; 65 67 66 66 - ret = amdgpu_file_to_fpriv(f, &fpriv); 67 67 - if (ret) 68 68 - return; 69 68 bus = adev->pdev->bus->number; 70 69 domain = pci_domain_nr(adev->pdev->bus); 71 70 dev = PCI_SLOT(adev->pdev->devfn); 72 71 fn = PCI_FUNC(adev->pdev->devfn); 73 72 74 74 - root = amdgpu_bo_ref(fpriv->vm.root.bo); 75 75 - if (!root) 73 73 + ret = amdgpu_bo_reserve(vm->root.bo, false); 74 74 + if (ret) 76 75 return; 77 76 78 78 - ret = amdgpu_bo_reserve(root, false); 79 79 - if (ret) { 80 80 - DRM_ERROR("Fail to reserve bo\n"); 81 81 - return; 82 82 - } 83 83 - amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem); 84 84 - amdgpu_bo_unreserve(root); 85 85 - amdgpu_bo_unref(&root); 77 77 + amdgpu_vm_get_memory(vm, &vram_mem, &gtt_mem, &cpu_mem); 78 78 + amdgpu_bo_unreserve(vm->root.bo); 86 79 87 87 - seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus, 88 88 - dev, fn, fpriv->vm.pasid); 89 89 - seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL); 90 90 - seq_printf(m, "gtt mem:\t%llu kB\n", gtt_mem/1024UL); 91 91 - seq_printf(m, "cpu mem:\t%llu kB\n", cpu_mem/1024UL); 92 92 - for (i = 0; i < AMDGPU_HW_IP_NUM; i++) { 93 93 - uint32_t count = amdgpu_ctx_num_entities[i]; 94 94 - int idx = 0; 95 95 - uint64_t total = 0, min = 0; 96 96 - uint32_t perc, frac; 80 80 + amdgpu_ctx_mgr_usage(&fpriv->ctx_mgr, usage); 97 81 98 98 - for (idx = 0; idx < count; idx++) { 99 99 - total = amdgpu_ctx_mgr_fence_usage(&fpriv->ctx_mgr, 100 100 - i, idx, &min); 101 101 - if ((total == 0) || (min == 0)) 102 102 - continue; 82 82 + /* 83 83 + * ****************************************************************** 84 84 + * For text output format description please see drm-usage-stats.rst! 85 85 + * ****************************************************************** 86 86 + */ 103 87 104 104 - perc = div64_u64(10000 * total, min); 105 105 - frac = perc % 100; 88 88 + seq_printf(m, "pasid:\t%u\n", fpriv->vm.pasid); 89 89 + seq_printf(m, "drm-driver:\t%s\n", file->minor->dev->driver->name); 90 90 + seq_printf(m, "drm-pdev:\t%04x:%02x:%02x.%d\n", domain, bus, dev, fn); 91 91 + seq_printf(m, "drm-client-id:\t%Lu\n", vm->immediate.fence_context); 92 92 + seq_printf(m, "drm-memory-vram:\t%llu KiB\n", vram_mem/1024UL); 93 93 + seq_printf(m, "drm-memory-gtt: \t%llu KiB\n", gtt_mem/1024UL); 94 94 + seq_printf(m, "drm-memory-cpu: \t%llu KiB\n", cpu_mem/1024UL); 95 95 + for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 96 96 + if (!usage[hw_ip]) 97 97 + continue; 106 98 107 107 - seq_printf(m, "%s%d:\t%d.%d%%\n", 108 108 - amdgpu_ip_name[i], 109 109 - idx, perc/100, frac); 110 110 - } 99 99 + seq_printf(m, "drm-engine-%s:\t%Ld ns\n", amdgpu_ip_name[hw_ip], 100 100 + ktime_to_ns(usage[hw_ip])); 111 101 } 112 102 }

+6 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

reviewed

··· 296 296 AMDGPU_GEM_CREATE_VRAM_CLEARED | 297 297 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 298 298 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 299 299 - AMDGPU_GEM_CREATE_ENCRYPTED)) 300 300 - 299 299 + AMDGPU_GEM_CREATE_ENCRYPTED | 300 300 + AMDGPU_GEM_CREATE_DISCARDABLE)) 301 301 return -EINVAL; 302 302 303 303 /* reject invalid gem domains */ ··· 645 645 pte_flag |= AMDGPU_PTE_WRITEABLE; 646 646 if (flags & AMDGPU_VM_PAGE_PRT) 647 647 pte_flag |= AMDGPU_PTE_PRT; 648 648 + if (flags & AMDGPU_VM_PAGE_NOALLOC) 649 649 + pte_flag |= AMDGPU_PTE_NOALLOC; 648 650 649 651 if (adev->gmc.gmc_funcs->map_mtype) 650 652 pte_flag |= amdgpu_gmc_map_mtype(adev, ··· 660 658 { 661 659 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 662 660 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 663 663 - AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 661 661 + AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK | 662 662 + AMDGPU_VM_PAGE_NOALLOC; 664 663 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 665 664 AMDGPU_VM_PAGE_PRT; 666 665

+20 -9

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

reviewed

··· 512 512 */ 513 513 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 514 514 { 515 515 - switch (adev->asic_type) { 516 516 - case CHIP_RAVEN: 517 517 - case CHIP_RENOIR: 515 515 + switch (adev->ip_versions[GC_HWIP][0]) { 516 516 + /* RAVEN */ 517 517 + case IP_VERSION(9, 2, 2): 518 518 + case IP_VERSION(9, 1, 0): 519 519 + /* RENOIR looks like RAVEN */ 520 520 + case IP_VERSION(9, 3, 0): 518 521 if (amdgpu_tmz == 0) { 519 522 adev->gmc.tmz_enabled = false; 520 523 dev_info(adev->dev, ··· 528 525 "Trusted Memory Zone (TMZ) feature enabled\n"); 529 526 } 530 527 break; 531 531 - case CHIP_NAVI10: 532 532 - case CHIP_NAVI14: 533 533 - case CHIP_NAVI12: 534 534 - case CHIP_VANGOGH: 535 535 - case CHIP_YELLOW_CARP: 536 536 - case CHIP_IP_DISCOVERY: 528 528 + case IP_VERSION(10, 1, 10): 529 529 + case IP_VERSION(10, 1, 1): 530 530 + case IP_VERSION(10, 1, 2): 531 531 + case IP_VERSION(10, 1, 3): 532 532 + case IP_VERSION(10, 3, 0): 533 533 + case IP_VERSION(10, 3, 2): 534 534 + case IP_VERSION(10, 3, 4): 535 535 + case IP_VERSION(10, 3, 5): 536 536 + /* VANGOGH */ 537 537 + case IP_VERSION(10, 3, 1): 538 538 + /* YELLOW_CARP*/ 539 539 + case IP_VERSION(10, 3, 3): 540 540 + /* GC 10.3.7 */ 541 541 + case IP_VERSION(10, 3, 7): 537 542 /* Don't enable it by default yet. 538 543 */ 539 544 if (amdgpu_tmz < 1) {

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

reviewed

··· 1152 1152 mutex_init(&fpriv->bo_list_lock); 1153 1153 idr_init(&fpriv->bo_list_handles); 1154 1154 1155 1155 - amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1155 1155 + amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1156 1156 1157 1157 file_priv->driver_priv = fpriv; 1158 1158 goto out_suspend;

+4 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

reviewed

··· 567 567 bp->domain; 568 568 bo->allowed_domains = bo->preferred_domains; 569 569 if (bp->type != ttm_bo_type_kernel && 570 570 + !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 570 571 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 571 572 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 572 573 ··· 1019 1018 "DDR3", 1020 1019 "DDR4", 1021 1020 "GDDR6", 1022 1022 - "DDR5" 1021 1021 + "DDR5", 1022 1022 + "LPDDR4", 1023 1023 + "LPDDR5" 1023 1024 }; 1024 1025 1025 1026 /**

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

reviewed

··· 41 41 42 42 /* BO flag to indicate a KFD userptr BO */ 43 43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63) 44 44 - #define AMDGPU_AMDKFD_CREATE_SVM_BO (1ULL << 62) 45 44 46 45 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo) 47 46 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

reviewed

··· 1177 1177 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1178 1178 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1179 1179 1180 1180 - if (!psp->xgmi_context.context.initialized) { 1180 1180 + if (!psp->xgmi_context.context.mem_context.shared_buf) { 1181 1181 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1182 1182 if (ret) 1183 1183 return ret;

+29 -11

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

reviewed

··· 726 726 /* Do not enable if it is not allowed. */ 727 727 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); 728 728 729 729 - if (!amdgpu_ras_intr_triggered()) { 729 729 + /* Only enable ras feature operation handle on host side */ 730 730 + if (!amdgpu_sriov_vf(adev) && 731 731 + !amdgpu_ras_intr_triggered()) { 730 732 ret = psp_ras_enable_features(&adev->psp, info, enable); 731 733 if (ret) { 732 734 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", ··· 1525 1523 */ 1526 1524 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) 1527 1525 { 1528 1528 - if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) 1526 1526 + /* Fatal error events are handled on host side */ 1527 1527 + if (amdgpu_sriov_vf(adev) || 1528 1528 + !amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) 1529 1529 return; 1530 1530 1531 1531 if (adev->nbio.ras && ··· 2274 2270 { 2275 2271 adev->ras_hw_enabled = adev->ras_enabled = 0; 2276 2272 2277 2277 - if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || 2273 2273 + if (!adev->is_atom_fw || 2278 2274 !amdgpu_ras_asic_supported(adev)) 2275 2275 + return; 2276 2276 + 2277 2277 + if (!(amdgpu_sriov_vf(adev) && 2278 2278 + (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))) 2279 2279 return; 2280 2280 2281 2281 if (!adev->gmc.xgmi.connected_to_cpu) { ··· 2293 2285 2294 2286 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { 2295 2287 dev_info(adev->dev, "SRAM ECC is active.\n"); 2296 2296 - adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | 2297 2297 - 1 << AMDGPU_RAS_BLOCK__DF); 2288 2288 + if (!amdgpu_sriov_vf(adev)) { 2289 2289 + adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | 2290 2290 + 1 << AMDGPU_RAS_BLOCK__DF); 2298 2291 2299 2299 - if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0)) 2300 2300 - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | 2301 2301 - 1 << AMDGPU_RAS_BLOCK__JPEG); 2302 2302 - else 2303 2303 - adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | 2304 2304 - 1 << AMDGPU_RAS_BLOCK__JPEG); 2292 2292 + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0)) 2293 2293 + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | 2294 2294 + 1 << AMDGPU_RAS_BLOCK__JPEG); 2295 2295 + else 2296 2296 + adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | 2297 2297 + 1 << AMDGPU_RAS_BLOCK__JPEG); 2298 2298 + } else { 2299 2299 + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | 2300 2300 + 1 << AMDGPU_RAS_BLOCK__SDMA | 2301 2301 + 1 << AMDGPU_RAS_BLOCK__GFX); 2302 2302 + } 2305 2303 } else { 2306 2304 dev_info(adev->dev, "SRAM ECC is not presented.\n"); 2307 2305 } ··· 2650 2636 struct amdgpu_ras_block_list *node, *tmp; 2651 2637 struct amdgpu_ras_block_object *obj; 2652 2638 int r; 2639 2639 + 2640 2640 + /* Guest side doesn't need init ras feature */ 2641 2641 + if (amdgpu_sriov_vf(adev)) 2642 2642 + return 0; 2653 2643 2654 2644 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { 2655 2645 if (!node->ras_obj) {

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c

reviewed

··· 124 124 struct amdgpu_iv_entry *entry) 125 125 { 126 126 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 127 127 + 128 128 + if (amdgpu_sriov_vf(adev)) 129 129 + return AMDGPU_RAS_SUCCESS; 130 130 + 127 131 amdgpu_ras_reset_gpu(adev); 128 132 129 133 return AMDGPU_RAS_SUCCESS;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

reviewed

··· 117 117 } 118 118 119 119 abo = ttm_to_amdgpu_bo(bo); 120 120 - if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 120 120 + if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) { 121 121 placement->num_placement = 0; 122 122 placement->num_busy_placement = 0; 123 123 return;

+15 -33

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

reviewed

··· 5111 5111 mutex_unlock(&adev->srbm_mutex); 5112 5112 5113 5113 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 5114 5114 - acccess. These should be enabled by FW for target VMIDs. */ 5114 5114 + access. These should be enabled by FW for target VMIDs. */ 5115 5115 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5116 5116 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5117 5117 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); ··· 6898 6898 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6899 6899 (order_base_2(prop->queue_size / 4) - 1)); 6900 6900 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6901 6901 - ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6901 6901 + (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6902 6902 #ifdef __BIG_ENDIAN 6903 6903 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6904 6904 #endif ··· 6918 6918 wb_gpu_addr = prop->wptr_gpu_addr; 6919 6919 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6920 6920 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6921 6921 - 6922 6922 - tmp = 0; 6923 6923 - /* enable the doorbell if requested */ 6924 6924 - if (prop->use_doorbell) { 6925 6925 - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6926 6926 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6927 6927 - DOORBELL_OFFSET, prop->doorbell_index); 6928 6928 - 6929 6929 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6930 6930 - DOORBELL_EN, 1); 6931 6931 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6932 6932 - DOORBELL_SOURCE, 0); 6933 6933 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6934 6934 - DOORBELL_HIT, 0); 6935 6935 - } 6936 6936 - 6937 6937 - mqd->cp_hqd_pq_doorbell_control = tmp; 6938 6921 6939 6922 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6940 6923 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); ··· 6956 6973 /* disable wptr polling */ 6957 6974 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6958 6975 6959 6959 - /* write the EOP addr */ 6960 6960 - WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6961 6961 - mqd->cp_hqd_eop_base_addr_lo); 6962 6962 - WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6963 6963 - mqd->cp_hqd_eop_base_addr_hi); 6964 6964 - 6965 6965 - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6966 6966 - WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6967 6967 - mqd->cp_hqd_eop_control); 6968 6968 - 6969 6969 - /* enable doorbell? */ 6970 6970 - WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6971 6971 - mqd->cp_hqd_pq_doorbell_control); 6972 6972 - 6973 6976 /* disable the queue if it's active */ 6974 6977 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6975 6978 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); ··· 6973 7004 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6974 7005 mqd->cp_hqd_pq_wptr_hi); 6975 7006 } 7007 7007 + 7008 7008 + /* disable doorbells */ 7009 7009 + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 7010 7010 + 7011 7011 + /* write the EOP addr */ 7012 7012 + WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 7013 7013 + mqd->cp_hqd_eop_base_addr_lo); 7014 7014 + WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 7015 7015 + mqd->cp_hqd_eop_base_addr_hi); 7016 7016 + 7017 7017 + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 7018 7018 + WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 7019 7019 + mqd->cp_hqd_eop_control); 6976 7020 6977 7021 /* set the pointer to the MQD */ 6978 7022 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

reviewed

··· 4082 4082 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4083 4083 (order_base_2(prop->queue_size / 4) - 1)); 4084 4084 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4085 4085 - ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4085 4085 + (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4086 4086 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4087 4087 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 4088 4088 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

+3 -3

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

reviewed

··· 3714 3714 mutex_unlock(&adev->srbm_mutex); 3715 3715 3716 3716 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 3717 3717 - acccess. These should be enabled by FW for target VMIDs. */ 3717 3717 + access. These should be enabled by FW for target VMIDs. */ 3718 3718 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 3719 3719 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); 3720 3720 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); ··· 4490 4490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4491 4491 (order_base_2(ring->ring_size / 4) - 1)); 4492 4492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4493 4493 - ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4493 4493 + (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4494 4494 #ifdef __BIG_ENDIAN 4495 4495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 4496 4496 #endif ··· 5815 5815 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5816 5816 gfx_v8_0_wait_for_rlc_serdes(adev); 5817 5817 5818 5818 - /* write cmd to Set CGCG Overrride */ 5818 5818 + /* write cmd to Set CGCG Override */ 5819 5819 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD); 5820 5820 5821 5821 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */

+2 -19

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

reviewed

··· 2535 2535 mutex_unlock(&adev->srbm_mutex); 2536 2536 2537 2537 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2538 2538 - acccess. These should be enabled by FW for target VMIDs. */ 2538 2538 + access. These should be enabled by FW for target VMIDs. */ 2539 2539 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2540 2540 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2541 2541 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); ··· 3514 3514 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3515 3515 (order_base_2(ring->ring_size / 4) - 1)); 3516 3516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3517 3517 - ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3517 3517 + (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3518 3518 #ifdef __BIG_ENDIAN 3519 3519 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3520 3520 #endif ··· 3534 3534 wb_gpu_addr = ring->wptr_gpu_addr; 3535 3535 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3536 3536 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3537 3537 - 3538 3538 - tmp = 0; 3539 3539 - /* enable the doorbell if requested */ 3540 3540 - if (ring->use_doorbell) { 3541 3541 - tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3542 3542 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3543 3543 - DOORBELL_OFFSET, ring->doorbell_index); 3544 3544 - 3545 3545 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3546 3546 - DOORBELL_EN, 1); 3547 3547 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3548 3548 - DOORBELL_SOURCE, 0); 3549 3549 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3550 3550 - DOORBELL_HIT, 0); 3551 3551 - } 3552 3552 - 3553 3553 - mqd->cp_hqd_pq_doorbell_control = tmp; 3554 3537 3555 3538 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3556 3539 ring->wptr = 0;

+3

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

reviewed

··· 613 613 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 614 614 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 615 615 616 616 + *flags &= ~AMDGPU_PTE_NOALLOC; 617 617 + *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 618 618 + 616 619 if (mapping->flags & AMDGPU_PTE_PRT) { 617 620 *flags |= AMDGPU_PTE_PRT; 618 621 *flags |= AMDGPU_PTE_SNOOPED;

+3

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

reviewed

··· 500 500 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 501 501 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 502 502 503 503 + *flags &= ~AMDGPU_PTE_NOALLOC; 504 504 + *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 505 505 + 503 506 if (mapping->flags & AMDGPU_PTE_PRT) { 504 507 *flags |= AMDGPU_PTE_PRT; 505 508 *flags |= AMDGPU_PTE_SNOOPED;

+6 -9

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

reviewed

··· 32 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 34 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 35 35 - MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 36 35 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 37 36 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 38 38 - MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin"); 39 37 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 41 - MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin"); 42 39 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 40 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 41 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); ··· 82 85 err = psp_init_sos_microcode(psp, chip_name); 83 86 if (err) 84 87 return err; 85 85 - err = psp_init_ta_microcode(&adev->psp, chip_name); 86 86 - if (err) 87 87 - return err; 88 88 + /* It's not necessary to load ras ta on Guest side */ 89 89 + if (!amdgpu_sriov_vf(adev)) { 90 90 + err = psp_init_ta_microcode(&adev->psp, chip_name); 91 91 + if (err) 92 92 + return err; 93 93 + } 88 94 break; 89 95 case IP_VERSION(13, 0, 1): 90 96 case IP_VERSION(13, 0, 3): 91 97 case IP_VERSION(13, 0, 5): 92 98 case IP_VERSION(13, 0, 8): 93 93 - err = psp_init_asd_microcode(psp, chip_name); 94 94 - if (err) 95 95 - return err; 96 99 err = psp_init_toc_microcode(psp, chip_name); 97 100 if (err) 98 101 return err;

+1

drivers/gpu/drm/amd/amdgpu/soc21.c

reviewed

··· 42 42 43 43 #include "soc15.h" 44 44 #include "soc15_common.h" 45 45 + #include "soc21.h" 45 46 46 47 static const struct amd_ip_funcs soc21_common_ip_funcs; 47 48

+2133 -1665

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h

reviewed

··· 166 166 0x807c847c, 0x806eff6e, 167 167 0x00000400, 0xbf0a757c, 168 168 0xbf85ffef, 0xbf9c0000, 169 169 - 0xbf8200cd, 0xbef8007e, 169 169 + 0xbf8200ce, 0xbef8007e, 170 170 0x8679ff7f, 0x0000ffff, 171 171 0x8779ff79, 0x00040000, 172 172 0xbefa0080, 0xbefb00ff, ··· 212 212 0x761e0000, 0xe0524100, 213 213 0x761e0100, 0xe0524200, 214 214 0x761e0200, 0xe0524300, 215 215 - 0x761e0300, 0xb8f22a05, 216 216 - 0x80728172, 0x8e728a72, 217 217 - 0xb8f61605, 0x80768176, 218 218 - 0x8e768676, 0x80727672, 219 219 - 0x80f2c072, 0xb8f31605, 220 220 - 0x80738173, 0x8e738473, 221 221 - 0x8e7a8273, 0xbefa00ff, 222 222 - 0x01000000, 0xbefc0073, 223 223 - 0xc031003c, 0x00000072, 224 224 - 0x80f2c072, 0xbf8c007f, 225 225 - 0x80fc907c, 0xbe802d00, 226 226 - 0xbe822d02, 0xbe842d04, 227 227 - 0xbe862d06, 0xbe882d08, 228 228 - 0xbe8a2d0a, 0xbe8c2d0c, 229 229 - 0xbe8e2d0e, 0xbf06807c, 230 230 - 0xbf84fff1, 0xb8f22a05, 231 231 - 0x80728172, 0x8e728a72, 232 232 - 0xb8f61605, 0x80768176, 233 233 - 0x8e768676, 0x80727672, 234 234 - 0xbefa0084, 0xbefa00ff, 235 235 - 0x01000000, 0xc0211cfc, 215 215 + 0x761e0300, 0xbf8c0f70, 216 216 + 0xb8f22a05, 0x80728172, 217 217 + 0x8e728a72, 0xb8f61605, 218 218 + 0x80768176, 0x8e768676, 219 219 + 0x80727672, 0x80f2c072, 220 220 + 0xb8f31605, 0x80738173, 221 221 + 0x8e738473, 0x8e7a8273, 222 222 + 0xbefa00ff, 0x01000000, 223 223 + 0xbefc0073, 0xc031003c, 224 224 + 0x00000072, 0x80f2c072, 225 225 + 0xbf8c007f, 0x80fc907c, 226 226 + 0xbe802d00, 0xbe822d02, 227 227 + 0xbe842d04, 0xbe862d06, 228 228 + 0xbe882d08, 0xbe8a2d0a, 229 229 + 0xbe8c2d0c, 0xbe8e2d0e, 230 230 + 0xbf06807c, 0xbf84fff1, 231 231 + 0xb8f22a05, 0x80728172, 232 232 + 0x8e728a72, 0xb8f61605, 233 233 + 0x80768176, 0x8e768676, 234 234 + 0x80727672, 0xbefa0084, 235 235 + 0xbefa00ff, 0x01000000, 236 236 + 0xc0211cfc, 0x00000072, 237 237 + 0x80728472, 0xc0211c3c, 236 238 0x00000072, 0x80728472, 237 237 - 0xc0211c3c, 0x00000072, 238 238 - 0x80728472, 0xc0211c7c, 239 239 + 0xc0211c7c, 0x00000072, 240 240 + 0x80728472, 0xc0211bbc, 239 241 0x00000072, 0x80728472, 240 240 - 0xc0211bbc, 0x00000072, 241 241 - 0x80728472, 0xc0211bfc, 242 242 + 0xc0211bfc, 0x00000072, 243 243 + 0x80728472, 0xc0211d3c, 242 244 0x00000072, 0x80728472, 243 243 - 0xc0211d3c, 0x00000072, 244 244 - 0x80728472, 0xc0211d7c, 245 245 + 0xc0211d7c, 0x00000072, 246 246 + 0x80728472, 0xc0211a3c, 245 247 0x00000072, 0x80728472, 246 246 - 0xc0211a3c, 0x00000072, 247 247 - 0x80728472, 0xc0211a7c, 248 248 + 0xc0211a7c, 0x00000072, 249 249 + 0x80728472, 0xc0211dfc, 248 250 0x00000072, 0x80728472, 249 249 - 0xc0211dfc, 0x00000072, 250 250 - 0x80728472, 0xc0211b3c, 251 251 + 0xc0211b3c, 0x00000072, 252 252 + 0x80728472, 0xc0211b7c, 251 253 0x00000072, 0x80728472, 252 252 - 0xc0211b7c, 0x00000072, 253 253 - 0x80728472, 0xbf8c007f, 254 254 - 0xbefc0073, 0xbefe006e, 255 255 - 0xbeff006f, 0x867375ff, 256 256 - 0x000003ff, 0xb9734803, 257 257 - 0x867375ff, 0xfffff800, 258 258 - 0x8f738b73, 0xb973a2c3, 259 259 - 0xb977f801, 0x8673ff71, 260 260 - 0xf0000000, 0x8f739c73, 261 261 - 0x8e739073, 0xbef60080, 262 262 - 0x87767376, 0x8673ff71, 263 263 - 0x08000000, 0x8f739b73, 264 264 - 0x8e738f73, 0x87767376, 265 265 - 0x8673ff74, 0x00800000, 266 266 - 0x8f739773, 0xb976f807, 267 267 - 0x8671ff71, 0x0000ffff, 268 268 - 0x86fe7e7e, 0x86ea6a6a, 269 269 - 0x8f768374, 0xb976e0c2, 270 270 - 0xbf800002, 0xb9740002, 271 271 - 0xbf8a0000, 0x95807370, 272 272 - 0xbf810000, 0x00000000, 254 254 + 0xbf8c007f, 0xbefc0073, 255 255 + 0xbefe006e, 0xbeff006f, 256 256 + 0x867375ff, 0x000003ff, 257 257 + 0xb9734803, 0x867375ff, 258 258 + 0xfffff800, 0x8f738b73, 259 259 + 0xb973a2c3, 0xb977f801, 260 260 + 0x8673ff71, 0xf0000000, 261 261 + 0x8f739c73, 0x8e739073, 262 262 + 0xbef60080, 0x87767376, 263 263 + 0x8673ff71, 0x08000000, 264 264 + 0x8f739b73, 0x8e738f73, 265 265 + 0x87767376, 0x8673ff74, 266 266 + 0x00800000, 0x8f739773, 267 267 + 0xb976f807, 0x8671ff71, 268 268 + 0x0000ffff, 0x86fe7e7e, 269 269 + 0x86ea6a6a, 0x8f768374, 270 270 + 0xb976e0c2, 0xbf800002, 271 271 + 0xb9740002, 0xbf8a0000, 272 272 + 0x95807370, 0xbf810000, 273 273 }; 274 274 275 275 276 276 static const uint32_t cwsr_trap_gfx9_hex[] = { 277 277 - 0xbf820001, 0xbf820248, 278 278 - 0xb8f8f802, 0x89788678, 279 279 - 0xb8eef801, 0x866eff6e, 280 280 - 0x00000800, 0xbf840003, 277 277 + 0xbf820001, 0xbf820254, 278 278 + 0xb8f8f802, 0x8978ff78, 279 279 + 0x00020006, 0xb8fbf803, 281 280 0x866eff78, 0x00002000, 282 282 - 0xbf840016, 0xb8fbf803, 281 281 + 0xbf840009, 0x866eff6d, 282 282 + 0x00ff0000, 0xbf85001e, 283 283 0x866eff7b, 0x00000400, 284 284 - 0xbf85003b, 0x866eff7b, 285 285 - 0x00000800, 0xbf850003, 286 286 - 0x866eff7b, 0x00000100, 287 287 - 0xbf84000c, 0x866eff78, 288 288 - 0x00002000, 0xbf840005, 289 289 - 0xbf8e0010, 0xb8eef803, 290 290 - 0x866eff6e, 0x00000400, 291 291 - 0xbf84fffb, 0x8778ff78, 292 292 - 0x00002000, 0x80ec886c, 293 293 - 0x82ed806d, 0xb8eef807, 294 294 - 0x866fff6e, 0x001f8000, 295 295 - 0x8e6f8b6f, 0x8977ff77, 296 296 - 0xfc000000, 0x87776f77, 297 297 - 0x896eff6e, 0x001f8000, 298 298 - 0xb96ef807, 0xb8faf812, 284 284 + 0xbf850051, 0xbf8e0010, 285 285 + 0xb8fbf803, 0xbf82fffa, 286 286 + 0x866eff7b, 0x00000900, 287 287 + 0xbf850015, 0x866eff7b, 288 288 + 0x000071ff, 0xbf840008, 289 289 + 0x866fff7b, 0x00007080, 290 290 + 0xbf840001, 0xbeee1a87, 291 291 + 0xb8eff801, 0x8e6e8c6e, 292 292 + 0x866e6f6e, 0xbf85000a, 293 293 + 0x866eff6d, 0x00ff0000, 294 294 + 0xbf850007, 0xb8eef801, 295 295 + 0x866eff6e, 0x00000800, 296 296 + 0xbf850003, 0x866eff7b, 297 297 + 0x00000400, 0xbf850036, 298 298 + 0xb8faf807, 0x867aff7a, 299 299 + 0x001f8000, 0x8e7a8b7a, 300 300 + 0x8977ff77, 0xfc000000, 301 301 + 0x87777a77, 0xba7ff807, 302 302 + 0x00000000, 0xb8faf812, 299 303 0xb8fbf813, 0x8efa887a, 300 300 - 0xc0071bbd, 0x00000000, 301 301 - 0xbf8cc07f, 0xc0071ebd, 302 302 - 0x00000008, 0xbf8cc07f, 303 303 - 0x86ee6e6e, 0xbf840001, 304 304 - 0xbe801d6e, 0xb8fbf803, 305 305 - 0x867bff7b, 0x000001ff, 304 304 + 0xc0031bbd, 0x00000010, 305 305 + 0xbf8cc07f, 0x8e6e976e, 306 306 + 0x8977ff77, 0x00800000, 307 307 + 0x87776e77, 0xc0071bbd, 308 308 + 0x00000000, 0xbf8cc07f, 309 309 + 0xc0071ebd, 0x00000008, 310 310 + 0xbf8cc07f, 0x86ee6e6e, 311 311 + 0xbf840001, 0xbe801d6e, 312 312 + 0x866eff6d, 0x01ff0000, 313 313 + 0xbf850005, 0x8778ff78, 314 314 + 0x00002000, 0x80ec886c, 315 315 + 0x82ed806d, 0xbf820005, 316 316 + 0x866eff6d, 0x01000000, 306 317 0xbf850002, 0x806c846c, 307 318 0x826d806d, 0x866dff6d, 308 308 - 0x0000ffff, 0x8f6e8b77, 309 309 - 0x866eff6e, 0x001f8000, 310 310 - 0xb96ef807, 0x86fe7e7e, 319 319 + 0x0000ffff, 0x8f7a8b77, 320 320 + 0x867aff7a, 0x001f8000, 321 321 + 0xb97af807, 0x86fe7e7e, 311 322 0x86ea6a6a, 0x8f6e8378, 312 323 0xb96ee0c2, 0xbf800002, 313 324 0xb9780002, 0xbe801f6c, 314 325 0x866dff6d, 0x0000ffff, 315 326 0xbefa0080, 0xb97a0283, 316 316 - 0xb8fa2407, 0x8e7a9b7a, 317 317 - 0x876d7a6d, 0xb8fa03c7, 318 318 - 0x8e7a9a7a, 0x876d7a6d, 319 327 0xb8faf807, 0x867aff7a, 320 320 - 0x00007fff, 0xb97af807, 321 321 - 0xbeee007e, 0xbeef007f, 322 322 - 0xbefe0180, 0xbf900004, 323 323 - 0x877a8478, 0xb97af802, 324 324 - 0xbf8e0002, 0xbf88fffe, 325 325 - 0xb8fa2a05, 0x807a817a, 326 326 - 0x8e7a8a7a, 0xb8fb1605, 327 327 - 0x807b817b, 0x8e7b867b, 328 328 - 0x807a7b7a, 0x807a7e7a, 329 329 - 0x827b807f, 0x867bff7b, 330 330 - 0x0000ffff, 0xc04b1c3d, 331 331 - 0x00000050, 0xbf8cc07f, 332 332 - 0xc04b1d3d, 0x00000060, 333 333 - 0xbf8cc07f, 0xc0431e7d, 334 334 - 0x00000074, 0xbf8cc07f, 335 335 - 0xbef4007e, 0x8675ff7f, 336 336 - 0x0000ffff, 0x8775ff75, 337 337 - 0x00040000, 0xbef60080, 338 338 - 0xbef700ff, 0x00807fac, 339 339 - 0x867aff7f, 0x08000000, 340 340 - 0x8f7a837a, 0x87777a77, 341 341 - 0x867aff7f, 0x70000000, 342 342 - 0x8f7a817a, 0x87777a77, 343 343 - 0xbef1007c, 0xbef00080, 344 344 - 0xb8f02a05, 0x80708170, 345 345 - 0x8e708a70, 0xb8fa1605, 346 346 - 0x807a817a, 0x8e7a867a, 347 347 - 0x80707a70, 0xbef60084, 348 348 - 0xbef600ff, 0x01000000, 349 349 - 0xbefe007c, 0xbefc0070, 350 350 - 0xc0611c7a, 0x0000007c, 351 351 - 0xbf8cc07f, 0x80708470, 352 352 - 0xbefc007e, 0xbefe007c, 353 353 - 0xbefc0070, 0xc0611b3a, 354 354 - 0x0000007c, 0xbf8cc07f, 355 355 - 0x80708470, 0xbefc007e, 356 356 - 0xbefe007c, 0xbefc0070, 357 357 - 0xc0611b7a, 0x0000007c, 358 358 - 0xbf8cc07f, 0x80708470, 359 359 - 0xbefc007e, 0xbefe007c, 360 360 - 0xbefc0070, 0xc0611bba, 361 361 - 0x0000007c, 0xbf8cc07f, 362 362 - 0x80708470, 0xbefc007e, 363 363 - 0xbefe007c, 0xbefc0070, 364 364 - 0xc0611bfa, 0x0000007c, 365 365 - 0xbf8cc07f, 0x80708470, 366 366 - 0xbefc007e, 0xbefe007c, 367 367 - 0xbefc0070, 0xc0611e3a, 368 368 - 0x0000007c, 0xbf8cc07f, 369 369 - 0x80708470, 0xbefc007e, 370 370 - 0xb8fbf803, 0xbefe007c, 371 371 - 0xbefc0070, 0xc0611efa, 372 372 - 0x0000007c, 0xbf8cc07f, 373 373 - 0x80708470, 0xbefc007e, 374 374 - 0xbefe007c, 0xbefc0070, 375 375 - 0xc0611a3a, 0x0000007c, 376 376 - 0xbf8cc07f, 0x80708470, 377 377 - 0xbefc007e, 0xbefe007c, 378 378 - 0xbefc0070, 0xc0611a7a, 379 379 - 0x0000007c, 0xbf8cc07f, 380 380 - 0x80708470, 0xbefc007e, 381 381 - 0xb8f1f801, 0xbefe007c, 382 382 - 0xbefc0070, 0xc0611c7a, 383 383 - 0x0000007c, 0xbf8cc07f, 384 384 - 0x80708470, 0xbefc007e, 385 385 - 0x867aff7f, 0x04000000, 386 386 - 0xbeef0080, 0x876f6f7a, 387 387 - 0xb8f02a05, 0x80708170, 388 388 - 0x8e708a70, 0xb8fb1605, 389 389 - 0x807b817b, 0x8e7b847b, 390 390 - 0x8e76827b, 0xbef600ff, 391 391 - 0x01000000, 0xbef20174, 392 392 - 0x80747074, 0x82758075, 393 393 - 0xbefc0080, 0xbf800000, 394 394 - 0xbe802b00, 0xbe822b02, 395 395 - 0xbe842b04, 0xbe862b06, 396 396 - 0xbe882b08, 0xbe8a2b0a, 397 397 - 0xbe8c2b0c, 0xbe8e2b0e, 398 398 - 0xc06b003a, 0x00000000, 399 399 - 0xbf8cc07f, 0xc06b013a, 400 400 - 0x00000010, 0xbf8cc07f, 401 401 - 0xc06b023a, 0x00000020, 402 402 - 0xbf8cc07f, 0xc06b033a, 403 403 - 0x00000030, 0xbf8cc07f, 404 404 - 0x8074c074, 0x82758075, 405 405 - 0x807c907c, 0xbf0a7b7c, 406 406 - 0xbf85ffe7, 0xbef40172, 407 407 - 0xbef00080, 0xbefe00c1, 408 408 - 0xbeff00c1, 0xbee80080, 409 409 - 0xbee90080, 0xbef600ff, 410 410 - 0x01000000, 0x867aff78, 411 411 - 0x00400000, 0xbf850003, 412 412 - 0xb8faf803, 0x897a7aff, 413 413 - 0x10000000, 0xbf85004d, 414 414 - 0xbe840080, 0xd2890000, 415 415 - 0x00000900, 0x80048104, 416 416 - 0xd2890001, 0x00000900, 417 417 - 0x80048104, 0xd2890002, 418 418 - 0x00000900, 0x80048104, 419 419 - 0xd2890003, 0x00000900, 420 420 - 0x80048104, 0xc069003a, 421 421 - 0x00000070, 0xbf8cc07f, 422 422 - 0x80709070, 0xbf06c004, 423 423 - 0xbf84ffee, 0xbe840080, 424 424 - 0xd2890000, 0x00000901, 425 425 - 0x80048104, 0xd2890001, 426 426 - 0x00000901, 0x80048104, 427 427 - 0xd2890002, 0x00000901, 428 428 - 0x80048104, 0xd2890003, 429 429 - 0x00000901, 0x80048104, 430 430 - 0xc069003a, 0x00000070, 431 431 - 0xbf8cc07f, 0x80709070, 432 432 - 0xbf06c004, 0xbf84ffee, 433 433 - 0xbe840080, 0xd2890000, 434 434 - 0x00000902, 0x80048104, 435 435 - 0xd2890001, 0x00000902, 436 436 - 0x80048104, 0xd2890002, 437 437 - 0x00000902, 0x80048104, 438 438 - 0xd2890003, 0x00000902, 439 439 - 0x80048104, 0xc069003a, 440 440 - 0x00000070, 0xbf8cc07f, 441 441 - 0x80709070, 0xbf06c004, 442 442 - 0xbf84ffee, 0xbe840080, 443 443 - 0xd2890000, 0x00000903, 444 444 - 0x80048104, 0xd2890001, 445 445 - 0x00000903, 0x80048104, 446 446 - 0xd2890002, 0x00000903, 447 447 - 0x80048104, 0xd2890003, 448 448 - 0x00000903, 0x80048104, 449 449 - 0xc069003a, 0x00000070, 450 450 - 0xbf8cc07f, 0x80709070, 451 451 - 0xbf06c004, 0xbf84ffee, 452 452 - 0xbf820008, 0xe0724000, 453 453 - 0x701d0000, 0xe0724100, 454 454 - 0x701d0100, 0xe0724200, 455 455 - 0x701d0200, 0xe0724300, 456 456 - 0x701d0300, 0xbefe00c1, 457 457 - 0xbeff00c1, 0xb8fb4306, 458 458 - 0x867bc17b, 0xbf840063, 459 459 - 0xbf8a0000, 0x867aff6f, 460 460 - 0x04000000, 0xbf84005f, 461 461 - 0x8e7b867b, 0x8e7b827b, 462 462 - 0xbef6007b, 0xb8f02a05, 463 463 - 0x80708170, 0x8e708a70, 464 464 - 0xb8fa1605, 0x807a817a, 465 465 - 0x8e7a867a, 0x80707a70, 466 466 - 0x8070ff70, 0x00000080, 467 467 - 0xbef600ff, 0x01000000, 468 468 - 0xbefc0080, 0xd28c0002, 469 469 - 0x000100c1, 0xd28d0003, 470 470 - 0x000204c1, 0x867aff78, 471 471 - 0x00400000, 0xbf850003, 472 472 - 0xb8faf803, 0x897a7aff, 473 473 - 0x10000000, 0xbf850030, 474 474 - 0x24040682, 0xd86e4000, 475 475 - 0x00000002, 0xbf8cc07f, 476 476 - 0xbe840080, 0xd2890000, 477 477 - 0x00000900, 0x80048104, 478 478 - 0xd2890001, 0x00000900, 479 479 - 0x80048104, 0xd2890002, 480 480 - 0x00000900, 0x80048104, 481 481 - 0xd2890003, 0x00000900, 482 482 - 0x80048104, 0xc069003a, 483 483 - 0x00000070, 0xbf8cc07f, 484 484 - 0x80709070, 0xbf06c004, 485 485 - 0xbf84ffee, 0xbe840080, 486 486 - 0xd2890000, 0x00000901, 487 487 - 0x80048104, 0xd2890001, 488 488 - 0x00000901, 0x80048104, 489 489 - 0xd2890002, 0x00000901, 490 490 - 0x80048104, 0xd2890003, 491 491 - 0x00000901, 0x80048104, 492 492 - 0xc069003a, 0x00000070, 493 493 - 0xbf8cc07f, 0x80709070, 494 494 - 0xbf06c004, 0xbf84ffee, 495 495 - 0x680404ff, 0x00000200, 496 496 - 0xd0c9006a, 0x0000f702, 497 497 - 0xbf87ffd2, 0xbf820015, 498 498 - 0xd1060002, 0x00011103, 499 499 - 0x7e0602ff, 0x00000200, 500 500 - 0xbefc00ff, 0x00010000, 501 501 - 0xbe800077, 0x8677ff77, 502 502 - 0xff7fffff, 0x8777ff77, 503 503 - 0x00058000, 0xd8ec0000, 504 504 - 0x00000002, 0xbf8cc07f, 505 505 - 0xe0765000, 0x701d0002, 506 506 - 0x68040702, 0xd0c9006a, 507 507 - 0x0000f702, 0xbf87fff7, 508 508 - 0xbef70000, 0xbef000ff, 509 509 - 0x00000400, 0xbefe00c1, 510 510 - 0xbeff00c1, 0xb8fb2a05, 511 511 - 0x807b817b, 0x8e7b827b, 512 512 - 0x8e76887b, 0xbef600ff, 513 513 - 0x01000000, 0xbefc0084, 514 514 - 0xbf0a7b7c, 0xbf84006d, 515 515 - 0xbf11017c, 0x807bff7b, 516 516 - 0x00001000, 0x867aff78, 517 517 - 0x00400000, 0xbf850003, 518 518 - 0xb8faf803, 0x897a7aff, 519 519 - 0x10000000, 0xbf850051, 520 520 - 0xbe840080, 0xd2890000, 521 521 - 0x00000900, 0x80048104, 522 522 - 0xd2890001, 0x00000900, 523 523 - 0x80048104, 0xd2890002, 524 524 - 0x00000900, 0x80048104, 525 525 - 0xd2890003, 0x00000900, 526 526 - 0x80048104, 0xc069003a, 527 527 - 0x00000070, 0xbf8cc07f, 528 528 - 0x80709070, 0xbf06c004, 529 529 - 0xbf84ffee, 0xbe840080, 530 530 - 0xd2890000, 0x00000901, 531 531 - 0x80048104, 0xd2890001, 532 532 - 0x00000901, 0x80048104, 533 533 - 0xd2890002, 0x00000901, 534 534 - 0x80048104, 0xd2890003, 535 535 - 0x00000901, 0x80048104, 536 536 - 0xc069003a, 0x00000070, 537 537 - 0xbf8cc07f, 0x80709070, 538 538 - 0xbf06c004, 0xbf84ffee, 539 539 - 0xbe840080, 0xd2890000, 540 540 - 0x00000902, 0x80048104, 541 541 - 0xd2890001, 0x00000902, 542 542 - 0x80048104, 0xd2890002, 543 543 - 0x00000902, 0x80048104, 544 544 - 0xd2890003, 0x00000902, 545 545 - 0x80048104, 0xc069003a, 546 546 - 0x00000070, 0xbf8cc07f, 547 547 - 0x80709070, 0xbf06c004, 548 548 - 0xbf84ffee, 0xbe840080, 549 549 - 0xd2890000, 0x00000903, 550 550 - 0x80048104, 0xd2890001, 551 551 - 0x00000903, 0x80048104, 552 552 - 0xd2890002, 0x00000903, 553 553 - 0x80048104, 0xd2890003, 554 554 - 0x00000903, 0x80048104, 555 555 - 0xc069003a, 0x00000070, 556 556 - 0xbf8cc07f, 0x80709070, 557 557 - 0xbf06c004, 0xbf84ffee, 558 558 - 0x807c847c, 0xbf0a7b7c, 559 559 - 0xbf85ffb1, 0xbf9c0000, 560 560 - 0xbf820012, 0x7e000300, 561 561 - 0x7e020301, 0x7e040302, 562 562 - 0x7e060303, 0xe0724000, 563 563 - 0x701d0000, 0xe0724100, 564 564 - 0x701d0100, 0xe0724200, 565 565 - 0x701d0200, 0xe0724300, 566 566 - 0x701d0300, 0x807c847c, 567 567 - 0x8070ff70, 0x00000400, 568 568 - 0xbf0a7b7c, 0xbf85ffef, 569 569 - 0xbf9c0000, 0xbf8200da, 570 570 - 0xbef4007e, 0x8675ff7f, 571 571 - 0x0000ffff, 0x8775ff75, 572 572 - 0x00040000, 0xbef60080, 573 573 - 0xbef700ff, 0x00807fac, 574 574 - 0x866eff7f, 0x08000000, 575 575 - 0x8f6e836e, 0x87776e77, 576 576 - 0x866eff7f, 0x70000000, 577 577 - 0x8f6e816e, 0x87776e77, 578 578 - 0x866eff7f, 0x04000000, 579 579 - 0xbf84001e, 0xbefe00c1, 580 580 - 0xbeff00c1, 0xb8ef4306, 581 581 - 0x866fc16f, 0xbf840019, 582 582 - 0x8e6f866f, 0x8e6f826f, 583 583 - 0xbef6006f, 0xb8f82a05, 584 584 - 0x80788178, 0x8e788a78, 585 585 - 0xb8ee1605, 0x806e816e, 586 586 - 0x8e6e866e, 0x80786e78, 587 587 - 0x8078ff78, 0x00000080, 588 588 - 0xbef600ff, 0x01000000, 589 589 - 0xbefc0080, 0xe0510000, 590 590 - 0x781d0000, 0xe0510100, 591 591 - 0x781d0000, 0x807cff7c, 592 592 - 0x00000200, 0x8078ff78, 593 593 - 0x00000200, 0xbf0a6f7c, 594 594 - 0xbf85fff6, 0xbef80080, 595 595 - 0xbefe00c1, 0xbeff00c1, 596 596 - 0xb8ef2a05, 0x806f816f, 597 597 - 0x8e6f826f, 0x8e76886f, 598 598 - 0xbef600ff, 0x01000000, 599 599 - 0xbeee0078, 0x8078ff78, 600 600 - 0x00000400, 0xbefc0084, 601 601 - 0xbf11087c, 0x806fff6f, 602 602 - 0x00008000, 0xe0524000, 603 603 - 0x781d0000, 0xe0524100, 604 604 - 0x781d0100, 0xe0524200, 605 605 - 0x781d0200, 0xe0524300, 606 606 - 0x781d0300, 0xbf8c0f70, 607 607 - 0x7e000300, 0x7e020301, 608 608 - 0x7e040302, 0x7e060303, 609 609 - 0x807c847c, 0x8078ff78, 610 610 - 0x00000400, 0xbf0a6f7c, 611 611 - 0xbf85ffee, 0xbf9c0000, 612 612 - 0xe0524000, 0x6e1d0000, 613 613 - 0xe0524100, 0x6e1d0100, 614 614 - 0xe0524200, 0x6e1d0200, 615 615 - 0xe0524300, 0x6e1d0300, 616 616 - 0xb8f82a05, 0x80788178, 617 617 - 0x8e788a78, 0xb8ee1605, 618 618 - 0x806e816e, 0x8e6e866e, 619 619 - 0x80786e78, 0x80f8c078, 620 620 - 0xb8ef1605, 0x806f816f, 621 621 - 0x8e6f846f, 0x8e76826f, 622 622 - 0xbef600ff, 0x01000000, 623 623 - 0xbefc006f, 0xc031003a, 624 624 - 0x00000078, 0x80f8c078, 625 625 - 0xbf8cc07f, 0x80fc907c, 626 626 - 0xbf800000, 0xbe802d00, 627 627 - 0xbe822d02, 0xbe842d04, 628 628 - 0xbe862d06, 0xbe882d08, 629 629 - 0xbe8a2d0a, 0xbe8c2d0c, 630 630 - 0xbe8e2d0e, 0xbf06807c, 631 631 - 0xbf84fff0, 0xb8f82a05, 632 632 - 0x80788178, 0x8e788a78, 633 633 - 0xb8ee1605, 0x806e816e, 634 634 - 0x8e6e866e, 0x80786e78, 635 635 - 0xbef60084, 0xbef600ff, 636 636 - 0x01000000, 0xc0211bfa, 637 637 - 0x00000078, 0x80788478, 638 638 - 0xc0211b3a, 0x00000078, 639 639 - 0x80788478, 0xc0211b7a, 640 640 - 0x00000078, 0x80788478, 641 641 - 0xc0211c3a, 0x00000078, 642 642 - 0x80788478, 0xc0211c7a, 643 643 - 0x00000078, 0x80788478, 644 644 - 0xc0211eba, 0x00000078, 645 645 - 0x80788478, 0xc0211efa, 646 646 - 0x00000078, 0x80788478, 647 647 - 0xc0211a3a, 0x00000078, 648 648 - 0x80788478, 0xc0211a7a, 649 649 - 0x00000078, 0x80788478, 650 650 - 0xc0211cfa, 0x00000078, 651 651 - 0x80788478, 0xbf8cc07f, 652 652 - 0xbefc006f, 0xbefe0070, 653 653 - 0xbeff0071, 0x866f7bff, 654 654 - 0x000003ff, 0xb96f4803, 655 655 - 0x866f7bff, 0xfffff800, 656 656 - 0x8f6f8b6f, 0xb96fa2c3, 657 657 - 0xb973f801, 0xb8ee2a05, 658 658 - 0x806e816e, 0x8e6e8a6e, 659 659 - 0xb8ef1605, 0x806f816f, 660 660 - 0x8e6f866f, 0x806e6f6e, 661 661 - 0x806e746e, 0x826f8075, 662 662 - 0x866fff6f, 0x0000ffff, 663 663 - 0xc00b1c37, 0x00000050, 664 664 - 0xc00b1d37, 0x00000060, 665 665 - 0xc0031e77, 0x00000074, 666 666 - 0xbf8cc07f, 0x866fff6d, 667 667 - 0xf8000000, 0x8f6f9b6f, 668 668 - 0x8e6f906f, 0xbeee0080, 669 669 - 0x876e6f6e, 0x866fff6d, 670 670 - 0x04000000, 0x8f6f9a6f, 671 671 - 0x8e6f8f6f, 0x876e6f6e, 672 672 - 0x866fff7a, 0x00800000, 673 673 - 0x8f6f976f, 0xb96ef807, 674 674 - 0x866dff6d, 0x0000ffff, 675 675 - 0x86fe7e7e, 0x86ea6a6a, 676 676 - 0x8f6e837a, 0xb96ee0c2, 677 677 - 0xbf800002, 0xb97a0002, 678 678 - 0xbf8a0000, 0x95806f6c, 679 679 - 0xbf810000, 0x00000000, 680 680 - }; 681 681 - 682 682 - static const uint32_t cwsr_trap_nv1x_hex[] = { 683 683 - 0xbf820001, 0xbf8201cd, 684 684 - 0xb0804004, 0xb978f802, 685 685 - 0x8a788678, 0xb96ef801, 686 686 - 0x876eff6e, 0x00000800, 687 687 - 0xbf840003, 0x876eff78, 688 688 - 0x00002000, 0xbf840009, 689 689 - 0xb97bf803, 0x876eff7b, 690 690 - 0x00000400, 0xbf850033, 691 691 - 0x876eff7b, 0x00000100, 692 692 - 0xbf840002, 0x8878ff78, 693 693 - 0x00002000, 0x8a77ff77, 694 694 - 0xff000000, 0xb96ef807, 695 695 - 0x876fff6e, 0x02000000, 696 696 - 0x8f6f866f, 0x88776f77, 697 697 - 0x876fff6e, 0x003f8000, 698 698 - 0x8f6f896f, 0x88776f77, 699 699 - 0x8a6eff6e, 0x023f8000, 700 700 - 0xb9eef807, 0xb97af812, 701 701 - 0xb97bf813, 0x8ffa887a, 702 702 - 0xf4051bbd, 0xfa000000, 703 703 - 0xbf8cc07f, 0xf4051ebd, 704 704 - 0xfa000008, 0xbf8cc07f, 705 705 - 0x87ee6e6e, 0xbf840001, 706 706 - 0xbe80206e, 0xb97bf803, 707 707 - 0x877bff7b, 0x000001ff, 708 708 - 0xbf850002, 0x806c846c, 709 709 - 0x826d806d, 0x876dff6d, 710 710 - 0x0000ffff, 0x906e8977, 711 711 - 0x876fff6e, 0x003f8000, 712 712 - 0x906e8677, 0x876eff6e, 713 713 - 0x02000000, 0x886e6f6e, 714 714 - 0xb9eef807, 0x87fe7e7e, 715 715 - 0x87ea6a6a, 0xb9f8f802, 716 716 - 0xbe80226c, 0x876dff6d, 717 717 - 0x0000ffff, 0xbefa0380, 718 718 - 0xb9fa0283, 0xb97a2c07, 719 719 - 0x8f7a9a7a, 0x886d7a6d, 720 720 - 0xb97a03c7, 0x8f7a997a, 721 721 - 0x886d7a6d, 0xb97a0647, 722 722 - 0x8f7a987a, 0x886d7a6d, 723 723 - 0xb97af807, 0x877aff7a, 724 724 - 0x00007fff, 0xb9faf807, 725 725 - 0xbeee037e, 0xbeef037f, 726 726 - 0xbefe0480, 0xbf900004, 727 727 - 0xbf8e0002, 0xbf88fffe, 728 728 - 0xb97b02dc, 0x8f7b997b, 729 729 - 0x887b7b7f, 0xb97a2a05, 730 730 - 0x807a817a, 0xbf0d997b, 731 731 - 0xbf850002, 0x8f7a897a, 732 732 - 0xbf820001, 0x8f7a8a7a, 733 733 - 0x877bff7f, 0x0000ffff, 734 734 - 0x807aff7a, 0x00000200, 735 735 - 0x807a7e7a, 0x827b807b, 736 736 - 0xf4491c3d, 0xfa000050, 737 737 - 0xf4491d3d, 0xfa000060, 738 738 - 0xf4411e7d, 0xfa000074, 739 739 - 0xbef4037e, 0x8775ff7f, 740 740 - 0x0000ffff, 0x8875ff75, 741 741 - 0x00040000, 0xbef60380, 742 742 - 0xbef703ff, 0x10807fac, 743 743 - 0x877aff7f, 0x08000000, 744 744 - 0x907a837a, 0x88777a77, 745 745 - 0x877aff7f, 0x70000000, 746 746 - 0x907a817a, 0x88777a77, 747 747 - 0xbef1037c, 0xbef00380, 748 748 - 0xb97302dc, 0x8f739973, 749 749 - 0x8873737f, 0xb97bf816, 750 750 - 0xba80f816, 0x00000000, 751 751 - 0xbefe03c1, 0x907c9973, 752 752 - 0x877c817c, 0xbf06817c, 753 753 - 0xbf850002, 0xbeff0380, 754 754 - 0xbf820002, 0xbeff03c1, 755 755 - 0xbf82000b, 0xbef603ff, 756 756 - 0x01000000, 0xe0704000, 757 757 - 0x705d0000, 0xe0704080, 758 758 - 0x705d0100, 0xe0704100, 759 759 - 0x705d0200, 0xe0704180, 760 760 - 0x705d0300, 0xbf82000a, 761 761 - 0xbef603ff, 0x01000000, 762 762 - 0xe0704000, 0x705d0000, 763 763 - 0xe0704100, 0x705d0100, 764 764 - 0xe0704200, 0x705d0200, 765 765 - 0xe0704300, 0x705d0300, 766 766 - 0xb9702a05, 0x80708170, 767 767 - 0xbf0d9973, 0xbf850002, 768 768 - 0x8f708970, 0xbf820001, 769 769 - 0x8f708a70, 0xb97a1e06, 770 770 - 0x8f7a8a7a, 0x80707a70, 771 771 - 0x8070ff70, 0x00000200, 772 772 - 0xbef603ff, 0x01000000, 773 773 - 0xbefe037c, 0xbefc0370, 774 774 - 0xf4611c7a, 0xf8000000, 775 775 - 0x80708470, 0xbefc037e, 776 776 - 0xbefe037c, 0xbefc0370, 777 777 - 0xf4611b3a, 0xf8000000, 778 778 - 0x80708470, 0xbefc037e, 779 779 - 0xbefe037c, 0xbefc0370, 780 780 - 0xf4611b7a, 0xf8000000, 781 781 - 0x80708470, 0xbefc037e, 782 782 - 0xbefe037c, 0xbefc0370, 783 783 - 0xf4611bba, 0xf8000000, 784 784 - 0x80708470, 0xbefc037e, 785 785 - 0xbefe037c, 0xbefc0370, 786 786 - 0xf4611bfa, 0xf8000000, 787 787 - 0x80708470, 0xbefc037e, 788 788 - 0xbefe037c, 0xbefc0370, 789 789 - 0xf4611e3a, 0xf8000000, 790 790 - 0x80708470, 0xbefc037e, 791 791 - 0xb97af803, 0xbefe037c, 792 792 - 0xbefc0370, 0xf4611eba, 793 793 - 0xf8000000, 0x80708470, 794 794 - 0xbefc037e, 0xbefe037c, 795 795 - 0xbefc0370, 0xf4611efa, 796 796 - 0xf8000000, 0x80708470, 797 797 - 0xbefc037e, 0xb971f801, 798 798 - 0xbefe037c, 0xbefc0370, 799 799 - 0xf4611c7a, 0xf8000000, 800 800 - 0x80708470, 0xbefc037e, 801 801 - 0xb971f814, 0xbefe037c, 802 802 - 0xbefc0370, 0xf4611c7a, 803 803 - 0xf8000000, 0x80708470, 804 804 - 0xbefc037e, 0xb971f815, 805 805 - 0xbefe037c, 0xbefc0370, 806 806 - 0xf4611c7a, 0xf8000000, 807 807 - 0x80708470, 0xbefc037e, 808 808 - 0xb9702a05, 0x80708170, 809 809 - 0xbf0d9973, 0xbf850002, 810 810 - 0x8f708970, 0xbf820001, 811 811 - 0x8f708a70, 0xb97a1e06, 812 812 - 0x8f7a8a7a, 0x80707a70, 813 813 - 0xbef603ff, 0x01000000, 814 814 - 0xbefb0374, 0x80747074, 815 815 - 0x82758075, 0xbefc0380, 816 816 - 0xbf800000, 0xbe802f00, 817 817 - 0xbe822f02, 0xbe842f04, 818 818 - 0xbe862f06, 0xbe882f08, 819 819 - 0xbe8a2f0a, 0xbe8c2f0c, 820 820 - 0xbe8e2f0e, 0xf469003a, 821 821 - 0xfa000000, 0xf469013a, 822 822 - 0xfa000010, 0xf469023a, 823 823 - 0xfa000020, 0xf469033a, 824 824 - 0xfa000030, 0x8074c074, 825 825 - 0x82758075, 0x807c907c, 826 826 - 0xbf0aff7c, 0x00000060, 827 827 - 0xbf85ffea, 0xbe802f00, 828 828 - 0xbe822f02, 0xbe842f04, 829 829 - 0xbe862f06, 0xbe882f08, 830 830 - 0xbe8a2f0a, 0xf469003a, 831 831 - 0xfa000000, 0xf469013a, 832 832 - 0xfa000010, 0xf469023a, 833 833 - 0xfa000020, 0x8074b074, 834 834 - 0x82758075, 0xbef4037b, 835 835 - 0xbefe03c1, 0x907c9973, 836 836 - 0x877c817c, 0xbf06817c, 837 837 - 0xbf850002, 0xbeff0380, 838 838 - 0xbf820001, 0xbeff03c1, 839 839 - 0xb97b4306, 0x877bc17b, 840 840 - 0xbf840044, 0xbf8a0000, 841 841 - 0x877aff73, 0x04000000, 842 842 - 0xbf840040, 0x8f7b867b, 843 843 - 0x8f7b827b, 0xbef6037b, 844 844 - 0xb9702a05, 0x80708170, 845 845 - 0xbf0d9973, 0xbf850002, 846 846 - 0x8f708970, 0xbf820001, 847 847 - 0x8f708a70, 0xb97a1e06, 848 848 - 0x8f7a8a7a, 0x80707a70, 849 849 - 0x8070ff70, 0x00000200, 850 850 - 0x8070ff70, 0x00000080, 851 851 - 0xbef603ff, 0x01000000, 852 852 - 0xd7650000, 0x000100c1, 853 853 - 0xd7660000, 0x000200c1, 854 854 - 0x16000084, 0x907c9973, 855 855 - 0x877c817c, 0xbf06817c, 856 856 - 0xbefc0380, 0xbf850012, 857 857 - 0xbe8303ff, 0x00000080, 858 858 - 0xbf800000, 0xbf800000, 859 859 - 0xbf800000, 0xd8d80000, 860 860 - 0x01000000, 0xbf8c0000, 861 861 - 0xe0704000, 0x705d0100, 862 862 - 0x807c037c, 0x80700370, 863 863 - 0xd5250000, 0x0001ff00, 864 864 - 0x00000080, 0xbf0a7b7c, 865 865 - 0xbf85fff4, 0xbf820011, 866 866 - 0xbe8303ff, 0x00000100, 867 867 - 0xbf800000, 0xbf800000, 868 868 - 0xbf800000, 0xd8d80000, 869 869 - 0x01000000, 0xbf8c0000, 870 870 - 0xe0704000, 0x705d0100, 871 871 - 0x807c037c, 0x80700370, 872 872 - 0xd5250000, 0x0001ff00, 873 873 - 0x00000100, 0xbf0a7b7c, 874 874 - 0xbf85fff4, 0xbefe03c1, 875 875 - 0x907c9973, 0x877c817c, 876 876 - 0xbf06817c, 0xbf850004, 877 877 - 0xbef003ff, 0x00000200, 878 878 - 0xbeff0380, 0xbf820003, 879 879 - 0xbef003ff, 0x00000400, 880 880 - 0xbeff03c1, 0xb97b2a05, 881 881 - 0x807b817b, 0x8f7b827b, 882 882 - 0x907c9973, 0x877c817c, 883 883 - 0xbf06817c, 0xbf850017, 884 884 - 0xbef603ff, 0x01000000, 885 885 - 0xbefc0384, 0xbf0a7b7c, 886 886 - 0xbf840037, 0x7e008700, 887 887 - 0x7e028701, 0x7e048702, 888 888 - 0x7e068703, 0xe0704000, 889 889 - 0x705d0000, 0xe0704080, 890 890 - 0x705d0100, 0xe0704100, 891 891 - 0x705d0200, 0xe0704180, 892 892 - 0x705d0300, 0x807c847c, 893 893 - 0x8070ff70, 0x00000200, 894 894 - 0xbf0a7b7c, 0xbf85ffef, 895 895 - 0xbf820025, 0xbef603ff, 896 896 - 0x01000000, 0xbefc0384, 897 897 - 0xbf0a7b7c, 0xbf840020, 898 898 - 0x7e008700, 0x7e028701, 899 899 - 0x7e048702, 0x7e068703, 900 900 - 0xe0704000, 0x705d0000, 901 901 - 0xe0704100, 0x705d0100, 902 902 - 0xe0704200, 0x705d0200, 903 903 - 0xe0704300, 0x705d0300, 904 904 - 0x807c847c, 0x8070ff70, 905 905 - 0x00000400, 0xbf0a7b7c, 906 906 - 0xbf85ffef, 0xb97b1e06, 907 907 - 0x877bc17b, 0xbf84000c, 908 908 - 0x8f7b837b, 0x807b7c7b, 909 909 - 0xbefe03c1, 0xbeff0380, 910 910 - 0x7e008700, 0xe0704000, 911 911 - 0x705d0000, 0x807c817c, 912 912 - 0x8070ff70, 0x00000080, 913 913 - 0xbf0a7b7c, 0xbf85fff8, 914 914 - 0xbf820151, 0xbef4037e, 915 915 - 0x8775ff7f, 0x0000ffff, 916 916 - 0x8875ff75, 0x00040000, 917 917 - 0xbef60380, 0xbef703ff, 918 918 - 0x10807fac, 0x876eff7f, 919 919 - 0x08000000, 0x906e836e, 920 920 - 0x88776e77, 0x876eff7f, 921 921 - 0x70000000, 0x906e816e, 922 922 - 0x88776e77, 0xb97202dc, 923 923 - 0x8f729972, 0x8872727f, 924 924 - 0x876eff7f, 0x04000000, 925 925 - 0xbf840034, 0xbefe03c1, 926 926 - 0x907c9972, 0x877c817c, 927 927 - 0xbf06817c, 0xbf850002, 928 928 - 0xbeff0380, 0xbf820001, 929 929 - 0xbeff03c1, 0xb96f4306, 930 930 - 0x876fc16f, 0xbf840029, 931 931 - 0x8f6f866f, 0x8f6f826f, 932 932 - 0xbef6036f, 0xb9782a05, 933 933 - 0x80788178, 0xbf0d9972, 934 934 - 0xbf850002, 0x8f788978, 935 935 - 0xbf820001, 0x8f788a78, 936 936 - 0xb96e1e06, 0x8f6e8a6e, 937 937 - 0x80786e78, 0x8078ff78, 938 938 - 0x00000200, 0x8078ff78, 939 939 - 0x00000080, 0xbef603ff, 940 940 - 0x01000000, 0x907c9972, 941 941 - 0x877c817c, 0xbf06817c, 942 942 - 0xbefc0380, 0xbf850009, 943 943 - 0xe0310000, 0x781d0000, 944 944 - 0x807cff7c, 0x00000080, 945 945 - 0x8078ff78, 0x00000080, 946 946 - 0xbf0a6f7c, 0xbf85fff8, 947 947 - 0xbf820008, 0xe0310000, 948 948 - 0x781d0000, 0x807cff7c, 949 949 - 0x00000100, 0x8078ff78, 950 950 - 0x00000100, 0xbf0a6f7c, 951 951 - 0xbf85fff8, 0xbef80380, 952 952 - 0xbefe03c1, 0x907c9972, 953 953 - 0x877c817c, 0xbf06817c, 954 954 - 0xbf850002, 0xbeff0380, 955 955 - 0xbf820001, 0xbeff03c1, 956 956 - 0xb96f2a05, 0x806f816f, 957 957 - 0x8f6f826f, 0x907c9972, 958 958 - 0x877c817c, 0xbf06817c, 959 959 - 0xbf850021, 0xbef603ff, 960 960 - 0x01000000, 0xbeee0378, 961 961 - 0x8078ff78, 0x00000200, 962 962 - 0xbefc0384, 0xe0304000, 963 963 - 0x785d0000, 0xe0304080, 964 964 - 0x785d0100, 0xe0304100, 965 965 - 0x785d0200, 0xe0304180, 966 966 - 0x785d0300, 0xbf8c3f70, 967 967 - 0x7e008500, 0x7e028501, 968 968 - 0x7e048502, 0x7e068503, 969 969 - 0x807c847c, 0x8078ff78, 970 970 - 0x00000200, 0xbf0a6f7c, 971 971 - 0xbf85ffee, 0xe0304000, 972 972 - 0x6e5d0000, 0xe0304080, 973 973 - 0x6e5d0100, 0xe0304100, 974 974 - 0x6e5d0200, 0xe0304180, 975 975 - 0x6e5d0300, 0xbf820032, 976 976 - 0xbef603ff, 0x01000000, 977 977 - 0xbeee0378, 0x8078ff78, 978 978 - 0x00000400, 0xbefc0384, 979 979 - 0xe0304000, 0x785d0000, 980 980 - 0xe0304100, 0x785d0100, 981 981 - 0xe0304200, 0x785d0200, 982 982 - 0xe0304300, 0x785d0300, 983 983 - 0xbf8c3f70, 0x7e008500, 984 984 - 0x7e028501, 0x7e048502, 985 985 - 0x7e068503, 0x807c847c, 986 986 - 0x8078ff78, 0x00000400, 987 987 - 0xbf0a6f7c, 0xbf85ffee, 988 988 - 0xb96f1e06, 0x876fc16f, 989 989 - 0xbf84000e, 0x8f6f836f, 990 990 - 0x806f7c6f, 0xbefe03c1, 991 991 - 0xbeff0380, 0xe0304000, 992 992 - 0x785d0000, 0xbf8c3f70, 993 993 - 0x7e008500, 0x807c817c, 994 994 - 0x8078ff78, 0x00000080, 995 995 - 0xbf0a6f7c, 0xbf85fff7, 996 996 - 0xbeff03c1, 0xe0304000, 997 997 - 0x6e5d0000, 0xe0304100, 998 998 - 0x6e5d0100, 0xe0304200, 999 999 - 0x6e5d0200, 0xe0304300, 1000 1000 - 0x6e5d0300, 0xbf8c3f70, 1001 1001 - 0xb9782a05, 0x80788178, 1002 1002 - 0xbf0d9972, 0xbf850002, 1003 1003 - 0x8f788978, 0xbf820001, 1004 1004 - 0x8f788a78, 0xb96e1e06, 1005 1005 - 0x8f6e8a6e, 0x80786e78, 1006 1006 - 0x8078ff78, 0x00000200, 1007 1007 - 0x80f8ff78, 0x00000050, 1008 1008 - 0xbef603ff, 0x01000000, 1009 1009 - 0xbefc03ff, 0x0000006c, 1010 1010 - 0x80f89078, 0xf429003a, 1011 1011 - 0xf0000000, 0xbf8cc07f, 1012 1012 - 0x80fc847c, 0xbf800000, 1013 1013 - 0xbe803100, 0xbe823102, 1014 1014 - 0x80f8a078, 0xf42d003a, 1015 1015 - 0xf0000000, 0xbf8cc07f, 1016 1016 - 0x80fc887c, 0xbf800000, 1017 1017 - 0xbe803100, 0xbe823102, 1018 1018 - 0xbe843104, 0xbe863106, 1019 1019 - 0x80f8c078, 0xf431003a, 1020 1020 - 0xf0000000, 0xbf8cc07f, 1021 1021 - 0x80fc907c, 0xbf800000, 1022 1022 - 0xbe803100, 0xbe823102, 1023 1023 - 0xbe843104, 0xbe863106, 1024 1024 - 0xbe883108, 0xbe8a310a, 1025 1025 - 0xbe8c310c, 0xbe8e310e, 1026 1026 - 0xbf06807c, 0xbf84fff0, 1027 1027 - 0xba80f801, 0x00000000, 1028 1028 - 0xbf8a0000, 0xb9782a05, 1029 1029 - 0x80788178, 0xbf0d9972, 1030 1030 - 0xbf850002, 0x8f788978, 1031 1031 - 0xbf820001, 0x8f788a78, 1032 1032 - 0xb96e1e06, 0x8f6e8a6e, 1033 1033 - 0x80786e78, 0x8078ff78, 1034 1034 - 0x00000200, 0xbef603ff, 1035 1035 - 0x01000000, 0xf4211bfa, 1036 1036 - 0xf0000000, 0x80788478, 1037 1037 - 0xf4211b3a, 0xf0000000, 1038 1038 - 0x80788478, 0xf4211b7a, 1039 1039 - 0xf0000000, 0x80788478, 1040 1040 - 0xf4211c3a, 0xf0000000, 1041 1041 - 0x80788478, 0xf4211c7a, 1042 1042 - 0xf0000000, 0x80788478, 1043 1043 - 0xf4211eba, 0xf0000000, 1044 1044 - 0x80788478, 0xf4211efa, 1045 1045 - 0xf0000000, 0x80788478, 1046 1046 - 0xf4211e7a, 0xf0000000, 1047 1047 - 0x80788478, 0xf4211cfa, 1048 1048 - 0xf0000000, 0x80788478, 1049 1049 - 0xf4211bba, 0xf0000000, 1050 1050 - 0x80788478, 0xbf8cc07f, 1051 1051 - 0xb9eef814, 0xf4211bba, 1052 1052 - 0xf0000000, 0x80788478, 1053 1053 - 0xbf8cc07f, 0xb9eef815, 1054 1054 - 0xbefc036f, 0xbefe0370, 1055 1055 - 0xbeff0371, 0x876f7bff, 1056 1056 - 0x000003ff, 0xb9ef4803, 1057 1057 - 0xb9f9f816, 0x876f7bff, 1058 1058 - 0xfffff800, 0x906f8b6f, 1059 1059 - 0xb9efa2c3, 0xb9f3f801, 1060 1060 - 0xb96e2a05, 0x806e816e, 1061 1061 - 0xbf0d9972, 0xbf850002, 1062 1062 - 0x8f6e896e, 0xbf820001, 1063 1063 - 0x8f6e8a6e, 0x806eff6e, 1064 1064 - 0x00000200, 0x806e746e, 1065 1065 - 0x826f8075, 0x876fff6f, 1066 1066 - 0x0000ffff, 0xf4091c37, 1067 1067 - 0xfa000050, 0xf4091d37, 1068 1068 - 0xfa000060, 0xf4011e77, 1069 1069 - 0xfa000074, 0xbf8cc07f, 1070 1070 - 0x876fff6d, 0xfc000000, 1071 1071 - 0x906f9a6f, 0x8f6f906f, 1072 1072 - 0xbeee0380, 0x886e6f6e, 1073 1073 - 0x876fff6d, 0x02000000, 1074 1074 - 0x906f996f, 0x8f6f8f6f, 1075 1075 - 0x886e6f6e, 0x876fff6d, 1076 1076 - 0x01000000, 0x906f986f, 1077 1077 - 0x8f6f996f, 0x886e6f6e, 1078 1078 - 0x876fff7a, 0x00800000, 1079 1079 - 0x906f976f, 0xb9eef807, 1080 1080 - 0x876dff6d, 0x0000ffff, 1081 1081 - 0x87fe7e7e, 0x87ea6a6a, 1082 1082 - 0xb9faf802, 0xbe80226c, 1083 1083 - 0xbf810000, 0xbf9f0000, 1084 1084 - 0xbf9f0000, 0xbf9f0000, 1085 1085 - 0xbf9f0000, 0xbf9f0000, 1086 1086 - }; 1087 1087 - 1088 1088 - static const uint32_t cwsr_trap_arcturus_hex[] = { 1089 1089 - 0xbf820001, 0xbf8202c4, 1090 1090 - 0xb8f8f802, 0x89788678, 1091 1091 - 0xb8eef801, 0x866eff6e, 1092 1092 - 0x00000800, 0xbf840003, 1093 1093 - 0x866eff78, 0x00002000, 1094 1094 - 0xbf840016, 0xb8fbf803, 1095 1095 - 0x866eff7b, 0x00000400, 1096 1096 - 0xbf85003b, 0x866eff7b, 1097 1097 - 0x00000800, 0xbf850003, 1098 1098 - 0x866eff7b, 0x00000100, 1099 1099 - 0xbf84000c, 0x866eff78, 1100 1100 - 0x00002000, 0xbf840005, 1101 1101 - 0xbf8e0010, 0xb8eef803, 1102 1102 - 0x866eff6e, 0x00000400, 1103 1103 - 0xbf84fffb, 0x8778ff78, 1104 1104 - 0x00002000, 0x80ec886c, 1105 1105 - 0x82ed806d, 0xb8eef807, 1106 1106 - 0x866fff6e, 0x001f8000, 1107 1107 - 0x8e6f8b6f, 0x8977ff77, 1108 1108 - 0xfc000000, 0x87776f77, 1109 1109 - 0x896eff6e, 0x001f8000, 1110 1110 - 0xb96ef807, 0xb8faf812, 1111 1111 - 0xb8fbf813, 0x8efa887a, 1112 1112 - 0xc0071bbd, 0x00000000, 1113 1113 - 0xbf8cc07f, 0xc0071ebd, 1114 1114 - 0x00000008, 0xbf8cc07f, 1115 1115 - 0x86ee6e6e, 0xbf840001, 1116 1116 - 0xbe801d6e, 0xb8fbf803, 1117 1117 - 0x867bff7b, 0x000001ff, 1118 1118 - 0xbf850002, 0x806c846c, 1119 1119 - 0x826d806d, 0x866dff6d, 1120 1120 - 0x0000ffff, 0x8f6e8b77, 1121 1121 - 0x866eff6e, 0x001f8000, 1122 1122 - 0xb96ef807, 0x86fe7e7e, 1123 1123 - 0x86ea6a6a, 0x8f6e8378, 1124 1124 - 0xb96ee0c2, 0xbf800002, 1125 1125 - 0xb9780002, 0xbe801f6c, 1126 1126 - 0x866dff6d, 0x0000ffff, 1127 1127 - 0xbefa0080, 0xb97a0283, 1128 1128 - 0xb8fa2407, 0x8e7a9b7a, 1129 1129 - 0x876d7a6d, 0xb8fa03c7, 1130 1130 - 0x8e7a9a7a, 0x876d7a6d, 1131 1131 - 0xb8faf807, 0x867aff7a, 1132 1132 - 0x00007fff, 0xb97af807, 1133 1133 - 0xbeee007e, 0xbeef007f, 1134 1134 - 0xbefe0180, 0xbf900004, 1135 1135 - 0x877a8478, 0xb97af802, 1136 1136 - 0xbf8e0002, 0xbf88fffe, 1137 1137 - 0xb8fa2a05, 0x807a817a, 1138 1138 - 0x8e7a8a7a, 0x8e7a817a, 328 328 + 0x001f8000, 0x8e7a8b7a, 329 329 + 0x8977ff77, 0xfc000000, 330 330 + 0x87777a77, 0xba7ff807, 331 331 + 0x00000000, 0xbeee007e, 332 332 + 0xbeef007f, 0xbefe0180, 333 333 + 0xbf900004, 0x877a8478, 334 334 + 0xb97af802, 0xbf8e0002, 335 335 + 0xbf88fffe, 0xb8fa2a05, 336 336 + 0x807a817a, 0x8e7a8a7a, 1139 337 0xb8fb1605, 0x807b817b, 1140 338 0x8e7b867b, 0x807a7b7a, 1141 339 0x807a7e7a, 0x827b807f, ··· 346 1148 0x8675ff7f, 0x0000ffff, 347 1149 0x8775ff75, 0x00040000, 348 1150 0xbef60080, 0xbef700ff, 349 349 - 0x00807fac, 0x867aff7f, 350 350 - 0x08000000, 0x8f7a837a, 351 351 - 0x87777a77, 0x867aff7f, 352 352 - 0x70000000, 0x8f7a817a, 353 353 - 0x87777a77, 0xbef1007c, 1151 1151 + 0x00807fac, 0xbef1007c, 354 1152 0xbef00080, 0xb8f02a05, 355 1153 0x80708170, 0x8e708a70, 356 356 - 0x8e708170, 0xb8fa1605, 357 357 - 0x807a817a, 0x8e7a867a, 358 358 - 0x80707a70, 0xbef60084, 359 359 - 0xbef600ff, 0x01000000, 360 360 - 0xbefe007c, 0xbefc0070, 361 361 - 0xc0611c7a, 0x0000007c, 362 362 - 0xbf8cc07f, 0x80708470, 363 363 - 0xbefc007e, 0xbefe007c, 364 364 - 0xbefc0070, 0xc0611b3a, 365 365 - 0x0000007c, 0xbf8cc07f, 366 366 - 0x80708470, 0xbefc007e, 367 367 - 0xbefe007c, 0xbefc0070, 368 368 - 0xc0611b7a, 0x0000007c, 369 369 - 0xbf8cc07f, 0x80708470, 370 370 - 0xbefc007e, 0xbefe007c, 371 371 - 0xbefc0070, 0xc0611bba, 372 372 - 0x0000007c, 0xbf8cc07f, 373 373 - 0x80708470, 0xbefc007e, 374 374 - 0xbefe007c, 0xbefc0070, 375 375 - 0xc0611bfa, 0x0000007c, 376 376 - 0xbf8cc07f, 0x80708470, 377 377 - 0xbefc007e, 0xbefe007c, 378 378 - 0xbefc0070, 0xc0611e3a, 379 379 - 0x0000007c, 0xbf8cc07f, 380 380 - 0x80708470, 0xbefc007e, 381 381 - 0xb8fbf803, 0xbefe007c, 382 382 - 0xbefc0070, 0xc0611efa, 383 383 - 0x0000007c, 0xbf8cc07f, 384 384 - 0x80708470, 0xbefc007e, 385 385 - 0xbefe007c, 0xbefc0070, 386 386 - 0xc0611a3a, 0x0000007c, 387 387 - 0xbf8cc07f, 0x80708470, 388 388 - 0xbefc007e, 0xbefe007c, 389 389 - 0xbefc0070, 0xc0611a7a, 390 390 - 0x0000007c, 0xbf8cc07f, 391 391 - 0x80708470, 0xbefc007e, 392 392 - 0xb8f1f801, 0xbefe007c, 1154 1154 + 0xb8fa1605, 0x807a817a, 1155 1155 + 0x8e7a867a, 0x80707a70, 1156 1156 + 0xbef60084, 0xbef600ff, 1157 1157 + 0x01000000, 0xbefe007c, 393 1158 0xbefc0070, 0xc0611c7a, 394 1159 0x0000007c, 0xbf8cc07f, 395 1160 0x80708470, 0xbefc007e, 396 396 - 0x867aff7f, 0x04000000, 397 397 - 0xbeef0080, 0x876f6f7a, 398 398 - 0xb8f02a05, 0x80708170, 399 399 - 0x8e708a70, 0x8e708170, 1161 1161 + 0xbefe007c, 0xbefc0070, 1162 1162 + 0xc0611b3a, 0x0000007c, 1163 1163 + 0xbf8cc07f, 0x80708470, 1164 1164 + 0xbefc007e, 0xbefe007c, 1165 1165 + 0xbefc0070, 0xc0611b7a, 1166 1166 + 0x0000007c, 0xbf8cc07f, 1167 1167 + 0x80708470, 0xbefc007e, 1168 1168 + 0xbefe007c, 0xbefc0070, 1169 1169 + 0xc0611bba, 0x0000007c, 1170 1170 + 0xbf8cc07f, 0x80708470, 1171 1171 + 0xbefc007e, 0xbefe007c, 1172 1172 + 0xbefc0070, 0xc0611bfa, 1173 1173 + 0x0000007c, 0xbf8cc07f, 1174 1174 + 0x80708470, 0xbefc007e, 1175 1175 + 0xbefe007c, 0xbefc0070, 1176 1176 + 0xc0611e3a, 0x0000007c, 1177 1177 + 0xbf8cc07f, 0x80708470, 1178 1178 + 0xbefc007e, 0xb8fbf803, 1179 1179 + 0xbefe007c, 0xbefc0070, 1180 1180 + 0xc0611efa, 0x0000007c, 1181 1181 + 0xbf8cc07f, 0x80708470, 1182 1182 + 0xbefc007e, 0xbefe007c, 1183 1183 + 0xbefc0070, 0xc0611a3a, 1184 1184 + 0x0000007c, 0xbf8cc07f, 1185 1185 + 0x80708470, 0xbefc007e, 1186 1186 + 0xbefe007c, 0xbefc0070, 1187 1187 + 0xc0611a7a, 0x0000007c, 1188 1188 + 0xbf8cc07f, 0x80708470, 1189 1189 + 0xbefc007e, 0xb8f1f801, 1190 1190 + 0xbefe007c, 0xbefc0070, 1191 1191 + 0xc0611c7a, 0x0000007c, 1192 1192 + 0xbf8cc07f, 0x80708470, 1193 1193 + 0xbefc007e, 0x867aff7f, 1194 1194 + 0x04000000, 0xbeef0080, 1195 1195 + 0x876f6f7a, 0xb8f02a05, 1196 1196 + 0x80708170, 0x8e708a70, 400 1197 0xb8fb1605, 0x807b817b, 401 1198 0x8e7b847b, 0x8e76827b, 402 1199 0xbef600ff, 0x01000000, ··· 462 1269 0xe0724300, 0x701d0300, 463 1270 0xbefe00c1, 0xbeff00c1, 464 1271 0xb8fb4306, 0x867bc17b, 465 465 - 0xbf840064, 0xbf8a0000, 1272 1272 + 0xbf840063, 0xbf8a0000, 466 1273 0x867aff6f, 0x04000000, 467 467 - 0xbf840060, 0x8e7b867b, 1274 1274 + 0xbf84005f, 0x8e7b867b, 468 1275 0x8e7b827b, 0xbef6007b, 469 1276 0xb8f02a05, 0x80708170, 470 470 - 0x8e708a70, 0x8e708170, 471 471 - 0xb8fa1605, 0x807a817a, 472 472 - 0x8e7a867a, 0x80707a70, 473 473 - 0x8070ff70, 0x00000080, 474 474 - 0xbef600ff, 0x01000000, 475 475 - 0xbefc0080, 0xd28c0002, 476 476 - 0x000100c1, 0xd28d0003, 477 477 - 0x000204c1, 0x867aff78, 1277 1277 + 0x8e708a70, 0xb8fa1605, 1278 1278 + 0x807a817a, 0x8e7a867a, 1279 1279 + 0x80707a70, 0x8070ff70, 1280 1280 + 0x00000080, 0xbef600ff, 1281 1281 + 0x01000000, 0xbefc0080, 1282 1282 + 0xd28c0002, 0x000100c1, 1283 1283 + 0xd28d0003, 0x000204c1, 1284 1284 + 0x867aff78, 0x00400000, 1285 1285 + 0xbf850003, 0xb8faf803, 1286 1286 + 0x897a7aff, 0x10000000, 1287 1287 + 0xbf850030, 0x24040682, 1288 1288 + 0xd86e4000, 0x00000002, 1289 1289 + 0xbf8cc07f, 0xbe840080, 1290 1290 + 0xd2890000, 0x00000900, 1291 1291 + 0x80048104, 0xd2890001, 1292 1292 + 0x00000900, 0x80048104, 1293 1293 + 0xd2890002, 0x00000900, 1294 1294 + 0x80048104, 0xd2890003, 1295 1295 + 0x00000900, 0x80048104, 1296 1296 + 0xc069003a, 0x00000070, 1297 1297 + 0xbf8cc07f, 0x80709070, 1298 1298 + 0xbf06c004, 0xbf84ffee, 1299 1299 + 0xbe840080, 0xd2890000, 1300 1300 + 0x00000901, 0x80048104, 1301 1301 + 0xd2890001, 0x00000901, 1302 1302 + 0x80048104, 0xd2890002, 1303 1303 + 0x00000901, 0x80048104, 1304 1304 + 0xd2890003, 0x00000901, 1305 1305 + 0x80048104, 0xc069003a, 1306 1306 + 0x00000070, 0xbf8cc07f, 1307 1307 + 0x80709070, 0xbf06c004, 1308 1308 + 0xbf84ffee, 0x680404ff, 1309 1309 + 0x00000200, 0xd0c9006a, 1310 1310 + 0x0000f702, 0xbf87ffd2, 1311 1311 + 0xbf820015, 0xd1060002, 1312 1312 + 0x00011103, 0x7e0602ff, 1313 1313 + 0x00000200, 0xbefc00ff, 1314 1314 + 0x00010000, 0xbe800077, 1315 1315 + 0x8677ff77, 0xff7fffff, 1316 1316 + 0x8777ff77, 0x00058000, 1317 1317 + 0xd8ec0000, 0x00000002, 1318 1318 + 0xbf8cc07f, 0xe0765000, 1319 1319 + 0x701d0002, 0x68040702, 1320 1320 + 0xd0c9006a, 0x0000f702, 1321 1321 + 0xbf87fff7, 0xbef70000, 1322 1322 + 0xbef000ff, 0x00000400, 1323 1323 + 0xbefe00c1, 0xbeff00c1, 1324 1324 + 0xb8fb2a05, 0x807b817b, 1325 1325 + 0x8e7b827b, 0xbef600ff, 1326 1326 + 0x01000000, 0xbefc0084, 1327 1327 + 0xbf0a7b7c, 0xbf84006d, 1328 1328 + 0xbf11017c, 0x807bff7b, 1329 1329 + 0x00001000, 0x867aff78, 478 1330 0x00400000, 0xbf850003, 479 1331 0xb8faf803, 0x897a7aff, 480 480 - 0x10000000, 0xbf850030, 481 481 - 0x24040682, 0xd86e4000, 482 482 - 0x00000002, 0xbf8cc07f, 1332 1332 + 0x10000000, 0xbf850051, 483 1333 0xbe840080, 0xd2890000, 484 1334 0x00000900, 0x80048104, 485 1335 0xd2890001, 0x00000900, ··· 542 1306 0xc069003a, 0x00000070, 543 1307 0xbf8cc07f, 0x80709070, 544 1308 0xbf06c004, 0xbf84ffee, 545 545 - 0x680404ff, 0x00000200, 1309 1309 + 0xbe840080, 0xd2890000, 1310 1310 + 0x00000902, 0x80048104, 1311 1311 + 0xd2890001, 0x00000902, 1312 1312 + 0x80048104, 0xd2890002, 1313 1313 + 0x00000902, 0x80048104, 1314 1314 + 0xd2890003, 0x00000902, 1315 1315 + 0x80048104, 0xc069003a, 1316 1316 + 0x00000070, 0xbf8cc07f, 1317 1317 + 0x80709070, 0xbf06c004, 1318 1318 + 0xbf84ffee, 0xbe840080, 1319 1319 + 0xd2890000, 0x00000903, 1320 1320 + 0x80048104, 0xd2890001, 1321 1321 + 0x00000903, 0x80048104, 1322 1322 + 0xd2890002, 0x00000903, 1323 1323 + 0x80048104, 0xd2890003, 1324 1324 + 0x00000903, 0x80048104, 1325 1325 + 0xc069003a, 0x00000070, 1326 1326 + 0xbf8cc07f, 0x80709070, 1327 1327 + 0xbf06c004, 0xbf84ffee, 1328 1328 + 0x807c847c, 0xbf0a7b7c, 1329 1329 + 0xbf85ffb1, 0xbf9c0000, 1330 1330 + 0xbf820012, 0x7e000300, 1331 1331 + 0x7e020301, 0x7e040302, 1332 1332 + 0x7e060303, 0xe0724000, 1333 1333 + 0x701d0000, 0xe0724100, 1334 1334 + 0x701d0100, 0xe0724200, 1335 1335 + 0x701d0200, 0xe0724300, 1336 1336 + 0x701d0300, 0x807c847c, 1337 1337 + 0x8070ff70, 0x00000400, 1338 1338 + 0xbf0a7b7c, 0xbf85ffef, 1339 1339 + 0xbf9c0000, 0xbf8200c7, 1340 1340 + 0xbef4007e, 0x8675ff7f, 1341 1341 + 0x0000ffff, 0x8775ff75, 1342 1342 + 0x00040000, 0xbef60080, 1343 1343 + 0xbef700ff, 0x00807fac, 1344 1344 + 0x866eff7f, 0x04000000, 1345 1345 + 0xbf84001e, 0xbefe00c1, 1346 1346 + 0xbeff00c1, 0xb8ef4306, 1347 1347 + 0x866fc16f, 0xbf840019, 1348 1348 + 0x8e6f866f, 0x8e6f826f, 1349 1349 + 0xbef6006f, 0xb8f82a05, 1350 1350 + 0x80788178, 0x8e788a78, 1351 1351 + 0xb8ee1605, 0x806e816e, 1352 1352 + 0x8e6e866e, 0x80786e78, 1353 1353 + 0x8078ff78, 0x00000080, 1354 1354 + 0xbef600ff, 0x01000000, 1355 1355 + 0xbefc0080, 0xe0510000, 1356 1356 + 0x781d0000, 0xe0510100, 1357 1357 + 0x781d0000, 0x807cff7c, 1358 1358 + 0x00000200, 0x8078ff78, 1359 1359 + 0x00000200, 0xbf0a6f7c, 1360 1360 + 0xbf85fff6, 0xbefe00c1, 1361 1361 + 0xbeff00c1, 0xbef600ff, 1362 1362 + 0x01000000, 0xb8ef2a05, 1363 1363 + 0x806f816f, 0x8e6f826f, 1364 1364 + 0x806fff6f, 0x00008000, 1365 1365 + 0xbef80080, 0xbeee0078, 1366 1366 + 0x8078ff78, 0x00000400, 1367 1367 + 0xbefc0084, 0xbf11087c, 1368 1368 + 0xe0524000, 0x781d0000, 1369 1369 + 0xe0524100, 0x781d0100, 1370 1370 + 0xe0524200, 0x781d0200, 1371 1371 + 0xe0524300, 0x781d0300, 1372 1372 + 0xbf8c0f70, 0x7e000300, 1373 1373 + 0x7e020301, 0x7e040302, 1374 1374 + 0x7e060303, 0x807c847c, 1375 1375 + 0x8078ff78, 0x00000400, 1376 1376 + 0xbf0a6f7c, 0xbf85ffee, 1377 1377 + 0xbf9c0000, 0xe0524000, 1378 1378 + 0x6e1d0000, 0xe0524100, 1379 1379 + 0x6e1d0100, 0xe0524200, 1380 1380 + 0x6e1d0200, 0xe0524300, 1381 1381 + 0x6e1d0300, 0xbf8c0f70, 1382 1382 + 0xb8f82a05, 0x80788178, 1383 1383 + 0x8e788a78, 0xb8ee1605, 1384 1384 + 0x806e816e, 0x8e6e866e, 1385 1385 + 0x80786e78, 0x80f8c078, 1386 1386 + 0xb8ef1605, 0x806f816f, 1387 1387 + 0x8e6f846f, 0x8e76826f, 1388 1388 + 0xbef600ff, 0x01000000, 1389 1389 + 0xbefc006f, 0xc031003a, 1390 1390 + 0x00000078, 0x80f8c078, 1391 1391 + 0xbf8cc07f, 0x80fc907c, 1392 1392 + 0xbf800000, 0xbe802d00, 1393 1393 + 0xbe822d02, 0xbe842d04, 1394 1394 + 0xbe862d06, 0xbe882d08, 1395 1395 + 0xbe8a2d0a, 0xbe8c2d0c, 1396 1396 + 0xbe8e2d0e, 0xbf06807c, 1397 1397 + 0xbf84fff0, 0xb8f82a05, 1398 1398 + 0x80788178, 0x8e788a78, 1399 1399 + 0xb8ee1605, 0x806e816e, 1400 1400 + 0x8e6e866e, 0x80786e78, 1401 1401 + 0xbef60084, 0xbef600ff, 1402 1402 + 0x01000000, 0xc0211bfa, 1403 1403 + 0x00000078, 0x80788478, 1404 1404 + 0xc0211b3a, 0x00000078, 1405 1405 + 0x80788478, 0xc0211b7a, 1406 1406 + 0x00000078, 0x80788478, 1407 1407 + 0xc0211c3a, 0x00000078, 1408 1408 + 0x80788478, 0xc0211c7a, 1409 1409 + 0x00000078, 0x80788478, 1410 1410 + 0xc0211eba, 0x00000078, 1411 1411 + 0x80788478, 0xc0211efa, 1412 1412 + 0x00000078, 0x80788478, 1413 1413 + 0xc0211a3a, 0x00000078, 1414 1414 + 0x80788478, 0xc0211a7a, 1415 1415 + 0x00000078, 0x80788478, 1416 1416 + 0xc0211cfa, 0x00000078, 1417 1417 + 0x80788478, 0xbf8cc07f, 1418 1418 + 0xbefc006f, 0xbefe0070, 1419 1419 + 0xbeff0071, 0x866f7bff, 1420 1420 + 0x000003ff, 0xb96f4803, 1421 1421 + 0x866f7bff, 0xfffff800, 1422 1422 + 0x8f6f8b6f, 0xb96fa2c3, 1423 1423 + 0xb973f801, 0xb8ee2a05, 1424 1424 + 0x806e816e, 0x8e6e8a6e, 1425 1425 + 0xb8ef1605, 0x806f816f, 1426 1426 + 0x8e6f866f, 0x806e6f6e, 1427 1427 + 0x806e746e, 0x826f8075, 1428 1428 + 0x866fff6f, 0x0000ffff, 1429 1429 + 0xc00b1c37, 0x00000050, 1430 1430 + 0xc00b1d37, 0x00000060, 1431 1431 + 0xc0031e77, 0x00000074, 1432 1432 + 0xbf8cc07f, 0x8f6e8b77, 1433 1433 + 0x866eff6e, 0x001f8000, 1434 1434 + 0xb96ef807, 0x866dff6d, 1435 1435 + 0x0000ffff, 0x86fe7e7e, 1436 1436 + 0x86ea6a6a, 0x8f6e837a, 1437 1437 + 0xb96ee0c2, 0xbf800002, 1438 1438 + 0xb97a0002, 0xbf8a0000, 1439 1439 + 0xbe801f6c, 0xbf810000, 1440 1440 + }; 1441 1441 + 1442 1442 + static const uint32_t cwsr_trap_nv1x_hex[] = { 1443 1443 + 0xbf820001, 0xbf8201f1, 1444 1444 + 0xb0804004, 0xb978f802, 1445 1445 + 0x8a78ff78, 0x00020006, 1446 1446 + 0xb97bf803, 0x876eff78, 1447 1447 + 0x00002000, 0xbf840009, 1448 1448 + 0x876eff6d, 0x00ff0000, 1449 1449 + 0xbf85001e, 0x876eff7b, 1450 1450 + 0x00000400, 0xbf850057, 1451 1451 + 0xbf8e0010, 0xb97bf803, 1452 1452 + 0xbf82fffa, 0x876eff7b, 1453 1453 + 0x00000900, 0xbf850015, 1454 1454 + 0x876eff7b, 0x000071ff, 1455 1455 + 0xbf840008, 0x876fff7b, 1456 1456 + 0x00007080, 0xbf840001, 1457 1457 + 0xbeee1d87, 0xb96ff801, 1458 1458 + 0x8f6e8c6e, 0x876e6f6e, 1459 1459 + 0xbf85000a, 0x876eff6d, 1460 1460 + 0x00ff0000, 0xbf850007, 1461 1461 + 0xb96ef801, 0x876eff6e, 1462 1462 + 0x00000800, 0xbf850003, 1463 1463 + 0x876eff7b, 0x00000400, 1464 1464 + 0xbf85003c, 0x8a77ff77, 1465 1465 + 0xff000000, 0xb97af807, 1466 1466 + 0x877bff7a, 0x02000000, 1467 1467 + 0x8f7b867b, 0x88777b77, 1468 1468 + 0x877bff7a, 0x003f8000, 1469 1469 + 0x8f7b897b, 0x88777b77, 1470 1470 + 0x8a7aff7a, 0x023f8000, 1471 1471 + 0xb9faf807, 0xb97af812, 1472 1472 + 0xb97bf813, 0x8ffa887a, 1473 1473 + 0xf4011bbd, 0xfa000010, 1474 1474 + 0xbf8cc07f, 0x8f6e976e, 1475 1475 + 0x8a77ff77, 0x00800000, 1476 1476 + 0x88776e77, 0xf4051bbd, 1477 1477 + 0xfa000000, 0xbf8cc07f, 1478 1478 + 0xf4051ebd, 0xfa000008, 1479 1479 + 0xbf8cc07f, 0x87ee6e6e, 1480 1480 + 0xbf840001, 0xbe80206e, 1481 1481 + 0x876eff6d, 0x01ff0000, 1482 1482 + 0xbf850005, 0x8878ff78, 1483 1483 + 0x00002000, 0x80ec886c, 1484 1484 + 0x82ed806d, 0xbf820005, 1485 1485 + 0x876eff6d, 0x01000000, 1486 1486 + 0xbf850002, 0x806c846c, 1487 1487 + 0x826d806d, 0x876dff6d, 1488 1488 + 0x0000ffff, 0x907a8977, 1489 1489 + 0x877bff7a, 0x003f8000, 1490 1490 + 0x907a8677, 0x877aff7a, 1491 1491 + 0x02000000, 0x887a7b7a, 1492 1492 + 0xb9faf807, 0x87fe7e7e, 1493 1493 + 0x87ea6a6a, 0xb9f8f802, 1494 1494 + 0xbe80226c, 0x876dff6d, 1495 1495 + 0x0000ffff, 0xbefa0380, 1496 1496 + 0xb9fa0283, 0x8a77ff77, 1497 1497 + 0xff000000, 0xb97af807, 1498 1498 + 0x877bff7a, 0x02000000, 1499 1499 + 0x8f7b867b, 0x88777b77, 1500 1500 + 0x877bff7a, 0x003f8000, 1501 1501 + 0x8f7b897b, 0x88777b77, 1502 1502 + 0x8a7aff7a, 0x023f8000, 1503 1503 + 0xb9faf807, 0xbeee037e, 1504 1504 + 0xbeef037f, 0xbefe0480, 1505 1505 + 0xbf900004, 0xbf8e0002, 1506 1506 + 0xbf88fffe, 0x877aff7f, 1507 1507 + 0x04000000, 0x8f7a857a, 1508 1508 + 0x886d7a6d, 0xb97b02dc, 1509 1509 + 0x8f7b997b, 0xb97a2a05, 1510 1510 + 0x807a817a, 0xbf0d997b, 1511 1511 + 0xbf850002, 0x8f7a897a, 1512 1512 + 0xbf820001, 0x8f7a8a7a, 1513 1513 + 0xb97b1e06, 0x8f7b8a7b, 1514 1514 + 0x807a7b7a, 0x877bff7f, 1515 1515 + 0x0000ffff, 0x807aff7a, 1516 1516 + 0x00000200, 0x807a7e7a, 1517 1517 + 0x827b807b, 0xf4491c3d, 1518 1518 + 0xfa000050, 0xf4491d3d, 1519 1519 + 0xfa000060, 0xf4411e7d, 1520 1520 + 0xfa000074, 0xbef4037e, 1521 1521 + 0x8775ff7f, 0x0000ffff, 1522 1522 + 0x8875ff75, 0x00040000, 1523 1523 + 0xbef60380, 0xbef703ff, 1524 1524 + 0x10807fac, 0xbef1037c, 1525 1525 + 0xbef00380, 0xb97302dc, 1526 1526 + 0x8f739973, 0xb97bf816, 1527 1527 + 0xba80f816, 0x00000000, 1528 1528 + 0xbefe03c1, 0x907c9973, 1529 1529 + 0x877c817c, 0xbf06817c, 1530 1530 + 0xbf850002, 0xbeff0380, 1531 1531 + 0xbf820002, 0xbeff03c1, 1532 1532 + 0xbf82000b, 0xbef603ff, 1533 1533 + 0x01000000, 0xe0704000, 1534 1534 + 0x705d0000, 0xe0704080, 1535 1535 + 0x705d0100, 0xe0704100, 1536 1536 + 0x705d0200, 0xe0704180, 1537 1537 + 0x705d0300, 0xbf82000a, 1538 1538 + 0xbef603ff, 0x01000000, 1539 1539 + 0xe0704000, 0x705d0000, 1540 1540 + 0xe0704100, 0x705d0100, 1541 1541 + 0xe0704200, 0x705d0200, 1542 1542 + 0xe0704300, 0x705d0300, 1543 1543 + 0xb9703a05, 0x80708170, 1544 1544 + 0xbf0d9973, 0xbf850002, 1545 1545 + 0x8f708970, 0xbf820001, 1546 1546 + 0x8f708a70, 0xb97a1e06, 1547 1547 + 0x8f7a8a7a, 0x80707a70, 1548 1548 + 0x8070ff70, 0x00000200, 1549 1549 + 0xbef603ff, 0x01000000, 1550 1550 + 0xbefe037c, 0xbefc0370, 1551 1551 + 0xf4611c7a, 0xf8000000, 1552 1552 + 0x80708470, 0xbefc037e, 1553 1553 + 0xbefe037c, 0xbefc0370, 1554 1554 + 0xf4611b3a, 0xf8000000, 1555 1555 + 0x80708470, 0xbefc037e, 1556 1556 + 0x8a7aff6d, 0x80000000, 1557 1557 + 0xbefe037c, 0xbefc0370, 1558 1558 + 0xf4611eba, 0xf8000000, 1559 1559 + 0x80708470, 0xbefc037e, 1560 1560 + 0xbefe037c, 0xbefc0370, 1561 1561 + 0xf4611bba, 0xf8000000, 1562 1562 + 0x80708470, 0xbefc037e, 1563 1563 + 0xbefe037c, 0xbefc0370, 1564 1564 + 0xf4611bfa, 0xf8000000, 1565 1565 + 0x80708470, 0xbefc037e, 1566 1566 + 0xbefe037c, 0xbefc0370, 1567 1567 + 0xf4611e3a, 0xf8000000, 1568 1568 + 0x80708470, 0xbefc037e, 1569 1569 + 0xb97af803, 0xbefe037c, 1570 1570 + 0xbefc0370, 0xf4611eba, 1571 1571 + 0xf8000000, 0x80708470, 1572 1572 + 0xbefc037e, 0xbefe037c, 1573 1573 + 0xbefc0370, 0xf4611efa, 1574 1574 + 0xf8000000, 0x80708470, 1575 1575 + 0xbefc037e, 0xb971f801, 1576 1576 + 0xbefe037c, 0xbefc0370, 1577 1577 + 0xf4611c7a, 0xf8000000, 1578 1578 + 0x80708470, 0xbefc037e, 1579 1579 + 0xb971f814, 0xbefe037c, 1580 1580 + 0xbefc0370, 0xf4611c7a, 1581 1581 + 0xf8000000, 0x80708470, 1582 1582 + 0xbefc037e, 0xb971f815, 1583 1583 + 0xbefe037c, 0xbefc0370, 1584 1584 + 0xf4611c7a, 0xf8000000, 1585 1585 + 0x80708470, 0xbefc037e, 1586 1586 + 0xb9702a05, 0x80708170, 1587 1587 + 0xbf0d9973, 0xbf850002, 1588 1588 + 0x8f708970, 0xbf820001, 1589 1589 + 0x8f708a70, 0xb97a1e06, 1590 1590 + 0x8f7a8a7a, 0x80707a70, 1591 1591 + 0xbef603ff, 0x01000000, 1592 1592 + 0xbefb0374, 0x80747074, 1593 1593 + 0x82758075, 0xbefc0380, 1594 1594 + 0xbf800000, 0xbe802f00, 1595 1595 + 0xbe822f02, 0xbe842f04, 1596 1596 + 0xbe862f06, 0xbe882f08, 1597 1597 + 0xbe8a2f0a, 0xbe8c2f0c, 1598 1598 + 0xbe8e2f0e, 0xf469003a, 1599 1599 + 0xfa000000, 0xf469013a, 1600 1600 + 0xfa000010, 0xf469023a, 1601 1601 + 0xfa000020, 0xf469033a, 1602 1602 + 0xfa000030, 0x8074c074, 1603 1603 + 0x82758075, 0x807c907c, 1604 1604 + 0xbf0aff7c, 0x00000060, 1605 1605 + 0xbf85ffea, 0xbe802f00, 1606 1606 + 0xbe822f02, 0xbe842f04, 1607 1607 + 0xbe862f06, 0xbe882f08, 1608 1608 + 0xbe8a2f0a, 0xf469003a, 1609 1609 + 0xfa000000, 0xf469013a, 1610 1610 + 0xfa000010, 0xf469023a, 1611 1611 + 0xfa000020, 0x8074b074, 1612 1612 + 0x82758075, 0xbef4037b, 1613 1613 + 0xbefe03c1, 0x907c9973, 1614 1614 + 0x877c817c, 0xbf06817c, 1615 1615 + 0xbf850002, 0xbeff0380, 1616 1616 + 0xbf820001, 0xbeff03c1, 1617 1617 + 0xb97b4306, 0x877bc17b, 1618 1618 + 0xbf840044, 0xbf8a0000, 1619 1619 + 0x877aff6d, 0x80000000, 1620 1620 + 0xbf840040, 0x8f7b867b, 1621 1621 + 0x8f7b827b, 0xbef6037b, 1622 1622 + 0xb9703a05, 0x80708170, 1623 1623 + 0xbf0d9973, 0xbf850002, 1624 1624 + 0x8f708970, 0xbf820001, 1625 1625 + 0x8f708a70, 0xb97a1e06, 1626 1626 + 0x8f7a8a7a, 0x80707a70, 1627 1627 + 0x8070ff70, 0x00000200, 1628 1628 + 0x8070ff70, 0x00000080, 1629 1629 + 0xbef603ff, 0x01000000, 1630 1630 + 0xd7650000, 0x000100c1, 1631 1631 + 0xd7660000, 0x000200c1, 1632 1632 + 0x16000084, 0x907c9973, 1633 1633 + 0x877c817c, 0xbf06817c, 1634 1634 + 0xbefc0380, 0xbf850012, 1635 1635 + 0xbe8303ff, 0x00000080, 1636 1636 + 0xbf800000, 0xbf800000, 1637 1637 + 0xbf800000, 0xd8d80000, 1638 1638 + 0x01000000, 0xbf8c0000, 1639 1639 + 0xe0704000, 0x705d0100, 1640 1640 + 0x807c037c, 0x80700370, 1641 1641 + 0xd5250000, 0x0001ff00, 1642 1642 + 0x00000080, 0xbf0a7b7c, 1643 1643 + 0xbf85fff4, 0xbf820011, 1644 1644 + 0xbe8303ff, 0x00000100, 1645 1645 + 0xbf800000, 0xbf800000, 1646 1646 + 0xbf800000, 0xd8d80000, 1647 1647 + 0x01000000, 0xbf8c0000, 1648 1648 + 0xe0704000, 0x705d0100, 1649 1649 + 0x807c037c, 0x80700370, 1650 1650 + 0xd5250000, 0x0001ff00, 1651 1651 + 0x00000100, 0xbf0a7b7c, 1652 1652 + 0xbf85fff4, 0xbefe03c1, 1653 1653 + 0x907c9973, 0x877c817c, 1654 1654 + 0xbf06817c, 0xbf850004, 1655 1655 + 0xbef003ff, 0x00000200, 1656 1656 + 0xbeff0380, 0xbf820003, 1657 1657 + 0xbef003ff, 0x00000400, 1658 1658 + 0xbeff03c1, 0xb97b3a05, 1659 1659 + 0x807b817b, 0x8f7b827b, 1660 1660 + 0x907c9973, 0x877c817c, 1661 1661 + 0xbf06817c, 0xbf850017, 1662 1662 + 0xbef603ff, 0x01000000, 1663 1663 + 0xbefc0384, 0xbf0a7b7c, 1664 1664 + 0xbf840037, 0x7e008700, 1665 1665 + 0x7e028701, 0x7e048702, 1666 1666 + 0x7e068703, 0xe0704000, 1667 1667 + 0x705d0000, 0xe0704080, 1668 1668 + 0x705d0100, 0xe0704100, 1669 1669 + 0x705d0200, 0xe0704180, 1670 1670 + 0x705d0300, 0x807c847c, 1671 1671 + 0x8070ff70, 0x00000200, 1672 1672 + 0xbf0a7b7c, 0xbf85ffef, 1673 1673 + 0xbf820025, 0xbef603ff, 1674 1674 + 0x01000000, 0xbefc0384, 1675 1675 + 0xbf0a7b7c, 0xbf840011, 1676 1676 + 0x7e008700, 0x7e028701, 1677 1677 + 0x7e048702, 0x7e068703, 1678 1678 + 0xe0704000, 0x705d0000, 1679 1679 + 0xe0704100, 0x705d0100, 1680 1680 + 0xe0704200, 0x705d0200, 1681 1681 + 0xe0704300, 0x705d0300, 1682 1682 + 0x807c847c, 0x8070ff70, 1683 1683 + 0x00000400, 0xbf0a7b7c, 1684 1684 + 0xbf85ffef, 0xb97b1e06, 1685 1685 + 0x877bc17b, 0xbf84000c, 1686 1686 + 0x8f7b837b, 0x807b7c7b, 1687 1687 + 0xbefe03c1, 0xbeff0380, 1688 1688 + 0x7e008700, 0xe0704000, 1689 1689 + 0x705d0000, 0x807c817c, 1690 1690 + 0x8070ff70, 0x00000080, 1691 1691 + 0xbf0a7b7c, 0xbf85fff8, 1692 1692 + 0xbf820144, 0xbef4037e, 1693 1693 + 0x8775ff7f, 0x0000ffff, 1694 1694 + 0x8875ff75, 0x00040000, 1695 1695 + 0xbef60380, 0xbef703ff, 1696 1696 + 0x10807fac, 0xb97202dc, 1697 1697 + 0x8f729972, 0x876eff7f, 1698 1698 + 0x04000000, 0xbf840034, 1699 1699 + 0xbefe03c1, 0x907c9972, 1700 1700 + 0x877c817c, 0xbf06817c, 1701 1701 + 0xbf850002, 0xbeff0380, 1702 1702 + 0xbf820001, 0xbeff03c1, 1703 1703 + 0xb96f4306, 0x876fc16f, 1704 1704 + 0xbf840029, 0x8f6f866f, 1705 1705 + 0x8f6f826f, 0xbef6036f, 1706 1706 + 0xb9783a05, 0x80788178, 1707 1707 + 0xbf0d9972, 0xbf850002, 1708 1708 + 0x8f788978, 0xbf820001, 1709 1709 + 0x8f788a78, 0xb96e1e06, 1710 1710 + 0x8f6e8a6e, 0x80786e78, 1711 1711 + 0x8078ff78, 0x00000200, 1712 1712 + 0x8078ff78, 0x00000080, 1713 1713 + 0xbef603ff, 0x01000000, 1714 1714 + 0x907c9972, 0x877c817c, 1715 1715 + 0xbf06817c, 0xbefc0380, 1716 1716 + 0xbf850009, 0xe0310000, 1717 1717 + 0x781d0000, 0x807cff7c, 1718 1718 + 0x00000080, 0x8078ff78, 1719 1719 + 0x00000080, 0xbf0a6f7c, 1720 1720 + 0xbf85fff8, 0xbf820008, 1721 1721 + 0xe0310000, 0x781d0000, 1722 1722 + 0x807cff7c, 0x00000100, 1723 1723 + 0x8078ff78, 0x00000100, 1724 1724 + 0xbf0a6f7c, 0xbf85fff8, 1725 1725 + 0xbef80380, 0xbefe03c1, 1726 1726 + 0x907c9972, 0x877c817c, 1727 1727 + 0xbf06817c, 0xbf850002, 1728 1728 + 0xbeff0380, 0xbf820001, 1729 1729 + 0xbeff03c1, 0xb96f3a05, 1730 1730 + 0x806f816f, 0x8f6f826f, 1731 1731 + 0x907c9972, 0x877c817c, 1732 1732 + 0xbf06817c, 0xbf850024, 1733 1733 + 0xbef603ff, 0x01000000, 1734 1734 + 0xbeee0378, 0x8078ff78, 1735 1735 + 0x00000200, 0xbefc0384, 1736 1736 + 0xbf0a6f7c, 0xbf840050, 1737 1737 + 0xe0304000, 0x785d0000, 1738 1738 + 0xe0304080, 0x785d0100, 1739 1739 + 0xe0304100, 0x785d0200, 1740 1740 + 0xe0304180, 0x785d0300, 1741 1741 + 0xbf8c3f70, 0x7e008500, 1742 1742 + 0x7e028501, 0x7e048502, 1743 1743 + 0x7e068503, 0x807c847c, 1744 1744 + 0x8078ff78, 0x00000200, 1745 1745 + 0xbf0a6f7c, 0xbf85ffee, 1746 1746 + 0xe0304000, 0x6e5d0000, 1747 1747 + 0xe0304080, 0x6e5d0100, 1748 1748 + 0xe0304100, 0x6e5d0200, 1749 1749 + 0xe0304180, 0x6e5d0300, 1750 1750 + 0xbf8c3f70, 0xbf820034, 1751 1751 + 0xbef603ff, 0x01000000, 1752 1752 + 0xbeee0378, 0x8078ff78, 1753 1753 + 0x00000400, 0xbefc0384, 1754 1754 + 0xbf0a6f7c, 0xbf840012, 1755 1755 + 0xe0304000, 0x785d0000, 1756 1756 + 0xe0304100, 0x785d0100, 1757 1757 + 0xe0304200, 0x785d0200, 1758 1758 + 0xe0304300, 0x785d0300, 1759 1759 + 0xbf8c3f70, 0x7e008500, 1760 1760 + 0x7e028501, 0x7e048502, 1761 1761 + 0x7e068503, 0x807c847c, 1762 1762 + 0x8078ff78, 0x00000400, 1763 1763 + 0xbf0a6f7c, 0xbf85ffee, 1764 1764 + 0xb96f1e06, 0x876fc16f, 1765 1765 + 0xbf84000e, 0x8f6f836f, 1766 1766 + 0x806f7c6f, 0xbefe03c1, 1767 1767 + 0xbeff0380, 0xe0304000, 1768 1768 + 0x785d0000, 0xbf8c3f70, 1769 1769 + 0x7e008500, 0x807c817c, 1770 1770 + 0x8078ff78, 0x00000080, 1771 1771 + 0xbf0a6f7c, 0xbf85fff7, 1772 1772 + 0xbeff03c1, 0xe0304000, 1773 1773 + 0x6e5d0000, 0xe0304100, 1774 1774 + 0x6e5d0100, 0xe0304200, 1775 1775 + 0x6e5d0200, 0xe0304300, 1776 1776 + 0x6e5d0300, 0xbf8c3f70, 1777 1777 + 0xb9783a05, 0x80788178, 1778 1778 + 0xbf0d9972, 0xbf850002, 1779 1779 + 0x8f788978, 0xbf820001, 1780 1780 + 0x8f788a78, 0xb96e1e06, 1781 1781 + 0x8f6e8a6e, 0x80786e78, 1782 1782 + 0x8078ff78, 0x00000200, 1783 1783 + 0x80f8ff78, 0x00000050, 1784 1784 + 0xbef603ff, 0x01000000, 1785 1785 + 0xbefc03ff, 0x0000006c, 1786 1786 + 0x80f89078, 0xf429003a, 1787 1787 + 0xf0000000, 0xbf8cc07f, 1788 1788 + 0x80fc847c, 0xbf800000, 1789 1789 + 0xbe803100, 0xbe823102, 1790 1790 + 0x80f8a078, 0xf42d003a, 1791 1791 + 0xf0000000, 0xbf8cc07f, 1792 1792 + 0x80fc887c, 0xbf800000, 1793 1793 + 0xbe803100, 0xbe823102, 1794 1794 + 0xbe843104, 0xbe863106, 1795 1795 + 0x80f8c078, 0xf431003a, 1796 1796 + 0xf0000000, 0xbf8cc07f, 1797 1797 + 0x80fc907c, 0xbf800000, 1798 1798 + 0xbe803100, 0xbe823102, 1799 1799 + 0xbe843104, 0xbe863106, 1800 1800 + 0xbe883108, 0xbe8a310a, 1801 1801 + 0xbe8c310c, 0xbe8e310e, 1802 1802 + 0xbf06807c, 0xbf84fff0, 1803 1803 + 0xba80f801, 0x00000000, 1804 1804 + 0xbf8a0000, 0xb9783a05, 1805 1805 + 0x80788178, 0xbf0d9972, 1806 1806 + 0xbf850002, 0x8f788978, 1807 1807 + 0xbf820001, 0x8f788a78, 1808 1808 + 0xb96e1e06, 0x8f6e8a6e, 1809 1809 + 0x80786e78, 0x8078ff78, 1810 1810 + 0x00000200, 0xbef603ff, 1811 1811 + 0x01000000, 0xf4211bfa, 1812 1812 + 0xf0000000, 0x80788478, 1813 1813 + 0xf4211b3a, 0xf0000000, 1814 1814 + 0x80788478, 0xf4211b7a, 1815 1815 + 0xf0000000, 0x80788478, 1816 1816 + 0xf4211c3a, 0xf0000000, 1817 1817 + 0x80788478, 0xf4211c7a, 1818 1818 + 0xf0000000, 0x80788478, 1819 1819 + 0xf4211eba, 0xf0000000, 1820 1820 + 0x80788478, 0xf4211efa, 1821 1821 + 0xf0000000, 0x80788478, 1822 1822 + 0xf4211e7a, 0xf0000000, 1823 1823 + 0x80788478, 0xf4211cfa, 1824 1824 + 0xf0000000, 0x80788478, 1825 1825 + 0xf4211bba, 0xf0000000, 1826 1826 + 0x80788478, 0xbf8cc07f, 1827 1827 + 0xb9eef814, 0xf4211bba, 1828 1828 + 0xf0000000, 0x80788478, 1829 1829 + 0xbf8cc07f, 0xb9eef815, 1830 1830 + 0xbefc036f, 0xbefe0370, 1831 1831 + 0xbeff0371, 0x876f7bff, 1832 1832 + 0x000003ff, 0xb9ef4803, 1833 1833 + 0xb9f9f816, 0x876f7bff, 1834 1834 + 0xfffff800, 0x906f8b6f, 1835 1835 + 0xb9efa2c3, 0xb9f3f801, 1836 1836 + 0xb96e2a05, 0x806e816e, 1837 1837 + 0xbf0d9972, 0xbf850002, 1838 1838 + 0x8f6e896e, 0xbf820001, 1839 1839 + 0x8f6e8a6e, 0xb96f1e06, 1840 1840 + 0x8f6f8a6f, 0x806e6f6e, 1841 1841 + 0x806eff6e, 0x00000200, 1842 1842 + 0x806e746e, 0x826f8075, 1843 1843 + 0x876fff6f, 0x0000ffff, 1844 1844 + 0xf4091c37, 0xfa000050, 1845 1845 + 0xf4091d37, 0xfa000060, 1846 1846 + 0xf4011e77, 0xfa000074, 1847 1847 + 0xbf8cc07f, 0x906e8977, 1848 1848 + 0x876fff6e, 0x003f8000, 1849 1849 + 0x906e8677, 0x876eff6e, 1850 1850 + 0x02000000, 0x886e6f6e, 1851 1851 + 0xb9eef807, 0x876dff6d, 1852 1852 + 0x0000ffff, 0x87fe7e7e, 1853 1853 + 0x87ea6a6a, 0xb9faf802, 1854 1854 + 0xbe80226c, 0xbf810000, 1855 1855 + 0xbf9f0000, 0xbf9f0000, 1856 1856 + 0xbf9f0000, 0xbf9f0000, 1857 1857 + 0xbf9f0000, 0x00000000, 1858 1858 + }; 1859 1859 + 1860 1860 + static const uint32_t cwsr_trap_arcturus_hex[] = { 1861 1861 + 0xbf820001, 0xbf8202d0, 1862 1862 + 0xb8f8f802, 0x8978ff78, 1863 1863 + 0x00020006, 0xb8fbf803, 1864 1864 + 0x866eff78, 0x00002000, 1865 1865 + 0xbf840009, 0x866eff6d, 1866 1866 + 0x00ff0000, 0xbf85001e, 1867 1867 + 0x866eff7b, 0x00000400, 1868 1868 + 0xbf850051, 0xbf8e0010, 1869 1869 + 0xb8fbf803, 0xbf82fffa, 1870 1870 + 0x866eff7b, 0x00000900, 1871 1871 + 0xbf850015, 0x866eff7b, 1872 1872 + 0x000071ff, 0xbf840008, 1873 1873 + 0x866fff7b, 0x00007080, 1874 1874 + 0xbf840001, 0xbeee1a87, 1875 1875 + 0xb8eff801, 0x8e6e8c6e, 1876 1876 + 0x866e6f6e, 0xbf85000a, 1877 1877 + 0x866eff6d, 0x00ff0000, 1878 1878 + 0xbf850007, 0xb8eef801, 1879 1879 + 0x866eff6e, 0x00000800, 1880 1880 + 0xbf850003, 0x866eff7b, 1881 1881 + 0x00000400, 0xbf850036, 1882 1882 + 0xb8faf807, 0x867aff7a, 1883 1883 + 0x001f8000, 0x8e7a8b7a, 1884 1884 + 0x8977ff77, 0xfc000000, 1885 1885 + 0x87777a77, 0xba7ff807, 1886 1886 + 0x00000000, 0xb8faf812, 1887 1887 + 0xb8fbf813, 0x8efa887a, 1888 1888 + 0xc0031bbd, 0x00000010, 1889 1889 + 0xbf8cc07f, 0x8e6e976e, 1890 1890 + 0x8977ff77, 0x00800000, 1891 1891 + 0x87776e77, 0xc0071bbd, 1892 1892 + 0x00000000, 0xbf8cc07f, 1893 1893 + 0xc0071ebd, 0x00000008, 1894 1894 + 0xbf8cc07f, 0x86ee6e6e, 1895 1895 + 0xbf840001, 0xbe801d6e, 1896 1896 + 0x866eff6d, 0x01ff0000, 1897 1897 + 0xbf850005, 0x8778ff78, 1898 1898 + 0x00002000, 0x80ec886c, 1899 1899 + 0x82ed806d, 0xbf820005, 1900 1900 + 0x866eff6d, 0x01000000, 1901 1901 + 0xbf850002, 0x806c846c, 1902 1902 + 0x826d806d, 0x866dff6d, 1903 1903 + 0x0000ffff, 0x8f7a8b77, 1904 1904 + 0x867aff7a, 0x001f8000, 1905 1905 + 0xb97af807, 0x86fe7e7e, 1906 1906 + 0x86ea6a6a, 0x8f6e8378, 1907 1907 + 0xb96ee0c2, 0xbf800002, 1908 1908 + 0xb9780002, 0xbe801f6c, 1909 1909 + 0x866dff6d, 0x0000ffff, 1910 1910 + 0xbefa0080, 0xb97a0283, 1911 1911 + 0xb8faf807, 0x867aff7a, 1912 1912 + 0x001f8000, 0x8e7a8b7a, 1913 1913 + 0x8977ff77, 0xfc000000, 1914 1914 + 0x87777a77, 0xba7ff807, 1915 1915 + 0x00000000, 0xbeee007e, 1916 1916 + 0xbeef007f, 0xbefe0180, 1917 1917 + 0xbf900004, 0x877a8478, 1918 1918 + 0xb97af802, 0xbf8e0002, 1919 1919 + 0xbf88fffe, 0xb8fa2a05, 1920 1920 + 0x807a817a, 0x8e7a8a7a, 1921 1921 + 0x8e7a817a, 0xb8fb1605, 1922 1922 + 0x807b817b, 0x8e7b867b, 1923 1923 + 0x807a7b7a, 0x807a7e7a, 1924 1924 + 0x827b807f, 0x867bff7b, 1925 1925 + 0x0000ffff, 0xc04b1c3d, 1926 1926 + 0x00000050, 0xbf8cc07f, 1927 1927 + 0xc04b1d3d, 0x00000060, 1928 1928 + 0xbf8cc07f, 0xc0431e7d, 1929 1929 + 0x00000074, 0xbf8cc07f, 1930 1930 + 0xbef4007e, 0x8675ff7f, 1931 1931 + 0x0000ffff, 0x8775ff75, 1932 1932 + 0x00040000, 0xbef60080, 1933 1933 + 0xbef700ff, 0x00807fac, 1934 1934 + 0xbef1007c, 0xbef00080, 1935 1935 + 0xb8f02a05, 0x80708170, 1936 1936 + 0x8e708a70, 0x8e708170, 1937 1937 + 0xb8fa1605, 0x807a817a, 1938 1938 + 0x8e7a867a, 0x80707a70, 1939 1939 + 0xbef60084, 0xbef600ff, 1940 1940 + 0x01000000, 0xbefe007c, 1941 1941 + 0xbefc0070, 0xc0611c7a, 1942 1942 + 0x0000007c, 0xbf8cc07f, 1943 1943 + 0x80708470, 0xbefc007e, 1944 1944 + 0xbefe007c, 0xbefc0070, 1945 1945 + 0xc0611b3a, 0x0000007c, 1946 1946 + 0xbf8cc07f, 0x80708470, 1947 1947 + 0xbefc007e, 0xbefe007c, 1948 1948 + 0xbefc0070, 0xc0611b7a, 1949 1949 + 0x0000007c, 0xbf8cc07f, 1950 1950 + 0x80708470, 0xbefc007e, 1951 1951 + 0xbefe007c, 0xbefc0070, 1952 1952 + 0xc0611bba, 0x0000007c, 1953 1953 + 0xbf8cc07f, 0x80708470, 1954 1954 + 0xbefc007e, 0xbefe007c, 1955 1955 + 0xbefc0070, 0xc0611bfa, 1956 1956 + 0x0000007c, 0xbf8cc07f, 1957 1957 + 0x80708470, 0xbefc007e, 1958 1958 + 0xbefe007c, 0xbefc0070, 1959 1959 + 0xc0611e3a, 0x0000007c, 1960 1960 + 0xbf8cc07f, 0x80708470, 1961 1961 + 0xbefc007e, 0xb8fbf803, 1962 1962 + 0xbefe007c, 0xbefc0070, 1963 1963 + 0xc0611efa, 0x0000007c, 1964 1964 + 0xbf8cc07f, 0x80708470, 1965 1965 + 0xbefc007e, 0xbefe007c, 1966 1966 + 0xbefc0070, 0xc0611a3a, 1967 1967 + 0x0000007c, 0xbf8cc07f, 1968 1968 + 0x80708470, 0xbefc007e, 1969 1969 + 0xbefe007c, 0xbefc0070, 1970 1970 + 0xc0611a7a, 0x0000007c, 1971 1971 + 0xbf8cc07f, 0x80708470, 1972 1972 + 0xbefc007e, 0xb8f1f801, 1973 1973 + 0xbefe007c, 0xbefc0070, 1974 1974 + 0xc0611c7a, 0x0000007c, 1975 1975 + 0xbf8cc07f, 0x80708470, 1976 1976 + 0xbefc007e, 0x867aff7f, 1977 1977 + 0x04000000, 0xbeef0080, 1978 1978 + 0x876f6f7a, 0xb8f02a05, 1979 1979 + 0x80708170, 0x8e708a70, 1980 1980 + 0x8e708170, 0xb8fb1605, 1981 1981 + 0x807b817b, 0x8e7b847b, 1982 1982 + 0x8e76827b, 0xbef600ff, 1983 1983 + 0x01000000, 0xbef20174, 1984 1984 + 0x80747074, 0x82758075, 1985 1985 + 0xbefc0080, 0xbf800000, 1986 1986 + 0xbe802b00, 0xbe822b02, 1987 1987 + 0xbe842b04, 0xbe862b06, 1988 1988 + 0xbe882b08, 0xbe8a2b0a, 1989 1989 + 0xbe8c2b0c, 0xbe8e2b0e, 1990 1990 + 0xc06b003a, 0x00000000, 1991 1991 + 0xbf8cc07f, 0xc06b013a, 1992 1992 + 0x00000010, 0xbf8cc07f, 1993 1993 + 0xc06b023a, 0x00000020, 1994 1994 + 0xbf8cc07f, 0xc06b033a, 1995 1995 + 0x00000030, 0xbf8cc07f, 1996 1996 + 0x8074c074, 0x82758075, 1997 1997 + 0x807c907c, 0xbf0a7b7c, 1998 1998 + 0xbf85ffe7, 0xbef40172, 1999 1999 + 0xbef00080, 0xbefe00c1, 2000 2000 + 0xbeff00c1, 0xbee80080, 2001 2001 + 0xbee90080, 0xbef600ff, 2002 2002 + 0x01000000, 0x867aff78, 2003 2003 + 0x00400000, 0xbf850003, 2004 2004 + 0xb8faf803, 0x897a7aff, 2005 2005 + 0x10000000, 0xbf85004d, 2006 2006 + 0xbe840080, 0xd2890000, 2007 2007 + 0x00000900, 0x80048104, 2008 2008 + 0xd2890001, 0x00000900, 2009 2009 + 0x80048104, 0xd2890002, 2010 2010 + 0x00000900, 0x80048104, 2011 2011 + 0xd2890003, 0x00000900, 2012 2012 + 0x80048104, 0xc069003a, 2013 2013 + 0x00000070, 0xbf8cc07f, 2014 2014 + 0x80709070, 0xbf06c004, 2015 2015 + 0xbf84ffee, 0xbe840080, 2016 2016 + 0xd2890000, 0x00000901, 2017 2017 + 0x80048104, 0xd2890001, 2018 2018 + 0x00000901, 0x80048104, 2019 2019 + 0xd2890002, 0x00000901, 2020 2020 + 0x80048104, 0xd2890003, 2021 2021 + 0x00000901, 0x80048104, 2022 2022 + 0xc069003a, 0x00000070, 2023 2023 + 0xbf8cc07f, 0x80709070, 2024 2024 + 0xbf06c004, 0xbf84ffee, 2025 2025 + 0xbe840080, 0xd2890000, 2026 2026 + 0x00000902, 0x80048104, 2027 2027 + 0xd2890001, 0x00000902, 2028 2028 + 0x80048104, 0xd2890002, 2029 2029 + 0x00000902, 0x80048104, 2030 2030 + 0xd2890003, 0x00000902, 2031 2031 + 0x80048104, 0xc069003a, 2032 2032 + 0x00000070, 0xbf8cc07f, 2033 2033 + 0x80709070, 0xbf06c004, 2034 2034 + 0xbf84ffee, 0xbe840080, 2035 2035 + 0xd2890000, 0x00000903, 2036 2036 + 0x80048104, 0xd2890001, 2037 2037 + 0x00000903, 0x80048104, 2038 2038 + 0xd2890002, 0x00000903, 2039 2039 + 0x80048104, 0xd2890003, 2040 2040 + 0x00000903, 0x80048104, 2041 2041 + 0xc069003a, 0x00000070, 2042 2042 + 0xbf8cc07f, 0x80709070, 2043 2043 + 0xbf06c004, 0xbf84ffee, 2044 2044 + 0xbf820008, 0xe0724000, 2045 2045 + 0x701d0000, 0xe0724100, 2046 2046 + 0x701d0100, 0xe0724200, 2047 2047 + 0x701d0200, 0xe0724300, 2048 2048 + 0x701d0300, 0xbefe00c1, 2049 2049 + 0xbeff00c1, 0xb8fb4306, 2050 2050 + 0x867bc17b, 0xbf840064, 2051 2051 + 0xbf8a0000, 0x867aff6f, 2052 2052 + 0x04000000, 0xbf840060, 2053 2053 + 0x8e7b867b, 0x8e7b827b, 2054 2054 + 0xbef6007b, 0xb8f02a05, 2055 2055 + 0x80708170, 0x8e708a70, 2056 2056 + 0x8e708170, 0xb8fa1605, 2057 2057 + 0x807a817a, 0x8e7a867a, 2058 2058 + 0x80707a70, 0x8070ff70, 2059 2059 + 0x00000080, 0xbef600ff, 2060 2060 + 0x01000000, 0xbefc0080, 2061 2061 + 0xd28c0002, 0x000100c1, 2062 2062 + 0xd28d0003, 0x000204c1, 2063 2063 + 0x867aff78, 0x00400000, 2064 2064 + 0xbf850003, 0xb8faf803, 2065 2065 + 0x897a7aff, 0x10000000, 2066 2066 + 0xbf850030, 0x24040682, 2067 2067 + 0xd86e4000, 0x00000002, 2068 2068 + 0xbf8cc07f, 0xbe840080, 2069 2069 + 0xd2890000, 0x00000900, 2070 2070 + 0x80048104, 0xd2890001, 2071 2071 + 0x00000900, 0x80048104, 2072 2072 + 0xd2890002, 0x00000900, 2073 2073 + 0x80048104, 0xd2890003, 2074 2074 + 0x00000900, 0x80048104, 2075 2075 + 0xc069003a, 0x00000070, 2076 2076 + 0xbf8cc07f, 0x80709070, 2077 2077 + 0xbf06c004, 0xbf84ffee, 2078 2078 + 0xbe840080, 0xd2890000, 2079 2079 + 0x00000901, 0x80048104, 2080 2080 + 0xd2890001, 0x00000901, 2081 2081 + 0x80048104, 0xd2890002, 2082 2082 + 0x00000901, 0x80048104, 2083 2083 + 0xd2890003, 0x00000901, 2084 2084 + 0x80048104, 0xc069003a, 2085 2085 + 0x00000070, 0xbf8cc07f, 2086 2086 + 0x80709070, 0xbf06c004, 2087 2087 + 0xbf84ffee, 0x680404ff, 2088 2088 + 0x00000200, 0xd0c9006a, 2089 2089 + 0x0000f702, 0xbf87ffd2, 2090 2090 + 0xbf820015, 0xd1060002, 2091 2091 + 0x00011103, 0x7e0602ff, 2092 2092 + 0x00000200, 0xbefc00ff, 2093 2093 + 0x00010000, 0xbe800077, 2094 2094 + 0x8677ff77, 0xff7fffff, 2095 2095 + 0x8777ff77, 0x00058000, 2096 2096 + 0xd8ec0000, 0x00000002, 2097 2097 + 0xbf8cc07f, 0xe0765000, 2098 2098 + 0x701d0002, 0x68040702, 546 2099 0xd0c9006a, 0x0000f702, 547 547 - 0xbf87ffd2, 0xbf820015, 548 548 - 0xd1060002, 0x00011103, 549 549 - 0x7e0602ff, 0x00000200, 550 550 - 0xbefc00ff, 0x00010000, 551 551 - 0xbe800077, 0x8677ff77, 552 552 - 0xff7fffff, 0x8777ff77, 553 553 - 0x00058000, 0xd8ec0000, 554 554 - 0x00000002, 0xbf8cc07f, 555 555 - 0xe0765000, 0x701d0002, 556 556 - 0x68040702, 0xd0c9006a, 557 557 - 0x0000f702, 0xbf87fff7, 558 558 - 0xbef70000, 0xbef000ff, 559 559 - 0x00000400, 0xbefe00c1, 560 560 - 0xbeff00c1, 0xb8fb2a05, 561 561 - 0x807b817b, 0x8e7b827b, 562 562 - 0x8e76887b, 0xbef600ff, 2100 2100 + 0xbf87fff7, 0xbef70000, 2101 2101 + 0xbef000ff, 0x00000400, 2102 2102 + 0xbefe00c1, 0xbeff00c1, 2103 2103 + 0xb8fb2a05, 0x807b817b, 2104 2104 + 0x8e7b827b, 0xbef600ff, 563 2105 0x01000000, 0xbefc0084, 564 2106 0xbf0a7b7c, 0xbf84006d, 565 2107 0xbf11017c, 0x807bff7b, ··· 1454 1440 0x701d0300, 0x807c847c, 1455 1441 0x8070ff70, 0x00000400, 1456 1442 0xbf0a7b7c, 0xbf85ffeb, 1457 1457 - 0xbf9c0000, 0xbf820106, 1443 1443 + 0xbf9c0000, 0xbf8200e3, 1458 1444 0xbef4007e, 0x8675ff7f, 1459 1445 0x0000ffff, 0x8775ff75, 1460 1446 0x00040000, 0xbef60080, 1461 1447 0xbef700ff, 0x00807fac, 1462 1462 - 0x866eff7f, 0x08000000, 1463 1463 - 0x8f6e836e, 0x87776e77, 1464 1464 - 0x866eff7f, 0x70000000, 1465 1465 - 0x8f6e816e, 0x87776e77, 1466 1448 0x866eff7f, 0x04000000, 1467 1449 0xbf84001f, 0xbefe00c1, 1468 1450 0xbeff00c1, 0xb8ef4306, ··· 1476 1466 0x807cff7c, 0x00000200, 1477 1467 0x8078ff78, 0x00000200, 1478 1468 0xbf0a6f7c, 0xbf85fff6, 1479 1479 - 0xbef80080, 0xbefe00c1, 1480 1480 - 0xbeff00c1, 0xb8ef2a05, 1481 1481 - 0x806f816f, 0x8e6f826f, 1482 1482 - 0x8e76886f, 0xbef90076, 1469 1469 + 0xbefe00c1, 0xbeff00c1, 1483 1470 0xbef600ff, 0x01000000, 1471 1471 + 0xb8ef2a05, 0x806f816f, 1472 1472 + 0x8e6f826f, 0x806fff6f, 1473 1473 + 0x00008000, 0xbef80080, 1484 1474 0xbeee0078, 0x8078ff78, 1485 1485 - 0x00000400, 0xbef30079, 1486 1486 - 0x8079ff79, 0x00000400, 1487 1487 - 0xbefc0084, 0xbf11087c, 1488 1488 - 0x806fff6f, 0x00008000, 1489 1489 - 0xe0524000, 0x791d0000, 1490 1490 - 0xe0524100, 0x791d0100, 1491 1491 - 0xe0524200, 0x791d0200, 1492 1492 - 0xe0524300, 0x791d0300, 1493 1493 - 0x8079ff79, 0x00000400, 1494 1494 - 0xbf8c0f70, 0xd3d94000, 1495 1495 - 0x18000100, 0xd3d94001, 1496 1496 - 0x18000101, 0xd3d94002, 1497 1497 - 0x18000102, 0xd3d94003, 1498 1498 - 0x18000103, 0xe0524000, 1475 1475 + 0x00000400, 0xbefc0084, 1476 1476 + 0xbf11087c, 0xe0524000, 1499 1477 0x781d0000, 0xe0524100, 1500 1478 0x781d0100, 0xe0524200, 1501 1479 0x781d0200, 0xe0524300, ··· 1492 1494 0x7e040302, 0x7e060303, 1493 1495 0x807c847c, 0x8078ff78, 1494 1496 0x00000400, 0xbf0a6f7c, 1495 1495 - 0xbf85ffdb, 0xbf9c0000, 1496 1496 - 0xe0524000, 0x731d0000, 1497 1497 - 0xe0524100, 0x731d0100, 1498 1498 - 0xe0524200, 0x731d0200, 1499 1499 - 0xe0524300, 0x731d0300, 1500 1500 - 0xbf8c0f70, 0xd3d94000, 1501 1501 - 0x18000100, 0xd3d94001, 1502 1502 - 0x18000101, 0xd3d94002, 1503 1503 - 0x18000102, 0xd3d94003, 1504 1504 - 0x18000103, 0xe0524000, 1505 1505 - 0x6e1d0000, 0xe0524100, 1506 1506 - 0x6e1d0100, 0xe0524200, 1507 1507 - 0x6e1d0200, 0xe0524300, 1508 1508 - 0x6e1d0300, 0xb8f82a05, 1497 1497 + 0xbf85ffee, 0xbefc0080, 1498 1498 + 0xbf11087c, 0xe0524000, 1499 1499 + 0x781d0000, 0xe0524100, 1500 1500 + 0x781d0100, 0xe0524200, 1501 1501 + 0x781d0200, 0xe0524300, 1502 1502 + 0x781d0300, 0xbf8c0f70, 1503 1503 + 0xd3d94000, 0x18000100, 1504 1504 + 0xd3d94001, 0x18000101, 1505 1505 + 0xd3d94002, 0x18000102, 1506 1506 + 0xd3d94003, 0x18000103, 1507 1507 + 0x807c847c, 0x8078ff78, 1508 1508 + 0x00000400, 0xbf0a6f7c, 1509 1509 + 0xbf85ffea, 0xbf9c0000, 1510 1510 + 0xe0524000, 0x6e1d0000, 1511 1511 + 0xe0524100, 0x6e1d0100, 1512 1512 + 0xe0524200, 0x6e1d0200, 1513 1513 + 0xe0524300, 0x6e1d0300, 1514 1514 + 0xbf8c0f70, 0xb8f82a05, 1509 1515 0x80788178, 0x8e788a78, 1510 1516 0x8e788178, 0xb8ee1605, 1511 1517 0x806e816e, 0x8e6e866e, ··· 1561 1559 0xc00b1c37, 0x00000050, 1562 1560 0xc00b1d37, 0x00000060, 1563 1561 0xc0031e77, 0x00000074, 1564 1564 - 0xbf8cc07f, 0x866fff6d, 1565 1565 - 0xf8000000, 0x8f6f9b6f, 1566 1566 - 0x8e6f906f, 0xbeee0080, 1567 1567 - 0x876e6f6e, 0x866fff6d, 1568 1568 - 0x04000000, 0x8f6f9a6f, 1569 1569 - 0x8e6f8f6f, 0x876e6f6e, 1570 1570 - 0x866fff7a, 0x00800000, 1571 1571 - 0x8f6f976f, 0xb96ef807, 1572 1572 - 0x866dff6d, 0x0000ffff, 1573 1573 - 0x86fe7e7e, 0x86ea6a6a, 1574 1574 - 0x8f6e837a, 0xb96ee0c2, 1575 1575 - 0xbf800002, 0xb97a0002, 1576 1576 - 0xbf8a0000, 0x95806f6c, 1577 1577 - 0xbf810000, 0x00000000, 1562 1562 + 0xbf8cc07f, 0x8f6e8b77, 1563 1563 + 0x866eff6e, 0x001f8000, 1564 1564 + 0xb96ef807, 0x866dff6d, 1565 1565 + 0x0000ffff, 0x86fe7e7e, 1566 1566 + 0x86ea6a6a, 0x8f6e837a, 1567 1567 + 0xb96ee0c2, 0xbf800002, 1568 1568 + 0xb97a0002, 0xbf8a0000, 1569 1569 + 0xbe801f6c, 0xbf810000, 1578 1570 }; 1579 1571 1580 1572 static const uint32_t cwsr_trap_aldebaran_hex[] = { 1581 1581 - 0xbf820001, 0xbf8202ce, 1582 1582 - 0xb8f8f802, 0x89788678, 1583 1583 - 0xb8eef801, 0x866eff6e, 1584 1584 - 0x00000800, 0xbf840003, 1573 1573 + 0xbf820001, 0xbf8202db, 1574 1574 + 0xb8f8f802, 0x8978ff78, 1575 1575 + 0x00020006, 0xb8fbf803, 1585 1576 0x866eff78, 0x00002000, 1586 1586 - 0xbf840016, 0xb8fbf803, 1577 1577 + 0xbf840009, 0x866eff6d, 1578 1578 + 0x00ff0000, 0xbf85001e, 1587 1579 0x866eff7b, 0x00000400, 1588 1588 - 0xbf85003b, 0x866eff7b, 1589 1589 - 0x00000800, 0xbf850003, 1590 1590 - 0x866eff7b, 0x00000100, 1591 1591 - 0xbf84000c, 0x866eff78, 1592 1592 - 0x00002000, 0xbf840005, 1593 1593 - 0xbf8e0010, 0xb8eef803, 1594 1594 - 0x866eff6e, 0x00000400, 1595 1595 - 0xbf84fffb, 0x8778ff78, 1596 1596 - 0x00002000, 0x80ec886c, 1597 1597 - 0x82ed806d, 0xb8eef807, 1598 1598 - 0x866fff6e, 0x001f8000, 1599 1599 - 0x8e6f8b6f, 0x8977ff77, 1600 1600 - 0xfc000000, 0x87776f77, 1601 1601 - 0x896eff6e, 0x001f8000, 1602 1602 - 0xb96ef807, 0xb8faf812, 1580 1580 + 0xbf850051, 0xbf8e0010, 1581 1581 + 0xb8fbf803, 0xbf82fffa, 1582 1582 + 0x866eff7b, 0x00000900, 1583 1583 + 0xbf850015, 0x866eff7b, 1584 1584 + 0x000071ff, 0xbf840008, 1585 1585 + 0x866fff7b, 0x00007080, 1586 1586 + 0xbf840001, 0xbeee1a87, 1587 1587 + 0xb8eff801, 0x8e6e8c6e, 1588 1588 + 0x866e6f6e, 0xbf85000a, 1589 1589 + 0x866eff6d, 0x00ff0000, 1590 1590 + 0xbf850007, 0xb8eef801, 1591 1591 + 0x866eff6e, 0x00000800, 1592 1592 + 0xbf850003, 0x866eff7b, 1593 1593 + 0x00000400, 0xbf850036, 1594 1594 + 0xb8faf807, 0x867aff7a, 1595 1595 + 0x001f8000, 0x8e7a8b7a, 1596 1596 + 0x8977ff77, 0xfc000000, 1597 1597 + 0x87777a77, 0xba7ff807, 1598 1598 + 0x00000000, 0xb8faf812, 1603 1599 0xb8fbf813, 0x8efa887a, 1604 1604 - 0xc0071bbd, 0x00000000, 1605 1605 - 0xbf8cc07f, 0xc0071ebd, 1606 1606 - 0x00000008, 0xbf8cc07f, 1607 1607 - 0x86ee6e6e, 0xbf840001, 1608 1608 - 0xbe801d6e, 0xb8fbf803, 1609 1609 - 0x867bff7b, 0x000001ff, 1600 1600 + 0xc0031bbd, 0x00000010, 1601 1601 + 0xbf8cc07f, 0x8e6e976e, 1602 1602 + 0x8977ff77, 0x00800000, 1603 1603 + 0x87776e77, 0xc0071bbd, 1604 1604 + 0x00000000, 0xbf8cc07f, 1605 1605 + 0xc0071ebd, 0x00000008, 1606 1606 + 0xbf8cc07f, 0x86ee6e6e, 1607 1607 + 0xbf840001, 0xbe801d6e, 1608 1608 + 0x866eff6d, 0x01ff0000, 1609 1609 + 0xbf850005, 0x8778ff78, 1610 1610 + 0x00002000, 0x80ec886c, 1611 1611 + 0x82ed806d, 0xbf820005, 1612 1612 + 0x866eff6d, 0x01000000, 1610 1613 0xbf850002, 0x806c846c, 1611 1614 0x826d806d, 0x866dff6d, 1612 1612 - 0x0000ffff, 0x8f6e8b77, 1613 1613 - 0x866eff6e, 0x001f8000, 1614 1614 - 0xb96ef807, 0x86fe7e7e, 1615 1615 + 0x0000ffff, 0x8f7a8b77, 1616 1616 + 0x867aff7a, 0x001f8000, 1617 1617 + 0xb97af807, 0x86fe7e7e, 1615 1618 0x86ea6a6a, 0x8f6e8378, 1616 1619 0xb96ee0c2, 0xbf800002, 1617 1620 0xb9780002, 0xbe801f6c, 1618 1621 0x866dff6d, 0x0000ffff, 1619 1622 0xbefa0080, 0xb97a0283, 1620 1620 - 0xb8fa2407, 0x8e7a9b7a, 1621 1621 - 0x876d7a6d, 0xb8fa03c7, 1622 1622 - 0x8e7a9a7a, 0x876d7a6d, 1623 1623 0xb8faf807, 0x867aff7a, 1624 1624 - 0x00007fff, 0xb97af807, 1625 1625 - 0xbeee007e, 0xbeef007f, 1626 1626 - 0xbefe0180, 0xbf900004, 1627 1627 - 0x877a8478, 0xb97af802, 1628 1628 - 0xbf8e0002, 0xbf88fffe, 1629 1629 - 0xb8fa2985, 0x807a817a, 1630 1630 - 0x8e7a8a7a, 0x8e7a817a, 1631 1631 - 0xb8fb1605, 0x807b817b, 1632 1632 - 0x8e7b867b, 0x807a7b7a, 1633 1633 - 0x807a7e7a, 0x827b807f, 1634 1634 - 0x867bff7b, 0x0000ffff, 1635 1635 - 0xc04b1c3d, 0x00000050, 1636 1636 - 0xbf8cc07f, 0xc04b1d3d, 1637 1637 - 0x00000060, 0xbf8cc07f, 1638 1638 - 0xc0431e7d, 0x00000074, 1639 1639 - 0xbf8cc07f, 0xbef4007e, 1640 1640 - 0x8675ff7f, 0x0000ffff, 1641 1641 - 0x8775ff75, 0x00040000, 1642 1642 - 0xbef60080, 0xbef700ff, 1643 1643 - 0x00807fac, 0x867aff7f, 1644 1644 - 0x08000000, 0x8f7a837a, 1645 1645 - 0x87777a77, 0x867aff7f, 1646 1646 - 0x70000000, 0x8f7a817a, 1647 1647 - 0x87777a77, 0xbef1007c, 1648 1648 - 0xbef00080, 0xb8f02985, 1649 1649 - 0x80708170, 0x8e708a70, 1650 1650 - 0x8e708170, 0xb8fa1605, 1651 1651 - 0x807a817a, 0x8e7a867a, 1652 1652 - 0x80707a70, 0xbef60084, 1653 1653 - 0xbef600ff, 0x01000000, 1654 1654 - 0xbefe007c, 0xbefc0070, 1655 1655 - 0xc0611c7a, 0x0000007c, 1656 1656 - 0xbf8cc07f, 0x80708470, 1657 1657 - 0xbefc007e, 0xbefe007c, 1658 1658 - 0xbefc0070, 0xc0611b3a, 1659 1659 - 0x0000007c, 0xbf8cc07f, 1660 1660 - 0x80708470, 0xbefc007e, 1661 1661 - 0xbefe007c, 0xbefc0070, 1662 1662 - 0xc0611b7a, 0x0000007c, 1663 1663 - 0xbf8cc07f, 0x80708470, 1664 1664 - 0xbefc007e, 0xbefe007c, 1665 1665 - 0xbefc0070, 0xc0611bba, 1666 1666 - 0x0000007c, 0xbf8cc07f, 1667 1667 - 0x80708470, 0xbefc007e, 1668 1668 - 0xbefe007c, 0xbefc0070, 1669 1669 - 0xc0611bfa, 0x0000007c, 1670 1670 - 0xbf8cc07f, 0x80708470, 1671 1671 - 0xbefc007e, 0xbefe007c, 1672 1672 - 0xbefc0070, 0xc0611e3a, 1673 1673 - 0x0000007c, 0xbf8cc07f, 1674 1674 - 0x80708470, 0xbefc007e, 1675 1675 - 0xb8fbf803, 0xbefe007c, 1676 1676 - 0xbefc0070, 0xc0611efa, 1677 1677 - 0x0000007c, 0xbf8cc07f, 1678 1678 - 0x80708470, 0xbefc007e, 1679 1679 - 0xbefe007c, 0xbefc0070, 1680 1680 - 0xc0611a3a, 0x0000007c, 1681 1681 - 0xbf8cc07f, 0x80708470, 1682 1682 - 0xbefc007e, 0xbefe007c, 1683 1683 - 0xbefc0070, 0xc0611a7a, 1684 1684 - 0x0000007c, 0xbf8cc07f, 1685 1685 - 0x80708470, 0xbefc007e, 1686 1686 - 0xb8f1f801, 0xbefe007c, 1687 1687 - 0xbefc0070, 0xc0611c7a, 1688 1688 - 0x0000007c, 0xbf8cc07f, 1689 1689 - 0x80708470, 0xbefc007e, 1690 1690 - 0x867aff7f, 0x04000000, 1691 1691 - 0xbeef0080, 0x876f6f7a, 1692 1692 - 0xb8f02985, 0x80708170, 1693 1693 - 0x8e708a70, 0x8e708170, 1694 1694 - 0xb8fb1605, 0x807b817b, 1695 1695 - 0x8e7b847b, 0x8e76827b, 1696 1696 - 0xbef600ff, 0x01000000, 1697 1697 - 0xbef20174, 0x80747074, 1698 1698 - 0x82758075, 0xbefc0080, 1699 1699 - 0xbf800000, 0xbe802b00, 1700 1700 - 0xbe822b02, 0xbe842b04, 1701 1701 - 0xbe862b06, 0xbe882b08, 1702 1702 - 0xbe8a2b0a, 0xbe8c2b0c, 1703 1703 - 0xbe8e2b0e, 0xc06b003a, 1704 1704 - 0x00000000, 0xbf8cc07f, 1705 1705 - 0xc06b013a, 0x00000010, 1706 1706 - 0xbf8cc07f, 0xc06b023a, 1707 1707 - 0x00000020, 0xbf8cc07f, 1708 1708 - 0xc06b033a, 0x00000030, 1709 1709 - 0xbf8cc07f, 0x8074c074, 1710 1710 - 0x82758075, 0x807c907c, 1711 1711 - 0xbf0a7b7c, 0xbf85ffe7, 1712 1712 - 0xbef40172, 0xbef00080, 1713 1713 - 0xbefe00c1, 0xbeff00c1, 1714 1714 - 0xbee80080, 0xbee90080, 1715 1715 - 0xbef600ff, 0x01000000, 1716 1716 - 0x867aff78, 0x00400000, 1717 1717 - 0xbf850003, 0xb8faf803, 1718 1718 - 0x897a7aff, 0x10000000, 1719 1719 - 0xbf85004d, 0xbe840080, 1720 1720 - 0xd2890000, 0x00000900, 1721 1721 - 0x80048104, 0xd2890001, 1722 1722 - 0x00000900, 0x80048104, 1723 1723 - 0xd2890002, 0x00000900, 1724 1724 - 0x80048104, 0xd2890003, 1725 1725 - 0x00000900, 0x80048104, 1726 1726 - 0xc069003a, 0x00000070, 1727 1727 - 0xbf8cc07f, 0x80709070, 1728 1728 - 0xbf06c004, 0xbf84ffee, 1729 1729 - 0xbe840080, 0xd2890000, 1730 1730 - 0x00000901, 0x80048104, 1731 1731 - 0xd2890001, 0x00000901, 1732 1732 - 0x80048104, 0xd2890002, 1733 1733 - 0x00000901, 0x80048104, 1734 1734 - 0xd2890003, 0x00000901, 1735 1735 - 0x80048104, 0xc069003a, 1736 1736 - 0x00000070, 0xbf8cc07f, 1737 1737 - 0x80709070, 0xbf06c004, 1738 1738 - 0xbf84ffee, 0xbe840080, 1739 1739 - 0xd2890000, 0x00000902, 1740 1740 - 0x80048104, 0xd2890001, 1741 1741 - 0x00000902, 0x80048104, 1742 1742 - 0xd2890002, 0x00000902, 1743 1743 - 0x80048104, 0xd2890003, 1744 1744 - 0x00000902, 0x80048104, 1745 1745 - 0xc069003a, 0x00000070, 1746 1746 - 0xbf8cc07f, 0x80709070, 1747 1747 - 0xbf06c004, 0xbf84ffee, 1748 1748 - 0xbe840080, 0xd2890000, 1749 1749 - 0x00000903, 0x80048104, 1750 1750 - 0xd2890001, 0x00000903, 1751 1751 - 0x80048104, 0xd2890002, 1752 1752 - 0x00000903, 0x80048104, 1753 1753 - 0xd2890003, 0x00000903, 1754 1754 - 0x80048104, 0xc069003a, 1755 1755 - 0x00000070, 0xbf8cc07f, 1756 1756 - 0x80709070, 0xbf06c004, 1757 1757 - 0xbf84ffee, 0xbf820008, 1758 1758 - 0xe0724000, 0x701d0000, 1759 1759 - 0xe0724100, 0x701d0100, 1760 1760 - 0xe0724200, 0x701d0200, 1761 1761 - 0xe0724300, 0x701d0300, 1762 1762 - 0xbefe00c1, 0xbeff00c1, 1763 1763 - 0xb8fb4306, 0x867bc17b, 1764 1764 - 0xbf840064, 0xbf8a0000, 1765 1765 - 0x867aff6f, 0x04000000, 1766 1766 - 0xbf840060, 0x8e7b867b, 1767 1767 - 0x8e7b827b, 0xbef6007b, 1624 1624 + 0x001f8000, 0x8e7a8b7a, 1625 1625 + 0x8977ff77, 0xfc000000, 1626 1626 + 0x87777a77, 0xba7ff807, 1627 1627 + 0x00000000, 0xbeee007e, 1628 1628 + 0xbeef007f, 0xbefe0180, 1629 1629 + 0xbf900004, 0x877a8478, 1630 1630 + 0xb97af802, 0xbf8e0002, 1631 1631 + 0xbf88fffe, 0xb8fa2985, 1632 1632 + 0x807a817a, 0x8e7a8a7a, 1633 1633 + 0x8e7a817a, 0xb8fb1605, 1634 1634 + 0x807b817b, 0x8e7b867b, 1635 1635 + 0x807a7b7a, 0x807a7e7a, 1636 1636 + 0x827b807f, 0x867bff7b, 1637 1637 + 0x0000ffff, 0xc04b1c3d, 1638 1638 + 0x00000050, 0xbf8cc07f, 1639 1639 + 0xc04b1d3d, 0x00000060, 1640 1640 + 0xbf8cc07f, 0xc0431e7d, 1641 1641 + 0x00000074, 0xbf8cc07f, 1642 1642 + 0xbef4007e, 0x8675ff7f, 1643 1643 + 0x0000ffff, 0x8775ff75, 1644 1644 + 0x00040000, 0xbef60080, 1645 1645 + 0xbef700ff, 0x00807fac, 1646 1646 + 0xbef1007c, 0xbef00080, 1768 1647 0xb8f02985, 0x80708170, 1769 1648 0x8e708a70, 0x8e708170, 1770 1649 0xb8fa1605, 0x807a817a, 1771 1650 0x8e7a867a, 0x80707a70, 1772 1772 - 0x8070ff70, 0x00000080, 1773 1773 - 0xbef600ff, 0x01000000, 1774 1774 - 0xbefc0080, 0xd28c0002, 1775 1775 - 0x000100c1, 0xd28d0003, 1776 1776 - 0x000204c1, 0x867aff78, 1651 1651 + 0xbef60084, 0xbef600ff, 1652 1652 + 0x01000000, 0xbefe007c, 1653 1653 + 0xbefc0070, 0xc0611c7a, 1654 1654 + 0x0000007c, 0xbf8cc07f, 1655 1655 + 0x80708470, 0xbefc007e, 1656 1656 + 0xbefe007c, 0xbefc0070, 1657 1657 + 0xc0611b3a, 0x0000007c, 1658 1658 + 0xbf8cc07f, 0x80708470, 1659 1659 + 0xbefc007e, 0xbefe007c, 1660 1660 + 0xbefc0070, 0xc0611b7a, 1661 1661 + 0x0000007c, 0xbf8cc07f, 1662 1662 + 0x80708470, 0xbefc007e, 1663 1663 + 0xbefe007c, 0xbefc0070, 1664 1664 + 0xc0611bba, 0x0000007c, 1665 1665 + 0xbf8cc07f, 0x80708470, 1666 1666 + 0xbefc007e, 0xbefe007c, 1667 1667 + 0xbefc0070, 0xc0611bfa, 1668 1668 + 0x0000007c, 0xbf8cc07f, 1669 1669 + 0x80708470, 0xbefc007e, 1670 1670 + 0xbefe007c, 0xbefc0070, 1671 1671 + 0xc0611e3a, 0x0000007c, 1672 1672 + 0xbf8cc07f, 0x80708470, 1673 1673 + 0xbefc007e, 0xb8fbf803, 1674 1674 + 0xbefe007c, 0xbefc0070, 1675 1675 + 0xc0611efa, 0x0000007c, 1676 1676 + 0xbf8cc07f, 0x80708470, 1677 1677 + 0xbefc007e, 0xbefe007c, 1678 1678 + 0xbefc0070, 0xc0611a3a, 1679 1679 + 0x0000007c, 0xbf8cc07f, 1680 1680 + 0x80708470, 0xbefc007e, 1681 1681 + 0xbefe007c, 0xbefc0070, 1682 1682 + 0xc0611a7a, 0x0000007c, 1683 1683 + 0xbf8cc07f, 0x80708470, 1684 1684 + 0xbefc007e, 0xb8f1f801, 1685 1685 + 0xbefe007c, 0xbefc0070, 1686 1686 + 0xc0611c7a, 0x0000007c, 1687 1687 + 0xbf8cc07f, 0x80708470, 1688 1688 + 0xbefc007e, 0x867aff7f, 1689 1689 + 0x04000000, 0xbeef0080, 1690 1690 + 0x876f6f7a, 0xb8f02985, 1691 1691 + 0x80708170, 0x8e708a70, 1692 1692 + 0x8e708170, 0xb8fb1605, 1693 1693 + 0x807b817b, 0x8e7b847b, 1694 1694 + 0x8e76827b, 0xbef600ff, 1695 1695 + 0x01000000, 0xbef20174, 1696 1696 + 0x80747074, 0x82758075, 1697 1697 + 0xbefc0080, 0xbf800000, 1698 1698 + 0xbe802b00, 0xbe822b02, 1699 1699 + 0xbe842b04, 0xbe862b06, 1700 1700 + 0xbe882b08, 0xbe8a2b0a, 1701 1701 + 0xbe8c2b0c, 0xbe8e2b0e, 1702 1702 + 0xc06b003a, 0x00000000, 1703 1703 + 0xbf8cc07f, 0xc06b013a, 1704 1704 + 0x00000010, 0xbf8cc07f, 1705 1705 + 0xc06b023a, 0x00000020, 1706 1706 + 0xbf8cc07f, 0xc06b033a, 1707 1707 + 0x00000030, 0xbf8cc07f, 1708 1708 + 0x8074c074, 0x82758075, 1709 1709 + 0x807c907c, 0xbf0a7b7c, 1710 1710 + 0xbf85ffe7, 0xbef40172, 1711 1711 + 0xbef00080, 0xbefe00c1, 1712 1712 + 0xbeff00c1, 0xbee80080, 1713 1713 + 0xbee90080, 0xbef600ff, 1714 1714 + 0x01000000, 0x867aff78, 1777 1715 0x00400000, 0xbf850003, 1778 1716 0xb8faf803, 0x897a7aff, 1779 1779 - 0x10000000, 0xbf850030, 1780 1780 - 0x24040682, 0xd86e4000, 1781 1781 - 0x00000002, 0xbf8cc07f, 1717 1717 + 0x10000000, 0xbf85004d, 1782 1718 0xbe840080, 0xd2890000, 1783 1719 0x00000900, 0x80048104, 1784 1720 0xd2890001, 0x00000900, ··· 1736 1796 0xc069003a, 0x00000070, 1737 1797 0xbf8cc07f, 0x80709070, 1738 1798 0xbf06c004, 0xbf84ffee, 1739 1739 - 0x680404ff, 0x00000200, 1740 1740 - 0xd0c9006a, 0x0000f702, 1741 1741 - 0xbf87ffd2, 0xbf820015, 1742 1742 - 0xd1060002, 0x00011103, 1743 1743 - 0x7e0602ff, 0x00000200, 1744 1744 - 0xbefc00ff, 0x00010000, 1745 1745 - 0xbe800077, 0x8677ff77, 1746 1746 - 0xff7fffff, 0x8777ff77, 1747 1747 - 0x00058000, 0xd8ec0000, 1748 1748 - 0x00000002, 0xbf8cc07f, 1749 1749 - 0xe0765000, 0x701d0002, 1750 1750 - 0x68040702, 0xd0c9006a, 1751 1751 - 0x0000f702, 0xbf87fff7, 1752 1752 - 0xbef70000, 0xbef000ff, 1753 1753 - 0x00000400, 0xbefe00c1, 1754 1754 - 0xbeff00c1, 0xb8fb2b05, 1755 1755 - 0x807b817b, 0x8e7b827b, 1756 1756 - 0xbef600ff, 0x01000000, 1757 1757 - 0xbefc0084, 0xbf0a7b7c, 1758 1758 - 0xbf84006d, 0xbf11017c, 1759 1759 - 0x807bff7b, 0x00001000, 1799 1799 + 0xbe840080, 0xd2890000, 1800 1800 + 0x00000902, 0x80048104, 1801 1801 + 0xd2890001, 0x00000902, 1802 1802 + 0x80048104, 0xd2890002, 1803 1803 + 0x00000902, 0x80048104, 1804 1804 + 0xd2890003, 0x00000902, 1805 1805 + 0x80048104, 0xc069003a, 1806 1806 + 0x00000070, 0xbf8cc07f, 1807 1807 + 0x80709070, 0xbf06c004, 1808 1808 + 0xbf84ffee, 0xbe840080, 1809 1809 + 0xd2890000, 0x00000903, 1810 1810 + 0x80048104, 0xd2890001, 1811 1811 + 0x00000903, 0x80048104, 1812 1812 + 0xd2890002, 0x00000903, 1813 1813 + 0x80048104, 0xd2890003, 1814 1814 + 0x00000903, 0x80048104, 1815 1815 + 0xc069003a, 0x00000070, 1816 1816 + 0xbf8cc07f, 0x80709070, 1817 1817 + 0xbf06c004, 0xbf84ffee, 1818 1818 + 0xbf820008, 0xe0724000, 1819 1819 + 0x701d0000, 0xe0724100, 1820 1820 + 0x701d0100, 0xe0724200, 1821 1821 + 0x701d0200, 0xe0724300, 1822 1822 + 0x701d0300, 0xbefe00c1, 1823 1823 + 0xbeff00c1, 0xb8fb4306, 1824 1824 + 0x867bc17b, 0xbf840064, 1825 1825 + 0xbf8a0000, 0x867aff6f, 1826 1826 + 0x04000000, 0xbf840060, 1827 1827 + 0x8e7b867b, 0x8e7b827b, 1828 1828 + 0xbef6007b, 0xb8f02985, 1829 1829 + 0x80708170, 0x8e708a70, 1830 1830 + 0x8e708170, 0xb8fa1605, 1831 1831 + 0x807a817a, 0x8e7a867a, 1832 1832 + 0x80707a70, 0x8070ff70, 1833 1833 + 0x00000080, 0xbef600ff, 1834 1834 + 0x01000000, 0xbefc0080, 1835 1835 + 0xd28c0002, 0x000100c1, 1836 1836 + 0xd28d0003, 0x000204c1, 1760 1837 0x867aff78, 0x00400000, 1761 1838 0xbf850003, 0xb8faf803, 1762 1839 0x897a7aff, 0x10000000, 1763 1763 - 0xbf850051, 0xbe840080, 1840 1840 + 0xbf850030, 0x24040682, 1841 1841 + 0xd86e4000, 0x00000002, 1842 1842 + 0xbf8cc07f, 0xbe840080, 1764 1843 0xd2890000, 0x00000900, 1765 1844 0x80048104, 0xd2890001, 1766 1845 0x00000900, 0x80048104, ··· 1798 1839 0x80048104, 0xc069003a, 1799 1840 0x00000070, 0xbf8cc07f, 1800 1841 0x80709070, 0xbf06c004, 1801 1801 - 0xbf84ffee, 0xbe840080, 1802 1802 - 0xd2890000, 0x00000902, 1803 1803 - 0x80048104, 0xd2890001, 1804 1804 - 0x00000902, 0x80048104, 1805 1805 - 0xd2890002, 0x00000902, 1806 1806 - 0x80048104, 0xd2890003, 1807 1807 - 0x00000902, 0x80048104, 1808 1808 - 0xc069003a, 0x00000070, 1809 1809 - 0xbf8cc07f, 0x80709070, 1810 1810 - 0xbf06c004, 0xbf84ffee, 1811 1811 - 0xbe840080, 0xd2890000, 1812 1812 - 0x00000903, 0x80048104, 1813 1813 - 0xd2890001, 0x00000903, 1814 1814 - 0x80048104, 0xd2890002, 1815 1815 - 0x00000903, 0x80048104, 1816 1816 - 0xd2890003, 0x00000903, 1817 1817 - 0x80048104, 0xc069003a, 1818 1818 - 0x00000070, 0xbf8cc07f, 1819 1819 - 0x80709070, 0xbf06c004, 1820 1820 - 0xbf84ffee, 0x807c847c, 1821 1821 - 0xbf0a7b7c, 0xbf85ffb1, 1822 1822 - 0xbf9c0000, 0xbf820012, 1823 1823 - 0x7e000300, 0x7e020301, 1824 1824 - 0x7e040302, 0x7e060303, 1825 1825 - 0xe0724000, 0x701d0000, 1826 1826 - 0xe0724100, 0x701d0100, 1827 1827 - 0xe0724200, 0x701d0200, 1828 1828 - 0xe0724300, 0x701d0300, 1829 1829 - 0x807c847c, 0x8070ff70, 1830 1830 - 0x00000400, 0xbf0a7b7c, 1831 1831 - 0xbf85ffef, 0xbf9c0000, 1832 1832 - 0xb8fb2985, 0x807b817b, 1833 1833 - 0x8e7b837b, 0xb8fa2b05, 1834 1834 - 0x807a817a, 0x8e7a827a, 1835 1835 - 0x80fb7a7b, 0x867b7b7b, 1836 1836 - 0xbf84007a, 0x807bff7b, 1837 1837 - 0x00001000, 0xbefc0080, 1838 1838 - 0xbf11017c, 0x867aff78, 1842 1842 + 0xbf84ffee, 0x680404ff, 1843 1843 + 0x00000200, 0xd0c9006a, 1844 1844 + 0x0000f702, 0xbf87ffd2, 1845 1845 + 0xbf820015, 0xd1060002, 1846 1846 + 0x00011103, 0x7e0602ff, 1847 1847 + 0x00000200, 0xbefc00ff, 1848 1848 + 0x00010000, 0xbe800077, 1849 1849 + 0x8677ff77, 0xff7fffff, 1850 1850 + 0x8777ff77, 0x00058000, 1851 1851 + 0xd8ec0000, 0x00000002, 1852 1852 + 0xbf8cc07f, 0xe0765000, 1853 1853 + 0x701d0002, 0x68040702, 1854 1854 + 0xd0c9006a, 0x0000f702, 1855 1855 + 0xbf87fff7, 0xbef70000, 1856 1856 + 0xbef000ff, 0x00000400, 1857 1857 + 0xbefe00c1, 0xbeff00c1, 1858 1858 + 0xb8fb2b05, 0x807b817b, 1859 1859 + 0x8e7b827b, 0xbef600ff, 1860 1860 + 0x01000000, 0xbefc0084, 1861 1861 + 0xbf0a7b7c, 0xbf84006d, 1862 1862 + 0xbf11017c, 0x807bff7b, 1863 1863 + 0x00001000, 0x867aff78, 1839 1864 0x00400000, 0xbf850003, 1840 1865 0xb8faf803, 0x897a7aff, 1841 1841 - 0x10000000, 0xbf850059, 1842 1842 - 0xd3d84000, 0x18000100, 1843 1843 - 0xd3d84001, 0x18000101, 1844 1844 - 0xd3d84002, 0x18000102, 1845 1845 - 0xd3d84003, 0x18000103, 1866 1866 + 0x10000000, 0xbf850051, 1846 1867 0xbe840080, 0xd2890000, 1847 1868 0x00000900, 0x80048104, 1848 1869 0xd2890001, 0x00000900, ··· 1862 1923 0xbf8cc07f, 0x80709070, 1863 1924 0xbf06c004, 0xbf84ffee, 1864 1925 0x807c847c, 0xbf0a7b7c, 1865 1865 - 0xbf85ffa9, 0xbf9c0000, 1866 1866 - 0xbf820016, 0xd3d84000, 1867 1867 - 0x18000100, 0xd3d84001, 1868 1868 - 0x18000101, 0xd3d84002, 1869 1869 - 0x18000102, 0xd3d84003, 1870 1870 - 0x18000103, 0xe0724000, 1926 1926 + 0xbf85ffb1, 0xbf9c0000, 1927 1927 + 0xbf820012, 0x7e000300, 1928 1928 + 0x7e020301, 0x7e040302, 1929 1929 + 0x7e060303, 0xe0724000, 1871 1930 0x701d0000, 0xe0724100, 1872 1931 0x701d0100, 0xe0724200, 1873 1932 0x701d0200, 0xe0724300, 1874 1933 0x701d0300, 0x807c847c, 1875 1934 0x8070ff70, 0x00000400, 1876 1876 - 0xbf0a7b7c, 0xbf85ffeb, 1877 1877 - 0xbf9c0000, 0xbf820101, 1878 1878 - 0xbef4007e, 0x8675ff7f, 1879 1879 - 0x0000ffff, 0x8775ff75, 1880 1880 - 0x00040000, 0xbef60080, 1881 1881 - 0xbef700ff, 0x00807fac, 1882 1882 - 0x866eff7f, 0x08000000, 1883 1883 - 0x8f6e836e, 0x87776e77, 1884 1884 - 0x866eff7f, 0x70000000, 1885 1885 - 0x8f6e816e, 0x87776e77, 1886 1886 - 0x866eff7f, 0x04000000, 1887 1887 - 0xbf84001f, 0xbefe00c1, 1888 1888 - 0xbeff00c1, 0xb8ef4306, 1889 1889 - 0x866fc16f, 0xbf84001a, 1890 1890 - 0x8e6f866f, 0x8e6f826f, 1891 1891 - 0xbef6006f, 0xb8f82985, 1892 1892 - 0x80788178, 0x8e788a78, 1893 1893 - 0x8e788178, 0xb8ee1605, 1894 1894 - 0x806e816e, 0x8e6e866e, 1895 1895 - 0x80786e78, 0x8078ff78, 1896 1896 - 0x00000080, 0xbef600ff, 1897 1897 - 0x01000000, 0xbefc0080, 1898 1898 - 0xe0510000, 0x781d0000, 1899 1899 - 0xe0510100, 0x781d0000, 1900 1900 - 0x807cff7c, 0x00000200, 1901 1901 - 0x8078ff78, 0x00000200, 1902 1902 - 0xbf0a6f7c, 0xbf85fff6, 1935 1935 + 0xbf0a7b7c, 0xbf85ffef, 1936 1936 + 0xbf9c0000, 0xb8fb2985, 1937 1937 + 0x807b817b, 0x8e7b837b, 1938 1938 + 0xb8fa2b05, 0x807a817a, 1939 1939 + 0x8e7a827a, 0x80fb7a7b, 1940 1940 + 0x867b7b7b, 0xbf84007a, 1941 1941 + 0x807bff7b, 0x00001000, 1942 1942 + 0xbefc0080, 0xbf11017c, 1943 1943 + 0x867aff78, 0x00400000, 1944 1944 + 0xbf850003, 0xb8faf803, 1945 1945 + 0x897a7aff, 0x10000000, 1946 1946 + 0xbf850059, 0xd3d84000, 1947 1947 + 0x18000100, 0xd3d84001, 1948 1948 + 0x18000101, 0xd3d84002, 1949 1949 + 0x18000102, 0xd3d84003, 1950 1950 + 0x18000103, 0xbe840080, 1951 1951 + 0xd2890000, 0x00000900, 1952 1952 + 0x80048104, 0xd2890001, 1953 1953 + 0x00000900, 0x80048104, 1954 1954 + 0xd2890002, 0x00000900, 1955 1955 + 0x80048104, 0xd2890003, 1956 1956 + 0x00000900, 0x80048104, 1957 1957 + 0xc069003a, 0x00000070, 1958 1958 + 0xbf8cc07f, 0x80709070, 1959 1959 + 0xbf06c004, 0xbf84ffee, 1960 1960 + 0xbe840080, 0xd2890000, 1961 1961 + 0x00000901, 0x80048104, 1962 1962 + 0xd2890001, 0x00000901, 1963 1963 + 0x80048104, 0xd2890002, 1964 1964 + 0x00000901, 0x80048104, 1965 1965 + 0xd2890003, 0x00000901, 1966 1966 + 0x80048104, 0xc069003a, 1967 1967 + 0x00000070, 0xbf8cc07f, 1968 1968 + 0x80709070, 0xbf06c004, 1969 1969 + 0xbf84ffee, 0xbe840080, 1970 1970 + 0xd2890000, 0x00000902, 1971 1971 + 0x80048104, 0xd2890001, 1972 1972 + 0x00000902, 0x80048104, 1973 1973 + 0xd2890002, 0x00000902, 1974 1974 + 0x80048104, 0xd2890003, 1975 1975 + 0x00000902, 0x80048104, 1976 1976 + 0xc069003a, 0x00000070, 1977 1977 + 0xbf8cc07f, 0x80709070, 1978 1978 + 0xbf06c004, 0xbf84ffee, 1979 1979 + 0xbe840080, 0xd2890000, 1980 1980 + 0x00000903, 0x80048104, 1981 1981 + 0xd2890001, 0x00000903, 1982 1982 + 0x80048104, 0xd2890002, 1983 1983 + 0x00000903, 0x80048104, 1984 1984 + 0xd2890003, 0x00000903, 1985 1985 + 0x80048104, 0xc069003a, 1986 1986 + 0x00000070, 0xbf8cc07f, 1987 1987 + 0x80709070, 0xbf06c004, 1988 1988 + 0xbf84ffee, 0x807c847c, 1989 1989 + 0xbf0a7b7c, 0xbf85ffa9, 1990 1990 + 0xbf9c0000, 0xbf820016, 1991 1991 + 0xd3d84000, 0x18000100, 1992 1992 + 0xd3d84001, 0x18000101, 1993 1993 + 0xd3d84002, 0x18000102, 1994 1994 + 0xd3d84003, 0x18000103, 1995 1995 + 0xe0724000, 0x701d0000, 1996 1996 + 0xe0724100, 0x701d0100, 1997 1997 + 0xe0724200, 0x701d0200, 1998 1998 + 0xe0724300, 0x701d0300, 1999 1999 + 0x807c847c, 0x8070ff70, 2000 2000 + 0x00000400, 0xbf0a7b7c, 2001 2001 + 0xbf85ffeb, 0xbf9c0000, 2002 2002 + 0xbf8200ee, 0xbef4007e, 2003 2003 + 0x8675ff7f, 0x0000ffff, 2004 2004 + 0x8775ff75, 0x00040000, 2005 2005 + 0xbef60080, 0xbef700ff, 2006 2006 + 0x00807fac, 0x866eff7f, 2007 2007 + 0x04000000, 0xbf84001f, 1903 2008 0xbefe00c1, 0xbeff00c1, 2009 2009 + 0xb8ef4306, 0x866fc16f, 2010 2010 + 0xbf84001a, 0x8e6f866f, 2011 2011 + 0x8e6f826f, 0xbef6006f, 2012 2012 + 0xb8f82985, 0x80788178, 2013 2013 + 0x8e788a78, 0x8e788178, 2014 2014 + 0xb8ee1605, 0x806e816e, 2015 2015 + 0x8e6e866e, 0x80786e78, 2016 2016 + 0x8078ff78, 0x00000080, 1904 2017 0xbef600ff, 0x01000000, 1905 1905 - 0xb8ef2b05, 0x806f816f, 1906 1906 - 0x8e6f826f, 0x806fff6f, 1907 1907 - 0x00008000, 0xbef80080, 1908 1908 - 0xbeee0078, 0x8078ff78, 1909 1909 - 0x00000400, 0xbefc0084, 2018 2018 + 0xbefc0080, 0xe0510000, 2019 2019 + 0x781d0000, 0xe0510100, 2020 2020 + 0x781d0000, 0x807cff7c, 2021 2021 + 0x00000200, 0x8078ff78, 2022 2022 + 0x00000200, 0xbf0a6f7c, 2023 2023 + 0xbf85fff6, 0xbefe00c1, 2024 2024 + 0xbeff00c1, 0xbef600ff, 2025 2025 + 0x01000000, 0xb8ef2b05, 2026 2026 + 0x806f816f, 0x8e6f826f, 2027 2027 + 0x806fff6f, 0x00008000, 2028 2028 + 0xbef80080, 0xbeee0078, 2029 2029 + 0x8078ff78, 0x00000400, 2030 2030 + 0xbefc0084, 0xbf11087c, 2031 2031 + 0xe0524000, 0x781d0000, 2032 2032 + 0xe0524100, 0x781d0100, 2033 2033 + 0xe0524200, 0x781d0200, 2034 2034 + 0xe0524300, 0x781d0300, 2035 2035 + 0xbf8c0f70, 0x7e000300, 2036 2036 + 0x7e020301, 0x7e040302, 2037 2037 + 0x7e060303, 0x807c847c, 2038 2038 + 0x8078ff78, 0x00000400, 2039 2039 + 0xbf0a6f7c, 0xbf85ffee, 2040 2040 + 0xb8ef2985, 0x806f816f, 2041 2041 + 0x8e6f836f, 0xb8f92b05, 2042 2042 + 0x80798179, 0x8e798279, 2043 2043 + 0x80ef796f, 0x866f6f6f, 2044 2044 + 0xbf84001a, 0x806fff6f, 2045 2045 + 0x00008000, 0xbefc0080, 1910 2046 0xbf11087c, 0xe0524000, 1911 2047 0x781d0000, 0xe0524100, 1912 2048 0x781d0100, 0xe0524200, 1913 2049 0x781d0200, 0xe0524300, 1914 2050 0x781d0300, 0xbf8c0f70, 1915 1915 - 0x7e000300, 0x7e020301, 1916 1916 - 0x7e040302, 0x7e060303, 2051 2051 + 0xd3d94000, 0x18000100, 2052 2052 + 0xd3d94001, 0x18000101, 2053 2053 + 0xd3d94002, 0x18000102, 2054 2054 + 0xd3d94003, 0x18000103, 1917 2055 0x807c847c, 0x8078ff78, 1918 2056 0x00000400, 0xbf0a6f7c, 1919 1919 - 0xbf85ffee, 0xb8ef2985, 1920 1920 - 0x806f816f, 0x8e6f836f, 1921 1921 - 0xb8f92b05, 0x80798179, 1922 1922 - 0x8e798279, 0x80ef796f, 1923 1923 - 0x866f6f6f, 0xbf84001a, 1924 1924 - 0x806fff6f, 0x00008000, 1925 1925 - 0xbefc0080, 0xbf11087c, 1926 1926 - 0xe0524000, 0x781d0000, 1927 1927 - 0xe0524100, 0x781d0100, 1928 1928 - 0xe0524200, 0x781d0200, 1929 1929 - 0xe0524300, 0x781d0300, 1930 1930 - 0xbf8c0f70, 0xd3d94000, 1931 1931 - 0x18000100, 0xd3d94001, 1932 1932 - 0x18000101, 0xd3d94002, 1933 1933 - 0x18000102, 0xd3d94003, 1934 1934 - 0x18000103, 0x807c847c, 1935 1935 - 0x8078ff78, 0x00000400, 1936 1936 - 0xbf0a6f7c, 0xbf85ffea, 1937 1937 - 0xbf9c0000, 0xe0524000, 1938 1938 - 0x6e1d0000, 0xe0524100, 1939 1939 - 0x6e1d0100, 0xe0524200, 1940 1940 - 0x6e1d0200, 0xe0524300, 1941 1941 - 0x6e1d0300, 0xbf8c0f70, 1942 1942 - 0xb8f82985, 0x80788178, 1943 1943 - 0x8e788a78, 0x8e788178, 1944 1944 - 0xb8ee1605, 0x806e816e, 1945 1945 - 0x8e6e866e, 0x80786e78, 1946 1946 - 0x80f8c078, 0xb8ef1605, 1947 1947 - 0x806f816f, 0x8e6f846f, 1948 1948 - 0x8e76826f, 0xbef600ff, 1949 1949 - 0x01000000, 0xbefc006f, 1950 1950 - 0xc031003a, 0x00000078, 1951 1951 - 0x80f8c078, 0xbf8cc07f, 1952 1952 - 0x80fc907c, 0xbf800000, 1953 1953 - 0xbe802d00, 0xbe822d02, 1954 1954 - 0xbe842d04, 0xbe862d06, 1955 1955 - 0xbe882d08, 0xbe8a2d0a, 1956 1956 - 0xbe8c2d0c, 0xbe8e2d0e, 1957 1957 - 0xbf06807c, 0xbf84fff0, 1958 1958 - 0xb8f82985, 0x80788178, 1959 1959 - 0x8e788a78, 0x8e788178, 1960 1960 - 0xb8ee1605, 0x806e816e, 1961 1961 - 0x8e6e866e, 0x80786e78, 1962 1962 - 0xbef60084, 0xbef600ff, 1963 1963 - 0x01000000, 0xc0211bfa, 2057 2057 + 0xbf85ffea, 0xbf9c0000, 2058 2058 + 0xe0524000, 0x6e1d0000, 2059 2059 + 0xe0524100, 0x6e1d0100, 2060 2060 + 0xe0524200, 0x6e1d0200, 2061 2061 + 0xe0524300, 0x6e1d0300, 2062 2062 + 0xbf8c0f70, 0xb8f82985, 2063 2063 + 0x80788178, 0x8e788a78, 2064 2064 + 0x8e788178, 0xb8ee1605, 2065 2065 + 0x806e816e, 0x8e6e866e, 2066 2066 + 0x80786e78, 0x80f8c078, 2067 2067 + 0xb8ef1605, 0x806f816f, 2068 2068 + 0x8e6f846f, 0x8e76826f, 2069 2069 + 0xbef600ff, 0x01000000, 2070 2070 + 0xbefc006f, 0xc031003a, 2071 2071 + 0x00000078, 0x80f8c078, 2072 2072 + 0xbf8cc07f, 0x80fc907c, 2073 2073 + 0xbf800000, 0xbe802d00, 2074 2074 + 0xbe822d02, 0xbe842d04, 2075 2075 + 0xbe862d06, 0xbe882d08, 2076 2076 + 0xbe8a2d0a, 0xbe8c2d0c, 2077 2077 + 0xbe8e2d0e, 0xbf06807c, 2078 2078 + 0xbf84fff0, 0xb8f82985, 2079 2079 + 0x80788178, 0x8e788a78, 2080 2080 + 0x8e788178, 0xb8ee1605, 2081 2081 + 0x806e816e, 0x8e6e866e, 2082 2082 + 0x80786e78, 0xbef60084, 2083 2083 + 0xbef600ff, 0x01000000, 2084 2084 + 0xc0211bfa, 0x00000078, 2085 2085 + 0x80788478, 0xc0211b3a, 1964 2086 0x00000078, 0x80788478, 1965 1965 - 0xc0211b3a, 0x00000078, 1966 1966 - 0x80788478, 0xc0211b7a, 2087 2087 + 0xc0211b7a, 0x00000078, 2088 2088 + 0x80788478, 0xc0211c3a, 1967 2089 0x00000078, 0x80788478, 1968 1968 - 0xc0211c3a, 0x00000078, 1969 1969 - 0x80788478, 0xc0211c7a, 2090 2090 + 0xc0211c7a, 0x00000078, 2091 2091 + 0x80788478, 0xc0211eba, 1970 2092 0x00000078, 0x80788478, 1971 1971 - 0xc0211eba, 0x00000078, 1972 1972 - 0x80788478, 0xc0211efa, 2093 2093 + 0xc0211efa, 0x00000078, 2094 2094 + 0x80788478, 0xc0211a3a, 1973 2095 0x00000078, 0x80788478, 1974 1974 - 0xc0211a3a, 0x00000078, 1975 1975 - 0x80788478, 0xc0211a7a, 2096 2096 + 0xc0211a7a, 0x00000078, 2097 2097 + 0x80788478, 0xc0211cfa, 1976 2098 0x00000078, 0x80788478, 1977 1977 - 0xc0211cfa, 0x00000078, 1978 1978 - 0x80788478, 0xbf8cc07f, 1979 1979 - 0xbefc006f, 0xbefe0070, 1980 1980 - 0xbeff0071, 0x866f7bff, 1981 1981 - 0x000003ff, 0xb96f4803, 1982 1982 - 0x866f7bff, 0xfffff800, 1983 1983 - 0x8f6f8b6f, 0xb96fa2c3, 1984 1984 - 0xb973f801, 0xb8ee2985, 1985 1985 - 0x806e816e, 0x8e6e8a6e, 1986 1986 - 0x8e6e816e, 0xb8ef1605, 1987 1987 - 0x806f816f, 0x8e6f866f, 1988 1988 - 0x806e6f6e, 0x806e746e, 1989 1989 - 0x826f8075, 0x866fff6f, 1990 1990 - 0x0000ffff, 0xc00b1c37, 1991 1991 - 0x00000050, 0xc00b1d37, 1992 1992 - 0x00000060, 0xc0031e77, 1993 1993 - 0x00000074, 0xbf8cc07f, 1994 1994 - 0x866fff6d, 0xf8000000, 1995 1995 - 0x8f6f9b6f, 0x8e6f906f, 1996 1996 - 0xbeee0080, 0x876e6f6e, 1997 1997 - 0x866fff6d, 0x04000000, 1998 1998 - 0x8f6f9a6f, 0x8e6f8f6f, 1999 1999 - 0x876e6f6e, 0x866fff7a, 2000 2000 - 0x00800000, 0x8f6f976f, 2099 2099 + 0xbf8cc07f, 0xbefc006f, 2100 2100 + 0xbefe0070, 0xbeff0071, 2101 2101 + 0x866f7bff, 0x000003ff, 2102 2102 + 0xb96f4803, 0x866f7bff, 2103 2103 + 0xfffff800, 0x8f6f8b6f, 2104 2104 + 0xb96fa2c3, 0xb973f801, 2105 2105 + 0xb8ee2985, 0x806e816e, 2106 2106 + 0x8e6e8a6e, 0x8e6e816e, 2107 2107 + 0xb8ef1605, 0x806f816f, 2108 2108 + 0x8e6f866f, 0x806e6f6e, 2109 2109 + 0x806e746e, 0x826f8075, 2110 2110 + 0x866fff6f, 0x0000ffff, 2111 2111 + 0xc00b1c37, 0x00000050, 2112 2112 + 0xc00b1d37, 0x00000060, 2113 2113 + 0xc0031e77, 0x00000074, 2114 2114 + 0xbf8cc07f, 0x8f6e8b77, 2115 2115 + 0x866eff6e, 0x001f8000, 2001 2116 0xb96ef807, 0x866dff6d, 2002 2117 0x0000ffff, 0x86fe7e7e, 2003 2118 0x86ea6a6a, 0x8f6e837a, 2004 2119 0xb96ee0c2, 0xbf800002, 2005 2120 0xb97a0002, 0xbf8a0000, 2006 2006 - 0x95806f6c, 0xbf810000, 2121 2121 + 0xbe801f6c, 0xbf810000, 2007 2122 }; 2008 2123 2009 2124 static const uint32_t cwsr_trap_gfx10_hex[] = { 2010 2010 - 0xbf820001, 0xbf8201cf, 2125 2125 + 0xbf820001, 0xbf82021c, 2011 2126 0xb0804004, 0xb978f802, 2012 2012 - 0x8a788678, 0xb96ef801, 2013 2013 - 0x876eff6e, 0x00000800, 2014 2014 - 0xbf840003, 0x876eff78, 2127 2127 + 0x8a78ff78, 0x00020006, 2128 2128 + 0xb97bf803, 0x876eff78, 2015 2129 0x00002000, 0xbf840009, 2016 2016 - 0xb97bf803, 0x876eff7b, 2017 2017 - 0x00000400, 0xbf85001d, 2018 2018 - 0x876eff7b, 0x00000100, 2019 2019 - 0xbf840002, 0x8878ff78, 2020 2020 - 0x00002000, 0xb97af812, 2130 2130 + 0x876eff6d, 0x00ff0000, 2131 2131 + 0xbf85001e, 0x876eff7b, 2132 2132 + 0x00000400, 0xbf850041, 2133 2133 + 0xbf8e0010, 0xb97bf803, 2134 2134 + 0xbf82fffa, 0x876eff7b, 2135 2135 + 0x00000900, 0xbf850015, 2136 2136 + 0x876eff7b, 0x000071ff, 2137 2137 + 0xbf840008, 0x876fff7b, 2138 2138 + 0x00007080, 0xbf840001, 2139 2139 + 0xbeee1d87, 0xb96ff801, 2140 2140 + 0x8f6e8c6e, 0x876e6f6e, 2141 2141 + 0xbf85000a, 0x876eff6d, 2142 2142 + 0x00ff0000, 0xbf850007, 2143 2143 + 0xb96ef801, 0x876eff6e, 2144 2144 + 0x00000800, 0xbf850003, 2145 2145 + 0x876eff7b, 0x00000400, 2146 2146 + 0xbf850026, 0xb97af812, 2021 2147 0xb97bf813, 0x8ffa887a, 2022 2022 - 0xf4051bbd, 0xfa000000, 2023 2023 - 0xbf8cc07f, 0xf4051ebd, 2024 2024 - 0xfa000008, 0xbf8cc07f, 2025 2025 - 0x87ee6e6e, 0xbf840001, 2026 2026 - 0xbe80206e, 0xb97bf803, 2027 2027 - 0x877bff7b, 0x000001ff, 2148 2148 + 0xf4011bbd, 0xfa000010, 2149 2149 + 0xbf8cc07f, 0x8f6e976e, 2150 2150 + 0x8a77ff77, 0x00800000, 2151 2151 + 0x88776e77, 0xf4051bbd, 2152 2152 + 0xfa000000, 0xbf8cc07f, 2153 2153 + 0xf4051ebd, 0xfa000008, 2154 2154 + 0xbf8cc07f, 0x87ee6e6e, 2155 2155 + 0xbf840001, 0xbe80206e, 2156 2156 + 0x876eff6d, 0x01ff0000, 2157 2157 + 0xbf850005, 0x8878ff78, 2158 2158 + 0x00002000, 0x80ec886c, 2159 2159 + 0x82ed806d, 0xbf820005, 2160 2160 + 0x876eff6d, 0x01000000, 2028 2161 0xbf850002, 0x806c846c, 2029 2162 0x826d806d, 0x876dff6d, 2030 2163 0x0000ffff, 0x87fe7e7e, ··· 2106 2095 0xb9fa0283, 0xbeee037e, 2107 2096 0xbeef037f, 0xbefe0480, 2108 2097 0xbf900004, 0xbf8cc07f, 2098 2098 + 0x877aff7f, 0x04000000, 2099 2099 + 0x8f7a857a, 0x886d7a6d, 2100 2100 + 0xbefa037e, 0x877bff7f, 2101 2101 + 0x0000ffff, 0xbefe03c1, 2102 2102 + 0xbeff03c1, 0xdc5f8000, 2103 2103 + 0x007a0000, 0x7e000280, 2104 2104 + 0xbefe037a, 0xbeff037b, 2109 2105 0xb97b02dc, 0x8f7b997b, 2110 2110 - 0x887b7b7f, 0xb97a2a05, 2111 2111 - 0x807a817a, 0xbf0d997b, 2112 2112 - 0xbf850002, 0x8f7a897a, 2113 2113 - 0xbf820001, 0x8f7a8a7a, 2106 2106 + 0xb97a2a05, 0x807a817a, 2107 2107 + 0xbf0d997b, 0xbf850002, 2108 2108 + 0x8f7a897a, 0xbf820001, 2109 2109 + 0x8f7a8a7a, 0xb97b1e06, 2110 2110 + 0x8f7b8a7b, 0x807a7b7a, 2114 2111 0x877bff7f, 0x0000ffff, 2115 2112 0x807aff7a, 0x00000200, 2116 2113 0x807a7e7a, 0x827b807b, 2117 2117 - 0xbef4037e, 0x8775ff7f, 2118 2118 - 0x0000ffff, 0x8875ff75, 2119 2119 - 0x00040000, 0xbef60380, 2120 2120 - 0xbef703ff, 0x10807fac, 2121 2121 - 0x877aff7f, 0x08000000, 2122 2122 - 0x907a837a, 0x88777a77, 2123 2123 - 0x877aff7f, 0x70000000, 2124 2124 - 0x907a817a, 0x88777a77, 2125 2125 - 0xbef1037c, 0xbef00380, 2126 2126 - 0xb97302dc, 0x8f739973, 2127 2127 - 0x8873737f, 0xbefe03c1, 2114 2114 + 0xd7610000, 0x00010870, 2115 2115 + 0xd7610000, 0x00010a71, 2116 2116 + 0xd7610000, 0x00010c72, 2117 2117 + 0xd7610000, 0x00010e73, 2118 2118 + 0xd7610000, 0x00011074, 2119 2119 + 0xd7610000, 0x00011275, 2120 2120 + 0xd7610000, 0x00011476, 2121 2121 + 0xd7610000, 0x00011677, 2122 2122 + 0xd7610000, 0x00011a79, 2123 2123 + 0xd7610000, 0x00011c7e, 2124 2124 + 0xd7610000, 0x00011e7f, 2125 2125 + 0xbefe03ff, 0x00003fff, 2126 2126 + 0xbeff0380, 0xdc5f8040, 2127 2127 + 0x007a0000, 0xd760007a, 2128 2128 + 0x00011d00, 0xd760007b, 2129 2129 + 0x00011f00, 0xbefe037a, 2130 2130 + 0xbeff037b, 0xbef4037e, 2131 2131 + 0x8775ff7f, 0x0000ffff, 2132 2132 + 0x8875ff75, 0x00040000, 2133 2133 + 0xbef60380, 0xbef703ff, 2134 2134 + 0x10807fac, 0xbef1037c, 2135 2135 + 0xbef00380, 0xb97302dc, 2136 2136 + 0x8f739973, 0xbefe03c1, 2128 2137 0x907c9973, 0x877c817c, 2129 2138 0xbf06817c, 0xbf850002, 2130 2139 0xbeff0380, 0xbf820002, 2131 2131 - 0xbeff03c1, 0xbf82000b, 2140 2140 + 0xbeff03c1, 0xbf820009, 2132 2141 0xbef603ff, 0x01000000, 2133 2133 - 0xe0704000, 0x705d0000, 2134 2142 0xe0704080, 0x705d0100, 2135 2143 0xe0704100, 0x705d0200, 2136 2144 0xe0704180, 0x705d0300, 2137 2137 - 0xbf82000a, 0xbef603ff, 2138 2138 - 0x01000000, 0xe0704000, 2139 2139 - 0x705d0000, 0xe0704100, 2145 2145 + 0xbf820008, 0xbef603ff, 2146 2146 + 0x01000000, 0xe0704100, 2140 2147 0x705d0100, 0xe0704200, 2141 2148 0x705d0200, 0xe0704300, 2142 2149 0x705d0300, 0xb9702a05, ··· 2169 2140 0xbefc0380, 0xd7610002, 2170 2141 0x0000f871, 0x807c817c, 2171 2142 0xd7610002, 0x0000f86c, 2172 2172 - 0x807c817c, 0xd7610002, 2173 2173 - 0x0000f86d, 0x807c817c, 2143 2143 + 0x807c817c, 0x8a7aff6d, 2144 2144 + 0x80000000, 0xd7610002, 2145 2145 + 0x0000f87a, 0x807c817c, 2174 2146 0xd7610002, 0x0000f86e, 2175 2147 0x807c817c, 0xd7610002, 2176 2148 0x0000f86f, 0x807c817c, ··· 2186 2156 0x0000f871, 0x807c817c, 2187 2157 0xb971f815, 0xd7610002, 2188 2158 0x0000f871, 0x807c817c, 2159 2159 + 0xbefe03ff, 0x0000ffff, 2189 2160 0xbeff0380, 0xe0704000, 2190 2190 - 0x705d0200, 0xb9702a05, 2161 2161 + 0x705d0200, 0xbefe03c1, 2162 2162 + 0xb9702a05, 0x80708170, 2163 2163 + 0xbf0d9973, 0xbf850002, 2164 2164 + 0x8f708970, 0xbf820001, 2165 2165 + 0x8f708a70, 0xb97a1e06, 2166 2166 + 0x8f7a8a7a, 0x80707a70, 2167 2167 + 0xbef603ff, 0x01000000, 2168 2168 + 0xbef90380, 0xbefc0380, 2169 2169 + 0xbf800000, 0xbe802f00, 2170 2170 + 0xbe822f02, 0xbe842f04, 2171 2171 + 0xbe862f06, 0xbe882f08, 2172 2172 + 0xbe8a2f0a, 0xbe8c2f0c, 2173 2173 + 0xbe8e2f0e, 0xd7610002, 2174 2174 + 0x0000f200, 0x80798179, 2175 2175 + 0xd7610002, 0x0000f201, 2176 2176 + 0x80798179, 0xd7610002, 2177 2177 + 0x0000f202, 0x80798179, 2178 2178 + 0xd7610002, 0x0000f203, 2179 2179 + 0x80798179, 0xd7610002, 2180 2180 + 0x0000f204, 0x80798179, 2181 2181 + 0xd7610002, 0x0000f205, 2182 2182 + 0x80798179, 0xd7610002, 2183 2183 + 0x0000f206, 0x80798179, 2184 2184 + 0xd7610002, 0x0000f207, 2185 2185 + 0x80798179, 0xd7610002, 2186 2186 + 0x0000f208, 0x80798179, 2187 2187 + 0xd7610002, 0x0000f209, 2188 2188 + 0x80798179, 0xd7610002, 2189 2189 + 0x0000f20a, 0x80798179, 2190 2190 + 0xd7610002, 0x0000f20b, 2191 2191 + 0x80798179, 0xd7610002, 2192 2192 + 0x0000f20c, 0x80798179, 2193 2193 + 0xd7610002, 0x0000f20d, 2194 2194 + 0x80798179, 0xd7610002, 2195 2195 + 0x0000f20e, 0x80798179, 2196 2196 + 0xd7610002, 0x0000f20f, 2197 2197 + 0x80798179, 0xbf06a079, 2198 2198 + 0xbf840006, 0xe0704000, 2199 2199 + 0x705d0200, 0x8070ff70, 2200 2200 + 0x00000080, 0xbef90380, 2201 2201 + 0x7e040280, 0x807c907c, 2202 2202 + 0xbf0aff7c, 0x00000060, 2203 2203 + 0xbf85ffbc, 0xbe802f00, 2204 2204 + 0xbe822f02, 0xbe842f04, 2205 2205 + 0xbe862f06, 0xbe882f08, 2206 2206 + 0xbe8a2f0a, 0xd7610002, 2207 2207 + 0x0000f200, 0x80798179, 2208 2208 + 0xd7610002, 0x0000f201, 2209 2209 + 0x80798179, 0xd7610002, 2210 2210 + 0x0000f202, 0x80798179, 2211 2211 + 0xd7610002, 0x0000f203, 2212 2212 + 0x80798179, 0xd7610002, 2213 2213 + 0x0000f204, 0x80798179, 2214 2214 + 0xd7610002, 0x0000f205, 2215 2215 + 0x80798179, 0xd7610002, 2216 2216 + 0x0000f206, 0x80798179, 2217 2217 + 0xd7610002, 0x0000f207, 2218 2218 + 0x80798179, 0xd7610002, 2219 2219 + 0x0000f208, 0x80798179, 2220 2220 + 0xd7610002, 0x0000f209, 2221 2221 + 0x80798179, 0xd7610002, 2222 2222 + 0x0000f20a, 0x80798179, 2223 2223 + 0xd7610002, 0x0000f20b, 2224 2224 + 0x80798179, 0xe0704000, 2225 2225 + 0x705d0200, 0xbefe03c1, 2226 2226 + 0x907c9973, 0x877c817c, 2227 2227 + 0xbf06817c, 0xbf850002, 2228 2228 + 0xbeff0380, 0xbf820001, 2229 2229 + 0xbeff03c1, 0xb97b4306, 2230 2230 + 0x877bc17b, 0xbf840044, 2231 2231 + 0xbf8a0000, 0x877aff6d, 2232 2232 + 0x80000000, 0xbf840040, 2233 2233 + 0x8f7b867b, 0x8f7b827b, 2234 2234 + 0xbef6037b, 0xb9703a05, 2191 2235 0x80708170, 0xbf0d9973, 2192 2236 0xbf850002, 0x8f708970, 2193 2237 0xbf820001, 0x8f708a70, 2194 2238 0xb97a1e06, 0x8f7a8a7a, 2195 2195 - 0x80707a70, 0xbef603ff, 2196 2196 - 0x01000000, 0xbef90380, 2197 2197 - 0xbefc0380, 0xbf800000, 2198 2198 - 0xbe802f00, 0xbe822f02, 2199 2199 - 0xbe842f04, 0xbe862f06, 2200 2200 - 0xbe882f08, 0xbe8a2f0a, 2201 2201 - 0xbe8c2f0c, 0xbe8e2f0e, 2239 2239 + 0x80707a70, 0x8070ff70, 2240 2240 + 0x00000200, 0x8070ff70, 2241 2241 + 0x00000080, 0xbef603ff, 2242 2242 + 0x01000000, 0xd7650000, 2243 2243 + 0x000100c1, 0xd7660000, 2244 2244 + 0x000200c1, 0x16000084, 2245 2245 + 0x907c9973, 0x877c817c, 2246 2246 + 0xbf06817c, 0xbefc0380, 2247 2247 + 0xbf850012, 0xbe8303ff, 2248 2248 + 0x00000080, 0xbf800000, 2249 2249 + 0xbf800000, 0xbf800000, 2250 2250 + 0xd8d80000, 0x01000000, 2251 2251 + 0xbf8c0000, 0xe0704000, 2252 2252 + 0x705d0100, 0x807c037c, 2253 2253 + 0x80700370, 0xd5250000, 2254 2254 + 0x0001ff00, 0x00000080, 2255 2255 + 0xbf0a7b7c, 0xbf85fff4, 2256 2256 + 0xbf820011, 0xbe8303ff, 2257 2257 + 0x00000100, 0xbf800000, 2258 2258 + 0xbf800000, 0xbf800000, 2259 2259 + 0xd8d80000, 0x01000000, 2260 2260 + 0xbf8c0000, 0xe0704000, 2261 2261 + 0x705d0100, 0x807c037c, 2262 2262 + 0x80700370, 0xd5250000, 2263 2263 + 0x0001ff00, 0x00000100, 2264 2264 + 0xbf0a7b7c, 0xbf85fff4, 2265 2265 + 0xbefe03c1, 0x907c9973, 2266 2266 + 0x877c817c, 0xbf06817c, 2267 2267 + 0xbf850004, 0xbef003ff, 2268 2268 + 0x00000200, 0xbeff0380, 2269 2269 + 0xbf820003, 0xbef003ff, 2270 2270 + 0x00000400, 0xbeff03c1, 2271 2271 + 0xb97b3a05, 0x807b817b, 2272 2272 + 0x8f7b827b, 0x907c9973, 2273 2273 + 0x877c817c, 0xbf06817c, 2274 2274 + 0xbf850017, 0xbef603ff, 2275 2275 + 0x01000000, 0xbefc0384, 2276 2276 + 0xbf0a7b7c, 0xbf840037, 2277 2277 + 0x7e008700, 0x7e028701, 2278 2278 + 0x7e048702, 0x7e068703, 2279 2279 + 0xe0704000, 0x705d0000, 2280 2280 + 0xe0704080, 0x705d0100, 2281 2281 + 0xe0704100, 0x705d0200, 2282 2282 + 0xe0704180, 0x705d0300, 2283 2283 + 0x807c847c, 0x8070ff70, 2284 2284 + 0x00000200, 0xbf0a7b7c, 2285 2285 + 0xbf85ffef, 0xbf820025, 2286 2286 + 0xbef603ff, 0x01000000, 2287 2287 + 0xbefc0384, 0xbf0a7b7c, 2288 2288 + 0xbf840011, 0x7e008700, 2289 2289 + 0x7e028701, 0x7e048702, 2290 2290 + 0x7e068703, 0xe0704000, 2291 2291 + 0x705d0000, 0xe0704100, 2292 2292 + 0x705d0100, 0xe0704200, 2293 2293 + 0x705d0200, 0xe0704300, 2294 2294 + 0x705d0300, 0x807c847c, 2295 2295 + 0x8070ff70, 0x00000400, 2296 2296 + 0xbf0a7b7c, 0xbf85ffef, 2297 2297 + 0xb97b1e06, 0x877bc17b, 2298 2298 + 0xbf84000c, 0x8f7b837b, 2299 2299 + 0x807b7c7b, 0xbefe03c1, 2300 2300 + 0xbeff0380, 0x7e008700, 2301 2301 + 0xe0704000, 0x705d0000, 2302 2302 + 0x807c817c, 0x8070ff70, 2303 2303 + 0x00000080, 0xbf0a7b7c, 2304 2304 + 0xbf85fff8, 0xbf82013b, 2305 2305 + 0xbef4037e, 0x8775ff7f, 2306 2306 + 0x0000ffff, 0x8875ff75, 2307 2307 + 0x00040000, 0xbef60380, 2308 2308 + 0xbef703ff, 0x10807fac, 2309 2309 + 0xb97202dc, 0x8f729972, 2310 2310 + 0x876eff7f, 0x04000000, 2311 2311 + 0xbf840034, 0xbefe03c1, 2312 2312 + 0x907c9972, 0x877c817c, 2313 2313 + 0xbf06817c, 0xbf850002, 2314 2314 + 0xbeff0380, 0xbf820001, 2315 2315 + 0xbeff03c1, 0xb96f4306, 2316 2316 + 0x876fc16f, 0xbf840029, 2317 2317 + 0x8f6f866f, 0x8f6f826f, 2318 2318 + 0xbef6036f, 0xb9783a05, 2319 2319 + 0x80788178, 0xbf0d9972, 2320 2320 + 0xbf850002, 0x8f788978, 2321 2321 + 0xbf820001, 0x8f788a78, 2322 2322 + 0xb96e1e06, 0x8f6e8a6e, 2323 2323 + 0x80786e78, 0x8078ff78, 2324 2324 + 0x00000200, 0x8078ff78, 2325 2325 + 0x00000080, 0xbef603ff, 2326 2326 + 0x01000000, 0x907c9972, 2327 2327 + 0x877c817c, 0xbf06817c, 2328 2328 + 0xbefc0380, 0xbf850009, 2329 2329 + 0xe0310000, 0x781d0000, 2330 2330 + 0x807cff7c, 0x00000080, 2331 2331 + 0x8078ff78, 0x00000080, 2332 2332 + 0xbf0a6f7c, 0xbf85fff8, 2333 2333 + 0xbf820008, 0xe0310000, 2334 2334 + 0x781d0000, 0x807cff7c, 2335 2335 + 0x00000100, 0x8078ff78, 2336 2336 + 0x00000100, 0xbf0a6f7c, 2337 2337 + 0xbf85fff8, 0xbef80380, 2338 2338 + 0xbefe03c1, 0x907c9972, 2339 2339 + 0x877c817c, 0xbf06817c, 2340 2340 + 0xbf850002, 0xbeff0380, 2341 2341 + 0xbf820001, 0xbeff03c1, 2342 2342 + 0xb96f3a05, 0x806f816f, 2343 2343 + 0x8f6f826f, 0x907c9972, 2344 2344 + 0x877c817c, 0xbf06817c, 2345 2345 + 0xbf850024, 0xbef603ff, 2346 2346 + 0x01000000, 0xbeee0378, 2347 2347 + 0x8078ff78, 0x00000200, 2348 2348 + 0xbefc0384, 0xbf0a6f7c, 2349 2349 + 0xbf840050, 0xe0304000, 2350 2350 + 0x785d0000, 0xe0304080, 2351 2351 + 0x785d0100, 0xe0304100, 2352 2352 + 0x785d0200, 0xe0304180, 2353 2353 + 0x785d0300, 0xbf8c3f70, 2354 2354 + 0x7e008500, 0x7e028501, 2355 2355 + 0x7e048502, 0x7e068503, 2356 2356 + 0x807c847c, 0x8078ff78, 2357 2357 + 0x00000200, 0xbf0a6f7c, 2358 2358 + 0xbf85ffee, 0xe0304000, 2359 2359 + 0x6e5d0000, 0xe0304080, 2360 2360 + 0x6e5d0100, 0xe0304100, 2361 2361 + 0x6e5d0200, 0xe0304180, 2362 2362 + 0x6e5d0300, 0xbf8c3f70, 2363 2363 + 0xbf820034, 0xbef603ff, 2364 2364 + 0x01000000, 0xbeee0378, 2365 2365 + 0x8078ff78, 0x00000400, 2366 2366 + 0xbefc0384, 0xbf0a6f7c, 2367 2367 + 0xbf840012, 0xe0304000, 2368 2368 + 0x785d0000, 0xe0304100, 2369 2369 + 0x785d0100, 0xe0304200, 2370 2370 + 0x785d0200, 0xe0304300, 2371 2371 + 0x785d0300, 0xbf8c3f70, 2372 2372 + 0x7e008500, 0x7e028501, 2373 2373 + 0x7e048502, 0x7e068503, 2374 2374 + 0x807c847c, 0x8078ff78, 2375 2375 + 0x00000400, 0xbf0a6f7c, 2376 2376 + 0xbf85ffee, 0xb96f1e06, 2377 2377 + 0x876fc16f, 0xbf84000e, 2378 2378 + 0x8f6f836f, 0x806f7c6f, 2379 2379 + 0xbefe03c1, 0xbeff0380, 2380 2380 + 0xe0304000, 0x785d0000, 2381 2381 + 0xbf8c3f70, 0x7e008500, 2382 2382 + 0x807c817c, 0x8078ff78, 2383 2383 + 0x00000080, 0xbf0a6f7c, 2384 2384 + 0xbf85fff7, 0xbeff03c1, 2385 2385 + 0xe0304000, 0x6e5d0000, 2386 2386 + 0xe0304100, 0x6e5d0100, 2387 2387 + 0xe0304200, 0x6e5d0200, 2388 2388 + 0xe0304300, 0x6e5d0300, 2389 2389 + 0xbf8c3f70, 0xb9783a05, 2390 2390 + 0x80788178, 0xbf0d9972, 2391 2391 + 0xbf850002, 0x8f788978, 2392 2392 + 0xbf820001, 0x8f788a78, 2393 2393 + 0xb96e1e06, 0x8f6e8a6e, 2394 2394 + 0x80786e78, 0x8078ff78, 2395 2395 + 0x00000200, 0x80f8ff78, 2396 2396 + 0x00000050, 0xbef603ff, 2397 2397 + 0x01000000, 0xbefc03ff, 2398 2398 + 0x0000006c, 0x80f89078, 2399 2399 + 0xf429003a, 0xf0000000, 2400 2400 + 0xbf8cc07f, 0x80fc847c, 2401 2401 + 0xbf800000, 0xbe803100, 2402 2402 + 0xbe823102, 0x80f8a078, 2403 2403 + 0xf42d003a, 0xf0000000, 2404 2404 + 0xbf8cc07f, 0x80fc887c, 2405 2405 + 0xbf800000, 0xbe803100, 2406 2406 + 0xbe823102, 0xbe843104, 2407 2407 + 0xbe863106, 0x80f8c078, 2408 2408 + 0xf431003a, 0xf0000000, 2409 2409 + 0xbf8cc07f, 0x80fc907c, 2410 2410 + 0xbf800000, 0xbe803100, 2411 2411 + 0xbe823102, 0xbe843104, 2412 2412 + 0xbe863106, 0xbe883108, 2413 2413 + 0xbe8a310a, 0xbe8c310c, 2414 2414 + 0xbe8e310e, 0xbf06807c, 2415 2415 + 0xbf84fff0, 0xba80f801, 2416 2416 + 0x00000000, 0xbf8a0000, 2417 2417 + 0xb9783a05, 0x80788178, 2418 2418 + 0xbf0d9972, 0xbf850002, 2419 2419 + 0x8f788978, 0xbf820001, 2420 2420 + 0x8f788a78, 0xb96e1e06, 2421 2421 + 0x8f6e8a6e, 0x80786e78, 2422 2422 + 0x8078ff78, 0x00000200, 2423 2423 + 0xbef603ff, 0x01000000, 2424 2424 + 0xf4211bfa, 0xf0000000, 2425 2425 + 0x80788478, 0xf4211b3a, 2426 2426 + 0xf0000000, 0x80788478, 2427 2427 + 0xf4211b7a, 0xf0000000, 2428 2428 + 0x80788478, 0xf4211c3a, 2429 2429 + 0xf0000000, 0x80788478, 2430 2430 + 0xf4211c7a, 0xf0000000, 2431 2431 + 0x80788478, 0xf4211eba, 2432 2432 + 0xf0000000, 0x80788478, 2433 2433 + 0xf4211efa, 0xf0000000, 2434 2434 + 0x80788478, 0xf4211e7a, 2435 2435 + 0xf0000000, 0x80788478, 2436 2436 + 0xf4211cfa, 0xf0000000, 2437 2437 + 0x80788478, 0xf4211bba, 2438 2438 + 0xf0000000, 0x80788478, 2439 2439 + 0xbf8cc07f, 0xb9eef814, 2440 2440 + 0xf4211bba, 0xf0000000, 2441 2441 + 0x80788478, 0xbf8cc07f, 2442 2442 + 0xb9eef815, 0xbefc036f, 2443 2443 + 0xbefe0370, 0xbeff0371, 2444 2444 + 0x876f7bff, 0x000003ff, 2445 2445 + 0xb9ef4803, 0x876f7bff, 2446 2446 + 0xfffff800, 0x906f8b6f, 2447 2447 + 0xb9efa2c3, 0xb9f3f801, 2448 2448 + 0xb96e2a05, 0x806e816e, 2449 2449 + 0xbf0d9972, 0xbf850002, 2450 2450 + 0x8f6e896e, 0xbf820001, 2451 2451 + 0x8f6e8a6e, 0xb96f1e06, 2452 2452 + 0x8f6f8a6f, 0x806e6f6e, 2453 2453 + 0x806eff6e, 0x00000200, 2454 2454 + 0x806e746e, 0x826f8075, 2455 2455 + 0x876fff6f, 0x0000ffff, 2456 2456 + 0xf4091c37, 0xfa000050, 2457 2457 + 0xf4091d37, 0xfa000060, 2458 2458 + 0xf4011e77, 0xfa000074, 2459 2459 + 0xbf8cc07f, 0x876dff6d, 2460 2460 + 0x0000ffff, 0x87fe7e7e, 2461 2461 + 0x87ea6a6a, 0xb9faf802, 2462 2462 + 0xbe80226c, 0xbf810000, 2463 2463 + 0xbf9f0000, 0xbf9f0000, 2464 2464 + 0xbf9f0000, 0xbf9f0000, 2465 2465 + 0xbf9f0000, 0x00000000, 2466 2466 + }; 2467 2467 + 2468 2468 + static const uint32_t cwsr_trap_gfx11_hex[] = { 2469 2469 + 0xbfa00001, 0xbfa0021b, 2470 2470 + 0xb0804006, 0xb8f8f802, 2471 2471 + 0x91788678, 0xb8fbf803, 2472 2472 + 0x8b6eff78, 0x00002000, 2473 2473 + 0xbfa10009, 0x8b6eff6d, 2474 2474 + 0x00ff0000, 0xbfa2001e, 2475 2475 + 0x8b6eff7b, 0x00000400, 2476 2476 + 0xbfa20041, 0xbf830010, 2477 2477 + 0xb8fbf803, 0xbfa0fffa, 2478 2478 + 0x8b6eff7b, 0x00000900, 2479 2479 + 0xbfa20015, 0x8b6eff7b, 2480 2480 + 0x000071ff, 0xbfa10008, 2481 2481 + 0x8b6fff7b, 0x00007080, 2482 2482 + 0xbfa10001, 0xbeee1287, 2483 2483 + 0xb8eff801, 0x846e8c6e, 2484 2484 + 0x8b6e6f6e, 0xbfa2000a, 2485 2485 + 0x8b6eff6d, 0x00ff0000, 2486 2486 + 0xbfa20007, 0xb8eef801, 2487 2487 + 0x8b6eff6e, 0x00000800, 2488 2488 + 0xbfa20003, 0x8b6eff7b, 2489 2489 + 0x00000400, 0xbfa20026, 2490 2490 + 0xbefa4d82, 0xbf89fc07, 2491 2491 + 0x84fa887a, 0xf4005bbd, 2492 2492 + 0xf8000010, 0xbf89fc07, 2493 2493 + 0x846e976e, 0x9177ff77, 2494 2494 + 0x00800000, 0x8c776e77, 2495 2495 + 0xf4045bbd, 0xf8000000, 2496 2496 + 0xbf89fc07, 0xf4045ebd, 2497 2497 + 0xf8000008, 0xbf89fc07, 2498 2498 + 0x8bee6e6e, 0xbfa10001, 2499 2499 + 0xbe80486e, 0x8b6eff6d, 2500 2500 + 0x01ff0000, 0xbfa20005, 2501 2501 + 0x8c78ff78, 0x00002000, 2502 2502 + 0x80ec886c, 0x82ed806d, 2503 2503 + 0xbfa00005, 0x8b6eff6d, 2504 2504 + 0x01000000, 0xbfa20002, 2505 2505 + 0x806c846c, 0x826d806d, 2506 2506 + 0x8b6dff6d, 0x0000ffff, 2507 2507 + 0x8bfe7e7e, 0x8bea6a6a, 2508 2508 + 0xb978f802, 0xbe804a6c, 2509 2509 + 0x8b6dff6d, 0x0000ffff, 2510 2510 + 0xbefa0080, 0xb97a0283, 2511 2511 + 0xbeee007e, 0xbeef007f, 2512 2512 + 0xbefe0180, 0xbefe4d84, 2513 2513 + 0xbf89fc07, 0x8b7aff7f, 2514 2514 + 0x04000000, 0x847a857a, 2515 2515 + 0x8c6d7a6d, 0xbefa007e, 2516 2516 + 0x8b7bff7f, 0x0000ffff, 2517 2517 + 0xbefe00c1, 0xbeff00c1, 2518 2518 + 0xdca6c000, 0x007a0000, 2519 2519 + 0x7e000280, 0xbefe007a, 2520 2520 + 0xbeff007b, 0xb8fb02dc, 2521 2521 + 0x847b997b, 0xb8fa3b05, 2522 2522 + 0x807a817a, 0xbf0d997b, 2523 2523 + 0xbfa20002, 0x847a897a, 2524 2524 + 0xbfa00001, 0x847a8a7a, 2525 2525 + 0xb8fb1e06, 0x847b8a7b, 2526 2526 + 0x807a7b7a, 0x8b7bff7f, 2527 2527 + 0x0000ffff, 0x807aff7a, 2528 2528 + 0x00000200, 0x807a7e7a, 2529 2529 + 0x827b807b, 0xd7610000, 2530 2530 + 0x00010870, 0xd7610000, 2531 2531 + 0x00010a71, 0xd7610000, 2532 2532 + 0x00010c72, 0xd7610000, 2533 2533 + 0x00010e73, 0xd7610000, 2534 2534 + 0x00011074, 0xd7610000, 2535 2535 + 0x00011275, 0xd7610000, 2536 2536 + 0x00011476, 0xd7610000, 2537 2537 + 0x00011677, 0xd7610000, 2538 2538 + 0x00011a79, 0xd7610000, 2539 2539 + 0x00011c7e, 0xd7610000, 2540 2540 + 0x00011e7f, 0xbefe00ff, 2541 2541 + 0x00003fff, 0xbeff0080, 2542 2542 + 0xdca6c040, 0x007a0000, 2543 2543 + 0xd760007a, 0x00011d00, 2544 2544 + 0xd760007b, 0x00011f00, 2545 2545 + 0xbefe007a, 0xbeff007b, 2546 2546 + 0xbef4007e, 0x8b75ff7f, 2547 2547 + 0x0000ffff, 0x8c75ff75, 2548 2548 + 0x00040000, 0xbef60080, 2549 2549 + 0xbef700ff, 0x10807fac, 2550 2550 + 0xbef1007d, 0xbef00080, 2551 2551 + 0xb8f302dc, 0x84739973, 2552 2552 + 0xbefe00c1, 0x857d9973, 2553 2553 + 0x8b7d817d, 0xbf06817d, 2554 2554 + 0xbfa20002, 0xbeff0080, 2555 2555 + 0xbfa00002, 0xbeff00c1, 2556 2556 + 0xbfa00009, 0xbef600ff, 2557 2557 + 0x01000000, 0xe0685080, 2558 2558 + 0x701d0100, 0xe0685100, 2559 2559 + 0x701d0200, 0xe0685180, 2560 2560 + 0x701d0300, 0xbfa00008, 2561 2561 + 0xbef600ff, 0x01000000, 2562 2562 + 0xe0685100, 0x701d0100, 2563 2563 + 0xe0685200, 0x701d0200, 2564 2564 + 0xe0685300, 0x701d0300, 2565 2565 + 0xb8f03b05, 0x80708170, 2566 2566 + 0xbf0d9973, 0xbfa20002, 2567 2567 + 0x84708970, 0xbfa00001, 2568 2568 + 0x84708a70, 0xb8fa1e06, 2569 2569 + 0x847a8a7a, 0x80707a70, 2570 2570 + 0x8070ff70, 0x00000200, 2571 2571 + 0xbef600ff, 0x01000000, 2572 2572 + 0x7e000280, 0x7e020280, 2573 2573 + 0x7e040280, 0xbefd0080, 2574 2574 + 0xd7610002, 0x0000fa71, 2575 2575 + 0x807d817d, 0xd7610002, 2576 2576 + 0x0000fa6c, 0x807d817d, 2577 2577 + 0x917aff6d, 0x80000000, 2578 2578 + 0xd7610002, 0x0000fa7a, 2579 2579 + 0x807d817d, 0xd7610002, 2580 2580 + 0x0000fa6e, 0x807d817d, 2581 2581 + 0xd7610002, 0x0000fa6f, 2582 2582 + 0x807d817d, 0xd7610002, 2583 2583 + 0x0000fa78, 0x807d817d, 2584 2584 + 0xb8faf803, 0xd7610002, 2585 2585 + 0x0000fa7a, 0x807d817d, 2586 2586 + 0xd7610002, 0x0000fa7b, 2587 2587 + 0x807d817d, 0xb8f1f801, 2588 2588 + 0xd7610002, 0x0000fa71, 2589 2589 + 0x807d817d, 0xb8f1f814, 2590 2590 + 0xd7610002, 0x0000fa71, 2591 2591 + 0x807d817d, 0xb8f1f815, 2592 2592 + 0xd7610002, 0x0000fa71, 2593 2593 + 0x807d817d, 0xbefe00ff, 2594 2594 + 0x0000ffff, 0xbeff0080, 2595 2595 + 0xe0685000, 0x701d0200, 2596 2596 + 0xbefe00c1, 0xb8f03b05, 2597 2597 + 0x80708170, 0xbf0d9973, 2598 2598 + 0xbfa20002, 0x84708970, 2599 2599 + 0xbfa00001, 0x84708a70, 2600 2600 + 0xb8fa1e06, 0x847a8a7a, 2601 2601 + 0x80707a70, 0xbef600ff, 2602 2602 + 0x01000000, 0xbef90080, 2603 2603 + 0xbefd0080, 0xbf800000, 2604 2604 + 0xbe804100, 0xbe824102, 2605 2605 + 0xbe844104, 0xbe864106, 2606 2606 + 0xbe884108, 0xbe8a410a, 2607 2607 + 0xbe8c410c, 0xbe8e410e, 2202 2608 0xd7610002, 0x0000f200, 2203 2609 0x80798179, 0xd7610002, 2204 2610 0x0000f201, 0x80798179, ··· 2659 2193 0xd7610002, 0x0000f20e, 2660 2194 0x80798179, 0xd7610002, 2661 2195 0x0000f20f, 0x80798179, 2662 2662 - 0xbf06a079, 0xbf840006, 2663 2663 - 0xe0704000, 0x705d0200, 2196 2196 + 0xbf06a079, 0xbfa10006, 2197 2197 + 0xe0685000, 0x701d0200, 2664 2198 0x8070ff70, 0x00000080, 2665 2665 - 0xbef90380, 0x7e040280, 2666 2666 - 0x807c907c, 0xbf0aff7c, 2667 2667 - 0x00000060, 0xbf85ffbc, 2668 2668 - 0xbe802f00, 0xbe822f02, 2669 2669 - 0xbe842f04, 0xbe862f06, 2670 2670 - 0xbe882f08, 0xbe8a2f0a, 2199 2199 + 0xbef90080, 0x7e040280, 2200 2200 + 0x807d907d, 0xbf0aff7d, 2201 2201 + 0x00000060, 0xbfa2ffbc, 2202 2202 + 0xbe804100, 0xbe824102, 2203 2203 + 0xbe844104, 0xbe864106, 2204 2204 + 0xbe884108, 0xbe8a410a, 2671 2205 0xd7610002, 0x0000f200, 2672 2206 0x80798179, 0xd7610002, 2673 2207 0x0000f201, 0x80798179, ··· 2686 2220 0xd7610002, 0x0000f20a, 2687 2221 0x80798179, 0xd7610002, 2688 2222 0x0000f20b, 0x80798179, 2689 2689 - 0xe0704000, 0x705d0200, 2690 2690 - 0xbefe03c1, 0x907c9973, 2691 2691 - 0x877c817c, 0xbf06817c, 2692 2692 - 0xbf850002, 0xbeff0380, 2693 2693 - 0xbf820001, 0xbeff03c1, 2694 2694 - 0xb97b4306, 0x877bc17b, 2695 2695 - 0xbf840044, 0xbf8a0000, 2696 2696 - 0x877aff73, 0x04000000, 2697 2697 - 0xbf840040, 0x8f7b867b, 2698 2698 - 0x8f7b827b, 0xbef6037b, 2699 2699 - 0xb9702a05, 0x80708170, 2700 2700 - 0xbf0d9973, 0xbf850002, 2701 2701 - 0x8f708970, 0xbf820001, 2702 2702 - 0x8f708a70, 0xb97a1e06, 2703 2703 - 0x8f7a8a7a, 0x80707a70, 2223 2223 + 0xe0685000, 0x701d0200, 2224 2224 + 0xbefe00c1, 0x857d9973, 2225 2225 + 0x8b7d817d, 0xbf06817d, 2226 2226 + 0xbfa20002, 0xbeff0080, 2227 2227 + 0xbfa00001, 0xbeff00c1, 2228 2228 + 0xb8fb4306, 0x8b7bc17b, 2229 2229 + 0xbfa10044, 0xbfbd0000, 2230 2230 + 0x8b7aff6d, 0x80000000, 2231 2231 + 0xbfa10040, 0x847b867b, 2232 2232 + 0x847b827b, 0xbef6007b, 2233 2233 + 0xb8f03b05, 0x80708170, 2234 2234 + 0xbf0d9973, 0xbfa20002, 2235 2235 + 0x84708970, 0xbfa00001, 2236 2236 + 0x84708a70, 0xb8fa1e06, 2237 2237 + 0x847a8a7a, 0x80707a70, 2704 2238 0x8070ff70, 0x00000200, 2705 2239 0x8070ff70, 0x00000080, 2706 2706 - 0xbef603ff, 0x01000000, 2707 2707 - 0xd7650000, 0x000100c1, 2708 2708 - 0xd7660000, 0x000200c1, 2709 2709 - 0x16000084, 0x907c9973, 2710 2710 - 0x877c817c, 0xbf06817c, 2711 2711 - 0xbefc0380, 0xbf850012, 2712 2712 - 0xbe8303ff, 0x00000080, 2240 2240 + 0xbef600ff, 0x01000000, 2241 2241 + 0xd71f0000, 0x000100c1, 2242 2242 + 0xd7200000, 0x000200c1, 2243 2243 + 0x16000084, 0x857d9973, 2244 2244 + 0x8b7d817d, 0xbf06817d, 2245 2245 + 0xbefd0080, 0xbfa20012, 2246 2246 + 0xbe8300ff, 0x00000080, 2713 2247 0xbf800000, 0xbf800000, 2714 2248 0xbf800000, 0xd8d80000, 2715 2715 - 0x01000000, 0xbf8c0000, 2716 2716 - 0xe0704000, 0x705d0100, 2717 2717 - 0x807c037c, 0x80700370, 2249 2249 + 0x01000000, 0xbf890000, 2250 2250 + 0xe0685000, 0x701d0100, 2251 2251 + 0x807d037d, 0x80700370, 2718 2252 0xd5250000, 0x0001ff00, 2719 2719 - 0x00000080, 0xbf0a7b7c, 2720 2720 - 0xbf85fff4, 0xbf820011, 2721 2721 - 0xbe8303ff, 0x00000100, 2253 2253 + 0x00000080, 0xbf0a7b7d, 2254 2254 + 0xbfa2fff4, 0xbfa00011, 2255 2255 + 0xbe8300ff, 0x00000100, 2722 2256 0xbf800000, 0xbf800000, 2723 2257 0xbf800000, 0xd8d80000, 2724 2724 - 0x01000000, 0xbf8c0000, 2725 2725 - 0xe0704000, 0x705d0100, 2726 2726 - 0x807c037c, 0x80700370, 2258 2258 + 0x01000000, 0xbf890000, 2259 2259 + 0xe0685000, 0x701d0100, 2260 2260 + 0x807d037d, 0x80700370, 2727 2261 0xd5250000, 0x0001ff00, 2728 2728 - 0x00000100, 0xbf0a7b7c, 2729 2729 - 0xbf85fff4, 0xbefe03c1, 2730 2730 - 0x907c9973, 0x877c817c, 2731 2731 - 0xbf06817c, 0xbf850004, 2732 2732 - 0xbef003ff, 0x00000200, 2733 2733 - 0xbeff0380, 0xbf820003, 2734 2734 - 0xbef003ff, 0x00000400, 2735 2735 - 0xbeff03c1, 0xb97b2a05, 2736 2736 - 0x807b817b, 0x8f7b827b, 2737 2737 - 0x907c9973, 0x877c817c, 2738 2738 - 0xbf06817c, 0xbf850017, 2739 2739 - 0xbef603ff, 0x01000000, 2740 2740 - 0xbefc0384, 0xbf0a7b7c, 2741 2741 - 0xbf840037, 0x7e008700, 2262 2262 + 0x00000100, 0xbf0a7b7d, 2263 2263 + 0xbfa2fff4, 0xbefe00c1, 2264 2264 + 0x857d9973, 0x8b7d817d, 2265 2265 + 0xbf06817d, 0xbfa20004, 2266 2266 + 0xbef000ff, 0x00000200, 2267 2267 + 0xbeff0080, 0xbfa00003, 2268 2268 + 0xbef000ff, 0x00000400, 2269 2269 + 0xbeff00c1, 0xb8fb3b05, 2270 2270 + 0x807b817b, 0x847b827b, 2271 2271 + 0x857d9973, 0x8b7d817d, 2272 2272 + 0xbf06817d, 0xbfa20017, 2273 2273 + 0xbef600ff, 0x01000000, 2274 2274 + 0xbefd0084, 0xbf0a7b7d, 2275 2275 + 0xbfa10037, 0x7e008700, 2742 2276 0x7e028701, 0x7e048702, 2743 2743 - 0x7e068703, 0xe0704000, 2744 2744 - 0x705d0000, 0xe0704080, 2745 2745 - 0x705d0100, 0xe0704100, 2746 2746 - 0x705d0200, 0xe0704180, 2747 2747 - 0x705d0300, 0x807c847c, 2277 2277 + 0x7e068703, 0xe0685000, 2278 2278 + 0x701d0000, 0xe0685080, 2279 2279 + 0x701d0100, 0xe0685100, 2280 2280 + 0x701d0200, 0xe0685180, 2281 2281 + 0x701d0300, 0x807d847d, 2748 2282 0x8070ff70, 0x00000200, 2749 2749 - 0xbf0a7b7c, 0xbf85ffef, 2750 2750 - 0xbf820025, 0xbef603ff, 2751 2751 - 0x01000000, 0xbefc0384, 2752 2752 - 0xbf0a7b7c, 0xbf840020, 2283 2283 + 0xbf0a7b7d, 0xbfa2ffef, 2284 2284 + 0xbfa00025, 0xbef600ff, 2285 2285 + 0x01000000, 0xbefd0084, 2286 2286 + 0xbf0a7b7d, 0xbfa10011, 2753 2287 0x7e008700, 0x7e028701, 2754 2288 0x7e048702, 0x7e068703, 2755 2755 - 0xe0704000, 0x705d0000, 2756 2756 - 0xe0704100, 0x705d0100, 2757 2757 - 0xe0704200, 0x705d0200, 2758 2758 - 0xe0704300, 0x705d0300, 2759 2759 - 0x807c847c, 0x8070ff70, 2760 2760 - 0x00000400, 0xbf0a7b7c, 2761 2761 - 0xbf85ffef, 0xb97b1e06, 2762 2762 - 0x877bc17b, 0xbf84000c, 2763 2763 - 0x8f7b837b, 0x807b7c7b, 2764 2764 - 0xbefe03c1, 0xbeff0380, 2765 2765 - 0x7e008700, 0xe0704000, 2766 2766 - 0x705d0000, 0x807c817c, 2289 2289 + 0xe0685000, 0x701d0000, 2290 2290 + 0xe0685100, 0x701d0100, 2291 2291 + 0xe0685200, 0x701d0200, 2292 2292 + 0xe0685300, 0x701d0300, 2293 2293 + 0x807d847d, 0x8070ff70, 2294 2294 + 0x00000400, 0xbf0a7b7d, 2295 2295 + 0xbfa2ffef, 0xb8fb1e06, 2296 2296 + 0x8b7bc17b, 0xbfa1000c, 2297 2297 + 0x847b837b, 0x807b7d7b, 2298 2298 + 0xbefe00c1, 0xbeff0080, 2299 2299 + 0x7e008700, 0xe0685000, 2300 2300 + 0x701d0000, 0x807d817d, 2767 2301 0x8070ff70, 0x00000080, 2768 2768 - 0xbf0a7b7c, 0xbf85fff8, 2769 2769 - 0xbf82013c, 0xbef4037e, 2770 2770 - 0x8775ff7f, 0x0000ffff, 2771 2771 - 0x8875ff75, 0x00040000, 2772 2772 - 0xbef60380, 0xbef703ff, 2773 2773 - 0x10807fac, 0x876eff7f, 2774 2774 - 0x08000000, 0x906e836e, 2775 2775 - 0x88776e77, 0x876eff7f, 2776 2776 - 0x70000000, 0x906e816e, 2777 2777 - 0x88776e77, 0xb97202dc, 2778 2778 - 0x8f729972, 0x8872727f, 2779 2779 - 0x876eff7f, 0x04000000, 2780 2780 - 0xbf840034, 0xbefe03c1, 2781 2781 - 0x907c9972, 0x877c817c, 2782 2782 - 0xbf06817c, 0xbf850002, 2783 2783 - 0xbeff0380, 0xbf820001, 2784 2784 - 0xbeff03c1, 0xb96f4306, 2785 2785 - 0x876fc16f, 0xbf840029, 2786 2786 - 0x8f6f866f, 0x8f6f826f, 2787 2787 - 0xbef6036f, 0xb9782a05, 2788 2788 - 0x80788178, 0xbf0d9972, 2789 2789 - 0xbf850002, 0x8f788978, 2790 2790 - 0xbf820001, 0x8f788a78, 2791 2791 - 0xb96e1e06, 0x8f6e8a6e, 2792 2792 - 0x80786e78, 0x8078ff78, 2793 2793 - 0x00000200, 0x8078ff78, 2794 2794 - 0x00000080, 0xbef603ff, 2795 2795 - 0x01000000, 0x907c9972, 2796 2796 - 0x877c817c, 0xbf06817c, 2797 2797 - 0xbefc0380, 0xbf850009, 2798 2798 - 0xe0310000, 0x781d0000, 2799 2799 - 0x807cff7c, 0x00000080, 2800 2800 - 0x8078ff78, 0x00000080, 2801 2801 - 0xbf0a6f7c, 0xbf85fff8, 2802 2802 - 0xbf820008, 0xe0310000, 2803 2803 - 0x781d0000, 0x807cff7c, 2804 2804 - 0x00000100, 0x8078ff78, 2805 2805 - 0x00000100, 0xbf0a6f7c, 2806 2806 - 0xbf85fff8, 0xbef80380, 2807 2807 - 0xbefe03c1, 0x907c9972, 2808 2808 - 0x877c817c, 0xbf06817c, 2809 2809 - 0xbf850002, 0xbeff0380, 2810 2810 - 0xbf820001, 0xbeff03c1, 2811 2811 - 0xb96f2a05, 0x806f816f, 2812 2812 - 0x8f6f826f, 0x907c9972, 2813 2813 - 0x877c817c, 0xbf06817c, 2814 2814 - 0xbf850021, 0xbef603ff, 2815 2815 - 0x01000000, 0xbeee0378, 2302 2302 + 0xbf0a7b7d, 0xbfa2fff8, 2303 2303 + 0xbfa00141, 0xbef4007e, 2304 2304 + 0x8b75ff7f, 0x0000ffff, 2305 2305 + 0x8c75ff75, 0x00040000, 2306 2306 + 0xbef60080, 0xbef700ff, 2307 2307 + 0x10807fac, 0xb8f202dc, 2308 2308 + 0x84729972, 0x8b6eff7f, 2309 2309 + 0x04000000, 0xbfa1003a, 2310 2310 + 0xbefe00c1, 0x857d9972, 2311 2311 + 0x8b7d817d, 0xbf06817d, 2312 2312 + 0xbfa20002, 0xbeff0080, 2313 2313 + 0xbfa00001, 0xbeff00c1, 2314 2314 + 0xb8ef4306, 0x8b6fc16f, 2315 2315 + 0xbfa1002f, 0x846f866f, 2316 2316 + 0x846f826f, 0xbef6006f, 2317 2317 + 0xb8f83b05, 0x80788178, 2318 2318 + 0xbf0d9972, 0xbfa20002, 2319 2319 + 0x84788978, 0xbfa00001, 2320 2320 + 0x84788a78, 0xb8ee1e06, 2321 2321 + 0x846e8a6e, 0x80786e78, 2816 2322 0x8078ff78, 0x00000200, 2817 2817 - 0xbefc0384, 0xe0304000, 2818 2818 - 0x785d0000, 0xe0304080, 2819 2819 - 0x785d0100, 0xe0304100, 2820 2820 - 0x785d0200, 0xe0304180, 2821 2821 - 0x785d0300, 0xbf8c3f70, 2822 2822 - 0x7e008500, 0x7e028501, 2823 2823 - 0x7e048502, 0x7e068503, 2824 2824 - 0x807c847c, 0x8078ff78, 2825 2825 - 0x00000200, 0xbf0a6f7c, 2826 2826 - 0xbf85ffee, 0xe0304000, 2827 2827 - 0x6e5d0000, 0xe0304080, 2828 2828 - 0x6e5d0100, 0xe0304100, 2829 2829 - 0x6e5d0200, 0xe0304180, 2830 2830 - 0x6e5d0300, 0xbf820032, 2831 2831 - 0xbef603ff, 0x01000000, 2832 2832 - 0xbeee0378, 0x8078ff78, 2833 2833 - 0x00000400, 0xbefc0384, 2834 2834 - 0xe0304000, 0x785d0000, 2835 2835 - 0xe0304100, 0x785d0100, 2836 2836 - 0xe0304200, 0x785d0200, 2837 2837 - 0xe0304300, 0x785d0300, 2838 2838 - 0xbf8c3f70, 0x7e008500, 2839 2839 - 0x7e028501, 0x7e048502, 2840 2840 - 0x7e068503, 0x807c847c, 2841 2841 - 0x8078ff78, 0x00000400, 2842 2842 - 0xbf0a6f7c, 0xbf85ffee, 2843 2843 - 0xb96f1e06, 0x876fc16f, 2844 2844 - 0xbf84000e, 0x8f6f836f, 2845 2845 - 0x806f7c6f, 0xbefe03c1, 2846 2846 - 0xbeff0380, 0xe0304000, 2847 2847 - 0x785d0000, 0xbf8c3f70, 2848 2848 - 0x7e008500, 0x807c817c, 2849 2323 0x8078ff78, 0x00000080, 2850 2850 - 0xbf0a6f7c, 0xbf85fff7, 2851 2851 - 0xbeff03c1, 0xe0304000, 2852 2852 - 0x6e5d0000, 0xe0304100, 2853 2853 - 0x6e5d0100, 0xe0304200, 2854 2854 - 0x6e5d0200, 0xe0304300, 2855 2855 - 0x6e5d0300, 0xbf8c3f70, 2856 2856 - 0xb9782a05, 0x80788178, 2857 2857 - 0xbf0d9972, 0xbf850002, 2858 2858 - 0x8f788978, 0xbf820001, 2859 2859 - 0x8f788a78, 0xb96e1e06, 2860 2860 - 0x8f6e8a6e, 0x80786e78, 2324 2324 + 0xbef600ff, 0x01000000, 2325 2325 + 0x857d9972, 0x8b7d817d, 2326 2326 + 0xbf06817d, 0xbefd0080, 2327 2327 + 0xbfa2000c, 0xe0500000, 2328 2328 + 0x781d0000, 0xbf8903f7, 2329 2329 + 0xdac00000, 0x00000000, 2330 2330 + 0x807dff7d, 0x00000080, 2331 2331 + 0x8078ff78, 0x00000080, 2332 2332 + 0xbf0a6f7d, 0xbfa2fff5, 2333 2333 + 0xbfa0000b, 0xe0500000, 2334 2334 + 0x781d0000, 0xbf8903f7, 2335 2335 + 0xdac00000, 0x00000000, 2336 2336 + 0x807dff7d, 0x00000100, 2337 2337 + 0x8078ff78, 0x00000100, 2338 2338 + 0xbf0a6f7d, 0xbfa2fff5, 2339 2339 + 0xbef80080, 0xbefe00c1, 2340 2340 + 0x857d9972, 0x8b7d817d, 2341 2341 + 0xbf06817d, 0xbfa20002, 2342 2342 + 0xbeff0080, 0xbfa00001, 2343 2343 + 0xbeff00c1, 0xb8ef3b05, 2344 2344 + 0x806f816f, 0x846f826f, 2345 2345 + 0x857d9972, 0x8b7d817d, 2346 2346 + 0xbf06817d, 0xbfa20024, 2347 2347 + 0xbef600ff, 0x01000000, 2348 2348 + 0xbeee0078, 0x8078ff78, 2349 2349 + 0x00000200, 0xbefd0084, 2350 2350 + 0xbf0a6f7d, 0xbfa10050, 2351 2351 + 0xe0505000, 0x781d0000, 2352 2352 + 0xe0505080, 0x781d0100, 2353 2353 + 0xe0505100, 0x781d0200, 2354 2354 + 0xe0505180, 0x781d0300, 2355 2355 + 0xbf8903f7, 0x7e008500, 2356 2356 + 0x7e028501, 0x7e048502, 2357 2357 + 0x7e068503, 0x807d847d, 2358 2358 + 0x8078ff78, 0x00000200, 2359 2359 + 0xbf0a6f7d, 0xbfa2ffee, 2360 2360 + 0xe0505000, 0x6e1d0000, 2361 2361 + 0xe0505080, 0x6e1d0100, 2362 2362 + 0xe0505100, 0x6e1d0200, 2363 2363 + 0xe0505180, 0x6e1d0300, 2364 2364 + 0xbf8903f7, 0xbfa00034, 2365 2365 + 0xbef600ff, 0x01000000, 2366 2366 + 0xbeee0078, 0x8078ff78, 2367 2367 + 0x00000400, 0xbefd0084, 2368 2368 + 0xbf0a6f7d, 0xbfa10012, 2369 2369 + 0xe0505000, 0x781d0000, 2370 2370 + 0xe0505100, 0x781d0100, 2371 2371 + 0xe0505200, 0x781d0200, 2372 2372 + 0xe0505300, 0x781d0300, 2373 2373 + 0xbf8903f7, 0x7e008500, 2374 2374 + 0x7e028501, 0x7e048502, 2375 2375 + 0x7e068503, 0x807d847d, 2376 2376 + 0x8078ff78, 0x00000400, 2377 2377 + 0xbf0a6f7d, 0xbfa2ffee, 2378 2378 + 0xb8ef1e06, 0x8b6fc16f, 2379 2379 + 0xbfa1000e, 0x846f836f, 2380 2380 + 0x806f7d6f, 0xbefe00c1, 2381 2381 + 0xbeff0080, 0xe0505000, 2382 2382 + 0x781d0000, 0xbf8903f7, 2383 2383 + 0x7e008500, 0x807d817d, 2384 2384 + 0x8078ff78, 0x00000080, 2385 2385 + 0xbf0a6f7d, 0xbfa2fff7, 2386 2386 + 0xbeff00c1, 0xe0505000, 2387 2387 + 0x6e1d0000, 0xe0505100, 2388 2388 + 0x6e1d0100, 0xe0505200, 2389 2389 + 0x6e1d0200, 0xe0505300, 2390 2390 + 0x6e1d0300, 0xbf8903f7, 2391 2391 + 0xb8f83b05, 0x80788178, 2392 2392 + 0xbf0d9972, 0xbfa20002, 2393 2393 + 0x84788978, 0xbfa00001, 2394 2394 + 0x84788a78, 0xb8ee1e06, 2395 2395 + 0x846e8a6e, 0x80786e78, 2861 2396 0x8078ff78, 0x00000200, 2862 2397 0x80f8ff78, 0x00000050, 2863 2863 - 0xbef603ff, 0x01000000, 2864 2864 - 0xbefc03ff, 0x0000006c, 2865 2865 - 0x80f89078, 0xf429003a, 2866 2866 - 0xf0000000, 0xbf8cc07f, 2867 2867 - 0x80fc847c, 0xbf800000, 2868 2868 - 0xbe803100, 0xbe823102, 2869 2869 - 0x80f8a078, 0xf42d003a, 2870 2870 - 0xf0000000, 0xbf8cc07f, 2871 2871 - 0x80fc887c, 0xbf800000, 2872 2872 - 0xbe803100, 0xbe823102, 2873 2873 - 0xbe843104, 0xbe863106, 2874 2874 - 0x80f8c078, 0xf431003a, 2875 2875 - 0xf0000000, 0xbf8cc07f, 2876 2876 - 0x80fc907c, 0xbf800000, 2877 2877 - 0xbe803100, 0xbe823102, 2878 2878 - 0xbe843104, 0xbe863106, 2879 2879 - 0xbe883108, 0xbe8a310a, 2880 2880 - 0xbe8c310c, 0xbe8e310e, 2881 2881 - 0xbf06807c, 0xbf84fff0, 2882 2882 - 0xba80f801, 0x00000000, 2883 2883 - 0xbf8a0000, 0xb9782a05, 2398 2398 + 0xbef600ff, 0x01000000, 2399 2399 + 0xbefd00ff, 0x0000006c, 2400 2400 + 0x80f89078, 0xf428403a, 2401 2401 + 0xf0000000, 0xbf89fc07, 2402 2402 + 0x80fd847d, 0xbf800000, 2403 2403 + 0xbe804300, 0xbe824302, 2404 2404 + 0x80f8a078, 0xf42c403a, 2405 2405 + 0xf0000000, 0xbf89fc07, 2406 2406 + 0x80fd887d, 0xbf800000, 2407 2407 + 0xbe804300, 0xbe824302, 2408 2408 + 0xbe844304, 0xbe864306, 2409 2409 + 0x80f8c078, 0xf430403a, 2410 2410 + 0xf0000000, 0xbf89fc07, 2411 2411 + 0x80fd907d, 0xbf800000, 2412 2412 + 0xbe804300, 0xbe824302, 2413 2413 + 0xbe844304, 0xbe864306, 2414 2414 + 0xbe884308, 0xbe8a430a, 2415 2415 + 0xbe8c430c, 0xbe8e430e, 2416 2416 + 0xbf06807d, 0xbfa1fff0, 2417 2417 + 0xb980f801, 0x00000000, 2418 2418 + 0xbfbd0000, 0xb8f83b05, 2884 2419 0x80788178, 0xbf0d9972, 2885 2885 - 0xbf850002, 0x8f788978, 2886 2886 - 0xbf820001, 0x8f788a78, 2887 2887 - 0xb96e1e06, 0x8f6e8a6e, 2420 2420 + 0xbfa20002, 0x84788978, 2421 2421 + 0xbfa00001, 0x84788a78, 2422 2422 + 0xb8ee1e06, 0x846e8a6e, 2888 2423 0x80786e78, 0x8078ff78, 2889 2889 - 0x00000200, 0xbef603ff, 2890 2890 - 0x01000000, 0xf4211bfa, 2424 2424 + 0x00000200, 0xbef600ff, 2425 2425 + 0x01000000, 0xf4205bfa, 2891 2426 0xf0000000, 0x80788478, 2892 2892 - 0xf4211b3a, 0xf0000000, 2893 2893 - 0x80788478, 0xf4211b7a, 2427 2427 + 0xf4205b3a, 0xf0000000, 2428 2428 + 0x80788478, 0xf4205b7a, 2894 2429 0xf0000000, 0x80788478, 2895 2895 - 0xf4211c3a, 0xf0000000, 2896 2896 - 0x80788478, 0xf4211c7a, 2430 2430 + 0xf4205c3a, 0xf0000000, 2431 2431 + 0x80788478, 0xf4205c7a, 2897 2432 0xf0000000, 0x80788478, 2898 2898 - 0xf4211eba, 0xf0000000, 2899 2899 - 0x80788478, 0xf4211efa, 2433 2433 + 0xf4205eba, 0xf0000000, 2434 2434 + 0x80788478, 0xf4205efa, 2900 2435 0xf0000000, 0x80788478, 2901 2901 - 0xf4211e7a, 0xf0000000, 2902 2902 - 0x80788478, 0xf4211cfa, 2436 2436 + 0xf4205e7a, 0xf0000000, 2437 2437 + 0x80788478, 0xf4205cfa, 2903 2438 0xf0000000, 0x80788478, 2904 2904 - 0xf4211bba, 0xf0000000, 2905 2905 - 0x80788478, 0xbf8cc07f, 2906 2906 - 0xb9eef814, 0xf4211bba, 2439 2439 + 0xf4205bba, 0xf0000000, 2440 2440 + 0x80788478, 0xbf89fc07, 2441 2441 + 0xb96ef814, 0xf4205bba, 2907 2442 0xf0000000, 0x80788478, 2908 2908 - 0xbf8cc07f, 0xb9eef815, 2909 2909 - 0xbefc036f, 0xbefe0370, 2910 2910 - 0xbeff0371, 0x876f7bff, 2911 2911 - 0x000003ff, 0xb9ef4803, 2912 2912 - 0x876f7bff, 0xfffff800, 2913 2913 - 0x906f8b6f, 0xb9efa2c3, 2914 2914 - 0xb9f3f801, 0xb96e2a05, 2443 2443 + 0xbf89fc07, 0xb96ef815, 2444 2444 + 0xbefd006f, 0xbefe0070, 2445 2445 + 0xbeff0071, 0x8b6f7bff, 2446 2446 + 0x000003ff, 0xb96f4803, 2447 2447 + 0x8b6f7bff, 0xfffff800, 2448 2448 + 0x856f8b6f, 0xb96fa2c3, 2449 2449 + 0xb973f801, 0xb8ee3b05, 2915 2450 0x806e816e, 0xbf0d9972, 2916 2916 - 0xbf850002, 0x8f6e896e, 2917 2917 - 0xbf820001, 0x8f6e8a6e, 2918 2918 - 0x806eff6e, 0x00000200, 2919 2919 - 0x806e746e, 0x826f8075, 2920 2920 - 0x876fff6f, 0x0000ffff, 2921 2921 - 0xf4091c37, 0xfa000050, 2922 2922 - 0xf4091d37, 0xfa000060, 2923 2923 - 0xf4011e77, 0xfa000074, 2924 2924 - 0xbf8cc07f, 0x876dff6d, 2925 2925 - 0x0000ffff, 0x87fe7e7e, 2926 2926 - 0x87ea6a6a, 0xb9faf802, 2927 2927 - 0xbe80226c, 0xbf810000, 2451 2451 + 0xbfa20002, 0x846e896e, 2452 2452 + 0xbfa00001, 0x846e8a6e, 2453 2453 + 0xb8ef1e06, 0x846f8a6f, 2454 2454 + 0x806e6f6e, 0x806eff6e, 2455 2455 + 0x00000200, 0x806e746e, 2456 2456 + 0x826f8075, 0x8b6fff6f, 2457 2457 + 0x0000ffff, 0xf4085c37, 2458 2458 + 0xf8000050, 0xf4085d37, 2459 2459 + 0xf8000060, 0xf4005e77, 2460 2460 + 0xf8000074, 0xbf89fc07, 2461 2461 + 0x8b6dff6d, 0x0000ffff, 2462 2462 + 0x8bfe7e7e, 0x8bea6a6a, 2463 2463 + 0xb97af802, 0xbe804a6c, 2464 2464 + 0xbfb00000, 0xbf9f0000, 2928 2465 0xbf9f0000, 0xbf9f0000, 2929 2466 0xbf9f0000, 0xbf9f0000, 2930 2930 - 0xbf9f0000, 0x00000000, 2931 2467 };

+254 -148

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm

reviewed

··· 23 23 /* To compile this assembly code: 24 24 * 25 25 * Navi1x: 26 26 - * cpp -DASIC_TARGET_NAVI1X=1 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3 27 27 - * sp3-nv1x nv1x.sp3 -hex nv1x.hex 26 26 + * cpp -DASIC_FAMILY=CHIP_NAVI10 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3 27 27 + * sp3 nv1x.sp3 -hex nv1x.hex 28 28 * 29 29 - * Others: 30 30 - * cpp -DASIC_TARGET_NAVI1X=0 cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3 31 31 - * sp3-gfx10 gfx10.sp3 -hex gfx10.hex 29 29 + * gfx10: 30 30 + * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3 31 31 + * sp3 gfx10.sp3 -hex gfx10.hex 32 32 + * 33 33 + * gfx11: 34 34 + * cpp -DASIC_FAMILY=CHIP_PLUM_BONITO cwsr_trap_handler_gfx10.asm -P -o gfx11.sp3 35 35 + * sp3 gfx11.sp3 -hex gfx11.hex 32 36 */ 33 37 34 34 - #define NO_SQC_STORE !ASIC_TARGET_NAVI1X 38 38 + #define CHIP_NAVI10 26 39 39 + #define CHIP_SIENNA_CICHLID 30 40 40 + #define CHIP_PLUM_BONITO 36 41 41 + 42 42 + #define NO_SQC_STORE (ASIC_FAMILY >= CHIP_SIENNA_CICHLID) 43 43 + #define HAVE_XNACK (ASIC_FAMILY < CHIP_SIENNA_CICHLID) 44 44 + #define HAVE_SENDMSG_RTN (ASIC_FAMILY >= CHIP_PLUM_BONITO) 45 45 + #define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY < CHIP_PLUM_BONITO) 35 46 36 47 var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 37 48 38 38 - var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 39 39 - var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 40 49 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 41 50 var SQ_WAVE_STATUS_HALT_MASK = 0x2000 51 51 + var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 42 52 43 53 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 44 54 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 45 45 - var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 46 46 - var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 47 47 - var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 48 48 - var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 4 55 55 + var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 49 56 var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 50 57 var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 51 58 var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11 52 59 var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1 53 60 61 61 + #if ASIC_FAMILY < CHIP_PLUM_BONITO 62 62 + var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 63 63 + #else 64 64 + var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 65 65 + #endif 66 66 + 54 67 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 55 55 - var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF 68 68 + var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 56 69 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 70 70 + var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 71 71 + var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 57 72 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 58 73 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 59 74 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF ··· 78 63 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 79 64 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 80 65 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 66 66 + var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 81 67 82 82 - var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 68 68 + var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 69 69 + var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 70 70 + 83 71 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 84 72 var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT = 25 85 85 - var SQ_WAVE_IB_STS_REPLAY_W64H_SIZE = 1 86 73 var SQ_WAVE_IB_STS_REPLAY_W64H_MASK = 0x02000000 87 87 - var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 88 88 - var SQ_WAVE_IB_STS_RCNT_SIZE = 6 89 74 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000 90 90 - var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF 91 75 92 76 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 93 93 - 94 94 - var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 95 95 - var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 96 77 97 78 // bits [31:24] unused by SPI debug data 98 79 var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31 99 80 var TTMP11_SAVE_REPLAY_W64H_MASK = 0x80000000 100 81 var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 24 101 82 var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0x7F000000 83 83 + var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 84 84 + var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 102 85 103 86 // SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] 104 87 // when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 105 88 var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 106 89 var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC 107 107 - 108 108 - var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 109 109 - var S_SAVE_SPI_INIT_ATC_SHIFT = 27 110 110 - var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 111 111 - var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 90 90 + var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 91 91 + var S_SAVE_PC_HI_HT_MASK = 0x01000000 112 92 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 113 93 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 114 94 115 115 - var S_SAVE_PC_HI_RCNT_SHIFT = 26 116 116 - var S_SAVE_PC_HI_RCNT_MASK = 0xFC000000 117 117 - var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 25 118 118 - var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x02000000 119 119 - var S_SAVE_PC_HI_REPLAY_W64H_SHIFT = 24 120 120 - var S_SAVE_PC_HI_REPLAY_W64H_MASK = 0x01000000 95 95 + var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 96 96 + var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 121 97 122 98 var s_sgpr_save_num = 108 123 99 ··· 136 130 var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 137 131 var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 138 132 139 139 - var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 140 140 - var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 141 141 - var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 142 142 - var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 143 133 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 144 134 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 145 135 var S_WAVE_SIZE = 25 146 146 - 147 147 - var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 148 148 - var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 149 149 - var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 150 150 - var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 151 136 152 137 var s_restore_spi_init_lo = exec_lo 153 138 var s_restore_spi_init_hi = exec_hi ··· 176 179 177 180 L_SKIP_RESTORE: 178 181 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 179 179 - s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK 180 182 181 181 - if SINGLE_STEP_MISSED_WORKAROUND 182 182 - // No single step exceptions if MODE.DEBUG_EN=0. 183 183 - s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 184 184 - s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 185 185 - s_cbranch_scc0 L_NO_SINGLE_STEP_WORKAROUND 186 186 - 187 187 - // Second-level trap already handled exception if STATUS.HALT=1. 188 188 - s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 189 189 - 190 190 - // Prioritize single step exception over context save. 191 191 - // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 192 192 - s_cbranch_scc0 L_FETCH_2ND_TRAP 193 193 - 194 194 - L_NO_SINGLE_STEP_WORKAROUND: 195 195 - end 196 196 - 183 183 + // Clear SPI_PRIO: do not save with elevated priority. 184 184 + // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 185 185 + s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 197 186 198 187 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 199 199 - s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 188 188 + 189 189 + s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 190 190 + s_cbranch_scc0 L_NOT_HALTED 191 191 + 192 192 + L_HALTED: 193 193 + // Host trap may occur while wave is halted. 194 194 + s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 195 195 + s_cbranch_scc1 L_FETCH_2ND_TRAP 196 196 + 197 197 + L_CHECK_SAVE: 198 198 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 200 199 s_cbranch_scc1 L_SAVE 201 200 202 202 - // If STATUS.MEM_VIOL is asserted then halt the wave to prevent 203 203 - // the exception raising again and blocking context save. 204 204 - s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 205 205 - s_cbranch_scc0 L_FETCH_2ND_TRAP 206 206 - s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 201 201 + // Wave is halted but neither host trap nor SAVECTX is raised. 202 202 + // Caused by instruction fetch memory violation. 203 203 + // Spin wait until context saved to prevent interrupt storm. 204 204 + s_sleep 0x10 205 205 + s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 206 206 + s_branch L_CHECK_SAVE 207 207 + 208 208 + L_NOT_HALTED: 209 209 + // Let second-level handle non-SAVECTX exception or trap. 210 210 + // Any concurrent SAVECTX will be handled upon re-entry once halted. 211 211 + 212 212 + // Check non-maskable exceptions. memory_violation, illegal_instruction 213 213 + // and xnack_error exceptions always cause the wave to enter the trap 214 214 + // handler. 215 215 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 216 216 + s_cbranch_scc1 L_FETCH_2ND_TRAP 217 217 + 218 218 + // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 219 219 + // Maskable exceptions only cause the wave to enter the trap handler if 220 220 + // their respective bit in mode.excp_en is set. 221 221 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 222 222 + s_cbranch_scc0 L_CHECK_TRAP_ID 223 223 + 224 224 + s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 225 225 + s_cbranch_scc0 L_NOT_ADDR_WATCH 226 226 + s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 227 227 + 228 228 + L_NOT_ADDR_WATCH: 229 229 + s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 230 230 + s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 231 231 + s_and_b32 ttmp2, ttmp2, ttmp3 232 232 + s_cbranch_scc1 L_FETCH_2ND_TRAP 233 233 + 234 234 + L_CHECK_TRAP_ID: 235 235 + // Check trap_id != 0 236 236 + s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 237 237 + s_cbranch_scc1 L_FETCH_2ND_TRAP 238 238 + 239 239 + if SINGLE_STEP_MISSED_WORKAROUND 240 240 + // Prioritize single step exception over context save. 241 241 + // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 242 242 + s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 243 243 + s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 244 244 + s_cbranch_scc1 L_FETCH_2ND_TRAP 245 245 + end 246 246 + 247 247 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 248 248 + s_cbranch_scc1 L_SAVE 207 249 208 250 L_FETCH_2ND_TRAP: 209 209 - 210 210 - #if ASIC_TARGET_NAVI1X 211 211 - // Preserve and clear scalar XNACK state before issuing scalar loads. 212 212 - // Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into 213 213 - // unused space ttmp11[31:24]. 214 214 - s_andn2_b32 ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK) 215 215 - s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) 216 216 - s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 217 217 - s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 218 218 - s_or_b32 ttmp11, ttmp11, ttmp3 219 219 - s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 220 220 - s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 221 221 - s_or_b32 ttmp11, ttmp11, ttmp3 222 222 - s_andn2_b32 ttmp2, ttmp2, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK) 223 223 - s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 251 251 + #if HAVE_XNACK 252 252 + save_and_clear_ib_sts(ttmp14, ttmp15) 224 253 #endif 225 254 226 255 // Read second-level TBA/TMA from first-level TMA and jump if available. 227 256 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 228 257 // ttmp12 holds SQ_WAVE_STATUS 258 258 + #if HAVE_SENDMSG_RTN 259 259 + s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) 260 260 + s_waitcnt lgkmcnt(0) 261 261 + #else 229 262 s_getreg_b32 ttmp14, hwreg(HW_REG_SHADER_TMA_LO) 230 263 s_getreg_b32 ttmp15, hwreg(HW_REG_SHADER_TMA_HI) 264 264 + #endif 231 265 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 266 266 + 267 267 + s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 268 268 + s_waitcnt lgkmcnt(0) 269 269 + s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 270 270 + s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 271 271 + s_or_b32 ttmp11, ttmp11, ttmp2 272 272 + 232 273 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 233 274 s_waitcnt lgkmcnt(0) 234 275 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 235 276 s_waitcnt lgkmcnt(0) 277 277 + 236 278 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 237 279 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 238 280 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 239 281 240 282 L_NO_NEXT_TRAP: 241 241 - s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 242 242 - s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK 243 243 - s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 244 244 - s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 245 245 - s_addc_u32 ttmp1, ttmp1, 0 246 246 - L_EXCP_CASE: 283 283 + // If not caused by trap then halt wave to prevent re-entry. 284 284 + s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 285 285 + s_cbranch_scc1 L_TRAP_CASE 286 286 + s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 287 287 + 288 288 + // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 289 289 + // Rewind the PC to prevent this from occurring. 290 290 + s_sub_u32 ttmp0, ttmp0, 0x8 291 291 + s_subb_u32 ttmp1, ttmp1, 0x0 292 292 + 293 293 + s_branch L_EXIT_TRAP 294 294 + 295 295 + L_TRAP_CASE: 296 296 + // Host trap will not cause trap re-entry. 297 297 + s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 298 298 + s_cbranch_scc1 L_EXIT_TRAP 299 299 + 300 300 + // Advance past trap instruction to prevent re-entry. 301 301 + s_add_u32 ttmp0, ttmp0, 0x4 302 302 + s_addc_u32 ttmp1, ttmp1, 0x0 303 303 + 304 304 + L_EXIT_TRAP: 247 305 s_and_b32 ttmp1, ttmp1, 0xFFFF 248 306 249 249 - #if ASIC_TARGET_NAVI1X 250 250 - // Restore SQ_WAVE_IB_STS. 251 251 - s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 252 252 - s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 253 253 - s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 254 254 - s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 255 255 - s_or_b32 ttmp2, ttmp2, ttmp3 256 256 - s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 307 307 + #if HAVE_XNACK 308 308 + restore_ib_sts(ttmp14, ttmp15) 257 309 #endif 258 310 259 311 // Restore SQ_WAVE_STATUS. ··· 317 271 s_mov_b32 s_save_tmp, 0 318 272 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 319 273 320 320 - #if ASIC_TARGET_NAVI1X 321 321 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) 322 322 - s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 323 323 - s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 324 324 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) 325 325 - s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 326 326 - s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 327 327 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT, SQ_WAVE_IB_STS_REPLAY_W64H_SIZE) 328 328 - s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_REPLAY_W64H_SHIFT 329 329 - s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 330 330 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY and REPLAY_W64H in IB_STS 331 331 - s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 332 332 - 333 333 - s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 274 274 + #if HAVE_XNACK 275 275 + save_and_clear_ib_sts(s_save_tmp, s_save_trapsts) 334 276 #endif 335 277 336 278 /* inform SPI the readiness and wait for SPI's go signal */ ··· 326 292 s_mov_b32 s_save_exec_hi, exec_hi 327 293 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 328 294 295 295 + #if HAVE_SENDMSG_RTN 296 296 + s_sendmsg_rtn_b64 [exec_lo, exec_hi], sendmsg(MSG_RTN_SAVE_WAVE) 297 297 + #else 329 298 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 299 299 + #endif 330 300 331 331 - #if ASIC_TARGET_NAVI1X 301 301 + #if ASIC_FAMILY < CHIP_SIENNA_CICHLID 332 302 L_SLEEP: 333 303 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause 334 304 // SQ hang, since the 7,8th wave could not get arbit to exec inst, while ··· 343 305 s_waitcnt lgkmcnt(0) 344 306 #endif 345 307 308 308 + // Save first_wave flag so we can clear high bits of save address. 309 309 + s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK 310 310 + s_lshl_b32 s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT) 311 311 + s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 312 312 + 313 313 + #if NO_SQC_STORE 314 314 + // Trap temporaries must be saved via VGPR but all VGPRs are in use. 315 315 + // There is no ttmp space to hold the resource constant for VGPR save. 316 316 + // Save v0 by itself since it requires only two SGPRs. 317 317 + s_mov_b32 s_save_ttmps_lo, exec_lo 318 318 + s_and_b32 s_save_ttmps_hi, exec_hi, 0xFFFF 319 319 + s_mov_b32 exec_lo, 0xFFFFFFFF 320 320 + s_mov_b32 exec_hi, 0xFFFFFFFF 321 321 + global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] slc:1 glc:1 322 322 + v_mov_b32 v0, 0x0 323 323 + s_mov_b32 exec_lo, s_save_ttmps_lo 324 324 + s_mov_b32 exec_hi, s_save_ttmps_hi 325 325 + #endif 326 326 + 346 327 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 347 347 - // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 328 328 + // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 348 329 get_wave_size(s_save_ttmps_hi) 349 330 get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi) 331 331 + get_svgpr_size_bytes(s_save_ttmps_hi) 332 332 + s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 350 333 s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, 0xFFFF 351 334 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, get_sgpr_size_bytes() 352 335 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 353 336 s_addc_u32 s_save_ttmps_hi, s_save_ttmps_hi, 0x0 354 337 355 355 - #if ASIC_TARGET_NAVI1X 338 338 + #if NO_SQC_STORE 339 339 + v_writelane_b32 v0, ttmp4, 0x4 340 340 + v_writelane_b32 v0, ttmp5, 0x5 341 341 + v_writelane_b32 v0, ttmp6, 0x6 342 342 + v_writelane_b32 v0, ttmp7, 0x7 343 343 + v_writelane_b32 v0, ttmp8, 0x8 344 344 + v_writelane_b32 v0, ttmp9, 0x9 345 345 + v_writelane_b32 v0, ttmp10, 0xA 346 346 + v_writelane_b32 v0, ttmp11, 0xB 347 347 + v_writelane_b32 v0, ttmp13, 0xD 348 348 + v_writelane_b32 v0, exec_lo, 0xE 349 349 + v_writelane_b32 v0, exec_hi, 0xF 350 350 + 351 351 + s_mov_b32 exec_lo, 0x3FFF 352 352 + s_mov_b32 exec_hi, 0x0 353 353 + global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 slc:1 glc:1 354 354 + v_readlane_b32 ttmp14, v0, 0xE 355 355 + v_readlane_b32 ttmp15, v0, 0xF 356 356 + s_mov_b32 exec_lo, ttmp14 357 357 + s_mov_b32 exec_hi, ttmp15 358 358 + #else 356 359 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 357 360 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 358 361 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 ··· 405 326 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 406 327 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 407 328 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 408 408 - s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 409 409 - s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) 410 410 - s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 411 411 - s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 412 412 - s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) 413 413 - s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 414 329 415 330 s_mov_b32 s_save_m0, m0 416 331 ··· 412 339 s_mov_b32 s_save_mem_offset, 0x0 413 340 get_wave_size(s_wave_size) 414 341 415 415 - #if ASIC_TARGET_NAVI1X 342 342 + #if HAVE_XNACK 416 343 // Save and clear vector XNACK state late to free up SGPRs. 417 344 s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK) 418 345 s_setreg_imm32_b32 hwreg(HW_REG_SHADER_XNACK_MASK), 0x0 ··· 434 361 435 362 // VGPR Allocated in 4-GPR granularity 436 363 364 364 + #if !NO_SQC_STORE 437 365 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 366 366 + #endif 438 367 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 439 368 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 440 369 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 ··· 447 372 448 373 // VGPR Allocated in 4-GPR granularity 449 374 375 375 + #if !NO_SQC_STORE 450 376 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 377 377 + #endif 451 378 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 452 379 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 453 380 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 ··· 474 397 475 398 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 476 399 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) 477 477 - write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 400 400 + s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 401 401 + write_hwreg_to_mem(s_save_tmp, s_save_buf_rsrc0, s_save_mem_offset) 478 402 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) 479 403 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 480 404 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) ··· 496 418 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 497 419 498 420 #if NO_SQC_STORE 499 499 - // Write HWREG/SGPRs with 32 VGPR lanes, wave32 is common case. 421 421 + // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 422 422 + s_mov_b32 exec_lo, 0xFFFF 500 423 s_mov_b32 exec_hi, 0x0 501 424 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 425 425 + 426 426 + // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. 427 427 + s_mov_b32 exec_lo, 0xFFFFFFFF 502 428 #endif 503 429 504 430 /* save SGPRs */ ··· 588 506 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 589 507 590 508 s_barrier //LDS is used? wait for other waves in the same TG 591 591 - s_and_b32 s_save_tmp, s_wave_size, S_SAVE_SPI_INIT_FIRST_WAVE_MASK 509 509 + s_and_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 592 510 s_cbranch_scc0 L_SAVE_LDS_DONE 593 511 594 512 // first wave do LDS save; ··· 710 628 // VGPR store using dw burst 711 629 s_mov_b32 m0, 0x4 //VGPR initial index value =4 712 630 s_cmp_lt_u32 m0, s_save_alloc_size 713 713 - s_cbranch_scc0 L_SAVE_VGPR_END 631 631 + s_cbranch_scc0 L_SAVE_SHARED_VGPR 714 632 715 633 L_SAVE_VGPR_W64_LOOP: 716 634 v_movrels_b32 v0, v0 //v0 = v[0+m0] ··· 728 646 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 729 647 s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? 730 648 649 649 + L_SAVE_SHARED_VGPR: 731 650 //Below part will be the save shared vgpr part (new for gfx10) 732 651 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 733 652 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? ··· 757 674 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 758 675 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 759 676 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 760 760 - s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 761 761 - s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) 762 762 - s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 763 763 - s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 764 764 - s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) 765 765 - s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 677 677 + 766 678 //determine it is wave32 or wave64 767 679 get_wave_size(s_restore_size) 768 680 ··· 800 722 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 801 723 802 724 L_RESTORE_LDS_LOOP_W32: 725 725 + #if HAVE_BUFFER_LDS_LOAD 803 726 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 727 727 + #else 728 728 + buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 729 729 + s_waitcnt vmcnt(0) 730 730 + ds_store_addtid_b32 v0 731 731 + #endif 804 732 s_add_u32 m0, m0, 128 // 128 DW 805 733 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW 806 734 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 ··· 814 730 s_branch L_RESTORE_VGPR 815 731 816 732 L_RESTORE_LDS_LOOP_W64: 733 733 + #if HAVE_BUFFER_LDS_LOAD 817 734 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 735 735 + #else 736 736 + buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 737 737 + s_waitcnt vmcnt(0) 738 738 + ds_store_addtid_b32 v0 739 739 + #endif 818 740 s_add_u32 m0, m0, 256 // 256 DW 819 741 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW 820 742 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 ··· 855 765 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 856 766 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 857 767 s_mov_b32 m0, 4 //VGPR initial index value = 4 768 768 + s_cmp_lt_u32 m0, s_restore_alloc_size 769 769 + s_cbranch_scc0 L_RESTORE_SGPR 858 770 859 771 L_RESTORE_VGPR_WAVE32_LOOP: 860 772 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 ··· 878 786 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128 879 787 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2 880 788 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3 789 789 + s_waitcnt vmcnt(0) 881 790 882 791 s_branch L_RESTORE_SGPR 883 792 ··· 889 796 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last 890 797 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 891 798 s_mov_b32 m0, 4 //VGPR initial index value = 4 799 799 + s_cmp_lt_u32 m0, s_restore_alloc_size 800 800 + s_cbranch_scc0 L_RESTORE_SHARED_VGPR 892 801 893 802 L_RESTORE_VGPR_WAVE64_LOOP: 894 803 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 ··· 907 812 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 908 813 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 909 814 815 815 + L_RESTORE_SHARED_VGPR: 910 816 //Below part will be the restore shared vgpr part (new for gfx10) 911 817 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size 912 818 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? ··· 1031 935 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1032 936 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1033 937 1034 1034 - #if ASIC_TARGET_NAVI1X 938 938 + #if HAVE_XNACK 1035 939 s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask 1036 940 #endif 1037 941 ··· 1041 945 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1042 946 1043 947 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1044 1044 - // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 948 948 + // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 1045 949 get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size) 950 950 + get_svgpr_size_bytes(s_restore_ttmps_hi) 951 951 + s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1046 952 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, get_sgpr_size_bytes() 1047 953 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1048 954 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 ··· 1054 956 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 1055 957 s_waitcnt lgkmcnt(0) 1056 958 1057 1057 - #if ASIC_TARGET_NAVI1X 1058 1058 - s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1059 1059 - s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1060 1060 - s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1061 1061 - s_mov_b32 s_restore_tmp, 0x0 1062 1062 - s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1063 1063 - s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1064 1064 - s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1065 1065 - s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1066 1066 - s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1067 1067 - s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_REPLAY_W64H_MASK 1068 1068 - s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_REPLAY_W64H_SHIFT 1069 1069 - s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT 1070 1070 - s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1071 1071 - 1072 1072 - s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1073 1073 - s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1074 1074 - s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 959 959 + #if HAVE_XNACK 960 960 + restore_ib_sts(s_restore_tmp, s_restore_m0) 1075 961 #endif 1076 962 1077 963 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS ··· 1171 1089 function get_wave_size(s_reg) 1172 1090 s_getreg_b32 s_reg, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) 1173 1091 s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE 1174 1174 - s_or_b32 s_reg, s_save_spi_init_hi, s_reg //share with exec_hi, it's at bit25 1092 1092 + end 1093 1093 + 1094 1094 + function save_and_clear_ib_sts(tmp1, tmp2) 1095 1095 + // Preserve and clear scalar XNACK state before issuing scalar loads. 1096 1096 + // Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into 1097 1097 + // unused space ttmp11[31:24]. 1098 1098 + s_andn2_b32 ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK) 1099 1099 + s_getreg_b32 tmp1, hwreg(HW_REG_IB_STS) 1100 1100 + s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 1101 1101 + s_lshl_b32 tmp2, tmp2, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 1102 1102 + s_or_b32 ttmp11, ttmp11, tmp2 1103 1103 + s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1104 1104 + s_lshl_b32 tmp2, tmp2, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1105 1105 + s_or_b32 ttmp11, ttmp11, tmp2 1106 1106 + s_andn2_b32 tmp1, tmp1, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK) 1107 1107 + s_setreg_b32 hwreg(HW_REG_IB_STS), tmp1 1108 1108 + end 1109 1109 + 1110 1110 + function restore_ib_sts(tmp1, tmp2) 1111 1111 + s_lshr_b32 tmp1, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1112 1112 + s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1113 1113 + s_lshr_b32 tmp1, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 1114 1114 + s_and_b32 tmp1, tmp1, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 1115 1115 + s_or_b32 tmp1, tmp1, tmp2 1116 1116 + s_setreg_b32 hwreg(HW_REG_IB_STS), tmp1 1175 1117 end

+121 -127

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm

reviewed

··· 46 46 /**************************************************************************/ 47 47 /* variables */ 48 48 /**************************************************************************/ 49 49 - var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 50 50 - var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 51 49 var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 52 50 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 53 51 var SQ_WAVE_STATUS_HALT_MASK = 0x2000 ··· 54 56 var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 55 57 var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 56 58 var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 59 59 + var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 57 60 58 61 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 59 62 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 ··· 71 72 #endif 72 73 73 74 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 74 74 - var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 75 75 + var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 75 76 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 77 77 + var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 78 78 + var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 76 79 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 77 80 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 78 81 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF ··· 84 83 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 85 84 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 86 85 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 86 86 + var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 87 87 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 88 88 89 89 - var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 89 89 + var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 90 90 + var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 91 91 + 90 92 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 91 93 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 92 92 - var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 93 94 94 95 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 95 96 96 96 - var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 97 97 - var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 98 98 - 99 97 var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 100 98 var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 99 99 + var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 100 100 + var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 101 101 102 102 /* Save */ 103 103 var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 104 104 var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 105 105 - 106 106 - var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 107 107 - var S_SAVE_SPI_INIT_ATC_SHIFT = 27 108 108 - var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 109 109 - var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 105 105 + var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 106 106 + var S_SAVE_PC_HI_HT_MASK = 0x01000000 110 107 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 111 108 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 112 112 - 113 113 - var S_SAVE_PC_HI_RCNT_SHIFT = 27 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 114 114 - var S_SAVE_PC_HI_RCNT_MASK = 0xF8000000 //FIXME 115 115 - var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 26 //FIXME 116 116 - var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x04000000 //FIXME 117 109 118 110 var s_save_spi_init_lo = exec_lo 119 111 var s_save_spi_init_hi = exec_hi ··· 134 140 var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 135 141 var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 136 142 137 137 - var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 138 138 - var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 139 139 - var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 140 140 - var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 141 143 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 142 144 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 143 143 - 144 144 - var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 145 145 - var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 146 146 - var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 147 147 - var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 148 145 149 146 var s_restore_spi_init_lo = exec_lo 150 147 var s_restore_spi_init_hi = exec_hi ··· 184 199 L_SKIP_RESTORE: 185 200 186 201 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 187 187 - s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 188 202 189 189 - if SINGLE_STEP_MISSED_WORKAROUND 190 190 - // No single step exceptions if MODE.DEBUG_EN=0. 191 191 - s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 192 192 - s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 193 193 - s_cbranch_scc0 L_NO_SINGLE_STEP_WORKAROUND 194 194 - 195 195 - // Second-level trap already handled exception if STATUS.HALT=1. 196 196 - s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 197 197 - 198 198 - // Prioritize single step exception over context save. 199 199 - // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 200 200 - s_cbranch_scc0 L_FETCH_2ND_TRAP 201 201 - 202 202 - L_NO_SINGLE_STEP_WORKAROUND: 203 203 - end 203 203 + // Clear SPI_PRIO: do not save with elevated priority. 204 204 + // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 205 205 + s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 204 206 205 207 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 208 208 + 209 209 + s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 210 210 + s_cbranch_scc0 L_NOT_HALTED 211 211 + 212 212 + L_HALTED: 213 213 + // Host trap may occur while wave is halted. 214 214 + s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 215 215 + s_cbranch_scc1 L_FETCH_2ND_TRAP 216 216 + 217 217 + L_CHECK_SAVE: 206 218 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 207 219 s_cbranch_scc1 L_SAVE //this is the operation for save 208 220 209 209 - // ********* Handle non-CWSR traps ******************* 210 210 - 211 211 - // Illegal instruction is a non-maskable exception which blocks context save. 212 212 - // Halt the wavefront and return from the trap. 213 213 - s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 214 214 - s_cbranch_scc1 L_HALT_WAVE 215 215 - 216 216 - // If STATUS.MEM_VIOL is asserted then we cannot fetch from the TMA. 217 217 - // Instead, halt the wavefront and return from the trap. 218 218 - s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 219 219 - s_cbranch_scc0 L_FETCH_2ND_TRAP 220 220 - 221 221 - L_HALT_WAVE: 222 222 - // If STATUS.HALT is set then this fault must come from SQC instruction fetch. 223 223 - // We cannot prevent further faults. Spin wait until context saved. 224 224 - s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 225 225 - s_cbranch_scc0 L_NOT_ALREADY_HALTED 226 226 - 227 227 - L_WAIT_CTX_SAVE: 221 221 + // Wave is halted but neither host trap nor SAVECTX is raised. 222 222 + // Caused by instruction fetch memory violation. 223 223 + // Spin wait until context saved to prevent interrupt storm. 228 224 s_sleep 0x10 229 229 - s_getreg_b32 ttmp2, hwreg(HW_REG_TRAPSTS) 230 230 - s_and_b32 ttmp2, ttmp2, SQ_WAVE_TRAPSTS_SAVECTX_MASK 231 231 - s_cbranch_scc0 L_WAIT_CTX_SAVE 225 225 + s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 226 226 + s_branch L_CHECK_SAVE 232 227 233 233 - L_NOT_ALREADY_HALTED: 234 234 - s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 228 228 + L_NOT_HALTED: 229 229 + // Let second-level handle non-SAVECTX exception or trap. 230 230 + // Any concurrent SAVECTX will be handled upon re-entry once halted. 235 231 236 236 - // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 237 237 - // Rewind the PC to prevent this from occurring. The debugger compensates for this. 238 238 - s_sub_u32 ttmp0, ttmp0, 0x8 239 239 - s_subb_u32 ttmp1, ttmp1, 0x0 232 232 + // Check non-maskable exceptions. memory_violation, illegal_instruction 233 233 + // and xnack_error exceptions always cause the wave to enter the trap 234 234 + // handler. 235 235 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 236 236 + s_cbranch_scc1 L_FETCH_2ND_TRAP 237 237 + 238 238 + // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 239 239 + // Maskable exceptions only cause the wave to enter the trap handler if 240 240 + // their respective bit in mode.excp_en is set. 241 241 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 242 242 + s_cbranch_scc0 L_CHECK_TRAP_ID 243 243 + 244 244 + s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 245 245 + s_cbranch_scc0 L_NOT_ADDR_WATCH 246 246 + s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 247 247 + 248 248 + L_NOT_ADDR_WATCH: 249 249 + s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 250 250 + s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 251 251 + s_and_b32 ttmp2, ttmp2, ttmp3 252 252 + s_cbranch_scc1 L_FETCH_2ND_TRAP 253 253 + 254 254 + L_CHECK_TRAP_ID: 255 255 + // Check trap_id != 0 256 256 + s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 257 257 + s_cbranch_scc1 L_FETCH_2ND_TRAP 258 258 + 259 259 + if SINGLE_STEP_MISSED_WORKAROUND 260 260 + // Prioritize single step exception over context save. 261 261 + // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 262 262 + s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 263 263 + s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 264 264 + s_cbranch_scc1 L_FETCH_2ND_TRAP 265 265 + end 266 266 + 267 267 + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 268 268 + s_cbranch_scc1 L_SAVE 240 269 241 270 L_FETCH_2ND_TRAP: 242 271 // Preserve and clear scalar XNACK state before issuing scalar reads. 243 243 - // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 244 244 - s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) 245 245 - s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 246 246 - s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 247 247 - s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 248 248 - s_or_b32 ttmp11, ttmp11, ttmp3 249 249 - 250 250 - s_andn2_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 251 251 - s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 272 272 + save_and_clear_ib_sts(ttmp14) 252 273 253 274 // Read second-level TBA/TMA from first-level TMA and jump if available. 254 275 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) ··· 262 271 s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) 263 272 s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) 264 273 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 274 274 + 275 275 + s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 276 276 + s_waitcnt lgkmcnt(0) 277 277 + s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 278 278 + s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 279 279 + s_or_b32 ttmp11, ttmp11, ttmp2 280 280 + 265 281 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 266 282 s_waitcnt lgkmcnt(0) 267 283 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 268 284 s_waitcnt lgkmcnt(0) 285 285 + 269 286 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 270 287 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 271 288 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 272 289 273 290 L_NO_NEXT_TRAP: 274 274 - s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 275 275 - s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 276 276 - s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 277 277 - s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 278 278 - s_addc_u32 ttmp1, ttmp1, 0 279 279 - L_EXCP_CASE: 291 291 + // If not caused by trap then halt wave to prevent re-entry. 292 292 + s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 293 293 + s_cbranch_scc1 L_TRAP_CASE 294 294 + s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 295 295 + 296 296 + // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 297 297 + // Rewind the PC to prevent this from occurring. 298 298 + s_sub_u32 ttmp0, ttmp0, 0x8 299 299 + s_subb_u32 ttmp1, ttmp1, 0x0 300 300 + 301 301 + s_branch L_EXIT_TRAP 302 302 + 303 303 + L_TRAP_CASE: 304 304 + // Host trap will not cause trap re-entry. 305 305 + s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 306 306 + s_cbranch_scc1 L_EXIT_TRAP 307 307 + 308 308 + // Advance past trap instruction to prevent re-entry. 309 309 + s_add_u32 ttmp0, ttmp0, 0x4 310 310 + s_addc_u32 ttmp1, ttmp1, 0x0 311 311 + 312 312 + L_EXIT_TRAP: 280 313 s_and_b32 ttmp1, ttmp1, 0xFFFF 281 314 282 282 - // Restore SQ_WAVE_IB_STS. 283 283 - s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 284 284 - s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 285 285 - s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 315 315 + restore_ib_sts(ttmp14) 286 316 287 317 // Restore SQ_WAVE_STATUS. 288 318 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 ··· 324 312 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 325 313 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 326 314 327 327 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 328 328 - s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 329 329 - s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 330 330 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 331 331 - s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 332 332 - s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 333 333 - s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 334 334 - s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 335 335 - 336 336 - s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 315 315 + save_and_clear_ib_sts(s_save_tmp) 337 316 338 317 /* inform SPI the readiness and wait for SPI's go signal */ 339 318 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI ··· 363 360 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 364 361 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 365 362 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 366 366 - s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 367 367 - s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 368 368 - s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 369 369 - s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 370 370 - s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 371 371 - s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 372 363 373 364 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 374 365 s_mov_b32 s_save_m0, m0 //save M0 ··· 687 690 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 688 691 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 689 692 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 690 690 - s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 691 691 - s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 692 692 - s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 693 693 - s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 694 694 - s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 695 695 - s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 696 693 697 694 /* global mem offset */ 698 695 // s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 ··· 880 889 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 881 890 s_waitcnt lgkmcnt(0) 882 891 883 883 - //reuse s_restore_m0 as a temp register 884 884 - s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 885 885 - s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 886 886 - s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 887 887 - s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 888 888 - s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 889 889 - s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 890 890 - s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 891 891 - s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 892 892 - s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 893 893 - s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 894 894 - s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 895 895 - s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 892 892 + restore_ib_sts(s_restore_tmp) 896 893 897 894 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 898 895 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 ··· 889 910 890 911 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 891 912 892 892 - // s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 893 893 - s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 913 913 + s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 894 914 895 915 896 916 /**************************************************************************/ ··· 1055 1077 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1056 1078 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1057 1079 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1080 1080 + end 1081 1081 + 1082 1082 + function save_and_clear_ib_sts(tmp) 1083 1083 + // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 1084 1084 + s_getreg_b32 tmp, hwreg(HW_REG_IB_STS) 1085 1085 + s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1086 1086 + s_lshl_b32 tmp, tmp, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1087 1087 + s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 1088 1088 + s_or_b32 ttmp11, ttmp11, tmp 1089 1089 + s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0x0 1090 1090 + end 1091 1091 + 1092 1092 + function restore_ib_sts(tmp) 1093 1093 + s_lshr_b32 tmp, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1094 1094 + s_and_b32 tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1095 1095 + s_setreg_b32 hwreg(HW_REG_IB_STS), tmp 1058 1096 end

+5 -1

drivers/gpu/drm/amd/amdkfd/kfd_device.c

reviewed

··· 441 441 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 442 442 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 443 443 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 444 444 - } else { 444 444 + } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 445 445 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 446 446 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 447 447 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 448 448 + } else { 449 449 + BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 450 450 + kfd->cwsr_isa = cwsr_trap_gfx11_hex; 451 451 + kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 448 452 } 449 453 450 454 kfd->cwsr_enabled = true;

+1 -1

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

reviewed

··· 531 531 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 532 532 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 533 533 bp.flags |= clear ? AMDGPU_GEM_CREATE_VRAM_CLEARED : 0; 534 534 - bp.flags |= AMDGPU_AMDKFD_CREATE_SVM_BO; 534 534 + bp.flags |= AMDGPU_GEM_CREATE_DISCARDABLE; 535 535 bp.type = ttm_bo_type_device; 536 536 bp.resv = NULL; 537 537

+6 -16

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

reviewed

··· 1271 1271 if (!peer_dev) 1272 1272 continue; 1273 1273 1274 1274 + /* Include the CPU peer in GPU hive if connected over xGMI. */ 1275 1275 + if (!peer_dev->gpu && !peer_dev->node_props.hive_id && 1276 1276 + dev->node_props.hive_id && 1277 1277 + dev->gpu->adev->gmc.xgmi.connected_to_cpu) 1278 1278 + peer_dev->node_props.hive_id = dev->node_props.hive_id; 1279 1279 + 1274 1280 list_for_each_entry(inbound_link, &peer_dev->io_link_props, 1275 1281 list) { 1276 1282 if (inbound_link->node_to != link->node_from) ··· 1307 1301 gpu_id = kfd_generate_gpu_id(gpu); 1308 1302 1309 1303 pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id); 1310 1310 - 1311 1311 - /* Include the CPU in xGMI hive if xGMI connected by assigning it the hive ID. */ 1312 1312 - if (gpu->hive_id && gpu->adev->gmc.xgmi.connected_to_cpu) { 1313 1313 - struct kfd_topology_device *top_dev; 1314 1314 - 1315 1315 - down_read(&topology_lock); 1316 1316 - 1317 1317 - list_for_each_entry(top_dev, &topology_device_list, list) { 1318 1318 - if (top_dev->gpu) 1319 1319 - break; 1320 1320 - 1321 1321 - top_dev->node_props.hive_id = gpu->hive_id; 1322 1322 - } 1323 1323 - 1324 1324 - up_read(&topology_lock); 1325 1325 - } 1326 1304 1327 1305 /* Check to see if this gpu device exists in the topology_device_list. 1328 1306 * If so, assign the gpu to that device,

+13 -6

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

reviewed

··· 769 769 770 770 do { 771 771 dc_stat_get_dmub_notification(adev->dm.dc, &notify); 772 772 - if (notify.type > ARRAY_SIZE(dm->dmub_thread_offload)) { 772 772 + if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 773 773 DRM_ERROR("DM: notify type %d invalid!", notify.type); 774 774 continue; 775 775 } ··· 5381 5381 5382 5382 static void 5383 5383 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 5384 5384 - bool *per_pixel_alpha, bool *global_alpha, 5385 5385 - int *global_alpha_value) 5384 5384 + bool *per_pixel_alpha, bool *pre_multiplied_alpha, 5385 5385 + bool *global_alpha, int *global_alpha_value) 5386 5386 { 5387 5387 *per_pixel_alpha = false; 5388 5388 + *pre_multiplied_alpha = true; 5388 5389 *global_alpha = false; 5389 5390 *global_alpha_value = 0xff; 5390 5391 5391 5392 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 5392 5393 return; 5393 5394 5394 5394 - if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 5395 5395 + if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 5396 5396 + plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 5395 5397 static const uint32_t alpha_formats[] = { 5396 5398 DRM_FORMAT_ARGB8888, 5397 5399 DRM_FORMAT_RGBA8888, ··· 5408 5406 break; 5409 5407 } 5410 5408 } 5409 5409 + 5410 5410 + if (per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 5411 5411 + *pre_multiplied_alpha = false; 5411 5412 } 5412 5413 5413 5414 if (plane_state->alpha < 0xffff) { ··· 5573 5568 return ret; 5574 5569 5575 5570 fill_blending_from_plane_state( 5576 5576 - plane_state, &plane_info->per_pixel_alpha, 5571 5571 + plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5577 5572 &plane_info->global_alpha, &plane_info->global_alpha_value); 5578 5573 5579 5574 return 0; ··· 5620 5615 dc_plane_state->tiling_info = plane_info.tiling_info; 5621 5616 dc_plane_state->visible = plane_info.visible; 5622 5617 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5618 5618 + dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5623 5619 dc_plane_state->global_alpha = plane_info.global_alpha; 5624 5620 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5625 5621 dc_plane_state->dcc = plane_info.dcc; ··· 7917 7911 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 7918 7912 plane_cap && plane_cap->per_pixel_alpha) { 7919 7913 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 7920 7920 - BIT(DRM_MODE_BLEND_PREMULTI); 7914 7914 + BIT(DRM_MODE_BLEND_PREMULTI) | 7915 7915 + BIT(DRM_MODE_BLEND_COVERAGE); 7921 7916 7922 7917 drm_plane_create_alpha_property(plane); 7923 7918 drm_plane_create_blend_mode_property(plane, blend_caps);

+1 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

reviewed

··· 122 122 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; 123 123 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 124 124 125 125 - prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; 125 125 + prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst]; 126 126 127 127 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) 128 128 clk_mgr->dccg->funcs->update_dpp_dto(

+2 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

reviewed

··· 91 91 92 92 if (pipe->top_pipe || pipe->prev_odm_pipe) 93 93 continue; 94 94 - if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { 94 94 + if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL || 95 95 + dc_is_virtual_signal(pipe->stream->signal))) { 95 96 if (disable) 96 97 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 97 98 else

+2 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

reviewed

··· 122 122 123 123 if (pipe->top_pipe || pipe->prev_odm_pipe) 124 124 continue; 125 125 - if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { 125 125 + if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL || 126 126 + dc_is_virtual_signal(pipe->stream->signal))) { 126 127 if (disable) 127 128 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 128 129 else

+9 -6

drivers/gpu/drm/amd/display/dc/core/dc.c

reviewed

··· 2901 2901 top_pipe_to_program->stream_res.tg); 2902 2902 } 2903 2903 2904 2904 - if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) 2904 2904 + if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 2905 2905 dc->hwss.interdependent_update_lock(dc, context, true); 2906 2906 - else 2906 2906 + } else { 2907 2907 /* Lock the top pipe while updating plane addrs, since freesync requires 2908 2908 * plane addr update event triggers to be synchronized. 2909 2909 * top_pipe_to_program is expected to never be NULL 2910 2910 */ 2911 2911 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); 2912 2912 + } 2912 2913 2913 2914 // Stream updates 2914 2915 if (stream_update) ··· 2925 2924 if (dc->hwss.program_front_end_for_ctx) 2926 2925 dc->hwss.program_front_end_for_ctx(dc, context); 2927 2926 2928 2928 - if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) 2927 2927 + if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 2929 2928 dc->hwss.interdependent_update_lock(dc, context, false); 2930 2930 - else 2929 2929 + } else { 2931 2930 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); 2931 2931 + } 2932 2932 dc->hwss.post_unlock_program_front_end(dc, context); 2933 2933 return; 2934 2934 } ··· 3054 3052 3055 3053 } 3056 3054 3057 3057 - if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) 3055 3055 + if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 3058 3056 dc->hwss.interdependent_update_lock(dc, context, false); 3059 3059 - else 3057 3057 + } else { 3060 3058 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); 3059 3059 + } 3061 3060 3062 3061 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) 3063 3062 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

+21 -3

drivers/gpu/drm/amd/display/dc/core/dc_link.c

reviewed

··· 33 33 #include "gpio_service_interface.h" 34 34 #include "core_status.h" 35 35 #include "dc_link_dp.h" 36 36 + #include "dc_link_dpia.h" 36 37 #include "dc_link_ddc.h" 37 38 #include "link_hwss.h" 38 39 #include "opp.h" ··· 241 240 242 241 /* Link may not have physical HPD pin. */ 243 242 if (link->ep_type != DISPLAY_ENDPOINT_PHY) { 244 244 - if (link->is_hpd_pending || !link->hpd_status) 243 243 + if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link)) 245 244 *type = dc_connection_none; 246 245 else 247 246 *type = dc_connection_single; ··· 1605 1604 if (link->hpd_gpio) { 1606 1605 if (!link->dc->config.allow_edp_hotplug_detection) 1607 1606 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; 1608 1608 - link->irq_source_hpd_rx = 1609 1609 - dal_irq_get_rx_source(link->hpd_gpio); 1607 1607 + 1608 1608 + switch (link->dc->config.allow_edp_hotplug_detection) { 1609 1609 + case 1: // only the 1st eDP handles hotplug 1610 1610 + if (link->link_index == 0) 1611 1611 + link->irq_source_hpd_rx = 1612 1612 + dal_irq_get_rx_source(link->hpd_gpio); 1613 1613 + else 1614 1614 + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; 1615 1615 + break; 1616 1616 + case 2: // only the 2nd eDP handles hotplug 1617 1617 + if (link->link_index == 1) 1618 1618 + link->irq_source_hpd_rx = 1619 1619 + dal_irq_get_rx_source(link->hpd_gpio); 1620 1620 + else 1621 1621 + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; 1622 1622 + break; 1623 1623 + default: 1624 1624 + break; 1625 1625 + } 1610 1626 } 1611 1627 1612 1628 break;

+121 -127

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

reviewed

··· 2783 2783 struct dc_link *link = stream->link; 2784 2784 enum dp_panel_mode panel_mode = dp_get_panel_mode(link); 2785 2785 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0; 2786 2786 - struct dc_link_settings current_setting = *link_setting; 2786 2786 + struct dc_link_settings cur_link_settings = *link_setting; 2787 2787 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2788 2788 int fail_count = 0; 2789 2789 + bool is_link_bw_low = false; /* link bandwidth < stream bandwidth */ 2790 2790 + bool is_link_bw_min = /* RBR x 1 */ 2791 2791 + (cur_link_settings.link_rate <= LINK_RATE_LOW) && 2792 2792 + (cur_link_settings.lane_count <= LANE_COUNT_ONE); 2789 2793 2790 2794 dp_trace_commit_lt_init(link); 2791 2795 2792 2796 2793 2793 - if (dp_get_link_encoding_format(&current_setting) == DP_8b_10b_ENCODING) 2797 2797 + if (dp_get_link_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING) 2794 2798 /* We need to do this before the link training to ensure the idle 2795 2799 * pattern in SST mode will be sent right after the link training 2796 2800 */ 2797 2801 link_hwss->setup_stream_encoder(pipe_ctx); 2798 2802 2799 2803 dp_trace_set_lt_start_timestamp(link, false); 2800 2800 - for (j = 0; j < attempts; ++j) { 2804 2804 + j = 0; 2805 2805 + while (j < attempts && fail_count < (attempts * 10)) { 2801 2806 2802 2802 - DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n", 2803 2803 - __func__, (unsigned int)j + 1, attempts); 2807 2807 + DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d @ rate(%d) x lane(%d)\n", 2808 2808 + __func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, 2809 2809 + cur_link_settings.lane_count); 2804 2810 2805 2811 dp_enable_link_phy( 2806 2812 link, 2807 2813 &pipe_ctx->link_res, 2808 2814 signal, 2809 2815 pipe_ctx->clock_source->id, 2810 2810 - &current_setting); 2816 2816 + &cur_link_settings); 2811 2817 2812 2818 if (stream->sink_patches.dppowerup_delay > 0) { 2813 2819 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay; ··· 2838 2832 dp_set_panel_mode(link, panel_mode); 2839 2833 2840 2834 if (link->aux_access_disabled) { 2841 2841 - dc_link_dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &current_setting); 2835 2835 + dc_link_dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings); 2842 2836 return true; 2843 2837 } else { 2844 2838 /** @todo Consolidate USB4 DP and DPx.x training. */ 2845 2839 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { 2846 2840 status = dc_link_dpia_perform_link_training(link, 2847 2841 &pipe_ctx->link_res, 2848 2848 - &current_setting, 2842 2842 + &cur_link_settings, 2849 2843 skip_video_pattern); 2850 2844 2851 2845 /* Transmit idle pattern once training successful. */ 2852 2852 - if (status == LINK_TRAINING_SUCCESS) 2846 2846 + if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) 2853 2847 dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); 2854 2848 } else { 2855 2849 status = dc_link_dp_perform_link_training(link, 2856 2850 &pipe_ctx->link_res, 2857 2857 - &current_setting, 2851 2851 + &cur_link_settings, 2858 2852 skip_video_pattern); 2859 2853 } 2860 2854 2861 2855 dp_trace_lt_total_count_increment(link, false); 2862 2856 dp_trace_lt_result_update(link, status, false); 2863 2857 dp_trace_set_lt_end_timestamp(link, false); 2864 2864 - if (status == LINK_TRAINING_SUCCESS) 2858 2858 + if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) 2865 2859 return true; 2866 2860 } 2867 2861 ··· 2872 2866 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY) 2873 2867 break; 2874 2868 2875 2875 - DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n", 2876 2876 - __func__, (unsigned int)j + 1, attempts); 2869 2869 + DC_LOG_WARNING("%s: Link training attempt %u of %d failed @ rate(%d) x lane(%d)\n", 2870 2870 + __func__, (unsigned int)j + 1, attempts, cur_link_settings.link_rate, 2871 2871 + cur_link_settings.lane_count); 2877 2872 2878 2873 dp_disable_link_phy(link, &pipe_ctx->link_res, signal); 2879 2874 ··· 2883 2876 enum dc_connection_type type = dc_connection_none; 2884 2877 2885 2878 dc_link_detect_sink(link, &type); 2886 2886 - if (type == dc_connection_none) 2879 2879 + if (type == dc_connection_none) { 2880 2880 + DC_LOG_HW_LINK_TRAINING("%s: Aborting training because sink unplugged\n", __func__); 2887 2881 break; 2888 2888 - } else if (do_fallback) { 2882 2882 + } 2883 2883 + } 2884 2884 + 2885 2885 + /* Try to train again at original settings if: 2886 2886 + * - not falling back between training attempts; 2887 2887 + * - aborted previous attempt due to reasons other than sink unplug; 2888 2888 + * - successfully trained but at a link rate lower than that required by stream; 2889 2889 + * - reached minimum link bandwidth. 2890 2890 + */ 2891 2891 + if (!do_fallback || (status == LINK_TRAINING_ABORT) || 2892 2892 + (status == LINK_TRAINING_SUCCESS && is_link_bw_low) || 2893 2893 + is_link_bw_min) { 2894 2894 + j++; 2895 2895 + cur_link_settings = *link_setting; 2896 2896 + delay_between_attempts += LINK_TRAINING_RETRY_DELAY; 2897 2897 + is_link_bw_low = false; 2898 2898 + is_link_bw_min = (cur_link_settings.link_rate <= LINK_RATE_LOW) && 2899 2899 + (cur_link_settings.lane_count <= LANE_COUNT_ONE); 2900 2900 + 2901 2901 + } else if (do_fallback) { /* Try training at lower link bandwidth if doing fallback. */ 2889 2902 uint32_t req_bw; 2890 2903 uint32_t link_bw; 2891 2904 2892 2892 - decide_fallback_link_setting(link, *link_setting, &current_setting, status); 2893 2893 - /* Fail link training if reduced link bandwidth no longer meets 2894 2894 - * stream requirements. 2905 2905 + decide_fallback_link_setting(link, *link_setting, &cur_link_settings, status); 2906 2906 + /* Flag if reduced link bandwidth no longer meets stream requirements or fallen back to 2907 2907 + * minimum link bandwidth. 2895 2908 */ 2896 2909 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing); 2897 2897 - link_bw = dc_link_bandwidth_kbps(link, &current_setting); 2898 2898 - if (req_bw > link_bw) 2899 2899 - break; 2910 2910 + link_bw = dc_link_bandwidth_kbps(link, &cur_link_settings); 2911 2911 + is_link_bw_low = (req_bw > link_bw); 2912 2912 + is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) && 2913 2913 + (cur_link_settings.lane_count <= LANE_COUNT_ONE)); 2914 2914 + 2915 2915 + if (is_link_bw_low) 2916 2916 + DC_LOG_WARNING("%s: Link bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n", 2917 2917 + __func__, req_bw, link_bw); 2900 2918 } 2901 2919 2902 2920 msleep(delay_between_attempts); 2903 2903 - 2904 2904 - delay_between_attempts += LINK_TRAINING_RETRY_DELAY; 2905 2921 } 2906 2906 - 2907 2922 return false; 2908 2923 } 2909 2924 ··· 5126 5097 return true; 5127 5098 } 5128 5099 5129 5129 - void dp_retrieve_lttpr_cap(struct dc_link *link) 5100 5100 + bool dp_retrieve_lttpr_cap(struct dc_link *link) 5130 5101 { 5102 5102 + uint8_t lttpr_dpcd_data[8]; 5131 5103 bool allow_lttpr_non_transparent_mode = 0; 5104 5104 + bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable; 5132 5105 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware; 5133 5106 enum dc_status status = DC_ERROR_UNEXPECTED; 5107 5107 + bool is_lttpr_present = false; 5134 5108 5135 5135 - memset(link->lttpr_dpcd_data, '\0', sizeof(link->lttpr_dpcd_data)); 5109 5109 + memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); 5136 5110 5137 5111 if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 && 5138 5112 link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) { ··· 5145 5113 allow_lttpr_non_transparent_mode = 1; 5146 5114 } 5147 5115 5148 5148 - link->lttpr_mode = LTTPR_MODE_NON_LTTPR; 5149 5149 - link->lttpr_support = LTTPR_UNSUPPORTED; 5150 5150 - 5151 5116 /* 5152 5152 - * Logic to determine LTTPR support 5117 5117 + * Logic to determine LTTPR mode 5153 5118 */ 5154 5154 - if (vbios_lttpr_interop) 5155 5155 - link->lttpr_support = LTTPR_SUPPORTED; 5156 5156 - else if (link->dc->config.allow_lttpr_non_transparent_mode.raw == 0 5157 5157 - || !link->dc->caps.extended_aux_timeout_support) 5158 5158 - link->lttpr_support = LTTPR_UNSUPPORTED; 5159 5159 - else 5160 5160 - link->lttpr_support = LTTPR_CHECK_EXT_SUPPORT; 5119 5119 + link->lttpr_mode = LTTPR_MODE_NON_LTTPR; 5120 5120 + if (vbios_lttpr_enable && vbios_lttpr_interop) 5121 5121 + link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; 5122 5122 + else if (!vbios_lttpr_enable && vbios_lttpr_interop) { 5123 5123 + if (allow_lttpr_non_transparent_mode) 5124 5124 + link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; 5125 5125 + else 5126 5126 + link->lttpr_mode = LTTPR_MODE_TRANSPARENT; 5127 5127 + } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) { 5128 5128 + if (!allow_lttpr_non_transparent_mode || !link->dc->caps.extended_aux_timeout_support) 5129 5129 + link->lttpr_mode = LTTPR_MODE_NON_LTTPR; 5130 5130 + else 5131 5131 + link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; 5132 5132 + } 5161 5133 5134 5134 + #if defined(CONFIG_DRM_AMD_DC_DCN) 5162 5135 /* Check DP tunnel LTTPR mode debug option. */ 5163 5136 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 5164 5137 link->dc->debug.dpia_debug.bits.force_non_lttpr) 5165 5165 - link->lttpr_support = LTTPR_UNSUPPORTED; 5138 5138 + link->lttpr_mode = LTTPR_MODE_NON_LTTPR; 5139 5139 + #endif 5166 5140 5167 5167 - if (link->lttpr_support > LTTPR_UNSUPPORTED) { 5141 5141 + if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { 5168 5142 /* By reading LTTPR capability, RX assumes that we will enable 5169 5143 * LTTPR extended aux timeout if LTTPR is present. 5170 5144 */ 5171 5145 status = core_link_read_dpcd( 5172 5146 link, 5173 5147 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 5174 5174 - link->lttpr_dpcd_data, 5175 5175 - sizeof(link->lttpr_dpcd_data)); 5148 5148 + lttpr_dpcd_data, 5149 5149 + sizeof(lttpr_dpcd_data)); 5150 5150 + 5151 5151 + link->dpcd_caps.lttpr_caps.revision.raw = 5152 5152 + lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - 5153 5153 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5154 5154 + 5155 5155 + link->dpcd_caps.lttpr_caps.max_link_rate = 5156 5156 + lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - 5157 5157 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5158 5158 + 5159 5159 + link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 5160 5160 + lttpr_dpcd_data[DP_PHY_REPEATER_CNT - 5161 5161 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5162 5162 + 5163 5163 + link->dpcd_caps.lttpr_caps.max_lane_count = 5164 5164 + lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - 5165 5165 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5166 5166 + 5167 5167 + link->dpcd_caps.lttpr_caps.mode = 5168 5168 + lttpr_dpcd_data[DP_PHY_REPEATER_MODE - 5169 5169 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5170 5170 + 5171 5171 + link->dpcd_caps.lttpr_caps.max_ext_timeout = 5172 5172 + lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - 5173 5173 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5174 5174 + link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw = 5175 5175 + lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 5176 5176 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5177 5177 + 5178 5178 + link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = 5179 5179 + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - 5180 5180 + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5181 5181 + 5182 5182 + /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ 5183 5183 + is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 0 && 5184 5184 + link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && 5185 5185 + link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); 5186 5186 + if (is_lttpr_present) { 5187 5187 + CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); 5188 5188 + configure_lttpr_mode_transparent(link); 5189 5189 + } else 5190 5190 + link->lttpr_mode = LTTPR_MODE_NON_LTTPR; 5176 5191 } 5177 5177 - } 5178 5178 - 5179 5179 - bool dp_parse_lttpr_mode(struct dc_link *link) 5180 5180 - { 5181 5181 - bool dpcd_allow_lttpr_non_transparent_mode = false; 5182 5182 - bool is_lttpr_present = false; 5183 5183 - 5184 5184 - bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable; 5185 5185 - 5186 5186 - if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 && 5187 5187 - link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) { 5188 5188 - dpcd_allow_lttpr_non_transparent_mode = true; 5189 5189 - } else if (link->dc->config.allow_lttpr_non_transparent_mode.bits.DP1_4A && 5190 5190 - !link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) { 5191 5191 - dpcd_allow_lttpr_non_transparent_mode = true; 5192 5192 - } 5193 5193 - 5194 5194 - /* 5195 5195 - * Logic to determine LTTPR mode 5196 5196 - */ 5197 5197 - if (link->lttpr_support == LTTPR_SUPPORTED) 5198 5198 - if (vbios_lttpr_enable) 5199 5199 - link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; 5200 5200 - else if (dpcd_allow_lttpr_non_transparent_mode) 5201 5201 - link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; 5202 5202 - else 5203 5203 - link->lttpr_mode = LTTPR_MODE_TRANSPARENT; 5204 5204 - else // lttpr_support == LTTPR_CHECK_EXT_SUPPORT 5205 5205 - if (dpcd_allow_lttpr_non_transparent_mode) { 5206 5206 - link->lttpr_support = LTTPR_SUPPORTED; 5207 5207 - link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; 5208 5208 - } else { 5209 5209 - link->lttpr_support = LTTPR_UNSUPPORTED; 5210 5210 - } 5211 5211 - 5212 5212 - if (link->lttpr_support == LTTPR_UNSUPPORTED) 5213 5213 - return false; 5214 5214 - 5215 5215 - link->dpcd_caps.lttpr_caps.revision.raw = 5216 5216 - link->lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - 5217 5217 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5218 5218 - 5219 5219 - link->dpcd_caps.lttpr_caps.max_link_rate = 5220 5220 - link->lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - 5221 5221 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5222 5222 - 5223 5223 - link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 5224 5224 - link->lttpr_dpcd_data[DP_PHY_REPEATER_CNT - 5225 5225 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5226 5226 - 5227 5227 - link->dpcd_caps.lttpr_caps.max_lane_count = 5228 5228 - link->lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - 5229 5229 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5230 5230 - 5231 5231 - link->dpcd_caps.lttpr_caps.mode = 5232 5232 - link->lttpr_dpcd_data[DP_PHY_REPEATER_MODE - 5233 5233 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5234 5234 - 5235 5235 - link->dpcd_caps.lttpr_caps.max_ext_timeout = 5236 5236 - link->lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - 5237 5237 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5238 5238 - 5239 5239 - link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw = 5240 5240 - link->lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 5241 5241 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5242 5242 - 5243 5243 - link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = 5244 5244 - link->lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - 5245 5245 - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 5246 5246 - 5247 5247 - 5248 5248 - /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ 5249 5249 - is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 0 && 5250 5250 - link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && 5251 5251 - link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); 5252 5252 - if (is_lttpr_present) { 5253 5253 - CONN_DATA_DETECT(link, link->lttpr_dpcd_data, sizeof(link->lttpr_dpcd_data), "LTTPR Caps: "); 5254 5254 - configure_lttpr_mode_transparent(link); 5255 5255 - } else 5256 5256 - link->lttpr_mode = LTTPR_MODE_NON_LTTPR; 5257 5257 - 5258 5192 return is_lttpr_present; 5259 5193 } 5260 5194 ··· 5372 5374 status = wa_try_to_wake_dprx(link, timeout_ms); 5373 5375 } 5374 5376 5375 5375 - dp_retrieve_lttpr_cap(link); 5376 5376 - 5377 5377 + is_lttpr_present = dp_retrieve_lttpr_cap(link); 5377 5378 /* Read DP tunneling information. */ 5378 5379 status = dpcd_get_tunneling_device_data(link); 5379 5380 ··· 5407 5410 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__); 5408 5411 return false; 5409 5412 } 5410 5410 - 5411 5411 - if (link->lttpr_support > LTTPR_UNSUPPORTED) 5412 5412 - is_lttpr_present = dp_parse_lttpr_mode(link); 5413 5413 5414 5414 if (!is_lttpr_present) 5415 5415 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);

+19

drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c

reviewed

··· 34 34 #include "dm_helpers.h" 35 35 #include "dmub/inc/dmub_cmd.h" 36 36 #include "inc/link_dpcd.h" 37 37 + #include "dc_dmub_srv.h" 37 38 38 39 #define DC_LOGGER \ 39 40 link->ctx->logger ··· 68 67 link->dpcd_caps.usb4_dp_tun_info.usb4_topology_id[i] = dpcd_topology_data[i]; 69 68 70 69 return status; 70 70 + } 71 71 + 72 72 + bool dc_link_dpia_query_hpd_status(struct dc_link *link) 73 73 + { 74 74 + union dmub_rb_cmd cmd = {0}; 75 75 + struct dc_dmub_srv *dmub_srv = link->ctx->dmub_srv; 76 76 + bool is_hpd_high = false; 77 77 + 78 78 + /* prepare QUERY_HPD command */ 79 79 + cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE; 80 80 + cmd.query_hpd.data.instance = link->link_id.enum_id - ENUM_ID_1; 81 81 + cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA; 82 82 + 83 83 + /* Return HPD status reported by DMUB if query successfully executed. */ 84 84 + if (dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd) && cmd.query_hpd.data.status == AUX_RET_SUCCESS) 85 85 + is_hpd_high = cmd.query_hpd.data.result; 86 86 + 87 87 + return is_hpd_high; 71 88 } 72 89 73 90 /* Configure link as prescribed in link_setting; set LTTPR mode; and

+2

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

reviewed

··· 61 61 plane_state->blend_tf->type = TF_TYPE_BYPASS; 62 62 } 63 63 64 64 + plane_state->pre_multiplied_alpha = true; 65 65 + 64 66 } 65 67 66 68 static void dc_plane_destruct(struct dc_plane_state *plane_state)

+4 -2

drivers/gpu/drm/amd/display/dc/dc.h

reviewed

··· 47 47 struct set_config_cmd_payload; 48 48 struct dmub_notification; 49 49 50 50 - #define DC_VER "3.2.185" 50 50 + #define DC_VER "3.2.186" 51 51 52 52 #define MAX_SURFACES 3 53 53 #define MAX_PLANES 6 ··· 329 329 bool disable_dmcu; 330 330 bool enable_4to1MPC; 331 331 bool enable_windowed_mpo_odm; 332 332 - bool allow_edp_hotplug_detection; 332 332 + uint32_t allow_edp_hotplug_detection; 333 333 bool clamp_min_dcfclk; 334 334 uint64_t vblank_alignment_dto_params; 335 335 uint8_t vblank_alignment_max_frame_time_diff; ··· 1011 1011 1012 1012 bool is_tiling_rotated; 1013 1013 bool per_pixel_alpha; 1014 1014 + bool pre_multiplied_alpha; 1014 1015 bool global_alpha; 1015 1016 int global_alpha_value; 1016 1017 bool visible; ··· 1046 1045 bool horizontal_mirror; 1047 1046 bool visible; 1048 1047 bool per_pixel_alpha; 1048 1048 + bool pre_multiplied_alpha; 1049 1049 bool global_alpha; 1050 1050 int global_alpha_value; 1051 1051 bool input_csc_enabled;

-2

drivers/gpu/drm/amd/display/dc/dc_link.h

reviewed

··· 129 129 bool link_state_valid; 130 130 bool aux_access_disabled; 131 131 bool sync_lt_in_progress; 132 132 - uint8_t lttpr_dpcd_data[8]; 133 133 - enum lttpr_support lttpr_support; 134 132 enum lttpr_mode lttpr_mode; 135 133 bool is_internal_display; 136 134

+2 -1

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

reviewed

··· 87 87 88 88 engine->ddc = NULL; 89 89 90 90 - REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1); 90 90 + REG_UPDATE_2(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1, 91 91 + AUX_SW_USE_AUX_REG_REQ, 0); 91 92 } 92 93 93 94 #define SW_CAN_ACCESS_AUX 1

+6 -3

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

reviewed

··· 1101 1101 * not be programmed equal to DPREFCLK 1102 1102 */ 1103 1103 modulo_hz = REG_READ(MODULO[inst]); 1104 1104 - *pixel_clk_khz = div_u64((uint64_t)clock_hz* 1105 1105 - clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, 1106 1106 - modulo_hz); 1104 1104 + if (modulo_hz) 1105 1105 + *pixel_clk_khz = div_u64((uint64_t)clock_hz* 1106 1106 + clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, 1107 1107 + modulo_hz); 1108 1108 + else 1109 1109 + *pixel_clk_khz = 0; 1107 1110 } else { 1108 1111 /* NOTE: There is agreement with VBIOS here that MODULO is 1109 1112 * programmed equal to DPREFCLK, in which case PHASE will be

+14 -13

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

reviewed

··· 2550 2550 blnd_cfg.overlap_only = false; 2551 2551 blnd_cfg.global_gain = 0xff; 2552 2552 2553 2553 - if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) { 2554 2554 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2555 2555 - blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2556 2556 - } else if (per_pixel_alpha) { 2557 2557 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2553 2553 + if (per_pixel_alpha) { 2554 2554 + /* DCN1.0 has output CM before MPC which seems to screw with 2555 2555 + * pre-multiplied alpha. 2556 2556 + */ 2557 2557 + blnd_cfg.pre_multiplied_alpha = (is_rgb_cspace( 2558 2558 + pipe_ctx->stream->output_color_space) 2559 2559 + && pipe_ctx->plane_state->pre_multiplied_alpha); 2560 2560 + if (pipe_ctx->plane_state->global_alpha) { 2561 2561 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2562 2562 + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2563 2563 + } else { 2564 2564 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2565 2565 + } 2558 2566 } else { 2567 2567 + blnd_cfg.pre_multiplied_alpha = false; 2559 2568 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2560 2569 } 2561 2570 ··· 2572 2563 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2573 2564 else 2574 2565 blnd_cfg.global_alpha = 0xff; 2575 2575 - 2576 2576 - /* DCN1.0 has output CM before MPC which seems to screw with 2577 2577 - * pre-multiplied alpha. 2578 2578 - */ 2579 2579 - blnd_cfg.pre_multiplied_alpha = is_rgb_cspace( 2580 2580 - pipe_ctx->stream->output_color_space) 2581 2581 - && per_pixel_alpha; 2582 2582 - 2583 2566 2584 2567 /* 2585 2568 * TODO: remove hack

+10 -7

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

reviewed

··· 1773 1773 */ 1774 1774 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1775 1775 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1776 1776 - 1777 1776 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1778 1777 struct hubp *hubp = pipe->plane_res.hubp; 1779 1778 int j = 0; ··· 2345 2346 blnd_cfg.overlap_only = false; 2346 2347 blnd_cfg.global_gain = 0xff; 2347 2348 2348 2348 - if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) { 2349 2349 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2350 2350 - blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2351 2351 - } else if (per_pixel_alpha) { 2352 2352 - blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2349 2349 + if (per_pixel_alpha) { 2350 2350 + blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2351 2351 + if (pipe_ctx->plane_state->global_alpha) { 2352 2352 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2353 2353 + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2354 2354 + } else { 2355 2355 + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2356 2356 + } 2353 2357 } else { 2358 2358 + blnd_cfg.pre_multiplied_alpha = false; 2354 2359 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2355 2360 } 2356 2361 ··· 2368 2365 blnd_cfg.top_gain = 0x1f000; 2369 2366 blnd_cfg.bottom_inside_gain = 0x1f000; 2370 2367 blnd_cfg.bottom_outside_gain = 0x1f000; 2371 2371 - blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2368 2368 + 2372 2369 if (pipe_ctx->plane_state->format 2373 2370 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2374 2371 blnd_cfg.pre_multiplied_alpha = false;

+10

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c

reviewed

··· 28 28 #include "dc.h" 29 29 #include "dcn_calc_math.h" 30 30 31 31 + #include "dml/dcn30/dcn30_fpu.h" 32 32 + 31 33 #define REG(reg)\ 32 34 optc1->tg_regs->reg 33 35 ··· 184 182 185 183 REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); 186 184 185 185 + } 186 186 + 187 187 + void optc3_set_vrr_m_const(struct timing_generator *optc, 188 188 + double vtotal_avg) 189 189 + { 190 190 + DC_FP_START(); 191 191 + optc3_fpu_set_vrr_m_const(optc, vtotal_avg); 192 192 + DC_FP_END(); 187 193 } 188 194 189 195 void optc3_set_odm_bypass(struct timing_generator *optc,

+41 -477

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

reviewed

··· 84 84 #include "dce/dce_aux.h" 85 85 #include "dce/dce_i2c.h" 86 86 87 87 + #include "dml/dcn30/dcn30_fpu.h" 87 88 #include "dml/dcn30/display_mode_vba_30.h" 88 89 #include "vm_helper.h" 89 90 #include "dcn20/dcn20_vmid.h" 90 91 #include "amdgpu_socbb.h" 91 92 92 93 #define DC_LOGGER_INIT(logger) 93 93 - 94 94 - struct _vcs_dpi_ip_params_st dcn3_0_ip = { 95 95 - .use_min_dcfclk = 0, 96 96 - .clamp_min_dcfclk = 0, 97 97 - .odm_capable = 1, 98 98 - .gpuvm_enable = 0, 99 99 - .hostvm_enable = 0, 100 100 - .gpuvm_max_page_table_levels = 4, 101 101 - .hostvm_max_page_table_levels = 4, 102 102 - .hostvm_cached_page_table_levels = 0, 103 103 - .pte_group_size_bytes = 2048, 104 104 - .num_dsc = 6, 105 105 - .rob_buffer_size_kbytes = 184, 106 106 - .det_buffer_size_kbytes = 184, 107 107 - .dpte_buffer_size_in_pte_reqs_luma = 84, 108 108 - .pde_proc_buffer_size_64k_reqs = 48, 109 109 - .dpp_output_buffer_pixels = 2560, 110 110 - .opp_output_buffer_lines = 1, 111 111 - .pixel_chunk_size_kbytes = 8, 112 112 - .pte_enable = 1, 113 113 - .max_page_table_levels = 2, 114 114 - .pte_chunk_size_kbytes = 2, // ? 115 115 - .meta_chunk_size_kbytes = 2, 116 116 - .writeback_chunk_size_kbytes = 8, 117 117 - .line_buffer_size_bits = 789504, 118 118 - .is_line_buffer_bpp_fixed = 0, // ? 119 119 - .line_buffer_fixed_bpp = 0, // ? 120 120 - .dcc_supported = true, 121 121 - .writeback_interface_buffer_size_kbytes = 90, 122 122 - .writeback_line_buffer_buffer_size = 0, 123 123 - .max_line_buffer_lines = 12, 124 124 - .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 125 125 - .writeback_chroma_buffer_size_kbytes = 8, 126 126 - .writeback_chroma_line_buffer_width_pixels = 4, 127 127 - .writeback_max_hscl_ratio = 1, 128 128 - .writeback_max_vscl_ratio = 1, 129 129 - .writeback_min_hscl_ratio = 1, 130 130 - .writeback_min_vscl_ratio = 1, 131 131 - .writeback_max_hscl_taps = 1, 132 132 - .writeback_max_vscl_taps = 1, 133 133 - .writeback_line_buffer_luma_buffer_size = 0, 134 134 - .writeback_line_buffer_chroma_buffer_size = 14643, 135 135 - .cursor_buffer_size = 8, 136 136 - .cursor_chunk_size = 2, 137 137 - .max_num_otg = 6, 138 138 - .max_num_dpp = 6, 139 139 - .max_num_wb = 1, 140 140 - .max_dchub_pscl_bw_pix_per_clk = 4, 141 141 - .max_pscl_lb_bw_pix_per_clk = 2, 142 142 - .max_lb_vscl_bw_pix_per_clk = 4, 143 143 - .max_vscl_hscl_bw_pix_per_clk = 4, 144 144 - .max_hscl_ratio = 6, 145 145 - .max_vscl_ratio = 6, 146 146 - .hscl_mults = 4, 147 147 - .vscl_mults = 4, 148 148 - .max_hscl_taps = 8, 149 149 - .max_vscl_taps = 8, 150 150 - .dispclk_ramp_margin_percent = 1, 151 151 - .underscan_factor = 1.11, 152 152 - .min_vblank_lines = 32, 153 153 - .dppclk_delay_subtotal = 46, 154 154 - .dynamic_metadata_vm_enabled = true, 155 155 - .dppclk_delay_scl_lb_only = 16, 156 156 - .dppclk_delay_scl = 50, 157 157 - .dppclk_delay_cnvc_formatter = 27, 158 158 - .dppclk_delay_cnvc_cursor = 6, 159 159 - .dispclk_delay_subtotal = 119, 160 160 - .dcfclk_cstate_latency = 5.2, // SRExitTime 161 161 - .max_inter_dcn_tile_repeaters = 8, 162 162 - .odm_combine_4to1_supported = true, 163 163 - 164 164 - .xfc_supported = false, 165 165 - .xfc_fill_bw_overhead_percent = 10.0, 166 166 - .xfc_fill_constant_bytes = 0, 167 167 - .gfx7_compat_tiling_supported = 0, 168 168 - .number_of_cursors = 1, 169 169 - }; 170 170 - 171 171 - struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { 172 172 - .clock_limits = { 173 173 - { 174 174 - .state = 0, 175 175 - .dispclk_mhz = 562.0, 176 176 - .dppclk_mhz = 300.0, 177 177 - .phyclk_mhz = 300.0, 178 178 - .phyclk_d18_mhz = 667.0, 179 179 - .dscclk_mhz = 405.6, 180 180 - }, 181 181 - }, 182 182 - .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 183 183 - .num_states = 1, 184 184 - .sr_exit_time_us = 15.5, 185 185 - .sr_enter_plus_exit_time_us = 20, 186 186 - .urgent_latency_us = 4.0, 187 187 - .urgent_latency_pixel_data_only_us = 4.0, 188 188 - .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 189 189 - .urgent_latency_vm_data_only_us = 4.0, 190 190 - .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 191 191 - .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 192 192 - .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 193 193 - .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 194 194 - .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 195 195 - .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 196 196 - .max_avg_sdp_bw_use_normal_percent = 60.0, 197 197 - .max_avg_dram_bw_use_normal_percent = 40.0, 198 198 - .writeback_latency_us = 12.0, 199 199 - .max_request_size_bytes = 256, 200 200 - .fabric_datapath_to_dcn_data_return_bytes = 64, 201 201 - .dcn_downspread_percent = 0.5, 202 202 - .downspread_percent = 0.38, 203 203 - .dram_page_open_time_ns = 50.0, 204 204 - .dram_rw_turnaround_time_ns = 17.5, 205 205 - .dram_return_buffer_per_channel_bytes = 8192, 206 206 - .round_trip_ping_latency_dcfclk_cycles = 191, 207 207 - .urgent_out_of_order_return_per_channel_bytes = 4096, 208 208 - .channel_interleave_bytes = 256, 209 209 - .num_banks = 8, 210 210 - .gpuvm_min_page_size_bytes = 4096, 211 211 - .hostvm_min_page_size_bytes = 4096, 212 212 - .dram_clock_change_latency_us = 404, 213 213 - .dummy_pstate_latency_us = 5, 214 214 - .writeback_dram_clock_change_latency_us = 23.0, 215 215 - .return_bus_width_bytes = 64, 216 216 - .dispclk_dppclk_vco_speed_mhz = 3650, 217 217 - .xfc_bus_transport_time_us = 20, // ? 218 218 - .xfc_xbuf_latency_tolerance_us = 4, // ? 219 219 - .use_urgent_burst_bw = 1, // ? 220 220 - .do_urgent_latency_adjustment = true, 221 221 - .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 222 222 - .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 223 223 - }; 224 94 225 95 enum dcn30_clk_src_array_id { 226 96 DCN30_CLK_SRC_PLL0, ··· 1350 1480 void dcn30_populate_dml_writeback_from_context( 1351 1481 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1352 1482 { 1353 1353 - int pipe_cnt, i, j; 1354 1354 - double max_calc_writeback_dispclk; 1355 1355 - double writeback_dispclk; 1356 1356 - struct writeback_st dout_wb; 1357 1357 - 1358 1358 - for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1359 1359 - struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream; 1360 1360 - 1361 1361 - if (!stream) 1362 1362 - continue; 1363 1363 - max_calc_writeback_dispclk = 0; 1364 1364 - 1365 1365 - /* Set writeback information */ 1366 1366 - pipes[pipe_cnt].dout.wb_enable = 0; 1367 1367 - pipes[pipe_cnt].dout.num_active_wb = 0; 1368 1368 - for (j = 0; j < stream->num_wb_info; j++) { 1369 1369 - struct dc_writeback_info *wb_info = &stream->writeback_info[j]; 1370 1370 - 1371 1371 - if (wb_info->wb_enabled && wb_info->writeback_source_plane && 1372 1372 - (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { 1373 1373 - pipes[pipe_cnt].dout.wb_enable = 1; 1374 1374 - pipes[pipe_cnt].dout.num_active_wb++; 1375 1375 - dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? 1376 1376 - wb_info->dwb_params.cnv_params.crop_height : 1377 1377 - wb_info->dwb_params.cnv_params.src_height; 1378 1378 - dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? 1379 1379 - wb_info->dwb_params.cnv_params.crop_width : 1380 1380 - wb_info->dwb_params.cnv_params.src_width; 1381 1381 - dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; 1382 1382 - dout_wb.wb_dst_height = wb_info->dwb_params.dest_height; 1383 1383 - 1384 1384 - /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */ 1385 1385 - if (dc->dml.ip.writeback_max_hscl_taps > 1) { 1386 1386 - dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; 1387 1387 - dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; 1388 1388 - } else { 1389 1389 - dout_wb.wb_htaps_luma = 1; 1390 1390 - dout_wb.wb_vtaps_luma = 1; 1391 1391 - } 1392 1392 - dout_wb.wb_htaps_chroma = 0; 1393 1393 - dout_wb.wb_vtaps_chroma = 0; 1394 1394 - dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ? 1395 1395 - (double)wb_info->dwb_params.cnv_params.crop_width / 1396 1396 - (double)wb_info->dwb_params.dest_width : 1397 1397 - (double)wb_info->dwb_params.cnv_params.src_width / 1398 1398 - (double)wb_info->dwb_params.dest_width; 1399 1399 - dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ? 1400 1400 - (double)wb_info->dwb_params.cnv_params.crop_height / 1401 1401 - (double)wb_info->dwb_params.dest_height : 1402 1402 - (double)wb_info->dwb_params.cnv_params.src_height / 1403 1403 - (double)wb_info->dwb_params.dest_height; 1404 1404 - if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB || 1405 1405 - wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA) 1406 1406 - dout_wb.wb_pixel_format = dm_444_64; 1407 1407 - else 1408 1408 - dout_wb.wb_pixel_format = dm_444_32; 1409 1409 - 1410 1410 - /* Workaround for cases where multiple writebacks are connected to same plane 1411 1411 - * In which case, need to compute worst case and set the associated writeback parameters 1412 1412 - * This workaround is necessary due to DML computation assuming only 1 set of writeback 1413 1413 - * parameters per pipe 1414 1414 - */ 1415 1415 - writeback_dispclk = dml30_CalculateWriteBackDISPCLK( 1416 1416 - dout_wb.wb_pixel_format, 1417 1417 - pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 1418 1418 - dout_wb.wb_hratio, 1419 1419 - dout_wb.wb_vratio, 1420 1420 - dout_wb.wb_htaps_luma, 1421 1421 - dout_wb.wb_vtaps_luma, 1422 1422 - dout_wb.wb_src_width, 1423 1423 - dout_wb.wb_dst_width, 1424 1424 - pipes[pipe_cnt].pipe.dest.htotal, 1425 1425 - dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); 1426 1426 - 1427 1427 - if (writeback_dispclk > max_calc_writeback_dispclk) { 1428 1428 - max_calc_writeback_dispclk = writeback_dispclk; 1429 1429 - pipes[pipe_cnt].dout.wb = dout_wb; 1430 1430 - } 1431 1431 - } 1432 1432 - } 1433 1433 - 1434 1434 - pipe_cnt++; 1435 1435 - } 1436 1436 - 1483 1483 + DC_FP_START(); 1484 1484 + dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); 1485 1485 + DC_FP_END(); 1437 1486 } 1438 1487 1439 1488 unsigned int dcn30_calc_max_scaled_time( ··· 1387 1598 enum mmhubbub_wbif_mode wbif_mode; 1388 1599 struct display_mode_lib *dml = &context->bw_ctx.dml; 1389 1600 struct mcif_arb_params *wb_arb_params; 1390 1390 - int i, j, k, dwb_pipe; 1601 1601 + int i, j, dwb_pipe; 1391 1602 1392 1603 /* Writeback MCIF_WB arbitration parameters */ 1393 1604 dwb_pipe = 0; ··· 1411 1622 else 1412 1623 wbif_mode = PACKED_444; 1413 1624 1414 1414 - for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 1415 1415 - wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; 1416 1416 - wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1417 1417 - } 1625 1625 + DC_FP_START(); 1626 1626 + dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); 1627 1627 + DC_FP_END(); 1418 1628 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */ 1419 1629 wb_arb_params->slice_lines = 32; 1420 1630 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */ 1421 1631 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel, 1422 1632 wbif_mode, 1423 1633 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 1424 1424 - wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ 1425 1634 1426 1635 dwb_pipe++; 1427 1636 ··· 1898 2111 return out; 1899 2112 } 1900 2113 1901 1901 - /* 1902 1902 - * This must be noinline to ensure anything that deals with FP registers 1903 1903 - * is contained within this call; previously our compiling with hard-float 1904 1904 - * would result in fp instructions being emitted outside of the boundaries 1905 1905 - * of the DC_FP_START/END macros, which makes sense as the compiler has no 1906 1906 - * idea about what is wrapped and what is not 1907 1907 - * 1908 1908 - * This is largely just a workaround to avoid breakage introduced with 5.6, 1909 1909 - * ideally all fp-using code should be moved into its own file, only that 1910 1910 - * should be compiled with hard-float, and all code exported from there 1911 1911 - * should be strictly wrapped with DC_FP_START/END 1912 1912 - */ 1913 1913 - static noinline void dcn30_calculate_wm_and_dlg_fp( 1914 1914 - struct dc *dc, struct dc_state *context, 1915 1915 - display_e2e_pipe_params_st *pipes, 1916 1916 - int pipe_cnt, 1917 1917 - int vlevel) 1918 1918 - { 1919 1919 - int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 1920 1920 - int i, pipe_idx; 1921 1921 - double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; 1922 1922 - bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; 1923 1923 - 1924 1924 - if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 1925 1925 - dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 1926 1926 - 1927 1927 - pipes[0].clks_cfg.voltage = vlevel; 1928 1928 - pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1929 1929 - pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 1930 1930 - 1931 1931 - /* Set B: 1932 1932 - * DCFCLK: 1GHz or min required above 1GHz 1933 1933 - * FCLK/UCLK: Max 1934 1934 - */ 1935 1935 - if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 1936 1936 - if (vlevel == 0) { 1937 1937 - pipes[0].clks_cfg.voltage = 1; 1938 1938 - pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 1939 1939 - } 1940 1940 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 1941 1941 - context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 1942 1942 - context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 1943 1943 - } 1944 1944 - context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1945 1945 - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1946 1946 - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1947 1947 - context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1948 1948 - context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1949 1949 - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1950 1950 - context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1951 1951 - context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1952 1952 - 1953 1953 - pipes[0].clks_cfg.voltage = vlevel; 1954 1954 - pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 1955 1955 - 1956 1956 - /* Set D: 1957 1957 - * DCFCLK: Min Required 1958 1958 - * FCLK(proportional to UCLK): 1GHz or Max 1959 1959 - * MALL stutter, sr_enter_exit = 4, sr_exit = 2us 1960 1960 - */ 1961 1961 - /* 1962 1962 - if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 1963 1963 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 1964 1964 - context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 1965 1965 - context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 1966 1966 - } 1967 1967 - context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1968 1968 - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1969 1969 - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1970 1970 - context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1971 1971 - context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1972 1972 - context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1973 1973 - context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1974 1974 - context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1975 1975 - */ 1976 1976 - 1977 1977 - /* Set C: 1978 1978 - * DCFCLK: Min Required 1979 1979 - * FCLK(proportional to UCLK): 1GHz or Max 1980 1980 - * pstate latency overridden to 5us 1981 1981 - */ 1982 1982 - if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 1983 1983 - unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 1984 1984 - unsigned int min_dram_speed_mts_margin = 160; 1985 1985 - 1986 1986 - if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported) 1987 1987 - min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16; 1988 1988 - 1989 1989 - /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */ 1990 1990 - for (i = 3; i > 0; i--) 1991 1991 - if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts) 1992 1992 - break; 1993 1993 - 1994 1994 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us; 1995 1995 - context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 1996 1996 - context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 1997 1997 - } 1998 1998 - 1999 1999 - context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2000 2000 - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2001 2001 - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2002 2002 - context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2003 2003 - context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2004 2004 - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2005 2005 - context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2006 2006 - context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2007 2007 - 2008 2008 - if (!pstate_en) { 2009 2009 - /* The only difference between A and C is p-state latency, if p-state is not supported we want to 2010 2010 - * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark 2011 2011 - */ 2012 2012 - context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 2013 2013 - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 2014 2014 - } else { 2015 2015 - /* Set A: 2016 2016 - * DCFCLK: Min Required 2017 2017 - * FCLK(proportional to UCLK): 1GHz or Max 2018 2018 - * 2019 2019 - * Set A calculated last so that following calculations are based on Set A 2020 2020 - */ 2021 2021 - dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 2022 2022 - context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2023 2023 - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2024 2024 - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2025 2025 - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2026 2026 - context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2027 2027 - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2028 2028 - context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2029 2029 - context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2030 2030 - } 2031 2031 - 2032 2032 - context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 2033 2033 - 2034 2034 - /* Make set D = set A until set D is enabled */ 2035 2035 - context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 2036 2036 - 2037 2037 - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2038 2038 - if (!context->res_ctx.pipe_ctx[i].stream) 2039 2039 - continue; 2040 2040 - 2041 2041 - pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 2042 2042 - pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 2043 2043 - 2044 2044 - if (dc->config.forced_clocks) { 2045 2045 - pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2046 2046 - pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2047 2047 - } 2048 2048 - if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 2049 2049 - pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2050 2050 - if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2051 2051 - pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2052 2052 - 2053 2053 - pipe_idx++; 2054 2054 - } 2055 2055 - 2056 2056 - DC_FP_START(); 2057 2057 - dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2058 2058 - DC_FP_END(); 2059 2059 - 2060 2060 - if (!pstate_en) 2061 2061 - /* Restore full p-state latency */ 2062 2062 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2063 2063 - dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2064 2064 - } 2065 2065 - 2066 2114 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 2067 2115 { 2068 2068 - if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { 2069 2069 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2070 2070 - context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 2071 2071 - context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 2072 2072 - } 2116 2116 + DC_FP_START(); 2117 2117 + dcn30_fpu_update_soc_for_wm_a(dc, context); 2118 2118 + DC_FP_END(); 2073 2119 } 2074 2120 2075 2121 void dcn30_calculate_wm_and_dlg( ··· 1912 2292 int vlevel) 1913 2293 { 1914 2294 DC_FP_START(); 1915 1915 - dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 2295 2295 + dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1916 2296 DC_FP_END(); 1917 2297 } 1918 2298 ··· 1971 2351 return out; 1972 2352 } 1973 2353 1974 1974 - /* 1975 1975 - * This must be noinline to ensure anything that deals with FP registers 1976 1976 - * is contained within this call; previously our compiling with hard-float 1977 1977 - * would result in fp instructions being emitted outside of the boundaries 1978 1978 - * of the DC_FP_START/END macros, which makes sense as the compiler has no 1979 1979 - * idea about what is wrapped and what is not 1980 1980 - * 1981 1981 - * This is largely just a workaround to avoid breakage introduced with 5.6, 1982 1982 - * ideally all fp-using code should be moved into its own file, only that 1983 1983 - * should be compiled with hard-float, and all code exported from there 1984 1984 - * should be strictly wrapped with DC_FP_START/END 1985 1985 - */ 1986 1986 - static noinline void dcn30_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1987 1987 - unsigned int *optimal_dcfclk, 1988 1988 - unsigned int *optimal_fclk) 1989 1989 - { 1990 1990 - double bw_from_dram, bw_from_dram1, bw_from_dram2; 1991 1991 - 1992 1992 - bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * 1993 1993 - dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); 1994 1994 - bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans * 1995 1995 - dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); 1996 1996 - 1997 1997 - bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1998 1998 - 1999 1999 - if (optimal_fclk) 2000 2000 - *optimal_fclk = bw_from_dram / 2001 2001 - (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2002 2002 - 2003 2003 - if (optimal_dcfclk) 2004 2004 - *optimal_dcfclk = bw_from_dram / 2005 2005 - (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2006 2006 - } 2007 2007 - 2008 2354 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2009 2355 { 2010 2356 unsigned int i, j; ··· 1985 2399 unsigned int num_dcfclk_sta_targets = 4; 1986 2400 unsigned int num_uclk_states; 1987 2401 2402 2402 + struct dc_bounding_box_max_clk dcn30_bb_max_clk; 2403 2403 + 2404 2404 + memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk)); 2405 2405 + 1988 2406 if (dc->ctx->dc_bios->vram_info.num_chans) 1989 2407 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1990 2408 1991 1991 - if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1992 1992 - dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1993 1993 - 1994 1994 - dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1995 1995 - dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2409 2409 + DC_FP_START(); 2410 2410 + dcn30_fpu_update_dram_channel_width_bytes(dc); 2411 2411 + DC_FP_END(); 1996 2412 1997 2413 if (bw_params->clk_table.entries[0].memclk_mhz) { 1998 1998 - int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1999 2414 2000 2415 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2001 2001 - if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 2002 2002 - max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2003 2003 - if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 2004 2004 - max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2005 2005 - if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 2006 2006 - max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2007 2007 - if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 2008 2008 - max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2416 2416 + if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) 2417 2417 + dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2418 2418 + if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) 2419 2419 + dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2420 2420 + if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) 2421 2421 + dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2422 2422 + if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) 2423 2423 + dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2009 2424 } 2010 2425 2011 2011 - if (!max_dcfclk_mhz) 2012 2012 - max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; 2013 2013 - if (!max_dispclk_mhz) 2014 2014 - max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; 2015 2015 - if (!max_dppclk_mhz) 2016 2016 - max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; 2017 2017 - if (!max_phyclk_mhz) 2018 2018 - max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; 2426 2426 + DC_FP_START(); 2427 2427 + dcn30_fpu_update_max_clk(&dcn30_bb_max_clk); 2428 2428 + DC_FP_END(); 2019 2429 2020 2020 - if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2430 2430 + if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2021 2431 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2022 2022 - dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 2432 2432 + dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; 2023 2433 num_dcfclk_sta_targets++; 2024 2024 - } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2434 2434 + } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2025 2435 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2026 2436 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2027 2027 - if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 2028 2028 - dcfclk_sta_targets[i] = max_dcfclk_mhz; 2437 2437 + if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) { 2438 2438 + dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz; 2029 2439 break; 2030 2440 } 2031 2441 } ··· 2034 2452 // Calculate optimal dcfclk for each uclk 2035 2453 for (i = 0; i < num_uclk_states; i++) { 2036 2454 DC_FP_START(); 2037 2037 - dcn30_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2455 2455 + dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2038 2456 &optimal_dcfclk_for_uclk[i], NULL); 2039 2457 DC_FP_END(); 2040 2458 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { ··· 2061 2479 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2062 2480 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2063 2481 } else { 2064 2064 - if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2482 2482 + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { 2065 2483 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2066 2484 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2067 2485 } else { ··· 2076 2494 } 2077 2495 2078 2496 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2079 2079 - optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 2497 2497 + optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { 2080 2498 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2081 2499 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2082 2500 } 2083 2501 2084 2502 dcn3_0_soc.num_states = num_states; 2085 2085 - for (i = 0; i < dcn3_0_soc.num_states; i++) { 2086 2086 - dcn3_0_soc.clock_limits[i].state = i; 2087 2087 - dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2088 2088 - dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2089 2089 - dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2090 2090 - 2091 2091 - /* Fill all states with max values of all other clocks */ 2092 2092 - dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 2093 2093 - dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 2094 2094 - dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 2095 2095 - dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; 2096 2096 - /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ 2097 2097 - /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 2098 2098 - dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; 2099 2099 - dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; 2100 2100 - dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; 2101 2101 - } 2102 2102 - /* re-init DML with updated bb */ 2103 2103 - dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2104 2104 - if (dc->current_state) 2105 2105 - dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2503 2503 + DC_FP_START(); 2504 2504 + dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); 2505 2505 + DC_FP_END(); 2106 2506 } 2107 2507 } 2108 2508

+5

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h

reviewed

··· 35 35 struct resource_pool; 36 36 struct _vcs_dpi_display_pipe_params_st; 37 37 38 38 + extern struct _vcs_dpi_ip_params_st dcn3_0_ip; 39 39 + extern struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc; 40 40 + 38 41 struct dcn30_resource_pool { 39 42 struct resource_pool base; 40 43 }; ··· 98 95 struct dc_stream_state *dc_stream); 99 96 100 97 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); 98 98 + 99 99 + void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context); 101 100 102 101 #endif /* _DCN30_RESOURCE_H_ */

+2

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

reviewed

··· 81 81 #include "dce/dce_aux.h" 82 82 #include "dce/dce_i2c.h" 83 83 84 84 + #include "dml/dcn30/dcn30_fpu.h" 85 85 + 84 86 #include "dml/dcn30/display_mode_vba_30.h" 85 87 #include "dml/dcn301/dcn301_fpu.h" 86 88 #include "vm_helper.h"

+2

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

reviewed

··· 43 43 #include "dcn20/dcn20_dsc.h" 44 44 #include "dcn20/dcn20_resource.h" 45 45 46 46 + #include "dml/dcn30/dcn30_fpu.h" 47 47 + 46 48 #include "dcn10/dcn10_resource.h" 47 49 48 50 #include "dce/dce_abm.h"

+2

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c

reviewed

··· 25 25 #include "dcn20/dcn20_dsc.h" 26 26 #include "dcn20/dcn20_resource.h" 27 27 28 28 + #include "dml/dcn30/dcn30_fpu.h" 29 29 + 28 30 #include "dcn10/dcn10_resource.h" 29 31 30 32 #include "dc_link_ddc.h"

+2

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

reviewed

··· 36 36 #include "dcn20/dcn20_resource.h" 37 37 #include "dcn30/dcn30_resource.h" 38 38 39 39 + #include "dml/dcn30/dcn30_fpu.h" 40 40 + 39 41 #include "dcn10/dcn10_ipp.h" 40 42 #include "dcn30/dcn30_hubbub.h" 41 43 #include "dcn31/dcn31_hubbub.h"

+2 -1

drivers/gpu/drm/amd/display/dc/dml/Makefile

reviewed

··· 71 71 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags) 72 72 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag) 73 73 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags) 74 74 + CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags) 74 75 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags) 75 76 CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags) 76 77 CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags) ··· 114 113 DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o 115 114 DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o 116 115 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o 117 117 - DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o 116 116 + DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o 118 117 DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o 119 118 DML += dcn31/dcn31_fpu.o 120 119 DML += dcn301/dcn301_fpu.o

+617

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

reviewed

··· 1 1 + /* 2 2 + * Copyright 2020-2021 Advanced Micro Devices, Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: AMD 23 23 + * 24 24 + */ 25 25 + #include "resource.h" 26 26 + #include "clk_mgr.h" 27 27 + #include "reg_helper.h" 28 28 + #include "dcn_calc_math.h" 29 29 + #include "dcn20/dcn20_resource.h" 30 30 + #include "dcn30/dcn30_resource.h" 31 31 + 32 32 + 33 33 + #include "display_mode_vba_30.h" 34 34 + #include "dcn30_fpu.h" 35 35 + 36 36 + #define REG(reg)\ 37 37 + optc1->tg_regs->reg 38 38 + 39 39 + #define CTX \ 40 40 + optc1->base.ctx 41 41 + 42 42 + #undef FN 43 43 + #define FN(reg_name, field_name) \ 44 44 + optc1->tg_shift->field_name, optc1->tg_mask->field_name 45 45 + 46 46 + 47 47 + struct _vcs_dpi_ip_params_st dcn3_0_ip = { 48 48 + .use_min_dcfclk = 0, 49 49 + .clamp_min_dcfclk = 0, 50 50 + .odm_capable = 1, 51 51 + .gpuvm_enable = 0, 52 52 + .hostvm_enable = 0, 53 53 + .gpuvm_max_page_table_levels = 4, 54 54 + .hostvm_max_page_table_levels = 4, 55 55 + .hostvm_cached_page_table_levels = 0, 56 56 + .pte_group_size_bytes = 2048, 57 57 + .num_dsc = 6, 58 58 + .rob_buffer_size_kbytes = 184, 59 59 + .det_buffer_size_kbytes = 184, 60 60 + .dpte_buffer_size_in_pte_reqs_luma = 84, 61 61 + .pde_proc_buffer_size_64k_reqs = 48, 62 62 + .dpp_output_buffer_pixels = 2560, 63 63 + .opp_output_buffer_lines = 1, 64 64 + .pixel_chunk_size_kbytes = 8, 65 65 + .pte_enable = 1, 66 66 + .max_page_table_levels = 2, 67 67 + .pte_chunk_size_kbytes = 2, // ? 68 68 + .meta_chunk_size_kbytes = 2, 69 69 + .writeback_chunk_size_kbytes = 8, 70 70 + .line_buffer_size_bits = 789504, 71 71 + .is_line_buffer_bpp_fixed = 0, // ? 72 72 + .line_buffer_fixed_bpp = 0, // ? 73 73 + .dcc_supported = true, 74 74 + .writeback_interface_buffer_size_kbytes = 90, 75 75 + .writeback_line_buffer_buffer_size = 0, 76 76 + .max_line_buffer_lines = 12, 77 77 + .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 78 78 + .writeback_chroma_buffer_size_kbytes = 8, 79 79 + .writeback_chroma_line_buffer_width_pixels = 4, 80 80 + .writeback_max_hscl_ratio = 1, 81 81 + .writeback_max_vscl_ratio = 1, 82 82 + .writeback_min_hscl_ratio = 1, 83 83 + .writeback_min_vscl_ratio = 1, 84 84 + .writeback_max_hscl_taps = 1, 85 85 + .writeback_max_vscl_taps = 1, 86 86 + .writeback_line_buffer_luma_buffer_size = 0, 87 87 + .writeback_line_buffer_chroma_buffer_size = 14643, 88 88 + .cursor_buffer_size = 8, 89 89 + .cursor_chunk_size = 2, 90 90 + .max_num_otg = 6, 91 91 + .max_num_dpp = 6, 92 92 + .max_num_wb = 1, 93 93 + .max_dchub_pscl_bw_pix_per_clk = 4, 94 94 + .max_pscl_lb_bw_pix_per_clk = 2, 95 95 + .max_lb_vscl_bw_pix_per_clk = 4, 96 96 + .max_vscl_hscl_bw_pix_per_clk = 4, 97 97 + .max_hscl_ratio = 6, 98 98 + .max_vscl_ratio = 6, 99 99 + .hscl_mults = 4, 100 100 + .vscl_mults = 4, 101 101 + .max_hscl_taps = 8, 102 102 + .max_vscl_taps = 8, 103 103 + .dispclk_ramp_margin_percent = 1, 104 104 + .underscan_factor = 1.11, 105 105 + .min_vblank_lines = 32, 106 106 + .dppclk_delay_subtotal = 46, 107 107 + .dynamic_metadata_vm_enabled = true, 108 108 + .dppclk_delay_scl_lb_only = 16, 109 109 + .dppclk_delay_scl = 50, 110 110 + .dppclk_delay_cnvc_formatter = 27, 111 111 + .dppclk_delay_cnvc_cursor = 6, 112 112 + .dispclk_delay_subtotal = 119, 113 113 + .dcfclk_cstate_latency = 5.2, // SRExitTime 114 114 + .max_inter_dcn_tile_repeaters = 8, 115 115 + .max_num_hdmi_frl_outputs = 1, 116 116 + .odm_combine_4to1_supported = true, 117 117 + 118 118 + .xfc_supported = false, 119 119 + .xfc_fill_bw_overhead_percent = 10.0, 120 120 + .xfc_fill_constant_bytes = 0, 121 121 + .gfx7_compat_tiling_supported = 0, 122 122 + .number_of_cursors = 1, 123 123 + }; 124 124 + 125 125 + struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { 126 126 + .clock_limits = { 127 127 + { 128 128 + .state = 0, 129 129 + .dispclk_mhz = 562.0, 130 130 + .dppclk_mhz = 300.0, 131 131 + .phyclk_mhz = 300.0, 132 132 + .phyclk_d18_mhz = 667.0, 133 133 + .dscclk_mhz = 405.6, 134 134 + }, 135 135 + }, 136 136 + 137 137 + .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 138 138 + .num_states = 1, 139 139 + .sr_exit_time_us = 15.5, 140 140 + .sr_enter_plus_exit_time_us = 20, 141 141 + .urgent_latency_us = 4.0, 142 142 + .urgent_latency_pixel_data_only_us = 4.0, 143 143 + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 144 144 + .urgent_latency_vm_data_only_us = 4.0, 145 145 + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 146 146 + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 147 147 + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 148 148 + .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 149 149 + .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 150 150 + .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 151 151 + .max_avg_sdp_bw_use_normal_percent = 60.0, 152 152 + .max_avg_dram_bw_use_normal_percent = 40.0, 153 153 + .writeback_latency_us = 12.0, 154 154 + .max_request_size_bytes = 256, 155 155 + .fabric_datapath_to_dcn_data_return_bytes = 64, 156 156 + .dcn_downspread_percent = 0.5, 157 157 + .downspread_percent = 0.38, 158 158 + .dram_page_open_time_ns = 50.0, 159 159 + .dram_rw_turnaround_time_ns = 17.5, 160 160 + .dram_return_buffer_per_channel_bytes = 8192, 161 161 + .round_trip_ping_latency_dcfclk_cycles = 191, 162 162 + .urgent_out_of_order_return_per_channel_bytes = 4096, 163 163 + .channel_interleave_bytes = 256, 164 164 + .num_banks = 8, 165 165 + .gpuvm_min_page_size_bytes = 4096, 166 166 + .hostvm_min_page_size_bytes = 4096, 167 167 + .dram_clock_change_latency_us = 404, 168 168 + .dummy_pstate_latency_us = 5, 169 169 + .writeback_dram_clock_change_latency_us = 23.0, 170 170 + .return_bus_width_bytes = 64, 171 171 + .dispclk_dppclk_vco_speed_mhz = 3650, 172 172 + .xfc_bus_transport_time_us = 20, // ? 173 173 + .xfc_xbuf_latency_tolerance_us = 4, // ? 174 174 + .use_urgent_burst_bw = 1, // ? 175 175 + .do_urgent_latency_adjustment = true, 176 176 + .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 177 177 + .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 178 178 + }; 179 179 + 180 180 + 181 181 + void optc3_fpu_set_vrr_m_const(struct timing_generator *optc, 182 182 + double vtotal_avg) 183 183 + { 184 184 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 185 185 + double vtotal_min, vtotal_max; 186 186 + double ratio, modulo, phase; 187 187 + uint32_t vblank_start; 188 188 + uint32_t v_total_mask_value = 0; 189 189 + 190 190 + dc_assert_fp_enabled(); 191 191 + 192 192 + /* Compute VTOTAL_MIN and VTOTAL_MAX, so that 193 193 + * VOTAL_MAX - VTOTAL_MIN = 1 194 194 + */ 195 195 + v_total_mask_value = 16; 196 196 + vtotal_min = dcn_bw_floor(vtotal_avg); 197 197 + vtotal_max = dcn_bw_ceil(vtotal_avg); 198 198 + 199 199 + /* Check that bottom VBLANK is at least 2 lines tall when running with 200 200 + * VTOTAL_MIN. Note that VTOTAL registers are defined as 'total number 201 201 + * of lines in a frame - 1'. 202 202 + */ 203 203 + REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, 204 204 + &vblank_start); 205 205 + ASSERT(vtotal_min >= vblank_start + 1); 206 206 + 207 207 + /* Special case where the average frame rate can be achieved 208 208 + * without using the DTO 209 209 + */ 210 210 + if (vtotal_min == vtotal_max) { 211 211 + REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min); 212 212 + 213 213 + optc->funcs->set_vtotal_min_max(optc, 0, 0); 214 214 + REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0); 215 215 + REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0); 216 216 + REG_UPDATE_3(OTG_V_TOTAL_CONTROL, 217 217 + OTG_V_TOTAL_MIN_SEL, 0, 218 218 + OTG_V_TOTAL_MAX_SEL, 0, 219 219 + OTG_SET_V_TOTAL_MIN_MASK_EN, 0); 220 220 + return; 221 221 + } 222 222 + 223 223 + ratio = vtotal_max - vtotal_avg; 224 224 + modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */ 225 225 + phase = ratio * modulo; 226 226 + 227 227 + /* Special cases where the DTO phase gets rounded to 0 or 228 228 + * to DTO modulo 229 229 + */ 230 230 + if (phase <= 0 || phase >= modulo) { 231 231 + REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, 232 232 + phase <= 0 ? 233 233 + (uint32_t)vtotal_max : (uint32_t)vtotal_min); 234 234 + REG_SET(OTG_V_TOTAL_MIN, 0, OTG_V_TOTAL_MIN, 0); 235 235 + REG_SET(OTG_V_TOTAL_MAX, 0, OTG_V_TOTAL_MAX, 0); 236 236 + REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0); 237 237 + REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0); 238 238 + REG_UPDATE_3(OTG_V_TOTAL_CONTROL, 239 239 + OTG_V_TOTAL_MIN_SEL, 0, 240 240 + OTG_V_TOTAL_MAX_SEL, 0, 241 241 + OTG_SET_V_TOTAL_MIN_MASK_EN, 0); 242 242 + return; 243 243 + } 244 244 + REG_UPDATE_6(OTG_V_TOTAL_CONTROL, 245 245 + OTG_V_TOTAL_MIN_SEL, 1, 246 246 + OTG_V_TOTAL_MAX_SEL, 1, 247 247 + OTG_SET_V_TOTAL_MIN_MASK_EN, 1, 248 248 + OTG_SET_V_TOTAL_MIN_MASK, v_total_mask_value, 249 249 + OTG_VTOTAL_MID_REPLACING_MIN_EN, 0, 250 250 + OTG_VTOTAL_MID_REPLACING_MAX_EN, 0); 251 251 + REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min); 252 252 + optc->funcs->set_vtotal_min_max(optc, vtotal_min, vtotal_max); 253 253 + REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, (uint32_t)phase); 254 254 + REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, (uint32_t)modulo); 255 255 + } 256 256 + 257 257 + void dcn30_fpu_populate_dml_writeback_from_context( 258 258 + struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 259 259 + { 260 260 + int pipe_cnt, i, j; 261 261 + double max_calc_writeback_dispclk; 262 262 + double writeback_dispclk; 263 263 + struct writeback_st dout_wb; 264 264 + 265 265 + dc_assert_fp_enabled(); 266 266 + 267 267 + for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 268 268 + struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream; 269 269 + 270 270 + if (!stream) 271 271 + continue; 272 272 + max_calc_writeback_dispclk = 0; 273 273 + 274 274 + /* Set writeback information */ 275 275 + pipes[pipe_cnt].dout.wb_enable = 0; 276 276 + pipes[pipe_cnt].dout.num_active_wb = 0; 277 277 + for (j = 0; j < stream->num_wb_info; j++) { 278 278 + struct dc_writeback_info *wb_info = &stream->writeback_info[j]; 279 279 + 280 280 + if (wb_info->wb_enabled && wb_info->writeback_source_plane && 281 281 + (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { 282 282 + pipes[pipe_cnt].dout.wb_enable = 1; 283 283 + pipes[pipe_cnt].dout.num_active_wb++; 284 284 + dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? 285 285 + wb_info->dwb_params.cnv_params.crop_height : 286 286 + wb_info->dwb_params.cnv_params.src_height; 287 287 + dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? 288 288 + wb_info->dwb_params.cnv_params.crop_width : 289 289 + wb_info->dwb_params.cnv_params.src_width; 290 290 + dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; 291 291 + dout_wb.wb_dst_height = wb_info->dwb_params.dest_height; 292 292 + 293 293 + /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */ 294 294 + if (dc->dml.ip.writeback_max_hscl_taps > 1) { 295 295 + dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; 296 296 + dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; 297 297 + } else { 298 298 + dout_wb.wb_htaps_luma = 1; 299 299 + dout_wb.wb_vtaps_luma = 1; 300 300 + } 301 301 + dout_wb.wb_htaps_chroma = 0; 302 302 + dout_wb.wb_vtaps_chroma = 0; 303 303 + dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ? 304 304 + (double)wb_info->dwb_params.cnv_params.crop_width / 305 305 + (double)wb_info->dwb_params.dest_width : 306 306 + (double)wb_info->dwb_params.cnv_params.src_width / 307 307 + (double)wb_info->dwb_params.dest_width; 308 308 + dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ? 309 309 + (double)wb_info->dwb_params.cnv_params.crop_height / 310 310 + (double)wb_info->dwb_params.dest_height : 311 311 + (double)wb_info->dwb_params.cnv_params.src_height / 312 312 + (double)wb_info->dwb_params.dest_height; 313 313 + if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB || 314 314 + wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA) 315 315 + dout_wb.wb_pixel_format = dm_444_64; 316 316 + else 317 317 + dout_wb.wb_pixel_format = dm_444_32; 318 318 + 319 319 + /* Workaround for cases where multiple writebacks are connected to same plane 320 320 + * In which case, need to compute worst case and set the associated writeback parameters 321 321 + * This workaround is necessary due to DML computation assuming only 1 set of writeback 322 322 + * parameters per pipe 323 323 + */ 324 324 + writeback_dispclk = dml30_CalculateWriteBackDISPCLK( 325 325 + dout_wb.wb_pixel_format, 326 326 + pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 327 327 + dout_wb.wb_hratio, 328 328 + dout_wb.wb_vratio, 329 329 + dout_wb.wb_htaps_luma, 330 330 + dout_wb.wb_vtaps_luma, 331 331 + dout_wb.wb_src_width, 332 332 + dout_wb.wb_dst_width, 333 333 + pipes[pipe_cnt].pipe.dest.htotal, 334 334 + dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); 335 335 + 336 336 + if (writeback_dispclk > max_calc_writeback_dispclk) { 337 337 + max_calc_writeback_dispclk = writeback_dispclk; 338 338 + pipes[pipe_cnt].dout.wb = dout_wb; 339 339 + } 340 340 + } 341 341 + } 342 342 + 343 343 + pipe_cnt++; 344 344 + } 345 345 + } 346 346 + 347 347 + void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, 348 348 + struct display_mode_lib *dml, 349 349 + display_e2e_pipe_params_st *pipes, 350 350 + int pipe_cnt, 351 351 + int cur_pipe) 352 352 + { 353 353 + int i; 354 354 + 355 355 + dc_assert_fp_enabled(); 356 356 + 357 357 + for (i = 0; i < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); i++) { 358 358 + wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; 359 359 + wb_arb_params->pstate_watermark[i] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 360 360 + } 361 361 + 362 362 + wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ 363 363 + } 364 364 + 365 365 + void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 366 366 + { 367 367 + 368 368 + dc_assert_fp_enabled(); 369 369 + 370 370 + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { 371 371 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 372 372 + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 373 373 + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 374 374 + } 375 375 + } 376 376 + 377 377 + void dcn30_fpu_calculate_wm_and_dlg( 378 378 + struct dc *dc, struct dc_state *context, 379 379 + display_e2e_pipe_params_st *pipes, 380 380 + int pipe_cnt, 381 381 + int vlevel) 382 382 + { 383 383 + int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; 384 384 + int i, pipe_idx; 385 385 + double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; 386 386 + bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; 387 387 + 388 388 + dc_assert_fp_enabled(); 389 389 + 390 390 + if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 391 391 + dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 392 392 + 393 393 + pipes[0].clks_cfg.voltage = vlevel; 394 394 + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 395 395 + pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 396 396 + 397 397 + /* Set B: 398 398 + * DCFCLK: 1GHz or min required above 1GHz 399 399 + * FCLK/UCLK: Max 400 400 + */ 401 401 + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 402 402 + if (vlevel == 0) { 403 403 + pipes[0].clks_cfg.voltage = 1; 404 404 + pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 405 405 + } 406 406 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 407 407 + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 408 408 + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 409 409 + } 410 410 + context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 411 411 + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 412 412 + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 413 413 + context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 414 414 + context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 415 415 + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 416 416 + context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 417 417 + context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 418 418 + 419 419 + pipes[0].clks_cfg.voltage = vlevel; 420 420 + pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 421 421 + 422 422 + /* Set D: 423 423 + * DCFCLK: Min Required 424 424 + * FCLK(proportional to UCLK): 1GHz or Max 425 425 + * MALL stutter, sr_enter_exit = 4, sr_exit = 2us 426 426 + */ 427 427 + /* 428 428 + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 429 429 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 430 430 + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 431 431 + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 432 432 + } 433 433 + context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 434 434 + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 435 435 + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 436 436 + context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 437 437 + context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 438 438 + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 439 439 + context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 440 440 + context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 441 441 + */ 442 442 + 443 443 + /* Set C: 444 444 + * DCFCLK: Min Required 445 445 + * FCLK(proportional to UCLK): 1GHz or Max 446 446 + * pstate latency overridden to 5us 447 447 + */ 448 448 + if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 449 449 + unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; 450 450 + unsigned int min_dram_speed_mts_margin = 160; 451 451 + 452 452 + if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported) 453 453 + min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16; 454 454 + 455 455 + /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */ 456 456 + for (i = 3; i > 0; i--) 457 457 + if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts) 458 458 + break; 459 459 + 460 460 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us; 461 461 + 462 462 + context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 463 463 + context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 464 464 + } 465 465 + 466 466 + context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 467 467 + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 468 468 + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 469 469 + context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 470 470 + context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 471 471 + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 472 472 + context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 473 473 + context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 474 474 + 475 475 + if (!pstate_en) { 476 476 + /* The only difference between A and C is p-state latency, if p-state is not supported we want to 477 477 + * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark 478 478 + */ 479 479 + context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; 480 480 + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; 481 481 + } else { 482 482 + /* Set A: 483 483 + * DCFCLK: Min Required 484 484 + * FCLK(proportional to UCLK): 1GHz or Max 485 485 + * 486 486 + * Set A calculated last so that following calculations are based on Set A 487 487 + */ 488 488 + dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 489 489 + context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 490 490 + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 491 491 + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 492 492 + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 493 493 + context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 494 494 + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 495 495 + context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 496 496 + context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 497 497 + } 498 498 + 499 499 + context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; 500 500 + 501 501 + /* Make set D = set A until set D is enabled */ 502 502 + context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 503 503 + 504 504 + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 505 505 + if (!context->res_ctx.pipe_ctx[i].stream) 506 506 + continue; 507 507 + 508 508 + pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 509 509 + pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 510 510 + 511 511 + if (dc->config.forced_clocks) { 512 512 + pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 513 513 + pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 514 514 + } 515 515 + if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 516 516 + pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 517 517 + if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 518 518 + pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 519 519 + 520 520 + pipe_idx++; 521 521 + } 522 522 + 523 523 + DC_FP_START(); 524 524 + dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 525 525 + DC_FP_END(); 526 526 + 527 527 + if (!pstate_en) 528 528 + /* Restore full p-state latency */ 529 529 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = 530 530 + dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 531 531 + 532 532 + } 533 533 + 534 534 + void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc) 535 535 + { 536 536 + dc_assert_fp_enabled(); 537 537 + 538 538 + if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 539 539 + dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 540 540 + } 541 541 + 542 542 + void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk) 543 543 + { 544 544 + dc_assert_fp_enabled(); 545 545 + 546 546 + if (!dcn30_bb_max_clk->max_dcfclk_mhz) 547 547 + dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; 548 548 + if (!dcn30_bb_max_clk->max_dispclk_mhz) 549 549 + dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; 550 550 + if (!dcn30_bb_max_clk->max_dppclk_mhz) 551 551 + dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; 552 552 + if (!dcn30_bb_max_clk->max_phyclk_mhz) 553 553 + dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; 554 554 + } 555 555 + 556 556 + void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 557 557 + unsigned int *optimal_dcfclk, 558 558 + unsigned int *optimal_fclk) 559 559 + { 560 560 + double bw_from_dram, bw_from_dram1, bw_from_dram2; 561 561 + 562 562 + dc_assert_fp_enabled(); 563 563 + 564 564 + bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * 565 565 + dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); 566 566 + bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans * 567 567 + dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); 568 568 + 569 569 + bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 570 570 + 571 571 + if (optimal_fclk) 572 572 + *optimal_fclk = bw_from_dram / 573 573 + (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 574 574 + 575 575 + if (optimal_dcfclk) 576 576 + *optimal_dcfclk = bw_from_dram / 577 577 + (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 578 578 + } 579 579 + 580 580 + void dcn30_fpu_update_bw_bounding_box(struct dc *dc, 581 581 + struct clk_bw_params *bw_params, 582 582 + struct dc_bounding_box_max_clk *dcn30_bb_max_clk, 583 583 + unsigned int *dcfclk_mhz, 584 584 + unsigned int *dram_speed_mts) 585 585 + { 586 586 + unsigned int i; 587 587 + 588 588 + dc_assert_fp_enabled(); 589 589 + 590 590 + dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 591 591 + dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 592 592 + 593 593 + for (i = 0; i < dcn3_0_soc.num_states; i++) { 594 594 + dcn3_0_soc.clock_limits[i].state = i; 595 595 + dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 596 596 + dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 597 597 + dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 598 598 + 599 599 + /* Fill all states with max values of all other clocks */ 600 600 + dcn3_0_soc.clock_limits[i].dispclk_mhz = dcn30_bb_max_clk->max_dispclk_mhz; 601 601 + dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn30_bb_max_clk->max_dppclk_mhz; 602 602 + dcn3_0_soc.clock_limits[i].phyclk_mhz = dcn30_bb_max_clk->max_phyclk_mhz; 603 603 + dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; 604 604 + /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ 605 605 + /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 606 606 + dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; 607 607 + dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; 608 608 + dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; 609 609 + } 610 610 + /* re-init DML with updated bb */ 611 611 + dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 612 612 + if (dc->current_state) 613 613 + dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 614 614 + 615 615 + } 616 616 + 617 617 +

+67

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

reviewed

··· 1 1 + /* 2 2 + * Copyright 2020-2021 Advanced Micro Devices, Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: AMD 23 23 + * 24 24 + */ 25 25 + 26 26 + #ifndef __DCN30_FPU_H__ 27 27 + #define __DCN30_FPU_H__ 28 28 + 29 29 + #include "core_types.h" 30 30 + #include "dcn20/dcn20_optc.h" 31 31 + 32 32 + void optc3_fpu_set_vrr_m_const(struct timing_generator *optc, 33 33 + double vtotal_avg); 34 34 + 35 35 + void dcn30_fpu_populate_dml_writeback_from_context( 36 36 + struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes); 37 37 + 38 38 + void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, 39 39 + struct display_mode_lib *dml, 40 40 + display_e2e_pipe_params_st *pipes, 41 41 + int pipe_cnt, 42 42 + int cur_pipe); 43 43 + 44 44 + void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context); 45 45 + 46 46 + void dcn30_fpu_calculate_wm_and_dlg( 47 47 + struct dc *dc, struct dc_state *context, 48 48 + display_e2e_pipe_params_st *pipes, 49 49 + int pipe_cnt, 50 50 + int vlevel); 51 51 + 52 52 + void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc); 53 53 + 54 54 + void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk); 55 55 + 56 56 + void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 57 57 + unsigned int *optimal_dcfclk, 58 58 + unsigned int *optimal_fclk); 59 59 + 60 60 + void dcn30_fpu_update_bw_bounding_box(struct dc *dc, 61 61 + struct clk_bw_params *bw_params, 62 62 + struct dc_bounding_box_max_clk *dcn30_bb_max_clk, 63 63 + unsigned int *dcfclk_mhz, 64 64 + unsigned int *dram_speed_mts); 65 65 + 66 66 + 67 67 + #endif /* __DCN30_FPU_H__*/

+7

drivers/gpu/drm/amd/display/dc/inc/core_types.h

reviewed

··· 486 486 } perf_params; 487 487 }; 488 488 489 489 + struct dc_bounding_box_max_clk { 490 490 + int max_dcfclk_mhz; 491 491 + int max_dispclk_mhz; 492 492 + int max_dppclk_mhz; 493 493 + int max_phyclk_mhz; 494 494 + }; 495 495 + 489 496 #endif /* _CORE_TYPES_H_ */

+1 -2

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

reviewed

··· 217 217 void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable); 218 218 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx); 219 219 220 220 - void dp_retrieve_lttpr_cap(struct dc_link *link); 221 221 - bool dp_apply_lttpr_mode(struct dc_link *link); 220 220 + bool dp_retrieve_lttpr_cap(struct dc_link *link); 222 221 void edp_panel_backlight_power_on(struct dc_link *link); 223 222 void dp_receiver_power_ctrl(struct dc_link *link, bool on); 224 223 void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode);

+5

drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h

reviewed

··· 87 87 */ 88 88 enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link); 89 89 90 90 + /* Query hot plug status of USB4 DP tunnel. 91 91 + * Returns true if HPD high. 92 92 + */ 93 93 + bool dc_link_dpia_query_hpd_status(struct dc_link *link); 94 94 + 90 95 /* Train DP tunneling link for USB4 DPIA display endpoint. 91 96 * DPIA equivalent of dc_link_dp_perfrorm_link_training. 92 97 * Aborts link training upon detection of sink unplug.

-6

drivers/gpu/drm/amd/display/include/link_service_types.h

reviewed

··· 80 80 DP_128b_132b_CDS_DONE_TIMEOUT, 81 81 }; 82 82 83 83 - enum lttpr_support { 84 84 - LTTPR_UNSUPPORTED, 85 85 - LTTPR_CHECK_EXT_SUPPORT, 86 86 - LTTPR_SUPPORTED, 87 87 - }; 88 88 - 89 83 enum lttpr_mode { 90 84 LTTPR_MODE_NON_LTTPR, 91 85 LTTPR_MODE_TRANSPARENT,

+2

drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h

reviewed

··· 6070 6070 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 6071 6071 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 6072 6072 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 6073 6073 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 6074 6074 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 6073 6075 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 6074 6076 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 6075 6077 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1

+2

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h

reviewed

··· 6058 6058 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 6059 6059 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 6060 6060 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 6061 6061 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 6062 6062 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 6061 6063 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 6062 6064 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 6063 6065 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1

+2

drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h

reviewed

··· 7142 7142 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 7143 7143 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 7144 7144 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 7145 7145 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 7146 7146 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 7145 7147 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 7146 7148 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 7147 7149 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1

+2

drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h

reviewed

··· 37285 37285 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 37286 37286 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 37287 37287 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 37288 37288 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 37288 37289 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 37289 37290 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 37290 37291 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 37291 37292 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 37292 37293 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 37293 37294 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 37295 37295 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L 37294 37296 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L 37295 37297 //DIG0_HDMI_INFOFRAME_CONTROL0 37296 37298 #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0

+2

drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h

reviewed

··· 5584 5584 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 5585 5585 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 5586 5586 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 5587 5587 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 5588 5588 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 5587 5589 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 5588 5590 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 5589 5591 #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1

+2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h

reviewed

··· 30357 30357 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 30358 30358 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 30359 30359 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 30360 30360 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 30360 30361 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 30361 30362 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 30362 30363 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 30363 30364 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 30364 30365 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 30365 30366 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 30367 30367 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L 30366 30368 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L 30367 30369 //DIG0_HDMI_INFOFRAME_CONTROL0 30368 30370 #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4

+2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h

reviewed

··· 39439 39439 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 39440 39440 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 39441 39441 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 39442 39442 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 39442 39443 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 39443 39444 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 39444 39445 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 39445 39446 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 39446 39447 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 39447 39448 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 39449 39449 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L 39448 39450 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L 39449 39451 //DIG0_HDMI_INFOFRAME_CONTROL0 39450 39452 #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4

+2 -2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h

reviewed

··· 16956 16956 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 16957 16957 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 16958 16958 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 16959 16959 - 16959 16959 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 16960 16960 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 16961 16961 16962 16962 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L ··· 16964 16964 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 16965 16965 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 16966 16966 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 16967 16967 - 16967 16967 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L 16968 16968 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L 16969 16969 16970 16970 //DIG0_HDMI_INFOFRAME_CONTROL0

+2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h

reviewed

··· 35487 35487 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 35488 35488 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 35489 35489 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 35490 35490 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 35490 35491 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 35491 35492 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 35492 35493 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 35493 35494 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 35494 35495 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 35495 35496 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 35497 35497 + #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L 35496 35498 #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L 35497 35499 //DIG0_HDMI_INFOFRAME_CONTROL0 35498 35500 #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4

+3

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

reviewed

··· 770 770 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 771 771 enum amd_dpm_forced_level level; 772 772 773 773 + if (!pp_funcs) 774 774 + return AMD_DPM_FORCED_LEVEL_AUTO; 775 775 + 773 776 mutex_lock(&adev->pm.mutex); 774 777 if (pp_funcs->get_performance_level) 775 778 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);

+1

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

reviewed

··· 1436 1436 case IP_VERSION(11, 0, 0): 1437 1437 case IP_VERSION(11, 0, 5): 1438 1438 case IP_VERSION(11, 0, 9): 1439 1439 + case IP_VERSION(13, 0, 0): 1439 1440 return 0; 1440 1441 default: 1441 1442 break;

+10 -12

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

reviewed

··· 671 671 uint16_t reserved[2]; 672 672 673 673 //Frequency changes 674 674 - uint16_t GfxclkFmin; // MHz 675 675 - uint16_t GfxclkFmax; // MHz 674 674 + int16_t GfxclkFmin; // MHz 675 675 + int16_t GfxclkFmax; // MHz 676 676 uint16_t UclkFmin; // MHz 677 677 uint16_t UclkFmax; // MHz 678 678 ··· 683 683 //Fan control 684 684 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 685 685 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 686 686 - uint16_t FanMaximumRpm; 687 686 uint16_t FanMinimumPwm; 688 688 - uint16_t FanAcousticLimitRpm; 687 687 + uint16_t AcousticTargetRpmThreshold; 688 688 + uint16_t AcousticLimitRpmThreshold; 689 689 uint16_t FanTargetTemperature; // Degree Celcius 690 690 uint8_t FanZeroRpmEnable; 691 691 uint8_t FanZeroRpmStopTemp; 692 692 uint8_t FanMode; 693 693 - uint8_t Padding[1]; 694 694 - 693 693 + uint8_t MaxOpTemp; 695 694 696 695 uint32_t Spare[13]; 697 696 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround ··· 718 719 719 720 uint8_t FanLinearPwmPoints; 720 721 uint8_t FanLinearTempPoints; 721 721 - uint16_t FanMaximumRpm; 722 722 uint16_t FanMinimumPwm; 723 723 - uint16_t FanAcousticLimitRpm; 723 723 + uint16_t AcousticTargetRpmThreshold; 724 724 + uint16_t AcousticLimitRpmThreshold; 724 725 uint16_t FanTargetTemperature; // Degree Celcius 725 726 uint8_t FanZeroRpmEnable; 726 727 uint8_t FanZeroRpmStopTemp; 727 728 uint8_t FanMode; 728 728 - uint8_t Padding[1]; 729 729 - 729 729 + uint8_t MaxOpTemp; 730 730 731 731 uint32_t Spare[13]; 732 732 ··· 995 997 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 996 998 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 997 999 998 998 - uint32_t SpareVmin[12]; 1000 1000 + QuadraticInt_t Vmin_droop; 1001 1001 + uint32_t SpareVmin[9]; 999 1002 1000 1003 1001 1004 //SECTION: DPM Configuration 1 ··· 1284 1285 1285 1286 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1286 1287 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1287 1287 - 1288 1288 1289 1289 // SECTION: Board Reserved 1290 1290 uint32_t BoardSpare[64];

+1 -1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

reviewed

··· 30 30 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 31 31 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04 32 32 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 33 33 - #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x27 33 33 + #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x28 34 34 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28 35 35 36 36 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms

+44 -13

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

reviewed

··· 697 697 uint32_t apu_percent = 0; 698 698 uint32_t dgpu_percent = 0; 699 699 700 700 - if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 701 701 - (smu->smc_fw_version >= 0x3A4900)) 702 702 - use_metrics_v3 = true; 703 703 - else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 704 704 - (smu->smc_fw_version >= 0x3A4300)) 705 705 - use_metrics_v2 = true; 700 700 + switch (smu->adev->ip_versions[MP1_HWIP][0]) { 701 701 + case IP_VERSION(11, 0, 7): 702 702 + if (smu->smc_fw_version >= 0x3A4900) 703 703 + use_metrics_v3 = true; 704 704 + else if (smu->smc_fw_version >= 0x3A4300) 705 705 + use_metrics_v2 = true; 706 706 + break; 707 707 + case IP_VERSION(11, 0, 11): 708 708 + if (smu->smc_fw_version >= 0x412D00) 709 709 + use_metrics_v2 = true; 710 710 + break; 711 711 + case IP_VERSION(11, 0, 12): 712 712 + if (smu->smc_fw_version >= 0x3B2300) 713 713 + use_metrics_v2 = true; 714 714 + break; 715 715 + case IP_VERSION(11, 0, 13): 716 716 + if (smu->smc_fw_version >= 0x491100) 717 717 + use_metrics_v2 = true; 718 718 + break; 719 719 + default: 720 720 + break; 721 721 + } 706 722 707 723 ret = smu_cmn_get_metrics_table(smu, 708 724 NULL, ··· 3849 3833 uint16_t average_gfx_activity; 3850 3834 int ret = 0; 3851 3835 3852 3852 - if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 3853 3853 - (smu->smc_fw_version >= 0x3A4900)) 3854 3854 - use_metrics_v3 = true; 3855 3855 - else if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 3856 3856 - (smu->smc_fw_version >= 0x3A4300)) 3857 3857 - use_metrics_v2 = true; 3858 3858 - 3836 3836 + switch (smu->adev->ip_versions[MP1_HWIP][0]) { 3837 3837 + case IP_VERSION(11, 0, 7): 3838 3838 + if (smu->smc_fw_version >= 0x3A4900) 3839 3839 + use_metrics_v3 = true; 3840 3840 + else if (smu->smc_fw_version >= 0x3A4300) 3841 3841 + use_metrics_v2 = true; 3842 3842 + break; 3843 3843 + case IP_VERSION(11, 0, 11): 3844 3844 + if (smu->smc_fw_version >= 0x412D00) 3845 3845 + use_metrics_v2 = true; 3846 3846 + break; 3847 3847 + case IP_VERSION(11, 0, 12): 3848 3848 + if (smu->smc_fw_version >= 0x3B2300) 3849 3849 + use_metrics_v2 = true; 3850 3850 + break; 3851 3851 + case IP_VERSION(11, 0, 13): 3852 3852 + if (smu->smc_fw_version >= 0x491100) 3853 3853 + use_metrics_v2 = true; 3854 3854 + break; 3855 3855 + default: 3856 3856 + break; 3857 3857 + } 3859 3858 3860 3859 ret = smu_cmn_get_metrics_table(smu, 3861 3860 &metrics_external,

+1

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

reviewed

··· 1666 1666 uint32_t feature_mask; 1667 1667 const char *label; 1668 1668 } logging_label[] = { 1669 1669 + {(1U << THROTTLER_TEMP_GPU_BIT), "GPU"}, 1669 1670 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 1670 1671 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 1671 1672 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},

+35 -12

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

reviewed

··· 218 218 pptable_id == 3688) 219 219 pptable_id = 36881; 220 220 /* 221 221 - * Temporary solution for SMU V13.0.0: 222 222 - * - use 99991 signed pptable when SCPM enabled 223 223 - * TODO: drop this when the pptable carried in vbios 224 224 - * is ready. 221 221 + * Temporary solution for SMU V13.0.0 with SCPM enabled: 222 222 + * - use 36831 signed pptable when pp_table_id is 3683 223 223 + * - use 36641 signed pptable when pp_table_id is 3664 or 0 224 224 + * TODO: drop these when the pptable carried in vbios is ready. 225 225 */ 226 226 - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) 227 227 - pptable_id = 99991; 226 226 + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) { 227 227 + switch (pptable_id) { 228 228 + case 0: 229 229 + case 3664: 230 230 + pptable_id = 36641; 231 231 + break; 232 232 + case 3683: 233 233 + pptable_id = 36831; 234 234 + break; 235 235 + default: 236 236 + dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id); 237 237 + return -EINVAL; 238 238 + } 239 239 + } 228 240 } 229 241 230 242 /* "pptable_id == 0" means vbios carries the pptable. */ ··· 460 448 pptable_id = smu->smu_table.boot_values.pp_table_id; 461 449 462 450 /* 463 463 - * Temporary solution for SMU V13.0.0: 464 464 - * - use 9999 unsigned pptable when SCPM disabled 465 465 - * TODO: drop this when the pptable carried in vbios 466 466 - * is ready. 451 451 + * Temporary solution for SMU V13.0.0 with SCPM disabled: 452 452 + * - use 3664 or 3683 on request 453 453 + * - use 3664 when pptable_id is 0 454 454 + * TODO: drop these when the pptable carried in vbios is ready. 467 455 */ 468 468 - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) 469 469 - pptable_id = 9999; 456 456 + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) { 457 457 + switch (pptable_id) { 458 458 + case 0: 459 459 + pptable_id = 3664; 460 460 + break; 461 461 + case 3664: 462 462 + case 3683: 463 463 + break; 464 464 + default: 465 465 + dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id); 466 466 + return -EINVAL; 467 467 + } 468 468 + } 470 469 } 471 470 472 471 /* force using vbios pptable in sriov mode */

+6 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

reviewed

··· 275 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 276 276 } 277 277 278 278 - #if 0 279 278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 280 280 - #endif 281 279 282 280 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 283 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); ··· 293 295 } 294 296 295 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); 298 298 + 299 299 + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 300 300 + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 301 301 + 302 302 + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 303 303 + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 296 304 297 305 return 0; 298 306 }

+30 -32

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

reviewed

··· 644 644 if (!table || !clock_ranges) 645 645 return -EINVAL; 646 646 647 647 - if (clock_ranges) { 648 648 - if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 649 649 - clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 650 650 - return -EINVAL; 647 647 + if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 648 648 + clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 649 649 + return -EINVAL; 651 650 652 652 - for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 653 653 - table->WatermarkRow[WM_DCFCLK][i].MinClock = 654 654 - clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 655 655 - table->WatermarkRow[WM_DCFCLK][i].MaxClock = 656 656 - clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 657 657 - table->WatermarkRow[WM_DCFCLK][i].MinMclk = 658 658 - clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 659 659 - table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 660 660 - clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 651 651 + for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 652 652 + table->WatermarkRow[WM_DCFCLK][i].MinClock = 653 653 + clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 654 654 + table->WatermarkRow[WM_DCFCLK][i].MaxClock = 655 655 + clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 656 656 + table->WatermarkRow[WM_DCFCLK][i].MinMclk = 657 657 + clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 658 658 + table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 659 659 + clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 661 660 662 662 - table->WatermarkRow[WM_DCFCLK][i].WmSetting = 663 663 - clock_ranges->reader_wm_sets[i].wm_inst; 664 664 - } 665 665 - 666 666 - for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 667 667 - table->WatermarkRow[WM_SOCCLK][i].MinClock = 668 668 - clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 669 669 - table->WatermarkRow[WM_SOCCLK][i].MaxClock = 670 670 - clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 671 671 - table->WatermarkRow[WM_SOCCLK][i].MinMclk = 672 672 - clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 673 673 - table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 674 674 - clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 675 675 - 676 676 - table->WatermarkRow[WM_SOCCLK][i].WmSetting = 677 677 - clock_ranges->writer_wm_sets[i].wm_inst; 678 678 - } 679 679 - 680 680 - smu->watermarks_bitmap |= WATERMARKS_EXIST; 661 661 + table->WatermarkRow[WM_DCFCLK][i].WmSetting = 662 662 + clock_ranges->reader_wm_sets[i].wm_inst; 681 663 } 664 664 + 665 665 + for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 666 666 + table->WatermarkRow[WM_SOCCLK][i].MinClock = 667 667 + clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 668 668 + table->WatermarkRow[WM_SOCCLK][i].MaxClock = 669 669 + clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 670 670 + table->WatermarkRow[WM_SOCCLK][i].MinMclk = 671 671 + clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 672 672 + table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 673 673 + clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 674 674 + 675 675 + table->WatermarkRow[WM_SOCCLK][i].WmSetting = 676 676 + clock_ranges->writer_wm_sets[i].wm_inst; 677 677 + } 678 678 + 679 679 + smu->watermarks_bitmap |= WATERMARKS_EXIST; 682 680 683 681 /* pass data to smu controller */ 684 682 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

+3

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

reviewed

··· 190 190 kfree(smu_table->watermarks_table); 191 191 smu_table->watermarks_table = NULL; 192 192 193 193 + kfree(smu_table->gpu_metrics_table); 194 194 + smu_table->gpu_metrics_table = NULL; 195 195 + 193 196 return 0; 194 197 } 195 198

-3

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

reviewed

··· 541 541 struct dpu_encoder_virt *dpu_enc; 542 542 struct msm_drm_private *priv; 543 543 struct dpu_kms *dpu_kms; 544 544 - const struct drm_display_mode *mode; 545 544 struct drm_display_mode *adj_mode; 546 545 struct msm_display_topology topology; 547 546 struct dpu_global_state *global_state; ··· 558 559 559 560 priv = drm_enc->dev->dev_private; 560 561 dpu_kms = to_dpu_kms(priv->kms); 561 561 - mode = &crtc_state->mode; 562 562 adj_mode = &crtc_state->adjusted_mode; 563 563 global_state = dpu_kms_get_global_state(crtc_state->state); 564 564 if (IS_ERR(global_state)) ··· 1812 1814 } 1813 1815 } 1814 1816 1815 1815 - dsc_common_mode = 0; 1816 1817 pic_width = dsc->drm->pic_width; 1817 1818 1818 1819 dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;

+2 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

reviewed

··· 574 574 */ 575 575 static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc) 576 576 { 577 577 - DPU_DEBUG("[wb:%d]\n", phys_enc->wb_idx - WB_0); 578 578 - 579 577 if (!phys_enc) 580 578 return; 579 579 + 580 580 + DPU_DEBUG("[wb:%d]\n", phys_enc->wb_idx - WB_0); 581 581 582 582 kfree(phys_enc); 583 583 }

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

reviewed

··· 49 49 #define DPU_DEBUGFS_DIR "msm_dpu" 50 50 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" 51 51 52 52 - #define MIN_IB_BW 400000000ULL /* Min ib vote 400MB */ 53 53 - 54 52 static int dpu_kms_hw_init(struct msm_kms *kms); 55 53 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); 56 54 ··· 1303 1305 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 1304 1306 struct drm_encoder *encoder; 1305 1307 struct drm_device *ddev; 1306 1306 - int i; 1307 1308 1308 1309 ddev = dpu_kms->dev; 1309 1309 - 1310 1310 - WARN_ON(!(dpu_kms->num_paths)); 1311 1311 - /* Min vote of BW is required before turning on AXI clk */ 1312 1312 - for (i = 0; i < dpu_kms->num_paths; i++) 1313 1313 - icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW)); 1314 1310 1315 1311 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); 1316 1312 if (rc) {

+7 -2

drivers/gpu/drm/msm/dp/dp_ctrl.c

reviewed

··· 1390 1390 1391 1391 dp_catalog_ctrl_reset(ctrl->catalog); 1392 1392 1393 1393 - if (enable) 1394 1394 - dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1393 1393 + /* 1394 1394 + * all dp controller programmable registers will not 1395 1395 + * be reset to default value after DP_SW_RESET 1396 1396 + * therefore interrupt mask bits have to be updated 1397 1397 + * to enable/disable interrupts 1398 1398 + */ 1399 1399 + dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1395 1400 } 1396 1401 1397 1402 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)

+57

drivers/gpu/drm/msm/msm_mdss.c

reviewed

··· 5 5 6 6 #include <linux/clk.h> 7 7 #include <linux/delay.h> 8 8 + #include <linux/interconnect.h> 8 9 #include <linux/irq.h> 9 10 #include <linux/irqchip.h> 10 11 #include <linux/irqdesc.h> ··· 26 25 #define UBWC_CTRL_2 0x150 27 26 #define UBWC_PREDICTION_MODE 0x154 28 27 28 28 + #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 29 29 + 29 30 struct msm_mdss { 30 31 struct device *dev; 31 32 ··· 39 36 unsigned long enabled_mask; 40 37 struct irq_domain *domain; 41 38 } irq_controller; 39 39 + struct icc_path *path[2]; 40 40 + u32 num_paths; 42 41 }; 42 42 + 43 43 + static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 44 44 + struct msm_mdss *msm_mdss) 45 45 + { 46 46 + struct icc_path *path0 = of_icc_get(dev, "mdp0-mem"); 47 47 + struct icc_path *path1 = of_icc_get(dev, "mdp1-mem"); 48 48 + 49 49 + if (IS_ERR_OR_NULL(path0)) 50 50 + return PTR_ERR_OR_ZERO(path0); 51 51 + 52 52 + msm_mdss->path[0] = path0; 53 53 + msm_mdss->num_paths = 1; 54 54 + 55 55 + if (!IS_ERR_OR_NULL(path1)) { 56 56 + msm_mdss->path[1] = path1; 57 57 + msm_mdss->num_paths++; 58 58 + } 59 59 + 60 60 + return 0; 61 61 + } 62 62 + 63 63 + static void msm_mdss_put_icc_path(void *data) 64 64 + { 65 65 + struct msm_mdss *msm_mdss = data; 66 66 + int i; 67 67 + 68 68 + for (i = 0; i < msm_mdss->num_paths; i++) 69 69 + icc_put(msm_mdss->path[i]); 70 70 + } 71 71 + 72 72 + static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) 73 73 + { 74 74 + int i; 75 75 + 76 76 + for (i = 0; i < msm_mdss->num_paths; i++) 77 77 + icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); 78 78 + } 43 79 44 80 static void msm_mdss_irq(struct irq_desc *desc) 45 81 { ··· 178 136 { 179 137 int ret; 180 138 139 139 + /* 140 140 + * Several components have AXI clocks that can only be turned on if 141 141 + * the interconnect is enabled (non-zero bandwidth). Let's make sure 142 142 + * that the interconnects are at least at a minimum amount. 143 143 + */ 144 144 + msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); 145 145 + 181 146 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 182 147 if (ret) { 183 148 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); ··· 227 178 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 228 179 { 229 180 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 181 181 + msm_mdss_icc_request_bw(msm_mdss, 0); 230 182 231 183 return 0; 232 184 } ··· 320 270 return ERR_CAST(msm_mdss->mmio); 321 271 322 272 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 273 273 + 274 274 + ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 275 275 + if (ret) 276 276 + return ERR_PTR(ret); 277 277 + ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); 278 278 + if (ret) 279 279 + return ERR_PTR(ret); 323 280 324 281 if (is_mdp5) 325 282 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);

+4

drivers/gpu/drm/radeon/radeon_connectors.c

reviewed

··· 473 473 native_mode->vdisplay != 0 && 474 474 native_mode->clock != 0) { 475 475 mode = drm_mode_duplicate(dev, native_mode); 476 476 + if (!mode) 477 477 + return NULL; 476 478 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 477 479 drm_mode_set_name(mode); 478 480 ··· 489 487 * simpler. 490 488 */ 491 489 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 490 490 + if (!mode) 491 491 + return NULL; 492 492 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 493 493 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 494 494 }

+5

drivers/gpu/host1x/Kconfig

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 2 + 3 3 + config TEGRA_HOST1X_CONTEXT_BUS 4 4 + bool 5 5 + 2 6 config TEGRA_HOST1X 3 7 tristate "NVIDIA Tegra host1x driver" 4 8 depends on ARCH_TEGRA || (ARM && COMPILE_TEST) 5 9 select DMA_SHARED_BUFFER 10 10 + select TEGRA_HOST1X_CONTEXT_BUS 6 11 select IOMMU_IOVA 7 12 help 8 13 Driver for the NVIDIA Tegra host1x hardware.

+1

drivers/gpu/host1x/Makefile

reviewed

··· 18 18 hw/host1x07.o 19 19 20 20 obj-$(CONFIG_TEGRA_HOST1X) += host1x.o 21 21 + obj-$(CONFIG_TEGRA_HOST1X_CONTEXT_BUS) += context_bus.o

+31

drivers/gpu/host1x/context_bus.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2021, NVIDIA Corporation. 4 4 + */ 5 5 + 6 6 + #include <linux/device.h> 7 7 + #include <linux/of.h> 8 8 + 9 9 + struct bus_type host1x_context_device_bus_type = { 10 10 + .name = "host1x-context", 11 11 + }; 12 12 + EXPORT_SYMBOL_GPL(host1x_context_device_bus_type); 13 13 + 14 14 + static int __init host1x_context_device_bus_init(void) 15 15 + { 16 16 + int err; 17 17 + 18 18 + if (!of_machine_is_compatible("nvidia,tegra186") && 19 19 + !of_machine_is_compatible("nvidia,tegra194") && 20 20 + !of_machine_is_compatible("nvidia,tegra234")) 21 21 + return 0; 22 22 + 23 23 + err = bus_register(&host1x_context_device_bus_type); 24 24 + if (err < 0) { 25 25 + pr_err("bus type registration failed: %d\n", err); 26 26 + return err; 27 27 + } 28 28 + 29 29 + return 0; 30 30 + } 31 31 + postcore_initcall(host1x_context_device_bus_init);

+15

include/linux/host1x_context_bus.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 2 + /* 3 3 + * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. 4 4 + */ 5 5 + 6 6 + #ifndef __LINUX_HOST1X_CONTEXT_BUS_H 7 7 + #define __LINUX_HOST1X_CONTEXT_BUS_H 8 8 + 9 9 + #include <linux/device.h> 10 10 + 11 11 + #ifdef CONFIG_TEGRA_HOST1X_CONTEXT_BUS 12 12 + extern struct bus_type host1x_context_device_bus_type; 13 13 + #endif 14 14 + 15 15 + #endif

+8

include/uapi/drm/amdgpu_drm.h

reviewed

··· 140 140 * not require GTT memory accounting 141 141 */ 142 142 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 143 143 + /* Flag that BO can be discarded under memory pressure without keeping the 144 144 + * content. 145 145 + */ 146 146 + #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 143 147 144 148 struct drm_amdgpu_gem_create_in { 145 149 /** the requested memory size */ ··· 533 529 #define AMDGPU_VM_MTYPE_UC (4 << 5) 534 530 /* Use Read Write MTYPE instead of default MTYPE */ 535 531 #define AMDGPU_VM_MTYPE_RW (5 << 5) 532 532 + /* don't allocate MALL */ 533 533 + #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 536 534 537 535 struct drm_amdgpu_gem_va { 538 536 /** GEM object handle */ ··· 994 988 #define AMDGPU_VRAM_TYPE_DDR4 8 995 989 #define AMDGPU_VRAM_TYPE_GDDR6 9 996 990 #define AMDGPU_VRAM_TYPE_DDR5 10 991 991 + #define AMDGPU_VRAM_TYPE_LPDDR4 11 992 992 + #define AMDGPU_VRAM_TYPE_LPDDR5 12 997 993 998 994 struct drm_amdgpu_info_device { 999 995 /** PCI Device ID */