Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add dce_v6_0_soft_reset() to DCE6
DCE6 was missing soft reset, but it was easily identifiable under radeon.
This should be it, pretty much as it is done under DCE8 and DCE10.
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Alexandre Demers
and committed by
Alex Deucher
ab23db6d
5f6021d5
+51
-2
+51
-2
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+51
-2
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
···
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return mmDC_GPIO_HPD_A;
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}
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+
static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
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{
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u32 crtc_hung = 0;
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u32 crtc_status[6];
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u32 i, j, tmp;
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+
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
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crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
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crtc_hung |= (1 << i);
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}
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}
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+
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for (j = 0; j < 10; j++) {
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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if (crtc_hung & (1 << i)) {
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tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
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if (tmp != crtc_status[i])
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crtc_hung &= ~(1 << i);
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}
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}
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if (crtc_hung == 0)
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return false;
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udelay(100);
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}
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return true;
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}
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+
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static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
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bool render)
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{
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if (!render)
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WREG32(mmVGA_RENDER_CONTROL,
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RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
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-
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}
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static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
···
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static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
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{
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-
DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
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+
u32 srbm_soft_reset = 0, tmp;
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struct amdgpu_device *adev = ip_block->adev;
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+
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if (dce_v6_0_is_display_hung(adev))
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
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+
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if (srbm_soft_reset) {
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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+
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udelay(50);
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+
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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+
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/* Wait a little for things to settle down */
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udelay(50);
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}
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return 0;
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}
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