drm/msm/dpu: move rot90 checking to dpu_plane_atomic_check_sspp()

+2

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

··· 144 144 * @src_rect: src ROI, caller takes into account the different operations 145 145 * such as decimation, flip etc to program this field 146 146 * @dest_rect: destination ROI. 147 + * @rotation: simplified drm rotation hint 147 148 */ 148 149 struct dpu_sw_pipe_cfg { 149 150 struct drm_rect src_rect; 150 151 struct drm_rect dst_rect; 152 + unsigned int rotation; 151 153 }; 152 154 153 155 /**

+29 -26

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

··· 528 528 529 529 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 530 530 const struct msm_format *fmt, bool color_fill, 531 - struct dpu_sw_pipe_cfg *pipe_cfg, 532 - unsigned int rotation) 531 + struct dpu_sw_pipe_cfg *pipe_cfg) 533 532 { 534 533 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 535 534 const struct drm_format_info *info = drm_format_info(fmt->pixel_format); ··· 551 552 dst_height, 552 553 &scaler3_cfg, fmt, 553 554 info->hsub, info->vsub, 554 - rotation); 555 + pipe_cfg->rotation); 555 556 556 557 /* configure pixel extension based on scalar config */ 557 558 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, ··· 603 604 if (pipe->sspp->ops.setup_rects) 604 605 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 605 606 606 - _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 607 + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg); 607 608 } 608 609 609 610 /** ··· 695 696 } 696 697 697 698 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 698 - const struct dpu_sspp_sub_blks *sblk, 699 - struct drm_rect src, const struct msm_format *fmt) 699 + struct dpu_sw_pipe *pipe, 700 + struct drm_rect src, 701 + const struct msm_format *fmt) 700 702 { 703 + const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk; 701 704 size_t num_formats; 702 705 const u32 *supported_formats; 706 + 707 + if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features)) 708 + return -EINVAL; 703 709 704 710 if (!sblk->rotation_cfg) { 705 711 DPU_ERROR("invalid rotation cfg\n"); ··· 735 731 { 736 732 uint32_t min_src_size; 737 733 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 734 + int ret; 738 735 739 736 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; 740 737 ··· 771 766 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 772 767 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 773 768 return -EINVAL; 769 + } 770 + 771 + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) { 772 + ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt); 773 + if (ret) 774 + return ret; 774 775 } 775 776 776 777 /* max clk check */ ··· 902 891 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 903 892 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 904 893 uint32_t max_linewidth; 905 - unsigned int rotation; 906 894 uint32_t supported_rotations; 907 895 const struct dpu_sspp_cfg *pipe_hw_caps; 908 896 const struct dpu_sspp_sub_blks *sblk; ··· 924 914 fmt = msm_framebuffer_format(new_plane_state->fb); 925 915 926 916 max_linewidth = pdpu->catalog->caps->max_linewidth; 917 + 918 + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 919 + 920 + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 921 + supported_rotations |= DRM_MODE_ROTATE_90; 922 + 923 + pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, 924 + supported_rotations); 925 + r_pipe_cfg->rotation = pipe_cfg->rotation; 927 926 928 927 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, 929 928 &crtc_state->adjusted_mode); ··· 957 938 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 958 939 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 959 940 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 941 + pipe_cfg->rotation & DRM_MODE_ROTATE_90 || 960 942 MSM_FORMAT_IS_YUV(fmt)) { 961 943 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 962 944 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); ··· 980 960 if (ret) 981 961 return ret; 982 962 } 983 - 984 - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 985 - 986 - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 987 - supported_rotations |= DRM_MODE_ROTATE_90; 988 - 989 - rotation = drm_rotation_simplify(new_plane_state->rotation, 990 - supported_rotations); 991 - 992 - if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 993 - (rotation & DRM_MODE_ROTATE_90)) { 994 - ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 995 - if (ret) 996 - return ret; 997 - } 998 - 999 - pstate->rotation = rotation; 1000 963 1001 964 return 0; 1002 965 } ··· 1120 1117 pipe_cfg); 1121 1118 } 1122 1119 1123 - _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1120 + _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg); 1124 1121 1125 1122 if (pipe->sspp->ops.setup_multirect) 1126 1123 pipe->sspp->ops.setup_multirect( 1127 1124 pipe); 1128 1125 1129 1126 if (pipe->sspp->ops.setup_format) { 1130 - unsigned int rotation = pstate->rotation; 1127 + unsigned int rotation = pipe_cfg->rotation; 1131 1128 1132 1129 src_flags = 0x0; 1133 1130

-2

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

··· 30 30 * @plane_fetch_bw: calculated BW per plane 31 31 * @plane_clk: calculated clk per plane 32 32 * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed 33 - * @rotation: simplified drm rotation hint 34 33 * @layout: framebuffer memory layout 35 34 */ 36 35 struct dpu_plane_state { ··· 47 48 u64 plane_clk; 48 49 49 50 bool needs_dirtyfb; 50 - unsigned int rotation; 51 51 52 52 struct dpu_hw_fmt_layout layout; 53 53 };

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