tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
"Here's the first round of MIPS fixes after the merge window:

- Detect Octeon III's PCI correctly.
- Fix return value of the MT7620 probing function.
- Wire up the copy_file_range syscall.
- Fix 64k page support on 32 bit kernels.
- Fix the early Coherency Manager probe.
- Allow only hardware-supported page sizes to be selected for R6000.
- Fix corner cases for the RDHWR nstruction emulation on old hardware.
- Fix FPU handling corner cases.
- Remove stale entry for BCM33xx from the MAINTAINERS file.
- 32 and 64 bit ELF headers are different, handle them correctly"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
mips: Differentiate between 32 and 64 bit ELF header
MIPS: Octeon: Update OCTEON_FEATURE_PCIE for Octeon III
MIPS: pci-mt7620: Fix return value check in mt7620_pci_probe()
MIPS: Fix early CM probing
MIPS: Wire up copy_file_range syscall.
MIPS: Fix 64k page support for 32 bit kernels.
MIPS: R6000: Don't allow 64k pages for R6000.
MIPS: traps.c: Correct microMIPS RDHWR emulation
MIPS: traps.c: Don't emulate RDHWR in the CpU #0 exception handler
MAINTAINERS: Remove stale entry for BCM33xx chips
MIPS: Fix FPU disable with preemption
MIPS: Properly disable FPU in start_thread()
MIPS: Fix buffer overflow in syscall_get_arguments()

Linus Torvalds ab57a611 be3f4e0f

+47 -72
-8
MAINTAINERS
··· 2362 2362 S: Maintained 2363 2363 N: bcm2835 2364 2364 2365 - BROADCOM BCM33XX MIPS ARCHITECTURE 2366 - M: Kevin Cernekee <cernekee@gmail.com> 2367 - L: linux-mips@linux-mips.org 2368 - S: Maintained 2369 - F: arch/mips/bcm3384/* 2370 - F: arch/mips/include/asm/mach-bcm3384/* 2371 - F: arch/mips/kernel/*bmips* 2372 - 2373 2365 BROADCOM BCM47XX MIPS ARCHITECTURE 2374 2366 M: Hauke Mehrtens <hauke@hauke-m.de> 2375 2367 M: Rafał Miłecki <zajec5@gmail.com>
+1 -1
arch/mips/Kconfig
··· 2085 2085 2086 2086 config PAGE_SIZE_64KB 2087 2087 bool "64kB" 2088 - depends on !CPU_R3000 && !CPU_TX39XX 2088 + depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000 2089 2089 help 2090 2090 Using 64kB page size will result in higher performance kernel at 2091 2091 the price of higher memory consumption. This option is available on
+7 -2
arch/mips/include/asm/elf.h
··· 227 227 int __res = 1; \ 228 228 struct elfhdr *__h = (hdr); \ 229 229 \ 230 - if (__h->e_machine != EM_MIPS) \ 230 + if (!mips_elf_check_machine(__h)) \ 231 231 __res = 0; \ 232 232 if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ 233 233 __res = 0; \ ··· 258 258 int __res = 1; \ 259 259 struct elfhdr *__h = (hdr); \ 260 260 \ 261 - if (__h->e_machine != EM_MIPS) \ 261 + if (!mips_elf_check_machine(__h)) \ 262 262 __res = 0; \ 263 263 if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ 264 264 __res = 0; \ ··· 284 284 #define ELF_ARCH EM_MIPS 285 285 286 286 #endif /* !defined(ELF_ARCH) */ 287 + 288 + #define mips_elf_check_machine(x) ((x)->e_machine == EM_MIPS) 289 + 290 + #define vmcore_elf32_check_arch mips_elf_check_machine 291 + #define vmcore_elf64_check_arch mips_elf_check_machine 287 292 288 293 struct mips_abi; 289 294
+4
arch/mips/include/asm/fpu.h
··· 179 179 if (save) 180 180 _save_fp(tsk); 181 181 __disable_fpu(); 182 + } else { 183 + /* FPU should not have been left enabled with no owner */ 184 + WARN(read_c0_status() & ST0_CU1, 185 + "Orphaned FPU left enabled"); 182 186 } 183 187 KSTK_STATUS(tsk) &= ~ST0_CU1; 184 188 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
+2 -1
arch/mips/include/asm/octeon/octeon-feature.h
··· 128 128 case OCTEON_FEATURE_PCIE: 129 129 return OCTEON_IS_MODEL(OCTEON_CN56XX) 130 130 || OCTEON_IS_MODEL(OCTEON_CN52XX) 131 - || OCTEON_IS_MODEL(OCTEON_CN6XXX); 131 + || OCTEON_IS_MODEL(OCTEON_CN6XXX) 132 + || OCTEON_IS_MODEL(OCTEON_CN7XXX); 132 133 133 134 case OCTEON_FEATURE_SRIO: 134 135 return OCTEON_IS_MODEL(OCTEON_CN63XX)
+1 -1
arch/mips/include/asm/processor.h
··· 45 45 * User space process size: 2GB. This is hardcoded into a few places, 46 46 * so don't change it unless you know what you are doing. 47 47 */ 48 - #define TASK_SIZE 0x7fff8000UL 48 + #define TASK_SIZE 0x80000000UL 49 49 #endif 50 50 51 51 #define STACK_TOP_MAX TASK_SIZE
+2 -2
arch/mips/include/asm/stackframe.h
··· 289 289 .set reorder 290 290 .set noat 291 291 mfc0 a0, CP0_STATUS 292 - li v1, 0xff00 292 + li v1, ST0_CU1 | ST0_IM 293 293 ori a0, STATMASK 294 294 xori a0, STATMASK 295 295 mtc0 a0, CP0_STATUS ··· 330 330 ori a0, STATMASK 331 331 xori a0, STATMASK 332 332 mtc0 a0, CP0_STATUS 333 - li v1, 0xff00 333 + li v1, ST0_CU1 | ST0_FR | ST0_IM 334 334 and a0, v1 335 335 LONG_L v0, PT_STATUS(sp) 336 336 nor v1, $0, v1
+1 -3
arch/mips/include/asm/syscall.h
··· 101 101 /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */ 102 102 if ((config_enabled(CONFIG_32BIT) || 103 103 test_tsk_thread_flag(task, TIF_32BIT_REGS)) && 104 - (regs->regs[2] == __NR_syscall)) { 104 + (regs->regs[2] == __NR_syscall)) 105 105 i++; 106 - n++; 107 - } 108 106 109 107 while (n--) 110 108 ret |= mips_get_syscall_arg(args++, task, regs, i++);
+9 -6
arch/mips/include/uapi/asm/unistd.h
··· 380 380 #define __NR_userfaultfd (__NR_Linux + 357) 381 381 #define __NR_membarrier (__NR_Linux + 358) 382 382 #define __NR_mlock2 (__NR_Linux + 359) 383 + #define __NR_copy_file_range (__NR_Linux + 360) 383 384 384 385 /* 385 386 * Offset of the last Linux o32 flavoured syscall 386 387 */ 387 - #define __NR_Linux_syscalls 359 388 + #define __NR_Linux_syscalls 360 388 389 389 390 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 390 391 391 392 #define __NR_O32_Linux 4000 392 - #define __NR_O32_Linux_syscalls 359 393 + #define __NR_O32_Linux_syscalls 360 393 394 394 395 #if _MIPS_SIM == _MIPS_SIM_ABI64 395 396 ··· 718 717 #define __NR_userfaultfd (__NR_Linux + 317) 719 718 #define __NR_membarrier (__NR_Linux + 318) 720 719 #define __NR_mlock2 (__NR_Linux + 319) 720 + #define __NR_copy_file_range (__NR_Linux + 320) 721 721 722 722 /* 723 723 * Offset of the last Linux 64-bit flavoured syscall 724 724 */ 725 - #define __NR_Linux_syscalls 319 725 + #define __NR_Linux_syscalls 320 726 726 727 727 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 728 728 729 729 #define __NR_64_Linux 5000 730 - #define __NR_64_Linux_syscalls 319 730 + #define __NR_64_Linux_syscalls 320 731 731 732 732 #if _MIPS_SIM == _MIPS_SIM_NABI32 733 733 ··· 1060 1058 #define __NR_userfaultfd (__NR_Linux + 321) 1061 1059 #define __NR_membarrier (__NR_Linux + 322) 1062 1060 #define __NR_mlock2 (__NR_Linux + 323) 1061 + #define __NR_copy_file_range (__NR_Linux + 324) 1063 1062 1064 1063 /* 1065 1064 * Offset of the last N32 flavoured syscall 1066 1065 */ 1067 - #define __NR_Linux_syscalls 323 1066 + #define __NR_Linux_syscalls 324 1068 1067 1069 1068 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 1070 1069 1071 1070 #define __NR_N32_Linux 6000 1072 - #define __NR_N32_Linux_syscalls 323 1071 + #define __NR_N32_Linux_syscalls 324 1073 1072 1074 1073 #endif /* _UAPI_ASM_UNISTD_H */
+1 -1
arch/mips/kernel/binfmt_elfn32.c
··· 35 35 int __res = 1; \ 36 36 struct elfhdr *__h = (hdr); \ 37 37 \ 38 - if (__h->e_machine != EM_MIPS) \ 38 + if (!mips_elf_check_machine(__h)) \ 39 39 __res = 0; \ 40 40 if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ 41 41 __res = 0; \
+1 -1
arch/mips/kernel/binfmt_elfo32.c
··· 47 47 int __res = 1; \ 48 48 struct elfhdr *__h = (hdr); \ 49 49 \ 50 - if (__h->e_machine != EM_MIPS) \ 50 + if (!mips_elf_check_machine(__h)) \ 51 51 __res = 0; \ 52 52 if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ 53 53 __res = 0; \
+3 -5
arch/mips/kernel/process.c
··· 65 65 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); 66 66 status |= KU_USER; 67 67 regs->cp0_status = status; 68 - clear_used_math(); 69 - clear_fpu_owner(); 70 - init_dsp(); 71 - clear_thread_flag(TIF_USEDMSA); 68 + lose_fpu(0); 72 69 clear_thread_flag(TIF_MSA_CTX_LIVE); 73 - disable_msa(); 70 + clear_used_math(); 71 + init_dsp(); 74 72 regs->cp0_epc = pc; 75 73 regs->regs[29] = sp; 76 74 }
+1
arch/mips/kernel/scall32-o32.S
··· 595 595 PTR sys_userfaultfd 596 596 PTR sys_membarrier 597 597 PTR sys_mlock2 598 + PTR sys_copy_file_range /* 4360 */
+1
arch/mips/kernel/scall64-64.S
··· 433 433 PTR sys_userfaultfd 434 434 PTR sys_membarrier 435 435 PTR sys_mlock2 436 + PTR sys_copy_file_range /* 5320 */ 436 437 .size sys_call_table,.-sys_call_table
+1
arch/mips/kernel/scall64-n32.S
··· 423 423 PTR sys_userfaultfd 424 424 PTR sys_membarrier 425 425 PTR sys_mlock2 426 + PTR sys_copy_file_range 426 427 .size sysn32_call_table,.-sysn32_call_table
+1
arch/mips/kernel/scall64-o32.S
··· 578 578 PTR sys_userfaultfd 579 579 PTR sys_membarrier 580 580 PTR sys_mlock2 581 + PTR sys_copy_file_range /* 4360 */ 581 582 .size sys32_call_table,.-sys32_call_table
+1
arch/mips/kernel/setup.c
··· 782 782 void __init setup_arch(char **cmdline_p) 783 783 { 784 784 cpu_probe(); 785 + mips_cm_probe(); 785 786 prom_init(); 786 787 787 788 setup_early_fdc_console();
+6 -19
arch/mips/kernel/traps.c
··· 663 663 return -1; 664 664 } 665 665 666 - static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) 666 + static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) 667 667 { 668 668 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 669 669 int rd = (opcode & MM_RS) >> 16; ··· 1119 1119 if (get_isa16_mode(regs->cp0_epc)) { 1120 1120 unsigned short mmop[2] = { 0 }; 1121 1121 1122 - if (unlikely(get_user(mmop[0], epc) < 0)) 1122 + if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) 1123 1123 status = SIGSEGV; 1124 - if (unlikely(get_user(mmop[1], epc) < 0)) 1124 + if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) 1125 1125 status = SIGSEGV; 1126 - opcode = (mmop[0] << 16) | mmop[1]; 1126 + opcode = mmop[0]; 1127 + opcode = (opcode << 16) | mmop[1]; 1127 1128 1128 1129 if (status < 0) 1129 1130 status = simulate_rdhwr_mm(regs, opcode); ··· 1370 1369 if (unlikely(compute_return_epc(regs) < 0)) 1371 1370 break; 1372 1371 1373 - if (get_isa16_mode(regs->cp0_epc)) { 1374 - unsigned short mmop[2] = { 0 }; 1375 - 1376 - if (unlikely(get_user(mmop[0], epc) < 0)) 1377 - status = SIGSEGV; 1378 - if (unlikely(get_user(mmop[1], epc) < 0)) 1379 - status = SIGSEGV; 1380 - opcode = (mmop[0] << 16) | mmop[1]; 1381 - 1382 - if (status < 0) 1383 - status = simulate_rdhwr_mm(regs, opcode); 1384 - } else { 1372 + if (!get_isa16_mode(regs->cp0_epc)) { 1385 1373 if (unlikely(get_user(opcode, epc) < 0)) 1386 1374 status = SIGSEGV; 1387 1375 1388 1376 if (!cpu_has_llsc && status < 0) 1389 1377 status = simulate_llsc(regs, opcode); 1390 - 1391 - if (status < 0) 1392 - status = simulate_rdhwr_normal(regs, opcode); 1393 1378 } 1394 1379 1395 1380 if (status < 0)
-10
arch/mips/mm/sc-mips.c
··· 181 181 return 1; 182 182 } 183 183 184 - void __weak platform_early_l2_init(void) 185 - { 186 - } 187 - 188 184 static inline int __init mips_sc_probe(void) 189 185 { 190 186 struct cpuinfo_mips *c = &current_cpu_data; ··· 189 193 190 194 /* Mark as not present until probe completed */ 191 195 c->scache.flags |= MIPS_CACHE_NOT_PRESENT; 192 - 193 - /* 194 - * Do we need some platform specific probing before 195 - * we configure L2? 196 - */ 197 - platform_early_l2_init(); 198 196 199 197 if (mips_cm_revision() >= CM_REV_CM3) 200 198 return mips_sc_probe_cm3();
-8
arch/mips/mti-malta/malta-init.c
··· 293 293 console_config(); 294 294 #endif 295 295 /* Early detection of CMP support */ 296 - mips_cm_probe(); 297 296 mips_cpc_probe(); 298 297 299 298 if (!register_cps_smp_ops()) ··· 302 303 if (!register_vsmp_smp_ops()) 303 304 return; 304 305 register_up_smp_ops(); 305 - } 306 - 307 - void platform_early_l2_init(void) 308 - { 309 - /* L2 configuration lives in the CM3 */ 310 - if (mips_cm_revision() >= CM_REV_CM3) 311 - mips_cm_probe(); 312 306 }
+4 -4
arch/mips/pci/pci-mt7620.c
··· 297 297 return PTR_ERR(rstpcie0); 298 298 299 299 bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res); 300 - if (!bridge_base) 301 - return -ENOMEM; 300 + if (IS_ERR(bridge_base)) 301 + return PTR_ERR(bridge_base); 302 302 303 303 pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res); 304 - if (!pcie_base) 305 - return -ENOMEM; 304 + if (IS_ERR(pcie_base)) 305 + return PTR_ERR(pcie_base); 306 306 307 307 iomem_resource.start = 0; 308 308 iomem_resource.end = ~0;