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spi: mt65xx: add dual and quad mode for standard spi device

Mediatek SPI hardware natively supports dual and quad modes, and these
modes are already enabled for SPI flash devices under spi-mem framework
in MTK SPI controller spi-mt65xx. However, other SPI devices, such as
touch panels, are limited to single mode because spi-mt65xx lacks SPI
mode argument parsing from SPI framework for these SPI devices outside
spi-mem framework.

This patch adds dual and quad mode support for these SPI devices by
introducing a new API, mtk_spi_set_nbits, for SPI mode argument parsing.

Signed-off-by: Tim Kuo <Tim.Kuo@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20250917055839.500615-1-Tim.Kuo@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Tim Kuo and committed by
Mark Brown ab63e991 b28a55db

+25 -3
+25 -3
drivers/spi/spi-mt65xx.c
··· 563 563 writel(reg_val, mdata->base + SPI_CFG1_REG); 564 564 } 565 565 566 + inline u32 mtk_spi_set_nbit(u32 nbit) 567 + { 568 + switch (nbit) { 569 + default: 570 + pr_warn_once("unknown nbit mode %u. Falling back to single mode\n", 571 + nbit); 572 + fallthrough; 573 + case SPI_NBITS_SINGLE: 574 + return 0x0; 575 + case SPI_NBITS_DUAL: 576 + return 0x1; 577 + case SPI_NBITS_QUAD: 578 + return 0x2; 579 + } 580 + } 581 + 566 582 static void mtk_spi_enable_transfer(struct spi_controller *host) 567 583 { 568 584 u32 cmd; ··· 745 729 746 730 /* prepare xfer direction and duplex mode */ 747 731 if (mdata->dev_comp->ipm_design) { 748 - if (!xfer->tx_buf || !xfer->rx_buf) { 732 + if (xfer->tx_buf && xfer->rx_buf) { 733 + reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_EN; 734 + } else if (xfer->tx_buf) { 749 735 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 750 - if (xfer->rx_buf) 751 - reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 736 + reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; 737 + reg_val |= mtk_spi_set_nbit(xfer->tx_nbits); 738 + } else { 739 + reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 740 + reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 741 + reg_val |= mtk_spi_set_nbit(xfer->rx_nbits); 752 742 } 753 743 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); 754 744 }