Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: ethernet: neterion: s2io: remove unused driver
The s2io driver supports Exar (formerly Neterion and S2io) PCI-X 10
Gigabit Ethernet cards. Hardware supporting PCI-X has not been
manufactured in years. On x86, it was quickly replaced by PCIe. While
it stuck around longer on POWER hardware, the last POWER hardware to
support it was POWER7, which is not supported by ppc64le Linux
distributions. The last supported mainstream ppc64 Linux distribution
was RHEL 7; while it is still supported under ELS, ELS is only
available for x86 and IBM Z. It is possible to use many PCI-X cards in
standard PCI slots (which are still available on new motherboards), but
it does not make sense to do so for 10 Gigabit Ethernet because the
maximum bandwidth of standard PCI is only 1067 Mbps. It is therefore
highly unlikely that this driver is still being used. Remove the
driver, and move the former maintainer to the CREDITS file (restoring
credit for the vxge driver, which was removed in commit f05643a0f60b
("eth: remove neterion/vxge").
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Link: https://patch.msgid.link/20260126031352.22997-1-enelsonmoore@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Ethan Nelson-Moore
and committed by
Jakub Kicinski
aba0138e
2f80b279
+4
-10911
+4
CREDITS
+4
CREDITS
-1
Documentation/.renames.txt
-1
Documentation/.renames.txt
···
819
819
networking/device_drivers/intel/ixgbevf networking/device_drivers/ethernet/intel/ixgbevf
820
820
networking/device_drivers/marvell/octeontx2 networking/device_drivers/ethernet/marvell/octeontx2
821
821
networking/device_drivers/microsoft/netvsc networking/device_drivers/ethernet/microsoft/netvsc
822
-
networking/device_drivers/neterion/s2io networking/device_drivers/ethernet/neterion/s2io
823
822
networking/device_drivers/netronome/nfp networking/device_drivers/ethernet/netronome/nfp
824
823
networking/device_drivers/pensando/ionic networking/device_drivers/ethernet/pensando/ionic
825
824
networking/device_drivers/qualcomm/rmnet networking/device_drivers/cellular/qualcomm/rmnet
-1
Documentation/PCI/pci-error-recovery.rst
-1
Documentation/PCI/pci-error-recovery.rst
-1
Documentation/networking/device_drivers/ethernet/index.rst
-1
Documentation/networking/device_drivers/ethernet/index.rst
-196
Documentation/networking/device_drivers/ethernet/neterion/s2io.rst
-196
Documentation/networking/device_drivers/ethernet/neterion/s2io.rst
···
1
-
.. SPDX-License-Identifier: GPL-2.0
2
-
3
-
=========================================================
4
-
Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver
5
-
=========================================================
6
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7
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Release notes for Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver.
8
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9
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.. Contents
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- 1. Introduction
11
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- 2. Identifying the adapter/interface
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- 3. Features supported
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- 4. Command line parameters
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- 5. Performance suggestions
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- 6. Available Downloads
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-
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1. Introduction
19
-
===============
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This Linux driver supports Neterion's Xframe I PCI-X 1.0 and
21
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Xframe II PCI-X 2.0 adapters. It supports several features
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such as jumbo frames, MSI/MSI-X, checksum offloads, TSO, UFO and so on.
23
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See below for complete list of features.
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All features are supported for both IPv4 and IPv6.
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-
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2. Identifying the adapter/interface
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-
====================================
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a. Insert the adapter(s) in your system.
31
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b. Build and load driver::
32
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# insmod s2io.ko
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c. View log messages::
36
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# dmesg | tail -40
38
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You will see messages similar to::
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eth3: Neterion Xframe I 10GbE adapter (rev 3), Version 2.0.9.1, Intr type INTA
42
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eth4: Neterion Xframe II 10GbE adapter (rev 2), Version 2.0.9.1, Intr type INTA
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eth4: Device is on 64 bit 133MHz PCIX(M1) bus
44
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The above messages identify the adapter type(Xframe I/II), adapter revision,
46
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driver version, interface name(eth3, eth4), Interrupt type(INTA, MSI, MSI-X).
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In case of Xframe II, the PCI/PCI-X bus width and frequency are displayed
48
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as well.
49
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50
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To associate an interface with a physical adapter use "ethtool -p <ethX>".
51
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The corresponding adapter's LED will blink multiple times.
52
-
53
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3. Features supported
54
-
=====================
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a. Jumbo frames. Xframe I/II supports MTU up to 9600 bytes,
56
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modifiable using ip command.
57
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58
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b. Offloads. Supports checksum offload(TCP/UDP/IP) on transmit
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and receive, TSO.
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61
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c. Multi-buffer receive mode. Scattering of packet across multiple
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buffers. Currently driver supports 2-buffer mode which yields
63
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significant performance improvement on certain platforms(SGI Altix,
64
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IBM xSeries).
65
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66
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d. MSI/MSI-X. Can be enabled on platforms which support this feature
67
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resulting in noticeable performance improvement (up to 7% on certain
68
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platforms).
69
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70
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e. Statistics. Comprehensive MAC-level and software statistics displayed
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using "ethtool -S" option.
72
-
73
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f. Multi-FIFO/Ring. Supports up to 8 transmit queues and receive rings,
74
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with multiple steering options.
75
-
76
-
4. Command line parameters
77
-
==========================
78
-
79
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a. tx_fifo_num
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Number of transmit queues
81
-
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Valid range: 1-8
83
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Default: 1
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-
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b. rx_ring_num
87
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Number of receive rings
88
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Valid range: 1-8
90
-
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Default: 1
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-
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c. tx_fifo_len
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Size of each transmit queue
95
-
96
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Valid range: Total length of all queues should not exceed 8192
97
-
98
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Default: 4096
99
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100
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d. rx_ring_sz
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Size of each receive ring(in 4K blocks)
102
-
103
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Valid range: Limited by memory on system
104
-
105
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Default: 30
106
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107
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e. intr_type
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Specifies interrupt type. Possible values 0(INTA), 2(MSI-X)
109
-
110
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Valid values: 0, 2
111
-
112
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Default: 2
113
-
114
-
5. Performance suggestions
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-
==========================
116
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117
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General:
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-
119
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a. Set MTU to maximum(9000 for switch setup, 9600 in back-to-back configuration)
120
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b. Set TCP windows size to optimal value.
121
-
122
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For instance, for MTU=1500 a value of 210K has been observed to result in
123
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good performance::
124
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# sysctl -w net.ipv4.tcp_rmem="210000 210000 210000"
126
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# sysctl -w net.ipv4.tcp_wmem="210000 210000 210000"
127
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128
-
For MTU=9000, TCP window size of 10 MB is recommended::
129
-
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# sysctl -w net.ipv4.tcp_rmem="10000000 10000000 10000000"
131
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# sysctl -w net.ipv4.tcp_wmem="10000000 10000000 10000000"
132
-
133
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Transmit performance:
134
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a. By default, the driver respects BIOS settings for PCI bus parameters.
136
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However, you may want to experiment with PCI bus parameters
137
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max-split-transactions(MOST) and MMRBC (use setpci command).
138
-
139
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A MOST value of 2 has been found optimal for Opterons and 3 for Itanium.
140
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141
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It could be different for your hardware.
142
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143
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Set MMRBC to 4K**.
144
-
145
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For example you can set
146
-
147
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For opteron::
148
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149
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#setpci -d 17d5:* 62=1d
150
-
151
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For Itanium::
152
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153
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#setpci -d 17d5:* 62=3d
154
-
155
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For detailed description of the PCI registers, please see Xframe User Guide.
156
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157
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b. Ensure Transmit Checksum offload is enabled. Use ethtool to set/verify this
158
-
parameter.
159
-
160
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c. Turn on TSO(using "ethtool -K")::
161
-
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# ethtool -K <ethX> tso on
163
-
164
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Receive performance:
165
-
166
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a. By default, the driver respects BIOS settings for PCI bus parameters.
167
-
However, you may want to set PCI latency timer to 248::
168
-
169
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#setpci -d 17d5:* LATENCY_TIMER=f8
170
-
171
-
For detailed description of the PCI registers, please see Xframe User Guide.
172
-
173
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b. Use 2-buffer mode. This results in large performance boost on
174
-
certain platforms(eg. SGI Altix, IBM xSeries).
175
-
176
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c. Ensure Receive Checksum offload is enabled. Use "ethtool -K ethX" command to
177
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set/verify this option.
178
-
179
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d. Enable NAPI feature(in kernel configuration Device Drivers ---> Network
180
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device support ---> Ethernet (10000 Mbit) ---> S2IO 10Gbe Xframe NIC) to
181
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bring down CPU utilization.
182
-
183
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.. note::
184
-
185
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For AMD opteron platforms with 8131 chipset, MMRBC=1 and MOST=1 are
186
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recommended as safe parameters.
187
-
188
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For more information, please review the AMD8131 errata at
189
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http://vip.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/
190
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26310_AMD-8131_HyperTransport_PCI-X_Tunnel_Revision_Guide_rev_3_18.pdf
191
-
192
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6. Support
193
-
==========
194
-
195
-
For further support please contact either your 10GbE Xframe NIC vendor (IBM,
196
-
HP, SGI etc.)
-7
MAINTAINERS
-7
MAINTAINERS
···
18035
18035
S: Maintained
18036
18036
F: net/sched/sch_netem.c
18037
18037
18038
-
NETERION 10GbE DRIVERS (s2io)
18039
-
M: Jon Mason <jdmason@kudzu.us>
18040
-
L: netdev@vger.kernel.org
18041
-
S: Maintained
18042
-
F: Documentation/networking/device_drivers/ethernet/neterion/s2io.rst
18043
-
F: drivers/net/ethernet/neterion/
18044
-
18045
18038
NETFILTER
18046
18039
M: Pablo Neira Ayuso <pablo@netfilter.org>
18047
18040
M: Florian Westphal <fw@strlen.de>
-1
arch/mips/configs/loongson2k_defconfig
-1
arch/mips/configs/loongson2k_defconfig
···
161
161
# CONFIG_NET_VENDOR_MICROSEMI is not set
162
162
# CONFIG_NET_VENDOR_MYRI is not set
163
163
# CONFIG_NET_VENDOR_NATSEMI is not set
164
-
# CONFIG_NET_VENDOR_NETERION is not set
165
164
# CONFIG_NET_VENDOR_NETRONOME is not set
166
165
# CONFIG_NET_VENDOR_NI is not set
167
166
# CONFIG_NET_VENDOR_NVIDIA is not set
-1
arch/mips/configs/mtx1_defconfig
-1
arch/mips/configs/mtx1_defconfig
-1
arch/powerpc/configs/powernv_defconfig
-1
arch/powerpc/configs/powernv_defconfig
-1
arch/powerpc/configs/ppc64_defconfig
-1
arch/powerpc/configs/ppc64_defconfig
-1
arch/powerpc/configs/ppc6xx_defconfig
-1
arch/powerpc/configs/ppc6xx_defconfig
-1
arch/powerpc/configs/skiroot_defconfig
-1
arch/powerpc/configs/skiroot_defconfig
-1
arch/s390/configs/debug_defconfig
-1
arch/s390/configs/debug_defconfig
···
560
560
# CONFIG_NET_VENDOR_MYRI is not set
561
561
# CONFIG_NET_VENDOR_NI is not set
562
562
# CONFIG_NET_VENDOR_NATSEMI is not set
563
-
# CONFIG_NET_VENDOR_NETERION is not set
564
563
# CONFIG_NET_VENDOR_NETRONOME is not set
565
564
# CONFIG_NET_VENDOR_NVIDIA is not set
566
565
# CONFIG_NET_VENDOR_OKI is not set
-1
arch/s390/configs/defconfig
-1
arch/s390/configs/defconfig
···
550
550
# CONFIG_NET_VENDOR_MYRI is not set
551
551
# CONFIG_NET_VENDOR_NI is not set
552
552
# CONFIG_NET_VENDOR_NATSEMI is not set
553
-
# CONFIG_NET_VENDOR_NETERION is not set
554
553
# CONFIG_NET_VENDOR_NETRONOME is not set
555
554
# CONFIG_NET_VENDOR_NVIDIA is not set
556
555
# CONFIG_NET_VENDOR_OKI is not set
-1
drivers/net/ethernet/Kconfig
-1
drivers/net/ethernet/Kconfig
···
131
131
132
132
source "drivers/net/ethernet/ni/Kconfig"
133
133
source "drivers/net/ethernet/natsemi/Kconfig"
134
-
source "drivers/net/ethernet/neterion/Kconfig"
135
134
source "drivers/net/ethernet/netronome/Kconfig"
136
135
source "drivers/net/ethernet/8390/Kconfig"
137
136
source "drivers/net/ethernet/nvidia/Kconfig"
-1
drivers/net/ethernet/Makefile
-1
drivers/net/ethernet/Makefile
···
68
68
obj-$(CONFIG_NET_VENDOR_MYRI) += myricom/
69
69
obj-$(CONFIG_FEALNX) += fealnx.o
70
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obj-$(CONFIG_NET_VENDOR_NATSEMI) += natsemi/
71
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obj-$(CONFIG_NET_VENDOR_NETERION) += neterion/
72
71
obj-$(CONFIG_NET_VENDOR_NETRONOME) += netronome/
73
72
obj-$(CONFIG_NET_VENDOR_NI) += ni/
74
73
obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
-35
drivers/net/ethernet/neterion/Kconfig
-35
drivers/net/ethernet/neterion/Kconfig
···
1
-
# SPDX-License-Identifier: GPL-2.0-only
2
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#
3
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# Exar device configuration
4
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#
5
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6
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config NET_VENDOR_NETERION
7
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bool "Neterion (Exar) devices"
8
-
default y
9
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depends on PCI
10
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help
11
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If you have a network (Ethernet) card belonging to this class, say Y.
12
-
13
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Note that the answer to this question doesn't directly affect the
14
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kernel: saying N will just cause the configurator to skip all
15
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the questions about Neterion/Exar cards. If you say Y, you will be
16
-
asked for your specific card in the following questions.
17
-
18
-
if NET_VENDOR_NETERION
19
-
20
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config S2IO
21
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tristate "Neterion (Exar) Xframe 10Gb Ethernet Adapter"
22
-
depends on PCI
23
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help
24
-
This driver supports Exar Corp's Xframe Series 10Gb Ethernet Adapters.
25
-
These were originally released from S2IO, which renamed itself
26
-
Neterion. So, the adapters might be labeled as either one, depending
27
-
on its age.
28
-
29
-
More specific information on configuring the driver is in
30
-
<file:Documentation/networking/device_drivers/ethernet/neterion/s2io.rst>.
31
-
32
-
To compile this driver as a module, choose M here. The module
33
-
will be called s2io.
34
-
35
-
endif # NET_VENDOR_NETERION
-6
drivers/net/ethernet/neterion/Makefile
-6
drivers/net/ethernet/neterion/Makefile
-958
drivers/net/ethernet/neterion/s2io-regs.h
-958
drivers/net/ethernet/neterion/s2io-regs.h
···
1
-
/************************************************************************
2
-
* regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3
-
* Copyright(c) 2002-2010 Exar Corp.
4
-
5
-
* This software may be used and distributed according to the terms of
6
-
* the GNU General Public License (GPL), incorporated herein by reference.
7
-
* Drivers based on or derived from this code fall under the GPL and must
8
-
* retain the authorship, copyright and license notice. This file is not
9
-
* a complete program and may only be used when the entire operating
10
-
* system is licensed under the GPL.
11
-
* See the file COPYING in this distribution for more information.
12
-
************************************************************************/
13
-
#ifndef _REGS_H
14
-
#define _REGS_H
15
-
16
-
#define TBD 0
17
-
18
-
struct XENA_dev_config {
19
-
/* Convention: mHAL_XXX is mask, vHAL_XXX is value */
20
-
21
-
/* General Control-Status Registers */
22
-
u64 general_int_status;
23
-
#define GEN_INTR_TXPIC s2BIT(0)
24
-
#define GEN_INTR_TXDMA s2BIT(1)
25
-
#define GEN_INTR_TXMAC s2BIT(2)
26
-
#define GEN_INTR_TXXGXS s2BIT(3)
27
-
#define GEN_INTR_TXTRAFFIC s2BIT(8)
28
-
#define GEN_INTR_RXPIC s2BIT(32)
29
-
#define GEN_INTR_RXDMA s2BIT(33)
30
-
#define GEN_INTR_RXMAC s2BIT(34)
31
-
#define GEN_INTR_MC s2BIT(35)
32
-
#define GEN_INTR_RXXGXS s2BIT(36)
33
-
#define GEN_INTR_RXTRAFFIC s2BIT(40)
34
-
#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35
-
GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36
-
GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37
-
GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
38
-
GEN_INTR_MC
39
-
40
-
u64 general_int_mask;
41
-
42
-
u8 unused0[0x100 - 0x10];
43
-
44
-
u64 sw_reset;
45
-
/* XGXS must be removed from reset only once. */
46
-
#define SW_RESET_XENA vBIT(0xA5,0,8)
47
-
#define SW_RESET_FLASH vBIT(0xA5,8,8)
48
-
#define SW_RESET_EOI vBIT(0xA5,16,8)
49
-
#define SW_RESET_ALL (SW_RESET_XENA | \
50
-
SW_RESET_FLASH | \
51
-
SW_RESET_EOI)
52
-
/* The SW_RESET register must read this value after a successful reset. */
53
-
#define SW_RESET_RAW_VAL 0xA5000000
54
-
55
-
56
-
u64 adapter_status;
57
-
#define ADAPTER_STATUS_TDMA_READY s2BIT(0)
58
-
#define ADAPTER_STATUS_RDMA_READY s2BIT(1)
59
-
#define ADAPTER_STATUS_PFC_READY s2BIT(2)
60
-
#define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3)
61
-
#define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5)
62
-
#define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6)
63
-
#define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7)
64
-
#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65
-
#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
66
-
#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
67
-
#define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24)
68
-
#define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25)
69
-
#define ADAPTER_STATUS_RIC_RUNNING s2BIT(26)
70
-
#define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30)
71
-
#define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31)
72
-
73
-
u64 adapter_control;
74
-
#define ADAPTER_CNTL_EN s2BIT(7)
75
-
#define ADAPTER_EOI_TX_ON s2BIT(15)
76
-
#define ADAPTER_LED_ON s2BIT(23)
77
-
#define ADAPTER_UDPI(val) vBIT(val,36,4)
78
-
#define ADAPTER_WAIT_INT s2BIT(48)
79
-
#define ADAPTER_ECC_EN s2BIT(55)
80
-
81
-
u64 serr_source;
82
-
#define SERR_SOURCE_PIC s2BIT(0)
83
-
#define SERR_SOURCE_TXDMA s2BIT(1)
84
-
#define SERR_SOURCE_RXDMA s2BIT(2)
85
-
#define SERR_SOURCE_MAC s2BIT(3)
86
-
#define SERR_SOURCE_MC s2BIT(4)
87
-
#define SERR_SOURCE_XGXS s2BIT(5)
88
-
#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
89
-
SERR_SOURCE_TXDMA | \
90
-
SERR_SOURCE_RXDMA | \
91
-
SERR_SOURCE_MAC | \
92
-
SERR_SOURCE_MC | \
93
-
SERR_SOURCE_XGXS)
94
-
95
-
u64 pci_mode;
96
-
#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
97
-
#define PCI_MODE_PCI_33 0
98
-
#define PCI_MODE_PCI_66 0x1
99
-
#define PCI_MODE_PCIX_M1_66 0x2
100
-
#define PCI_MODE_PCIX_M1_100 0x3
101
-
#define PCI_MODE_PCIX_M1_133 0x4
102
-
#define PCI_MODE_PCIX_M2_66 0x5
103
-
#define PCI_MODE_PCIX_M2_100 0x6
104
-
#define PCI_MODE_PCIX_M2_133 0x7
105
-
#define PCI_MODE_UNSUPPORTED s2BIT(0)
106
-
#define PCI_MODE_32_BITS s2BIT(8)
107
-
#define PCI_MODE_UNKNOWN_MODE s2BIT(9)
108
-
109
-
u8 unused_0[0x800 - 0x128];
110
-
111
-
/* PCI-X Controller registers */
112
-
u64 pic_int_status;
113
-
u64 pic_int_mask;
114
-
#define PIC_INT_TX s2BIT(0)
115
-
#define PIC_INT_FLSH s2BIT(1)
116
-
#define PIC_INT_MDIO s2BIT(2)
117
-
#define PIC_INT_IIC s2BIT(3)
118
-
#define PIC_INT_GPIO s2BIT(4)
119
-
#define PIC_INT_RX s2BIT(32)
120
-
121
-
u64 txpic_int_reg;
122
-
u64 txpic_int_mask;
123
-
#define PCIX_INT_REG_ECC_SG_ERR s2BIT(0)
124
-
#define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)
125
-
#define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)
126
-
#define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9)
127
-
#define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10)
128
-
#define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11)
129
-
#define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13)
130
-
#define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14)
131
-
#define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15)
132
-
#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21)
133
-
#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23)
134
-
#define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48)
135
-
#define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50)
136
-
/*
137
-
#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52)
138
-
#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54)
139
-
#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58)
140
-
*/
141
-
u64 txpic_alarms;
142
-
u64 rxpic_int_reg;
143
-
u64 rxpic_int_mask;
144
-
u64 rxpic_alarms;
145
-
146
-
u64 flsh_int_reg;
147
-
u64 flsh_int_mask;
148
-
#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63)
149
-
#define PIC_FLSH_INT_REG_ERR s2BIT(62)
150
-
u64 flash_alarms;
151
-
152
-
u64 mdio_int_reg;
153
-
u64 mdio_int_mask;
154
-
#define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0)
155
-
#define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)
156
-
#define MDIO_INT_REG_LASI s2BIT(39)
157
-
u64 mdio_alarms;
158
-
159
-
u64 iic_int_reg;
160
-
u64 iic_int_mask;
161
-
#define IIC_INT_REG_BUS_FSM_ERR s2BIT(4)
162
-
#define IIC_INT_REG_BIT_FSM_ERR s2BIT(5)
163
-
#define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6)
164
-
#define IIC_INT_REG_REQ_FSM_ERR s2BIT(7)
165
-
#define IIC_INT_REG_ACK_ERR s2BIT(8)
166
-
u64 iic_alarms;
167
-
168
-
u8 unused4[0x08];
169
-
170
-
u64 gpio_int_reg;
171
-
#define GPIO_INT_REG_DP_ERR_INT s2BIT(0)
172
-
#define GPIO_INT_REG_LINK_DOWN s2BIT(1)
173
-
#define GPIO_INT_REG_LINK_UP s2BIT(2)
174
-
u64 gpio_int_mask;
175
-
#define GPIO_INT_MASK_LINK_DOWN s2BIT(1)
176
-
#define GPIO_INT_MASK_LINK_UP s2BIT(2)
177
-
u64 gpio_alarms;
178
-
179
-
u8 unused5[0x38];
180
-
181
-
u64 tx_traffic_int;
182
-
#define TX_TRAFFIC_INT_n(n) s2BIT(n)
183
-
u64 tx_traffic_mask;
184
-
185
-
u64 rx_traffic_int;
186
-
#define RX_TRAFFIC_INT_n(n) s2BIT(n)
187
-
u64 rx_traffic_mask;
188
-
189
-
/* PIC Control registers */
190
-
u64 pic_control;
191
-
#define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0)
192
-
#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
193
-
194
-
u64 swapper_ctrl;
195
-
#define SWAPPER_CTRL_PIF_R_FE s2BIT(0)
196
-
#define SWAPPER_CTRL_PIF_R_SE s2BIT(1)
197
-
#define SWAPPER_CTRL_PIF_W_FE s2BIT(8)
198
-
#define SWAPPER_CTRL_PIF_W_SE s2BIT(9)
199
-
#define SWAPPER_CTRL_TXP_FE s2BIT(16)
200
-
#define SWAPPER_CTRL_TXP_SE s2BIT(17)
201
-
#define SWAPPER_CTRL_TXD_R_FE s2BIT(18)
202
-
#define SWAPPER_CTRL_TXD_R_SE s2BIT(19)
203
-
#define SWAPPER_CTRL_TXD_W_FE s2BIT(20)
204
-
#define SWAPPER_CTRL_TXD_W_SE s2BIT(21)
205
-
#define SWAPPER_CTRL_TXF_R_FE s2BIT(22)
206
-
#define SWAPPER_CTRL_TXF_R_SE s2BIT(23)
207
-
#define SWAPPER_CTRL_RXD_R_FE s2BIT(32)
208
-
#define SWAPPER_CTRL_RXD_R_SE s2BIT(33)
209
-
#define SWAPPER_CTRL_RXD_W_FE s2BIT(34)
210
-
#define SWAPPER_CTRL_RXD_W_SE s2BIT(35)
211
-
#define SWAPPER_CTRL_RXF_W_FE s2BIT(36)
212
-
#define SWAPPER_CTRL_RXF_W_SE s2BIT(37)
213
-
#define SWAPPER_CTRL_XMSI_FE s2BIT(40)
214
-
#define SWAPPER_CTRL_XMSI_SE s2BIT(41)
215
-
#define SWAPPER_CTRL_STATS_FE s2BIT(48)
216
-
#define SWAPPER_CTRL_STATS_SE s2BIT(49)
217
-
218
-
u64 pif_rd_swapper_fb;
219
-
#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
220
-
221
-
u64 scheduled_int_ctrl;
222
-
#define SCHED_INT_CTRL_TIMER_EN s2BIT(0)
223
-
#define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)
224
-
#define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
225
-
#define SCHED_INT_PERIOD TBD
226
-
227
-
u64 txreqtimeout;
228
-
#define TXREQTO_VAL(val) vBIT(val,0,32)
229
-
#define TXREQTO_EN s2BIT(63)
230
-
231
-
u64 statsreqtimeout;
232
-
#define STATREQTO_VAL(n) TBD
233
-
#define STATREQTO_EN s2BIT(63)
234
-
235
-
u64 read_retry_delay;
236
-
u64 read_retry_acceleration;
237
-
u64 write_retry_delay;
238
-
u64 write_retry_acceleration;
239
-
240
-
u64 xmsi_control;
241
-
u64 xmsi_access;
242
-
u64 xmsi_address;
243
-
u64 xmsi_data;
244
-
245
-
u64 rx_mat;
246
-
#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
247
-
248
-
u8 unused6[0x8];
249
-
250
-
u64 tx_mat0_n[0x8];
251
-
#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
252
-
253
-
u64 xmsi_mask_reg;
254
-
u64 stat_byte_cnt;
255
-
#define STAT_BC(n) vBIT(n,4,12)
256
-
257
-
/* Automated statistics collection */
258
-
u64 stat_cfg;
259
-
#define STAT_CFG_STAT_EN s2BIT(0)
260
-
#define STAT_CFG_ONE_SHOT_EN s2BIT(1)
261
-
#define STAT_CFG_STAT_NS_EN s2BIT(8)
262
-
#define STAT_CFG_STAT_RO s2BIT(9)
263
-
#define STAT_TRSF_PER(n) TBD
264
-
#define PER_SEC 0x208d5
265
-
#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
266
-
#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
267
-
268
-
u64 stat_addr;
269
-
270
-
/* General Configuration */
271
-
u64 mdio_control;
272
-
#define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
273
-
#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
274
-
#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
275
-
#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
276
-
#define MDIO_OP(val) vBIT(val, 60, 2)
277
-
#define MDIO_OP_ADDR_TRANS 0x0
278
-
#define MDIO_OP_WRITE_TRANS 0x1
279
-
#define MDIO_OP_READ_POST_INC_TRANS 0x2
280
-
#define MDIO_OP_READ_TRANS 0x3
281
-
#define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
282
-
283
-
u64 dtx_control;
284
-
285
-
u64 i2c_control;
286
-
#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
287
-
#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
288
-
#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
289
-
#define I2C_CONTROL_READ s2BIT(24)
290
-
#define I2C_CONTROL_NACK s2BIT(25)
291
-
#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
292
-
#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
293
-
#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
294
-
#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
295
-
296
-
u64 gpio_control;
297
-
#define GPIO_CTRL_GPIO_0 s2BIT(8)
298
-
u64 misc_control;
299
-
#define FAULT_BEHAVIOUR s2BIT(0)
300
-
#define EXT_REQ_EN s2BIT(1)
301
-
#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
302
-
303
-
u8 unused7_1[0x230 - 0x208];
304
-
305
-
u64 pic_control2;
306
-
u64 ini_dperr_ctrl;
307
-
308
-
u64 wreq_split_mask;
309
-
#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
310
-
311
-
u8 unused7_2[0x800 - 0x248];
312
-
313
-
/* TxDMA registers */
314
-
u64 txdma_int_status;
315
-
u64 txdma_int_mask;
316
-
#define TXDMA_PFC_INT s2BIT(0)
317
-
#define TXDMA_TDA_INT s2BIT(1)
318
-
#define TXDMA_PCC_INT s2BIT(2)
319
-
#define TXDMA_TTI_INT s2BIT(3)
320
-
#define TXDMA_LSO_INT s2BIT(4)
321
-
#define TXDMA_TPA_INT s2BIT(5)
322
-
#define TXDMA_SM_INT s2BIT(6)
323
-
u64 pfc_err_reg;
324
-
#define PFC_ECC_SG_ERR s2BIT(7)
325
-
#define PFC_ECC_DB_ERR s2BIT(15)
326
-
#define PFC_SM_ERR_ALARM s2BIT(23)
327
-
#define PFC_MISC_0_ERR s2BIT(31)
328
-
#define PFC_MISC_1_ERR s2BIT(32)
329
-
#define PFC_PCIX_ERR s2BIT(39)
330
-
u64 pfc_err_mask;
331
-
u64 pfc_err_alarm;
332
-
333
-
u64 tda_err_reg;
334
-
#define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
335
-
#define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
336
-
#define TDA_SM0_ERR_ALARM s2BIT(22)
337
-
#define TDA_SM1_ERR_ALARM s2BIT(23)
338
-
#define TDA_PCIX_ERR s2BIT(39)
339
-
u64 tda_err_mask;
340
-
u64 tda_err_alarm;
341
-
342
-
u64 pcc_err_reg;
343
-
#define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
344
-
#define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
345
-
#define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
346
-
#define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
347
-
#define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
348
-
#define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
349
-
#define PCC_N_SERR vBIT(0xff,48,8)
350
-
#define PCC_6_COF_OV_ERR s2BIT(56)
351
-
#define PCC_7_COF_OV_ERR s2BIT(57)
352
-
#define PCC_6_LSO_OV_ERR s2BIT(58)
353
-
#define PCC_7_LSO_OV_ERR s2BIT(59)
354
-
#define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
355
-
u64 pcc_err_mask;
356
-
u64 pcc_err_alarm;
357
-
358
-
u64 tti_err_reg;
359
-
#define TTI_ECC_SG_ERR s2BIT(7)
360
-
#define TTI_ECC_DB_ERR s2BIT(15)
361
-
#define TTI_SM_ERR_ALARM s2BIT(23)
362
-
u64 tti_err_mask;
363
-
u64 tti_err_alarm;
364
-
365
-
u64 lso_err_reg;
366
-
#define LSO6_SEND_OFLOW s2BIT(12)
367
-
#define LSO7_SEND_OFLOW s2BIT(13)
368
-
#define LSO6_ABORT s2BIT(14)
369
-
#define LSO7_ABORT s2BIT(15)
370
-
#define LSO6_SM_ERR_ALARM s2BIT(22)
371
-
#define LSO7_SM_ERR_ALARM s2BIT(23)
372
-
u64 lso_err_mask;
373
-
u64 lso_err_alarm;
374
-
375
-
u64 tpa_err_reg;
376
-
#define TPA_TX_FRM_DROP s2BIT(7)
377
-
#define TPA_SM_ERR_ALARM s2BIT(23)
378
-
379
-
u64 tpa_err_mask;
380
-
u64 tpa_err_alarm;
381
-
382
-
u64 sm_err_reg;
383
-
#define SM_SM_ERR_ALARM s2BIT(15)
384
-
u64 sm_err_mask;
385
-
u64 sm_err_alarm;
386
-
387
-
u8 unused8[0x100 - 0xB8];
388
-
389
-
/* TxDMA arbiter */
390
-
u64 tx_dma_wrap_stat;
391
-
392
-
/* Tx FIFO controller */
393
-
#define X_MAX_FIFOS 8
394
-
#define X_FIFO_MAX_LEN 0x1FFF /*8191 */
395
-
u64 tx_fifo_partition_0;
396
-
#define TX_FIFO_PARTITION_EN s2BIT(0)
397
-
#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
398
-
#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
399
-
#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
400
-
#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
401
-
402
-
u64 tx_fifo_partition_1;
403
-
#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
404
-
#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
405
-
#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
406
-
#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
407
-
408
-
u64 tx_fifo_partition_2;
409
-
#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
410
-
#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
411
-
#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
412
-
#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
413
-
414
-
u64 tx_fifo_partition_3;
415
-
#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
416
-
#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
417
-
#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
418
-
#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
419
-
420
-
#define TX_FIFO_PARTITION_PRI_0 0 /* highest */
421
-
#define TX_FIFO_PARTITION_PRI_1 1
422
-
#define TX_FIFO_PARTITION_PRI_2 2
423
-
#define TX_FIFO_PARTITION_PRI_3 3
424
-
#define TX_FIFO_PARTITION_PRI_4 4
425
-
#define TX_FIFO_PARTITION_PRI_5 5
426
-
#define TX_FIFO_PARTITION_PRI_6 6
427
-
#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
428
-
429
-
u64 tx_w_round_robin_0;
430
-
u64 tx_w_round_robin_1;
431
-
u64 tx_w_round_robin_2;
432
-
u64 tx_w_round_robin_3;
433
-
u64 tx_w_round_robin_4;
434
-
435
-
u64 tti_command_mem;
436
-
#define TTI_CMD_MEM_WE s2BIT(7)
437
-
#define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
438
-
#define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15)
439
-
#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
440
-
441
-
u64 tti_data1_mem;
442
-
#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
443
-
#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
444
-
#define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38)
445
-
#define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39)
446
-
#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
447
-
#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
448
-
#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
449
-
450
-
u64 tti_data2_mem;
451
-
#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
452
-
#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
453
-
#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
454
-
#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
455
-
456
-
/* Tx Protocol assist */
457
-
u64 tx_pa_cfg;
458
-
#define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
459
-
#define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
460
-
#define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
461
-
#define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
462
-
#define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15)
463
-
464
-
/* Recent add, used only debug purposes. */
465
-
u64 pcc_enable;
466
-
467
-
u8 unused9[0x700 - 0x178];
468
-
469
-
u64 txdma_debug_ctrl;
470
-
471
-
u8 unused10[0x1800 - 0x1708];
472
-
473
-
/* RxDMA Registers */
474
-
u64 rxdma_int_status;
475
-
u64 rxdma_int_mask;
476
-
#define RXDMA_INT_RC_INT_M s2BIT(0)
477
-
#define RXDMA_INT_RPA_INT_M s2BIT(1)
478
-
#define RXDMA_INT_RDA_INT_M s2BIT(2)
479
-
#define RXDMA_INT_RTI_INT_M s2BIT(3)
480
-
481
-
u64 rda_err_reg;
482
-
#define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
483
-
#define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
484
-
#define RDA_FRM_ECC_SG_ERR s2BIT(23)
485
-
#define RDA_FRM_ECC_DB_N_AERR s2BIT(31)
486
-
#define RDA_SM1_ERR_ALARM s2BIT(38)
487
-
#define RDA_SM0_ERR_ALARM s2BIT(39)
488
-
#define RDA_MISC_ERR s2BIT(47)
489
-
#define RDA_PCIX_ERR s2BIT(55)
490
-
#define RDA_RXD_ECC_DB_SERR s2BIT(63)
491
-
u64 rda_err_mask;
492
-
u64 rda_err_alarm;
493
-
494
-
u64 rc_err_reg;
495
-
#define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
496
-
#define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
497
-
#define RC_FTC_ECC_SG_ERR s2BIT(23)
498
-
#define RC_FTC_ECC_DB_ERR s2BIT(31)
499
-
#define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
500
-
#define RC_FTC_SM_ERR_ALARM s2BIT(47)
501
-
#define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
502
-
u64 rc_err_mask;
503
-
u64 rc_err_alarm;
504
-
505
-
u64 prc_pcix_err_reg;
506
-
#define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
507
-
#define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
508
-
#define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
509
-
#define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
510
-
#define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
511
-
#define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
512
-
u64 prc_pcix_err_mask;
513
-
u64 prc_pcix_err_alarm;
514
-
515
-
u64 rpa_err_reg;
516
-
#define RPA_ECC_SG_ERR s2BIT(7)
517
-
#define RPA_ECC_DB_ERR s2BIT(15)
518
-
#define RPA_FLUSH_REQUEST s2BIT(22)
519
-
#define RPA_SM_ERR_ALARM s2BIT(23)
520
-
#define RPA_CREDIT_ERR s2BIT(31)
521
-
u64 rpa_err_mask;
522
-
u64 rpa_err_alarm;
523
-
524
-
u64 rti_err_reg;
525
-
#define RTI_ECC_SG_ERR s2BIT(7)
526
-
#define RTI_ECC_DB_ERR s2BIT(15)
527
-
#define RTI_SM_ERR_ALARM s2BIT(23)
528
-
u64 rti_err_mask;
529
-
u64 rti_err_alarm;
530
-
531
-
u8 unused11[0x100 - 0x88];
532
-
533
-
/* DMA arbiter */
534
-
u64 rx_queue_priority;
535
-
#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
536
-
#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
537
-
#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
538
-
#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
539
-
#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
540
-
#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
541
-
#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
542
-
#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
543
-
544
-
#define RX_QUEUE_PRI_0 0 /* highest */
545
-
#define RX_QUEUE_PRI_1 1
546
-
#define RX_QUEUE_PRI_2 2
547
-
#define RX_QUEUE_PRI_3 3
548
-
#define RX_QUEUE_PRI_4 4
549
-
#define RX_QUEUE_PRI_5 5
550
-
#define RX_QUEUE_PRI_6 6
551
-
#define RX_QUEUE_PRI_7 7 /* lowest */
552
-
553
-
u64 rx_w_round_robin_0;
554
-
u64 rx_w_round_robin_1;
555
-
u64 rx_w_round_robin_2;
556
-
u64 rx_w_round_robin_3;
557
-
u64 rx_w_round_robin_4;
558
-
559
-
/* Per-ring controller regs */
560
-
#define RX_MAX_RINGS 8
561
-
#if 0
562
-
#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
563
-
#define RX_MIN_RINGS_SZ 0x3F /* 63 */
564
-
#endif
565
-
u64 prc_rxd0_n[RX_MAX_RINGS];
566
-
u64 prc_ctrl_n[RX_MAX_RINGS];
567
-
#define PRC_CTRL_RC_ENABLED s2BIT(7)
568
-
#define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15))
569
-
#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
570
-
#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
571
-
#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
572
-
#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
573
-
#define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23))
574
-
#define PRC_CTRL_NO_SNOOP_DESC s2BIT(22)
575
-
#define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23)
576
-
#define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37)
577
-
#define PRC_CTRL_GROUP_READS s2BIT(38)
578
-
#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
579
-
580
-
u64 prc_alarm_action;
581
-
#define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3)
582
-
#define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7)
583
-
#define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11)
584
-
#define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15)
585
-
#define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19)
586
-
#define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23)
587
-
#define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27)
588
-
#define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31)
589
-
#define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35)
590
-
#define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39)
591
-
#define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43)
592
-
#define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47)
593
-
#define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51)
594
-
#define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55)
595
-
#define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59)
596
-
#define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63)
597
-
598
-
/* Receive traffic interrupts */
599
-
u64 rti_command_mem;
600
-
#define RTI_CMD_MEM_WE s2BIT(7)
601
-
#define RTI_CMD_MEM_STROBE s2BIT(15)
602
-
#define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
603
-
#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15)
604
-
#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
605
-
606
-
u64 rti_data1_mem;
607
-
#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
608
-
#define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38)
609
-
#define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39)
610
-
#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
611
-
#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
612
-
#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
613
-
614
-
u64 rti_data2_mem;
615
-
#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
616
-
#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
617
-
#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
618
-
#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
619
-
620
-
u64 rx_pa_cfg;
621
-
#define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
622
-
#define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2)
623
-
#define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3)
624
-
#define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6)
625
-
626
-
u64 unused_11_1;
627
-
628
-
u64 ring_bump_counter1;
629
-
u64 ring_bump_counter2;
630
-
631
-
u8 unused12[0x700 - 0x1F0];
632
-
633
-
u64 rxdma_debug_ctrl;
634
-
635
-
u8 unused13[0x2000 - 0x1f08];
636
-
637
-
/* Media Access Controller Register */
638
-
u64 mac_int_status;
639
-
u64 mac_int_mask;
640
-
#define MAC_INT_STATUS_TMAC_INT s2BIT(0)
641
-
#define MAC_INT_STATUS_RMAC_INT s2BIT(1)
642
-
643
-
u64 mac_tmac_err_reg;
644
-
#define TMAC_ECC_SG_ERR s2BIT(7)
645
-
#define TMAC_ECC_DB_ERR s2BIT(15)
646
-
#define TMAC_TX_BUF_OVRN s2BIT(23)
647
-
#define TMAC_TX_CRI_ERR s2BIT(31)
648
-
#define TMAC_TX_SM_ERR s2BIT(39)
649
-
#define TMAC_DESC_ECC_SG_ERR s2BIT(47)
650
-
#define TMAC_DESC_ECC_DB_ERR s2BIT(55)
651
-
652
-
u64 mac_tmac_err_mask;
653
-
u64 mac_tmac_err_alarm;
654
-
655
-
u64 mac_rmac_err_reg;
656
-
#define RMAC_RX_BUFF_OVRN s2BIT(0)
657
-
#define RMAC_FRM_RCVD_INT s2BIT(1)
658
-
#define RMAC_UNUSED_INT s2BIT(2)
659
-
#define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5)
660
-
#define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6)
661
-
#define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7)
662
-
#define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)
663
-
#define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9)
664
-
#define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10)
665
-
#define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11)
666
-
#define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13)
667
-
#define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14)
668
-
#define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15)
669
-
#define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16)
670
-
#define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17)
671
-
#define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18)
672
-
#define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19)
673
-
#define RMAC_LINK_STATE_CHANGE_INT s2BIT(31)
674
-
#define RMAC_RX_SM_ERR s2BIT(39)
675
-
#define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\
676
-
s2BIT(8) | s2BIT(9) | s2BIT(10)|\
677
-
s2BIT(11))
678
-
#define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\
679
-
s2BIT(16) | s2BIT(17) | s2BIT(18)|\
680
-
s2BIT(19))
681
-
u64 mac_rmac_err_mask;
682
-
u64 mac_rmac_err_alarm;
683
-
684
-
u8 unused14[0x100 - 0x40];
685
-
686
-
u64 mac_cfg;
687
-
#define MAC_CFG_TMAC_ENABLE s2BIT(0)
688
-
#define MAC_CFG_RMAC_ENABLE s2BIT(1)
689
-
#define MAC_CFG_LAN_NOT_WAN s2BIT(2)
690
-
#define MAC_CFG_TMAC_LOOPBACK s2BIT(3)
691
-
#define MAC_CFG_TMAC_APPEND_PAD s2BIT(4)
692
-
#define MAC_CFG_RMAC_STRIP_FCS s2BIT(5)
693
-
#define MAC_CFG_RMAC_STRIP_PAD s2BIT(6)
694
-
#define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7)
695
-
#define MAC_RMAC_DISCARD_PFRM s2BIT(8)
696
-
#define MAC_RMAC_BCAST_ENABLE s2BIT(9)
697
-
#define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10)
698
-
#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
699
-
700
-
u64 tmac_avg_ipg;
701
-
#define TMAC_AVG_IPG(val) vBIT(val,0,8)
702
-
703
-
u64 rmac_max_pyld_len;
704
-
#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
705
-
#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
706
-
#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
707
-
708
-
u64 rmac_err_cfg;
709
-
#define RMAC_ERR_FCS s2BIT(0)
710
-
#define RMAC_ERR_FCS_ACCEPT s2BIT(1)
711
-
#define RMAC_ERR_TOO_LONG s2BIT(1)
712
-
#define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)
713
-
#define RMAC_ERR_RUNT s2BIT(2)
714
-
#define RMAC_ERR_RUNT_ACCEPT s2BIT(2)
715
-
#define RMAC_ERR_LEN_MISMATCH s2BIT(3)
716
-
#define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3)
717
-
718
-
u64 rmac_cfg_key;
719
-
#define RMAC_CFG_KEY(val) vBIT(val,0,16)
720
-
721
-
#define S2IO_MAC_ADDR_START_OFFSET 0
722
-
723
-
#define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */
724
-
#define S2IO_HERC_MAX_MC_ADDRESSES 256
725
-
726
-
#define S2IO_XENA_MAX_MAC_ADDRESSES 16
727
-
#define S2IO_HERC_MAX_MAC_ADDRESSES 64
728
-
729
-
#define S2IO_XENA_MC_ADDR_START_OFFSET 16
730
-
#define S2IO_HERC_MC_ADDR_START_OFFSET 64
731
-
732
-
u64 rmac_addr_cmd_mem;
733
-
#define RMAC_ADDR_CMD_MEM_WE s2BIT(7)
734
-
#define RMAC_ADDR_CMD_MEM_RD 0
735
-
#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15)
736
-
#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15)
737
-
#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
738
-
739
-
u64 rmac_addr_data0_mem;
740
-
#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
741
-
#define RMAC_ADDR_DATA0_MEM_USER s2BIT(48)
742
-
743
-
u64 rmac_addr_data1_mem;
744
-
#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
745
-
746
-
u8 unused15[0x8];
747
-
748
-
/*
749
-
u64 rmac_addr_cfg;
750
-
#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
751
-
#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
752
-
#define RMAC_ADDR_BCAST_EN vBIT(0)_48
753
-
#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
754
-
*/
755
-
u64 tmac_ipg_cfg;
756
-
757
-
u64 rmac_pause_cfg;
758
-
#define RMAC_PAUSE_GEN s2BIT(0)
759
-
#define RMAC_PAUSE_GEN_ENABLE s2BIT(0)
760
-
#define RMAC_PAUSE_RX s2BIT(1)
761
-
#define RMAC_PAUSE_RX_ENABLE s2BIT(1)
762
-
#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
763
-
#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
764
-
765
-
u64 rmac_red_cfg;
766
-
767
-
u64 rmac_red_rate_q0q3;
768
-
u64 rmac_red_rate_q4q7;
769
-
770
-
u64 mac_link_util;
771
-
#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
772
-
#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
773
-
#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
774
-
#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
775
-
#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
776
-
#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
777
-
778
-
#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
779
-
MAC_RX_LINK_UTIL_DISABLE
780
-
781
-
u64 rmac_invalid_ipg;
782
-
783
-
/* rx traffic steering */
784
-
#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
785
-
u64 rts_frm_len_n[8];
786
-
787
-
u64 rts_qos_steering;
788
-
789
-
#define MAX_DIX_MAP 4
790
-
u64 rts_dix_map_n[MAX_DIX_MAP];
791
-
#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
792
-
#define RTS_DIX_MAP_SCW(val) s2BIT(val,21)
793
-
794
-
u64 rts_q_alternates;
795
-
u64 rts_default_q;
796
-
797
-
u64 rts_ctrl;
798
-
#define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2)
799
-
#define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3)
800
-
801
-
u64 rts_pn_cam_ctrl;
802
-
#define RTS_PN_CAM_CTRL_WE s2BIT(7)
803
-
#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15)
804
-
#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15)
805
-
#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
806
-
u64 rts_pn_cam_data;
807
-
#define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7)
808
-
#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
809
-
#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
810
-
811
-
u64 rts_ds_mem_ctrl;
812
-
#define RTS_DS_MEM_CTRL_WE s2BIT(7)
813
-
#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15)
814
-
#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15)
815
-
#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
816
-
u64 rts_ds_mem_data;
817
-
#define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
818
-
819
-
u8 unused16[0x700 - 0x220];
820
-
821
-
u64 mac_debug_ctrl;
822
-
#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
823
-
824
-
u8 unused17[0x2800 - 0x2708];
825
-
826
-
/* memory controller registers */
827
-
u64 mc_int_status;
828
-
#define MC_INT_STATUS_MC_INT s2BIT(0)
829
-
u64 mc_int_mask;
830
-
#define MC_INT_MASK_MC_INT s2BIT(0)
831
-
832
-
u64 mc_err_reg;
833
-
#define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14)
834
-
#define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15)
835
-
#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18)
836
-
#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20)
837
-
#define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22)
838
-
#define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23)
839
-
#define MC_ERR_REG_SM_ERR s2BIT(31)
840
-
#define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\
841
-
s2BIT(17) | s2BIT(19))
842
-
#define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\
843
-
s2BIT(13) | s2BIT(18) | s2BIT(20))
844
-
#define PLL_LOCK_N s2BIT(39)
845
-
u64 mc_err_mask;
846
-
u64 mc_err_alarm;
847
-
848
-
u8 unused18[0x100 - 0x28];
849
-
850
-
/* MC configuration */
851
-
u64 rx_queue_cfg;
852
-
#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
853
-
#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
854
-
#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
855
-
#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
856
-
#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
857
-
#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
858
-
#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
859
-
#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
860
-
861
-
u64 mc_rldram_mrs;
862
-
#define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39)
863
-
#define MC_RLDRAM_MRS_ENABLE s2BIT(47)
864
-
865
-
u64 mc_rldram_interleave;
866
-
867
-
u64 mc_pause_thresh_q0q3;
868
-
u64 mc_pause_thresh_q4q7;
869
-
870
-
u64 mc_red_thresh_q[8];
871
-
872
-
u8 unused19[0x200 - 0x168];
873
-
u64 mc_rldram_ref_per;
874
-
u8 unused20[0x220 - 0x208];
875
-
u64 mc_rldram_test_ctrl;
876
-
#define MC_RLDRAM_TEST_MODE s2BIT(47)
877
-
#define MC_RLDRAM_TEST_WRITE s2BIT(7)
878
-
#define MC_RLDRAM_TEST_GO s2BIT(15)
879
-
#define MC_RLDRAM_TEST_DONE s2BIT(23)
880
-
#define MC_RLDRAM_TEST_PASS s2BIT(31)
881
-
882
-
u8 unused21[0x240 - 0x228];
883
-
u64 mc_rldram_test_add;
884
-
u8 unused22[0x260 - 0x248];
885
-
u64 mc_rldram_test_d0;
886
-
u8 unused23[0x280 - 0x268];
887
-
u64 mc_rldram_test_d1;
888
-
u8 unused24[0x300 - 0x288];
889
-
u64 mc_rldram_test_d2;
890
-
891
-
u8 unused24_1[0x360 - 0x308];
892
-
u64 mc_rldram_ctrl;
893
-
#define MC_RLDRAM_ENABLE_ODT s2BIT(7)
894
-
895
-
u8 unused24_2[0x640 - 0x368];
896
-
u64 mc_rldram_ref_per_herc;
897
-
#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
898
-
899
-
u8 unused24_3[0x660 - 0x648];
900
-
u64 mc_rldram_mrs_herc;
901
-
902
-
u8 unused25[0x700 - 0x668];
903
-
u64 mc_debug_ctrl;
904
-
905
-
u8 unused26[0x3000 - 0x2f08];
906
-
907
-
/* XGXG */
908
-
/* XGXS control registers */
909
-
910
-
u64 xgxs_int_status;
911
-
#define XGXS_INT_STATUS_TXGXS s2BIT(0)
912
-
#define XGXS_INT_STATUS_RXGXS s2BIT(1)
913
-
u64 xgxs_int_mask;
914
-
#define XGXS_INT_MASK_TXGXS s2BIT(0)
915
-
#define XGXS_INT_MASK_RXGXS s2BIT(1)
916
-
917
-
u64 xgxs_txgxs_err_reg;
918
-
#define TXGXS_ECC_SG_ERR s2BIT(7)
919
-
#define TXGXS_ECC_DB_ERR s2BIT(15)
920
-
#define TXGXS_ESTORE_UFLOW s2BIT(31)
921
-
#define TXGXS_TX_SM_ERR s2BIT(39)
922
-
923
-
u64 xgxs_txgxs_err_mask;
924
-
u64 xgxs_txgxs_err_alarm;
925
-
926
-
u64 xgxs_rxgxs_err_reg;
927
-
#define RXGXS_ESTORE_OFLOW s2BIT(7)
928
-
#define RXGXS_RX_SM_ERR s2BIT(39)
929
-
u64 xgxs_rxgxs_err_mask;
930
-
u64 xgxs_rxgxs_err_alarm;
931
-
932
-
u8 unused27[0x100 - 0x40];
933
-
934
-
u64 xgxs_cfg;
935
-
u64 xgxs_status;
936
-
937
-
u64 xgxs_cfg_key;
938
-
u64 xgxs_efifo_cfg; /* CHANGED */
939
-
u64 rxgxs_ber_0; /* CHANGED */
940
-
u64 rxgxs_ber_1; /* CHANGED */
941
-
942
-
u64 spi_control;
943
-
#define SPI_CONTROL_KEY(key) vBIT(key,0,4)
944
-
#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
945
-
#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
946
-
#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
947
-
#define SPI_CONTROL_SEL1 s2BIT(4)
948
-
#define SPI_CONTROL_REQ s2BIT(7)
949
-
#define SPI_CONTROL_NACK s2BIT(5)
950
-
#define SPI_CONTROL_DONE s2BIT(6)
951
-
u64 spi_data;
952
-
#define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
953
-
};
954
-
955
-
#define XENA_REG_SPACE sizeof(struct XENA_dev_config)
956
-
#define XENA_EEPROM_SPACE (0x01 << 11)
957
-
958
-
#endif /* _REGS_H */
-8572
drivers/net/ethernet/neterion/s2io.c
-8572
drivers/net/ethernet/neterion/s2io.c
···
1
-
/************************************************************************
2
-
* s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3
-
* Copyright(c) 2002-2010 Exar Corp.
4
-
*
5
-
* This software may be used and distributed according to the terms of
6
-
* the GNU General Public License (GPL), incorporated herein by reference.
7
-
* Drivers based on or derived from this code fall under the GPL and must
8
-
* retain the authorship, copyright and license notice. This file is not
9
-
* a complete program and may only be used when the entire operating
10
-
* system is licensed under the GPL.
11
-
* See the file COPYING in this distribution for more information.
12
-
*
13
-
* Credits:
14
-
* Jeff Garzik : For pointing out the improper error condition
15
-
* check in the s2io_xmit routine and also some
16
-
* issues in the Tx watch dog function. Also for
17
-
* patiently answering all those innumerable
18
-
* questions regaring the 2.6 porting issues.
19
-
* Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20
-
* macros available only in 2.6 Kernel.
21
-
* Francois Romieu : For pointing out all code part that were
22
-
* deprecated and also styling related comments.
23
-
* Grant Grundler : For helping me get rid of some Architecture
24
-
* dependent code.
25
-
* Christopher Hellwig : Some more 2.6 specific issues in the driver.
26
-
*
27
-
* The module loadable parameters that are supported by the driver and a brief
28
-
* explanation of all the variables.
29
-
*
30
-
* rx_ring_num : This can be used to program the number of receive rings used
31
-
* in the driver.
32
-
* rx_ring_sz: This defines the number of receive blocks each ring can have.
33
-
* This is also an array of size 8.
34
-
* rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35
-
* values are 1, 2.
36
-
* tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37
-
* tx_fifo_len: This too is an array of 8. Each element defines the number of
38
-
* Tx descriptors that can be associated with each corresponding FIFO.
39
-
* intr_type: This defines the type of interrupt. The values can be 0(INTA),
40
-
* 2(MSI_X). Default value is '2(MSI_X)'
41
-
* lro_max_pkts: This parameter defines maximum number of packets can be
42
-
* aggregated as a single large packet
43
-
* napi: This parameter used to enable/disable NAPI (polling Rx)
44
-
* Possible values '1' for enable and '0' for disable. Default is '1'
45
-
* vlan_tag_strip: This can be used to enable or disable vlan stripping.
46
-
* Possible values '1' for enable , '0' for disable.
47
-
* Default is '2' - which means disable in promisc mode
48
-
* and enable in non-promiscuous mode.
49
-
* multiq: This parameter used to enable/disable MULTIQUEUE support.
50
-
* Possible values '1' for enable and '0' for disable. Default is '0'
51
-
************************************************************************/
52
-
53
-
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54
-
55
-
#include <linux/module.h>
56
-
#include <linux/types.h>
57
-
#include <linux/errno.h>
58
-
#include <linux/ioport.h>
59
-
#include <linux/pci.h>
60
-
#include <linux/dma-mapping.h>
61
-
#include <linux/kernel.h>
62
-
#include <linux/netdevice.h>
63
-
#include <linux/etherdevice.h>
64
-
#include <linux/mdio.h>
65
-
#include <linux/skbuff.h>
66
-
#include <linux/init.h>
67
-
#include <linux/delay.h>
68
-
#include <linux/stddef.h>
69
-
#include <linux/ioctl.h>
70
-
#include <linux/timex.h>
71
-
#include <linux/ethtool.h>
72
-
#include <linux/workqueue.h>
73
-
#include <linux/if_vlan.h>
74
-
#include <linux/ip.h>
75
-
#include <linux/tcp.h>
76
-
#include <linux/uaccess.h>
77
-
#include <linux/io.h>
78
-
#include <linux/io-64-nonatomic-lo-hi.h>
79
-
#include <linux/slab.h>
80
-
#include <linux/prefetch.h>
81
-
#include <net/tcp.h>
82
-
#include <net/checksum.h>
83
-
84
-
#include <asm/div64.h>
85
-
#include <asm/irq.h>
86
-
87
-
/* local include */
88
-
#include "s2io.h"
89
-
#include "s2io-regs.h"
90
-
91
-
#define DRV_VERSION "2.0.26.28"
92
-
93
-
/* S2io Driver name & version. */
94
-
static const char s2io_driver_name[] = "Neterion";
95
-
static const char s2io_driver_version[] = DRV_VERSION;
96
-
97
-
static const int rxd_size[2] = {32, 48};
98
-
static const int rxd_count[2] = {127, 85};
99
-
100
-
static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
101
-
{
102
-
int ret;
103
-
104
-
ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
105
-
(GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
106
-
107
-
return ret;
108
-
}
109
-
110
-
/*
111
-
* Cards with following subsystem_id have a link state indication
112
-
* problem, 600B, 600C, 600D, 640B, 640C and 640D.
113
-
* macro below identifies these cards given the subsystem_id.
114
-
*/
115
-
#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
116
-
(dev_type == XFRAME_I_DEVICE) ? \
117
-
((((subid >= 0x600B) && (subid <= 0x600D)) || \
118
-
((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
119
-
120
-
#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
121
-
ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
122
-
123
-
static inline int is_s2io_card_up(const struct s2io_nic *sp)
124
-
{
125
-
return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
126
-
}
127
-
128
-
/* Ethtool related variables and Macros. */
129
-
static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
130
-
"Register test\t(offline)",
131
-
"Eeprom test\t(offline)",
132
-
"Link test\t(online)",
133
-
"RLDRAM test\t(offline)",
134
-
"BIST Test\t(offline)"
135
-
};
136
-
137
-
static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
138
-
{"tmac_frms"},
139
-
{"tmac_data_octets"},
140
-
{"tmac_drop_frms"},
141
-
{"tmac_mcst_frms"},
142
-
{"tmac_bcst_frms"},
143
-
{"tmac_pause_ctrl_frms"},
144
-
{"tmac_ttl_octets"},
145
-
{"tmac_ucst_frms"},
146
-
{"tmac_nucst_frms"},
147
-
{"tmac_any_err_frms"},
148
-
{"tmac_ttl_less_fb_octets"},
149
-
{"tmac_vld_ip_octets"},
150
-
{"tmac_vld_ip"},
151
-
{"tmac_drop_ip"},
152
-
{"tmac_icmp"},
153
-
{"tmac_rst_tcp"},
154
-
{"tmac_tcp"},
155
-
{"tmac_udp"},
156
-
{"rmac_vld_frms"},
157
-
{"rmac_data_octets"},
158
-
{"rmac_fcs_err_frms"},
159
-
{"rmac_drop_frms"},
160
-
{"rmac_vld_mcst_frms"},
161
-
{"rmac_vld_bcst_frms"},
162
-
{"rmac_in_rng_len_err_frms"},
163
-
{"rmac_out_rng_len_err_frms"},
164
-
{"rmac_long_frms"},
165
-
{"rmac_pause_ctrl_frms"},
166
-
{"rmac_unsup_ctrl_frms"},
167
-
{"rmac_ttl_octets"},
168
-
{"rmac_accepted_ucst_frms"},
169
-
{"rmac_accepted_nucst_frms"},
170
-
{"rmac_discarded_frms"},
171
-
{"rmac_drop_events"},
172
-
{"rmac_ttl_less_fb_octets"},
173
-
{"rmac_ttl_frms"},
174
-
{"rmac_usized_frms"},
175
-
{"rmac_osized_frms"},
176
-
{"rmac_frag_frms"},
177
-
{"rmac_jabber_frms"},
178
-
{"rmac_ttl_64_frms"},
179
-
{"rmac_ttl_65_127_frms"},
180
-
{"rmac_ttl_128_255_frms"},
181
-
{"rmac_ttl_256_511_frms"},
182
-
{"rmac_ttl_512_1023_frms"},
183
-
{"rmac_ttl_1024_1518_frms"},
184
-
{"rmac_ip"},
185
-
{"rmac_ip_octets"},
186
-
{"rmac_hdr_err_ip"},
187
-
{"rmac_drop_ip"},
188
-
{"rmac_icmp"},
189
-
{"rmac_tcp"},
190
-
{"rmac_udp"},
191
-
{"rmac_err_drp_udp"},
192
-
{"rmac_xgmii_err_sym"},
193
-
{"rmac_frms_q0"},
194
-
{"rmac_frms_q1"},
195
-
{"rmac_frms_q2"},
196
-
{"rmac_frms_q3"},
197
-
{"rmac_frms_q4"},
198
-
{"rmac_frms_q5"},
199
-
{"rmac_frms_q6"},
200
-
{"rmac_frms_q7"},
201
-
{"rmac_full_q0"},
202
-
{"rmac_full_q1"},
203
-
{"rmac_full_q2"},
204
-
{"rmac_full_q3"},
205
-
{"rmac_full_q4"},
206
-
{"rmac_full_q5"},
207
-
{"rmac_full_q6"},
208
-
{"rmac_full_q7"},
209
-
{"rmac_pause_cnt"},
210
-
{"rmac_xgmii_data_err_cnt"},
211
-
{"rmac_xgmii_ctrl_err_cnt"},
212
-
{"rmac_accepted_ip"},
213
-
{"rmac_err_tcp"},
214
-
{"rd_req_cnt"},
215
-
{"new_rd_req_cnt"},
216
-
{"new_rd_req_rtry_cnt"},
217
-
{"rd_rtry_cnt"},
218
-
{"wr_rtry_rd_ack_cnt"},
219
-
{"wr_req_cnt"},
220
-
{"new_wr_req_cnt"},
221
-
{"new_wr_req_rtry_cnt"},
222
-
{"wr_rtry_cnt"},
223
-
{"wr_disc_cnt"},
224
-
{"rd_rtry_wr_ack_cnt"},
225
-
{"txp_wr_cnt"},
226
-
{"txd_rd_cnt"},
227
-
{"txd_wr_cnt"},
228
-
{"rxd_rd_cnt"},
229
-
{"rxd_wr_cnt"},
230
-
{"txf_rd_cnt"},
231
-
{"rxf_wr_cnt"}
232
-
};
233
-
234
-
static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
235
-
{"rmac_ttl_1519_4095_frms"},
236
-
{"rmac_ttl_4096_8191_frms"},
237
-
{"rmac_ttl_8192_max_frms"},
238
-
{"rmac_ttl_gt_max_frms"},
239
-
{"rmac_osized_alt_frms"},
240
-
{"rmac_jabber_alt_frms"},
241
-
{"rmac_gt_max_alt_frms"},
242
-
{"rmac_vlan_frms"},
243
-
{"rmac_len_discard"},
244
-
{"rmac_fcs_discard"},
245
-
{"rmac_pf_discard"},
246
-
{"rmac_da_discard"},
247
-
{"rmac_red_discard"},
248
-
{"rmac_rts_discard"},
249
-
{"rmac_ingm_full_discard"},
250
-
{"link_fault_cnt"}
251
-
};
252
-
253
-
static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
254
-
{"\n DRIVER STATISTICS"},
255
-
{"single_bit_ecc_errs"},
256
-
{"double_bit_ecc_errs"},
257
-
{"parity_err_cnt"},
258
-
{"serious_err_cnt"},
259
-
{"soft_reset_cnt"},
260
-
{"fifo_full_cnt"},
261
-
{"ring_0_full_cnt"},
262
-
{"ring_1_full_cnt"},
263
-
{"ring_2_full_cnt"},
264
-
{"ring_3_full_cnt"},
265
-
{"ring_4_full_cnt"},
266
-
{"ring_5_full_cnt"},
267
-
{"ring_6_full_cnt"},
268
-
{"ring_7_full_cnt"},
269
-
{"alarm_transceiver_temp_high"},
270
-
{"alarm_transceiver_temp_low"},
271
-
{"alarm_laser_bias_current_high"},
272
-
{"alarm_laser_bias_current_low"},
273
-
{"alarm_laser_output_power_high"},
274
-
{"alarm_laser_output_power_low"},
275
-
{"warn_transceiver_temp_high"},
276
-
{"warn_transceiver_temp_low"},
277
-
{"warn_laser_bias_current_high"},
278
-
{"warn_laser_bias_current_low"},
279
-
{"warn_laser_output_power_high"},
280
-
{"warn_laser_output_power_low"},
281
-
{"lro_aggregated_pkts"},
282
-
{"lro_flush_both_count"},
283
-
{"lro_out_of_sequence_pkts"},
284
-
{"lro_flush_due_to_max_pkts"},
285
-
{"lro_avg_aggr_pkts"},
286
-
{"mem_alloc_fail_cnt"},
287
-
{"pci_map_fail_cnt"},
288
-
{"watchdog_timer_cnt"},
289
-
{"mem_allocated"},
290
-
{"mem_freed"},
291
-
{"link_up_cnt"},
292
-
{"link_down_cnt"},
293
-
{"link_up_time"},
294
-
{"link_down_time"},
295
-
{"tx_tcode_buf_abort_cnt"},
296
-
{"tx_tcode_desc_abort_cnt"},
297
-
{"tx_tcode_parity_err_cnt"},
298
-
{"tx_tcode_link_loss_cnt"},
299
-
{"tx_tcode_list_proc_err_cnt"},
300
-
{"rx_tcode_parity_err_cnt"},
301
-
{"rx_tcode_abort_cnt"},
302
-
{"rx_tcode_parity_abort_cnt"},
303
-
{"rx_tcode_rda_fail_cnt"},
304
-
{"rx_tcode_unkn_prot_cnt"},
305
-
{"rx_tcode_fcs_err_cnt"},
306
-
{"rx_tcode_buf_size_err_cnt"},
307
-
{"rx_tcode_rxd_corrupt_cnt"},
308
-
{"rx_tcode_unkn_err_cnt"},
309
-
{"tda_err_cnt"},
310
-
{"pfc_err_cnt"},
311
-
{"pcc_err_cnt"},
312
-
{"tti_err_cnt"},
313
-
{"tpa_err_cnt"},
314
-
{"sm_err_cnt"},
315
-
{"lso_err_cnt"},
316
-
{"mac_tmac_err_cnt"},
317
-
{"mac_rmac_err_cnt"},
318
-
{"xgxs_txgxs_err_cnt"},
319
-
{"xgxs_rxgxs_err_cnt"},
320
-
{"rc_err_cnt"},
321
-
{"prc_pcix_err_cnt"},
322
-
{"rpa_err_cnt"},
323
-
{"rda_err_cnt"},
324
-
{"rti_err_cnt"},
325
-
{"mc_err_cnt"}
326
-
};
327
-
328
-
#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
329
-
#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
330
-
#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
331
-
332
-
#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
333
-
#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
334
-
335
-
#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
336
-
#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
337
-
338
-
#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
339
-
#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
340
-
341
-
/* copy mac addr to def_mac_addr array */
342
-
static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
343
-
{
344
-
sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
345
-
sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
346
-
sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
347
-
sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
348
-
sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
349
-
sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
350
-
}
351
-
352
-
/*
353
-
* Constants to be programmed into the Xena's registers, to configure
354
-
* the XAUI.
355
-
*/
356
-
357
-
#define END_SIGN 0x0
358
-
static const u64 herc_act_dtx_cfg[] = {
359
-
/* Set address */
360
-
0x8000051536750000ULL, 0x80000515367500E0ULL,
361
-
/* Write data */
362
-
0x8000051536750004ULL, 0x80000515367500E4ULL,
363
-
/* Set address */
364
-
0x80010515003F0000ULL, 0x80010515003F00E0ULL,
365
-
/* Write data */
366
-
0x80010515003F0004ULL, 0x80010515003F00E4ULL,
367
-
/* Set address */
368
-
0x801205150D440000ULL, 0x801205150D4400E0ULL,
369
-
/* Write data */
370
-
0x801205150D440004ULL, 0x801205150D4400E4ULL,
371
-
/* Set address */
372
-
0x80020515F2100000ULL, 0x80020515F21000E0ULL,
373
-
/* Write data */
374
-
0x80020515F2100004ULL, 0x80020515F21000E4ULL,
375
-
/* Done */
376
-
END_SIGN
377
-
};
378
-
379
-
static const u64 xena_dtx_cfg[] = {
380
-
/* Set address */
381
-
0x8000051500000000ULL, 0x80000515000000E0ULL,
382
-
/* Write data */
383
-
0x80000515D9350004ULL, 0x80000515D93500E4ULL,
384
-
/* Set address */
385
-
0x8001051500000000ULL, 0x80010515000000E0ULL,
386
-
/* Write data */
387
-
0x80010515001E0004ULL, 0x80010515001E00E4ULL,
388
-
/* Set address */
389
-
0x8002051500000000ULL, 0x80020515000000E0ULL,
390
-
/* Write data */
391
-
0x80020515F2100004ULL, 0x80020515F21000E4ULL,
392
-
END_SIGN
393
-
};
394
-
395
-
/*
396
-
* Constants for Fixing the MacAddress problem seen mostly on
397
-
* Alpha machines.
398
-
*/
399
-
static const u64 fix_mac[] = {
400
-
0x0060000000000000ULL, 0x0060600000000000ULL,
401
-
0x0040600000000000ULL, 0x0000600000000000ULL,
402
-
0x0020600000000000ULL, 0x0060600000000000ULL,
403
-
0x0020600000000000ULL, 0x0060600000000000ULL,
404
-
0x0020600000000000ULL, 0x0060600000000000ULL,
405
-
0x0020600000000000ULL, 0x0060600000000000ULL,
406
-
0x0020600000000000ULL, 0x0060600000000000ULL,
407
-
0x0020600000000000ULL, 0x0060600000000000ULL,
408
-
0x0020600000000000ULL, 0x0060600000000000ULL,
409
-
0x0020600000000000ULL, 0x0060600000000000ULL,
410
-
0x0020600000000000ULL, 0x0060600000000000ULL,
411
-
0x0020600000000000ULL, 0x0060600000000000ULL,
412
-
0x0020600000000000ULL, 0x0000600000000000ULL,
413
-
0x0040600000000000ULL, 0x0060600000000000ULL,
414
-
END_SIGN
415
-
};
416
-
417
-
MODULE_DESCRIPTION("Neterion 10GbE driver");
418
-
MODULE_LICENSE("GPL");
419
-
MODULE_VERSION(DRV_VERSION);
420
-
421
-
422
-
/* Module Loadable parameters. */
423
-
S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
424
-
S2IO_PARM_INT(rx_ring_num, 1);
425
-
S2IO_PARM_INT(multiq, 0);
426
-
S2IO_PARM_INT(rx_ring_mode, 1);
427
-
S2IO_PARM_INT(use_continuous_tx_intrs, 1);
428
-
S2IO_PARM_INT(rmac_pause_time, 0x100);
429
-
S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
430
-
S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
431
-
S2IO_PARM_INT(shared_splits, 0);
432
-
S2IO_PARM_INT(tmac_util_period, 5);
433
-
S2IO_PARM_INT(rmac_util_period, 5);
434
-
S2IO_PARM_INT(l3l4hdr_size, 128);
435
-
/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
436
-
S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
437
-
/* Frequency of Rx desc syncs expressed as power of 2 */
438
-
S2IO_PARM_INT(rxsync_frequency, 3);
439
-
/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
440
-
S2IO_PARM_INT(intr_type, 2);
441
-
/* Large receive offload feature */
442
-
443
-
/* Max pkts to be aggregated by LRO at one time. If not specified,
444
-
* aggregation happens until we hit max IP pkt size(64K)
445
-
*/
446
-
S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
447
-
S2IO_PARM_INT(indicate_max_pkts, 0);
448
-
449
-
S2IO_PARM_INT(napi, 1);
450
-
S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
451
-
452
-
static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
453
-
{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
454
-
static unsigned int rx_ring_sz[MAX_RX_RINGS] =
455
-
{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
456
-
static unsigned int rts_frm_len[MAX_RX_RINGS] =
457
-
{[0 ...(MAX_RX_RINGS - 1)] = 0 };
458
-
459
-
module_param_array(tx_fifo_len, uint, NULL, 0);
460
-
module_param_array(rx_ring_sz, uint, NULL, 0);
461
-
module_param_array(rts_frm_len, uint, NULL, 0);
462
-
463
-
/*
464
-
* S2IO device table.
465
-
* This table lists all the devices that this driver supports.
466
-
*/
467
-
static const struct pci_device_id s2io_tbl[] = {
468
-
{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
469
-
PCI_ANY_ID, PCI_ANY_ID},
470
-
{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
471
-
PCI_ANY_ID, PCI_ANY_ID},
472
-
{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
473
-
PCI_ANY_ID, PCI_ANY_ID},
474
-
{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
475
-
PCI_ANY_ID, PCI_ANY_ID},
476
-
{0,}
477
-
};
478
-
479
-
MODULE_DEVICE_TABLE(pci, s2io_tbl);
480
-
481
-
static const struct pci_error_handlers s2io_err_handler = {
482
-
.error_detected = s2io_io_error_detected,
483
-
.slot_reset = s2io_io_slot_reset,
484
-
.resume = s2io_io_resume,
485
-
};
486
-
487
-
static struct pci_driver s2io_driver = {
488
-
.name = "S2IO",
489
-
.id_table = s2io_tbl,
490
-
.probe = s2io_init_nic,
491
-
.remove = s2io_rem_nic,
492
-
.err_handler = &s2io_err_handler,
493
-
};
494
-
495
-
/* A simplifier macro used both by init and free shared_mem Fns(). */
496
-
#define TXD_MEM_PAGE_CNT(len, per_each) DIV_ROUND_UP(len, per_each)
497
-
498
-
/* netqueue manipulation helper functions */
499
-
static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
500
-
{
501
-
if (!sp->config.multiq) {
502
-
int i;
503
-
504
-
for (i = 0; i < sp->config.tx_fifo_num; i++)
505
-
sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
506
-
}
507
-
netif_tx_stop_all_queues(sp->dev);
508
-
}
509
-
510
-
static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
511
-
{
512
-
if (!sp->config.multiq)
513
-
sp->mac_control.fifos[fifo_no].queue_state =
514
-
FIFO_QUEUE_STOP;
515
-
516
-
netif_tx_stop_all_queues(sp->dev);
517
-
}
518
-
519
-
static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
520
-
{
521
-
if (!sp->config.multiq) {
522
-
int i;
523
-
524
-
for (i = 0; i < sp->config.tx_fifo_num; i++)
525
-
sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
526
-
}
527
-
netif_tx_start_all_queues(sp->dev);
528
-
}
529
-
530
-
static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
531
-
{
532
-
if (!sp->config.multiq) {
533
-
int i;
534
-
535
-
for (i = 0; i < sp->config.tx_fifo_num; i++)
536
-
sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
537
-
}
538
-
netif_tx_wake_all_queues(sp->dev);
539
-
}
540
-
541
-
static inline void s2io_wake_tx_queue(
542
-
struct fifo_info *fifo, int cnt, u8 multiq)
543
-
{
544
-
545
-
if (multiq) {
546
-
if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
547
-
netif_wake_subqueue(fifo->dev, fifo->fifo_no);
548
-
} else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
549
-
if (netif_queue_stopped(fifo->dev)) {
550
-
fifo->queue_state = FIFO_QUEUE_START;
551
-
netif_wake_queue(fifo->dev);
552
-
}
553
-
}
554
-
}
555
-
556
-
/**
557
-
* init_shared_mem - Allocation and Initialization of Memory
558
-
* @nic: Device private variable.
559
-
* Description: The function allocates all the memory areas shared
560
-
* between the NIC and the driver. This includes Tx descriptors,
561
-
* Rx descriptors and the statistics block.
562
-
*/
563
-
564
-
static int init_shared_mem(struct s2io_nic *nic)
565
-
{
566
-
u32 size;
567
-
void *tmp_v_addr, *tmp_v_addr_next;
568
-
dma_addr_t tmp_p_addr, tmp_p_addr_next;
569
-
struct RxD_block *pre_rxd_blk = NULL;
570
-
int i, j, blk_cnt;
571
-
int lst_size, lst_per_page;
572
-
struct net_device *dev = nic->dev;
573
-
unsigned long tmp;
574
-
struct buffAdd *ba;
575
-
struct config_param *config = &nic->config;
576
-
struct mac_info *mac_control = &nic->mac_control;
577
-
unsigned long long mem_allocated = 0;
578
-
579
-
/* Allocation and initialization of TXDLs in FIFOs */
580
-
size = 0;
581
-
for (i = 0; i < config->tx_fifo_num; i++) {
582
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
583
-
584
-
size += tx_cfg->fifo_len;
585
-
}
586
-
if (size > MAX_AVAILABLE_TXDS) {
587
-
DBG_PRINT(ERR_DBG,
588
-
"Too many TxDs requested: %d, max supported: %d\n",
589
-
size, MAX_AVAILABLE_TXDS);
590
-
return -EINVAL;
591
-
}
592
-
593
-
size = 0;
594
-
for (i = 0; i < config->tx_fifo_num; i++) {
595
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
596
-
597
-
size = tx_cfg->fifo_len;
598
-
/*
599
-
* Legal values are from 2 to 8192
600
-
*/
601
-
if (size < 2) {
602
-
DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
603
-
"Valid lengths are 2 through 8192\n",
604
-
i, size);
605
-
return -EINVAL;
606
-
}
607
-
}
608
-
609
-
lst_size = (sizeof(struct TxD) * config->max_txds);
610
-
lst_per_page = PAGE_SIZE / lst_size;
611
-
612
-
for (i = 0; i < config->tx_fifo_num; i++) {
613
-
struct fifo_info *fifo = &mac_control->fifos[i];
614
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
615
-
int fifo_len = tx_cfg->fifo_len;
616
-
int list_holder_size = fifo_len * sizeof(struct list_info_hold);
617
-
618
-
fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
619
-
if (!fifo->list_info) {
620
-
DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
621
-
return -ENOMEM;
622
-
}
623
-
mem_allocated += list_holder_size;
624
-
}
625
-
for (i = 0; i < config->tx_fifo_num; i++) {
626
-
int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
627
-
lst_per_page);
628
-
struct fifo_info *fifo = &mac_control->fifos[i];
629
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
630
-
631
-
fifo->tx_curr_put_info.offset = 0;
632
-
fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
633
-
fifo->tx_curr_get_info.offset = 0;
634
-
fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
635
-
fifo->fifo_no = i;
636
-
fifo->nic = nic;
637
-
fifo->max_txds = MAX_SKB_FRAGS + 2;
638
-
fifo->dev = dev;
639
-
640
-
for (j = 0; j < page_num; j++) {
641
-
int k = 0;
642
-
dma_addr_t tmp_p;
643
-
void *tmp_v;
644
-
tmp_v = dma_alloc_coherent(&nic->pdev->dev, PAGE_SIZE,
645
-
&tmp_p, GFP_KERNEL);
646
-
if (!tmp_v) {
647
-
DBG_PRINT(INFO_DBG,
648
-
"dma_alloc_coherent failed for TxDL\n");
649
-
return -ENOMEM;
650
-
}
651
-
/* If we got a zero DMA address(can happen on
652
-
* certain platforms like PPC), reallocate.
653
-
* Store virtual address of page we don't want,
654
-
* to be freed later.
655
-
*/
656
-
if (!tmp_p) {
657
-
mac_control->zerodma_virt_addr = tmp_v;
658
-
DBG_PRINT(INIT_DBG,
659
-
"%s: Zero DMA address for TxDL. "
660
-
"Virtual address %p\n",
661
-
dev->name, tmp_v);
662
-
tmp_v = dma_alloc_coherent(&nic->pdev->dev,
663
-
PAGE_SIZE, &tmp_p,
664
-
GFP_KERNEL);
665
-
if (!tmp_v) {
666
-
DBG_PRINT(INFO_DBG,
667
-
"dma_alloc_coherent failed for TxDL\n");
668
-
return -ENOMEM;
669
-
}
670
-
mem_allocated += PAGE_SIZE;
671
-
}
672
-
while (k < lst_per_page) {
673
-
int l = (j * lst_per_page) + k;
674
-
if (l == tx_cfg->fifo_len)
675
-
break;
676
-
fifo->list_info[l].list_virt_addr =
677
-
tmp_v + (k * lst_size);
678
-
fifo->list_info[l].list_phy_addr =
679
-
tmp_p + (k * lst_size);
680
-
k++;
681
-
}
682
-
}
683
-
}
684
-
685
-
for (i = 0; i < config->tx_fifo_num; i++) {
686
-
struct fifo_info *fifo = &mac_control->fifos[i];
687
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
688
-
689
-
size = tx_cfg->fifo_len;
690
-
fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
691
-
if (!fifo->ufo_in_band_v)
692
-
return -ENOMEM;
693
-
mem_allocated += (size * sizeof(u64));
694
-
}
695
-
696
-
/* Allocation and initialization of RXDs in Rings */
697
-
size = 0;
698
-
for (i = 0; i < config->rx_ring_num; i++) {
699
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
700
-
struct ring_info *ring = &mac_control->rings[i];
701
-
702
-
if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
703
-
DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
704
-
"multiple of RxDs per Block\n",
705
-
dev->name, i);
706
-
return FAILURE;
707
-
}
708
-
size += rx_cfg->num_rxd;
709
-
ring->block_count = rx_cfg->num_rxd /
710
-
(rxd_count[nic->rxd_mode] + 1);
711
-
ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
712
-
}
713
-
if (nic->rxd_mode == RXD_MODE_1)
714
-
size = (size * (sizeof(struct RxD1)));
715
-
else
716
-
size = (size * (sizeof(struct RxD3)));
717
-
718
-
for (i = 0; i < config->rx_ring_num; i++) {
719
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
720
-
struct ring_info *ring = &mac_control->rings[i];
721
-
722
-
ring->rx_curr_get_info.block_index = 0;
723
-
ring->rx_curr_get_info.offset = 0;
724
-
ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
725
-
ring->rx_curr_put_info.block_index = 0;
726
-
ring->rx_curr_put_info.offset = 0;
727
-
ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
728
-
ring->nic = nic;
729
-
ring->ring_no = i;
730
-
731
-
blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
732
-
/* Allocating all the Rx blocks */
733
-
for (j = 0; j < blk_cnt; j++) {
734
-
struct rx_block_info *rx_blocks;
735
-
int l;
736
-
737
-
rx_blocks = &ring->rx_blocks[j];
738
-
size = SIZE_OF_BLOCK; /* size is always page size */
739
-
tmp_v_addr = dma_alloc_coherent(&nic->pdev->dev, size,
740
-
&tmp_p_addr, GFP_KERNEL);
741
-
if (tmp_v_addr == NULL) {
742
-
/*
743
-
* In case of failure, free_shared_mem()
744
-
* is called, which should free any
745
-
* memory that was alloced till the
746
-
* failure happened.
747
-
*/
748
-
rx_blocks->block_virt_addr = tmp_v_addr;
749
-
return -ENOMEM;
750
-
}
751
-
mem_allocated += size;
752
-
753
-
size = sizeof(struct rxd_info) *
754
-
rxd_count[nic->rxd_mode];
755
-
rx_blocks->block_virt_addr = tmp_v_addr;
756
-
rx_blocks->block_dma_addr = tmp_p_addr;
757
-
rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
758
-
if (!rx_blocks->rxds)
759
-
return -ENOMEM;
760
-
mem_allocated += size;
761
-
for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
762
-
rx_blocks->rxds[l].virt_addr =
763
-
rx_blocks->block_virt_addr +
764
-
(rxd_size[nic->rxd_mode] * l);
765
-
rx_blocks->rxds[l].dma_addr =
766
-
rx_blocks->block_dma_addr +
767
-
(rxd_size[nic->rxd_mode] * l);
768
-
}
769
-
}
770
-
/* Interlinking all Rx Blocks */
771
-
for (j = 0; j < blk_cnt; j++) {
772
-
int next = (j + 1) % blk_cnt;
773
-
tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
774
-
tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
775
-
tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
776
-
tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
777
-
778
-
pre_rxd_blk = tmp_v_addr;
779
-
pre_rxd_blk->reserved_2_pNext_RxD_block =
780
-
(unsigned long)tmp_v_addr_next;
781
-
pre_rxd_blk->pNext_RxD_Blk_physical =
782
-
(u64)tmp_p_addr_next;
783
-
}
784
-
}
785
-
if (nic->rxd_mode == RXD_MODE_3B) {
786
-
/*
787
-
* Allocation of Storages for buffer addresses in 2BUFF mode
788
-
* and the buffers as well.
789
-
*/
790
-
for (i = 0; i < config->rx_ring_num; i++) {
791
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
792
-
struct ring_info *ring = &mac_control->rings[i];
793
-
794
-
blk_cnt = rx_cfg->num_rxd /
795
-
(rxd_count[nic->rxd_mode] + 1);
796
-
size = sizeof(struct buffAdd *) * blk_cnt;
797
-
ring->ba = kmalloc(size, GFP_KERNEL);
798
-
if (!ring->ba)
799
-
return -ENOMEM;
800
-
mem_allocated += size;
801
-
for (j = 0; j < blk_cnt; j++) {
802
-
int k = 0;
803
-
804
-
size = sizeof(struct buffAdd) *
805
-
(rxd_count[nic->rxd_mode] + 1);
806
-
ring->ba[j] = kmalloc(size, GFP_KERNEL);
807
-
if (!ring->ba[j])
808
-
return -ENOMEM;
809
-
mem_allocated += size;
810
-
while (k != rxd_count[nic->rxd_mode]) {
811
-
ba = &ring->ba[j][k];
812
-
size = BUF0_LEN + ALIGN_SIZE;
813
-
ba->ba_0_org = kmalloc(size, GFP_KERNEL);
814
-
if (!ba->ba_0_org)
815
-
return -ENOMEM;
816
-
mem_allocated += size;
817
-
tmp = (unsigned long)ba->ba_0_org;
818
-
tmp += ALIGN_SIZE;
819
-
tmp &= ~((unsigned long)ALIGN_SIZE);
820
-
ba->ba_0 = (void *)tmp;
821
-
822
-
size = BUF1_LEN + ALIGN_SIZE;
823
-
ba->ba_1_org = kmalloc(size, GFP_KERNEL);
824
-
if (!ba->ba_1_org)
825
-
return -ENOMEM;
826
-
mem_allocated += size;
827
-
tmp = (unsigned long)ba->ba_1_org;
828
-
tmp += ALIGN_SIZE;
829
-
tmp &= ~((unsigned long)ALIGN_SIZE);
830
-
ba->ba_1 = (void *)tmp;
831
-
k++;
832
-
}
833
-
}
834
-
}
835
-
}
836
-
837
-
/* Allocation and initialization of Statistics block */
838
-
size = sizeof(struct stat_block);
839
-
mac_control->stats_mem =
840
-
dma_alloc_coherent(&nic->pdev->dev, size,
841
-
&mac_control->stats_mem_phy, GFP_KERNEL);
842
-
843
-
if (!mac_control->stats_mem) {
844
-
/*
845
-
* In case of failure, free_shared_mem() is called, which
846
-
* should free any memory that was alloced till the
847
-
* failure happened.
848
-
*/
849
-
return -ENOMEM;
850
-
}
851
-
mem_allocated += size;
852
-
mac_control->stats_mem_sz = size;
853
-
854
-
tmp_v_addr = mac_control->stats_mem;
855
-
mac_control->stats_info = tmp_v_addr;
856
-
memset(tmp_v_addr, 0, size);
857
-
DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
858
-
dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
859
-
mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
860
-
return SUCCESS;
861
-
}
862
-
863
-
/**
864
-
* free_shared_mem - Free the allocated Memory
865
-
* @nic: Device private variable.
866
-
* Description: This function is to free all memory locations allocated by
867
-
* the init_shared_mem() function and return it to the kernel.
868
-
*/
869
-
870
-
static void free_shared_mem(struct s2io_nic *nic)
871
-
{
872
-
int i, j, blk_cnt, size;
873
-
void *tmp_v_addr;
874
-
dma_addr_t tmp_p_addr;
875
-
int lst_size, lst_per_page;
876
-
struct net_device *dev;
877
-
int page_num = 0;
878
-
struct config_param *config;
879
-
struct mac_info *mac_control;
880
-
struct stat_block *stats;
881
-
struct swStat *swstats;
882
-
883
-
if (!nic)
884
-
return;
885
-
886
-
dev = nic->dev;
887
-
888
-
config = &nic->config;
889
-
mac_control = &nic->mac_control;
890
-
stats = mac_control->stats_info;
891
-
swstats = &stats->sw_stat;
892
-
893
-
lst_size = sizeof(struct TxD) * config->max_txds;
894
-
lst_per_page = PAGE_SIZE / lst_size;
895
-
896
-
for (i = 0; i < config->tx_fifo_num; i++) {
897
-
struct fifo_info *fifo = &mac_control->fifos[i];
898
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
899
-
900
-
page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
901
-
for (j = 0; j < page_num; j++) {
902
-
int mem_blks = (j * lst_per_page);
903
-
struct list_info_hold *fli;
904
-
905
-
if (!fifo->list_info)
906
-
return;
907
-
908
-
fli = &fifo->list_info[mem_blks];
909
-
if (!fli->list_virt_addr)
910
-
break;
911
-
dma_free_coherent(&nic->pdev->dev, PAGE_SIZE,
912
-
fli->list_virt_addr,
913
-
fli->list_phy_addr);
914
-
swstats->mem_freed += PAGE_SIZE;
915
-
}
916
-
/* If we got a zero DMA address during allocation,
917
-
* free the page now
918
-
*/
919
-
if (mac_control->zerodma_virt_addr) {
920
-
dma_free_coherent(&nic->pdev->dev, PAGE_SIZE,
921
-
mac_control->zerodma_virt_addr,
922
-
(dma_addr_t)0);
923
-
DBG_PRINT(INIT_DBG,
924
-
"%s: Freeing TxDL with zero DMA address. "
925
-
"Virtual address %p\n",
926
-
dev->name, mac_control->zerodma_virt_addr);
927
-
swstats->mem_freed += PAGE_SIZE;
928
-
}
929
-
kfree(fifo->list_info);
930
-
swstats->mem_freed += tx_cfg->fifo_len *
931
-
sizeof(struct list_info_hold);
932
-
}
933
-
934
-
size = SIZE_OF_BLOCK;
935
-
for (i = 0; i < config->rx_ring_num; i++) {
936
-
struct ring_info *ring = &mac_control->rings[i];
937
-
938
-
blk_cnt = ring->block_count;
939
-
for (j = 0; j < blk_cnt; j++) {
940
-
tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
941
-
tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
942
-
if (tmp_v_addr == NULL)
943
-
break;
944
-
dma_free_coherent(&nic->pdev->dev, size, tmp_v_addr,
945
-
tmp_p_addr);
946
-
swstats->mem_freed += size;
947
-
kfree(ring->rx_blocks[j].rxds);
948
-
swstats->mem_freed += sizeof(struct rxd_info) *
949
-
rxd_count[nic->rxd_mode];
950
-
}
951
-
}
952
-
953
-
if (nic->rxd_mode == RXD_MODE_3B) {
954
-
/* Freeing buffer storage addresses in 2BUFF mode. */
955
-
for (i = 0; i < config->rx_ring_num; i++) {
956
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
957
-
struct ring_info *ring = &mac_control->rings[i];
958
-
959
-
blk_cnt = rx_cfg->num_rxd /
960
-
(rxd_count[nic->rxd_mode] + 1);
961
-
for (j = 0; j < blk_cnt; j++) {
962
-
int k = 0;
963
-
if (!ring->ba[j])
964
-
continue;
965
-
while (k != rxd_count[nic->rxd_mode]) {
966
-
struct buffAdd *ba = &ring->ba[j][k];
967
-
kfree(ba->ba_0_org);
968
-
swstats->mem_freed +=
969
-
BUF0_LEN + ALIGN_SIZE;
970
-
kfree(ba->ba_1_org);
971
-
swstats->mem_freed +=
972
-
BUF1_LEN + ALIGN_SIZE;
973
-
k++;
974
-
}
975
-
kfree(ring->ba[j]);
976
-
swstats->mem_freed += sizeof(struct buffAdd) *
977
-
(rxd_count[nic->rxd_mode] + 1);
978
-
}
979
-
kfree(ring->ba);
980
-
swstats->mem_freed += sizeof(struct buffAdd *) *
981
-
blk_cnt;
982
-
}
983
-
}
984
-
985
-
for (i = 0; i < nic->config.tx_fifo_num; i++) {
986
-
struct fifo_info *fifo = &mac_control->fifos[i];
987
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
988
-
989
-
if (fifo->ufo_in_band_v) {
990
-
swstats->mem_freed += tx_cfg->fifo_len *
991
-
sizeof(u64);
992
-
kfree(fifo->ufo_in_band_v);
993
-
}
994
-
}
995
-
996
-
if (mac_control->stats_mem) {
997
-
swstats->mem_freed += mac_control->stats_mem_sz;
998
-
dma_free_coherent(&nic->pdev->dev, mac_control->stats_mem_sz,
999
-
mac_control->stats_mem,
1000
-
mac_control->stats_mem_phy);
1001
-
}
1002
-
}
1003
-
1004
-
/*
1005
-
* s2io_verify_pci_mode -
1006
-
*/
1007
-
1008
-
static int s2io_verify_pci_mode(struct s2io_nic *nic)
1009
-
{
1010
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
1011
-
register u64 val64 = 0;
1012
-
int mode;
1013
-
1014
-
val64 = readq(&bar0->pci_mode);
1015
-
mode = (u8)GET_PCI_MODE(val64);
1016
-
1017
-
if (val64 & PCI_MODE_UNKNOWN_MODE)
1018
-
return -1; /* Unknown PCI mode */
1019
-
return mode;
1020
-
}
1021
-
1022
-
#define NEC_VENID 0x1033
1023
-
#define NEC_DEVID 0x0125
1024
-
static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1025
-
{
1026
-
struct pci_dev *tdev = NULL;
1027
-
for_each_pci_dev(tdev) {
1028
-
if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1029
-
if (tdev->bus == s2io_pdev->bus->parent) {
1030
-
pci_dev_put(tdev);
1031
-
return 1;
1032
-
}
1033
-
}
1034
-
}
1035
-
return 0;
1036
-
}
1037
-
1038
-
static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1039
-
/*
1040
-
* s2io_print_pci_mode -
1041
-
*/
1042
-
static int s2io_print_pci_mode(struct s2io_nic *nic)
1043
-
{
1044
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
1045
-
register u64 val64 = 0;
1046
-
int mode;
1047
-
struct config_param *config = &nic->config;
1048
-
const char *pcimode;
1049
-
1050
-
val64 = readq(&bar0->pci_mode);
1051
-
mode = (u8)GET_PCI_MODE(val64);
1052
-
1053
-
if (val64 & PCI_MODE_UNKNOWN_MODE)
1054
-
return -1; /* Unknown PCI mode */
1055
-
1056
-
config->bus_speed = bus_speed[mode];
1057
-
1058
-
if (s2io_on_nec_bridge(nic->pdev)) {
1059
-
DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1060
-
nic->dev->name);
1061
-
return mode;
1062
-
}
1063
-
1064
-
switch (mode) {
1065
-
case PCI_MODE_PCI_33:
1066
-
pcimode = "33MHz PCI bus";
1067
-
break;
1068
-
case PCI_MODE_PCI_66:
1069
-
pcimode = "66MHz PCI bus";
1070
-
break;
1071
-
case PCI_MODE_PCIX_M1_66:
1072
-
pcimode = "66MHz PCIX(M1) bus";
1073
-
break;
1074
-
case PCI_MODE_PCIX_M1_100:
1075
-
pcimode = "100MHz PCIX(M1) bus";
1076
-
break;
1077
-
case PCI_MODE_PCIX_M1_133:
1078
-
pcimode = "133MHz PCIX(M1) bus";
1079
-
break;
1080
-
case PCI_MODE_PCIX_M2_66:
1081
-
pcimode = "133MHz PCIX(M2) bus";
1082
-
break;
1083
-
case PCI_MODE_PCIX_M2_100:
1084
-
pcimode = "200MHz PCIX(M2) bus";
1085
-
break;
1086
-
case PCI_MODE_PCIX_M2_133:
1087
-
pcimode = "266MHz PCIX(M2) bus";
1088
-
break;
1089
-
default:
1090
-
pcimode = "unsupported bus!";
1091
-
mode = -1;
1092
-
}
1093
-
1094
-
DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1095
-
nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1096
-
1097
-
return mode;
1098
-
}
1099
-
1100
-
/**
1101
-
* init_tti - Initialization transmit traffic interrupt scheme
1102
-
* @nic: device private variable
1103
-
* @link: link status (UP/DOWN) used to enable/disable continuous
1104
-
* transmit interrupts
1105
-
* @may_sleep: parameter indicates if sleeping when waiting for
1106
-
* command complete
1107
-
* Description: The function configures transmit traffic interrupts
1108
-
* Return Value: SUCCESS on success and
1109
-
* '-1' on failure
1110
-
*/
1111
-
1112
-
static int init_tti(struct s2io_nic *nic, int link, bool may_sleep)
1113
-
{
1114
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
1115
-
register u64 val64 = 0;
1116
-
int i;
1117
-
struct config_param *config = &nic->config;
1118
-
1119
-
for (i = 0; i < config->tx_fifo_num; i++) {
1120
-
/*
1121
-
* TTI Initialization. Default Tx timer gets us about
1122
-
* 250 interrupts per sec. Continuous interrupts are enabled
1123
-
* by default.
1124
-
*/
1125
-
if (nic->device_type == XFRAME_II_DEVICE) {
1126
-
int count = (nic->config.bus_speed * 125)/2;
1127
-
val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1128
-
} else
1129
-
val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1130
-
1131
-
val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1132
-
TTI_DATA1_MEM_TX_URNG_B(0x10) |
1133
-
TTI_DATA1_MEM_TX_URNG_C(0x30) |
1134
-
TTI_DATA1_MEM_TX_TIMER_AC_EN;
1135
-
if (i == 0)
1136
-
if (use_continuous_tx_intrs && (link == LINK_UP))
1137
-
val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1138
-
writeq(val64, &bar0->tti_data1_mem);
1139
-
1140
-
if (nic->config.intr_type == MSI_X) {
1141
-
val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1142
-
TTI_DATA2_MEM_TX_UFC_B(0x100) |
1143
-
TTI_DATA2_MEM_TX_UFC_C(0x200) |
1144
-
TTI_DATA2_MEM_TX_UFC_D(0x300);
1145
-
} else {
1146
-
if ((nic->config.tx_steering_type ==
1147
-
TX_DEFAULT_STEERING) &&
1148
-
(config->tx_fifo_num > 1) &&
1149
-
(i >= nic->udp_fifo_idx) &&
1150
-
(i < (nic->udp_fifo_idx +
1151
-
nic->total_udp_fifos)))
1152
-
val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1153
-
TTI_DATA2_MEM_TX_UFC_B(0x80) |
1154
-
TTI_DATA2_MEM_TX_UFC_C(0x100) |
1155
-
TTI_DATA2_MEM_TX_UFC_D(0x120);
1156
-
else
1157
-
val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1158
-
TTI_DATA2_MEM_TX_UFC_B(0x20) |
1159
-
TTI_DATA2_MEM_TX_UFC_C(0x40) |
1160
-
TTI_DATA2_MEM_TX_UFC_D(0x80);
1161
-
}
1162
-
1163
-
writeq(val64, &bar0->tti_data2_mem);
1164
-
1165
-
val64 = TTI_CMD_MEM_WE |
1166
-
TTI_CMD_MEM_STROBE_NEW_CMD |
1167
-
TTI_CMD_MEM_OFFSET(i);
1168
-
writeq(val64, &bar0->tti_command_mem);
1169
-
1170
-
if (wait_for_cmd_complete(&bar0->tti_command_mem,
1171
-
TTI_CMD_MEM_STROBE_NEW_CMD,
1172
-
S2IO_BIT_RESET, may_sleep) != SUCCESS)
1173
-
return FAILURE;
1174
-
}
1175
-
1176
-
return SUCCESS;
1177
-
}
1178
-
1179
-
/**
1180
-
* init_nic - Initialization of hardware
1181
-
* @nic: device private variable
1182
-
* Description: The function sequentially configures every block
1183
-
* of the H/W from their reset values.
1184
-
* Return Value: SUCCESS on success and
1185
-
* '-1' on failure (endian settings incorrect).
1186
-
*/
1187
-
1188
-
static int init_nic(struct s2io_nic *nic)
1189
-
{
1190
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
1191
-
struct net_device *dev = nic->dev;
1192
-
register u64 val64 = 0;
1193
-
void __iomem *add;
1194
-
u32 time;
1195
-
int i, j;
1196
-
int dtx_cnt = 0;
1197
-
unsigned long long mem_share;
1198
-
int mem_size;
1199
-
struct config_param *config = &nic->config;
1200
-
struct mac_info *mac_control = &nic->mac_control;
1201
-
1202
-
/* to set the swapper controle on the card */
1203
-
if (s2io_set_swapper(nic)) {
1204
-
DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1205
-
return -EIO;
1206
-
}
1207
-
1208
-
/*
1209
-
* Herc requires EOI to be removed from reset before XGXS, so..
1210
-
*/
1211
-
if (nic->device_type & XFRAME_II_DEVICE) {
1212
-
val64 = 0xA500000000ULL;
1213
-
writeq(val64, &bar0->sw_reset);
1214
-
msleep(500);
1215
-
val64 = readq(&bar0->sw_reset);
1216
-
}
1217
-
1218
-
/* Remove XGXS from reset state */
1219
-
val64 = 0;
1220
-
writeq(val64, &bar0->sw_reset);
1221
-
msleep(500);
1222
-
val64 = readq(&bar0->sw_reset);
1223
-
1224
-
/* Ensure that it's safe to access registers by checking
1225
-
* RIC_RUNNING bit is reset. Check is valid only for XframeII.
1226
-
*/
1227
-
if (nic->device_type == XFRAME_II_DEVICE) {
1228
-
for (i = 0; i < 50; i++) {
1229
-
val64 = readq(&bar0->adapter_status);
1230
-
if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1231
-
break;
1232
-
msleep(10);
1233
-
}
1234
-
if (i == 50)
1235
-
return -ENODEV;
1236
-
}
1237
-
1238
-
/* Enable Receiving broadcasts */
1239
-
add = &bar0->mac_cfg;
1240
-
val64 = readq(&bar0->mac_cfg);
1241
-
val64 |= MAC_RMAC_BCAST_ENABLE;
1242
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1243
-
writel((u32)val64, add);
1244
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1245
-
writel((u32) (val64 >> 32), (add + 4));
1246
-
1247
-
/* Read registers in all blocks */
1248
-
val64 = readq(&bar0->mac_int_mask);
1249
-
val64 = readq(&bar0->mc_int_mask);
1250
-
val64 = readq(&bar0->xgxs_int_mask);
1251
-
1252
-
/* Set MTU */
1253
-
val64 = dev->mtu;
1254
-
writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1255
-
1256
-
if (nic->device_type & XFRAME_II_DEVICE) {
1257
-
while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1258
-
SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1259
-
&bar0->dtx_control, UF);
1260
-
if (dtx_cnt & 0x1)
1261
-
msleep(1); /* Necessary!! */
1262
-
dtx_cnt++;
1263
-
}
1264
-
} else {
1265
-
while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1266
-
SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1267
-
&bar0->dtx_control, UF);
1268
-
val64 = readq(&bar0->dtx_control);
1269
-
dtx_cnt++;
1270
-
}
1271
-
}
1272
-
1273
-
/* Tx DMA Initialization */
1274
-
val64 = 0;
1275
-
writeq(val64, &bar0->tx_fifo_partition_0);
1276
-
writeq(val64, &bar0->tx_fifo_partition_1);
1277
-
writeq(val64, &bar0->tx_fifo_partition_2);
1278
-
writeq(val64, &bar0->tx_fifo_partition_3);
1279
-
1280
-
for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1281
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1282
-
1283
-
val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1284
-
vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1285
-
1286
-
if (i == (config->tx_fifo_num - 1)) {
1287
-
if (i % 2 == 0)
1288
-
i++;
1289
-
}
1290
-
1291
-
switch (i) {
1292
-
case 1:
1293
-
writeq(val64, &bar0->tx_fifo_partition_0);
1294
-
val64 = 0;
1295
-
j = 0;
1296
-
break;
1297
-
case 3:
1298
-
writeq(val64, &bar0->tx_fifo_partition_1);
1299
-
val64 = 0;
1300
-
j = 0;
1301
-
break;
1302
-
case 5:
1303
-
writeq(val64, &bar0->tx_fifo_partition_2);
1304
-
val64 = 0;
1305
-
j = 0;
1306
-
break;
1307
-
case 7:
1308
-
writeq(val64, &bar0->tx_fifo_partition_3);
1309
-
val64 = 0;
1310
-
j = 0;
1311
-
break;
1312
-
default:
1313
-
j++;
1314
-
break;
1315
-
}
1316
-
}
1317
-
1318
-
/*
1319
-
* Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1320
-
* SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1321
-
*/
1322
-
if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1323
-
writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1324
-
1325
-
val64 = readq(&bar0->tx_fifo_partition_0);
1326
-
DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1327
-
&bar0->tx_fifo_partition_0, (unsigned long long)val64);
1328
-
1329
-
/*
1330
-
* Initialization of Tx_PA_CONFIG register to ignore packet
1331
-
* integrity checking.
1332
-
*/
1333
-
val64 = readq(&bar0->tx_pa_cfg);
1334
-
val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1335
-
TX_PA_CFG_IGNORE_SNAP_OUI |
1336
-
TX_PA_CFG_IGNORE_LLC_CTRL |
1337
-
TX_PA_CFG_IGNORE_L2_ERR;
1338
-
writeq(val64, &bar0->tx_pa_cfg);
1339
-
1340
-
/* Rx DMA initialization. */
1341
-
val64 = 0;
1342
-
for (i = 0; i < config->rx_ring_num; i++) {
1343
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1344
-
1345
-
val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1346
-
}
1347
-
writeq(val64, &bar0->rx_queue_priority);
1348
-
1349
-
/*
1350
-
* Allocating equal share of memory to all the
1351
-
* configured Rings.
1352
-
*/
1353
-
val64 = 0;
1354
-
if (nic->device_type & XFRAME_II_DEVICE)
1355
-
mem_size = 32;
1356
-
else
1357
-
mem_size = 64;
1358
-
1359
-
for (i = 0; i < config->rx_ring_num; i++) {
1360
-
switch (i) {
1361
-
case 0:
1362
-
mem_share = (mem_size / config->rx_ring_num +
1363
-
mem_size % config->rx_ring_num);
1364
-
val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1365
-
continue;
1366
-
case 1:
1367
-
mem_share = (mem_size / config->rx_ring_num);
1368
-
val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1369
-
continue;
1370
-
case 2:
1371
-
mem_share = (mem_size / config->rx_ring_num);
1372
-
val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1373
-
continue;
1374
-
case 3:
1375
-
mem_share = (mem_size / config->rx_ring_num);
1376
-
val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1377
-
continue;
1378
-
case 4:
1379
-
mem_share = (mem_size / config->rx_ring_num);
1380
-
val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1381
-
continue;
1382
-
case 5:
1383
-
mem_share = (mem_size / config->rx_ring_num);
1384
-
val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1385
-
continue;
1386
-
case 6:
1387
-
mem_share = (mem_size / config->rx_ring_num);
1388
-
val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1389
-
continue;
1390
-
case 7:
1391
-
mem_share = (mem_size / config->rx_ring_num);
1392
-
val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1393
-
continue;
1394
-
}
1395
-
}
1396
-
writeq(val64, &bar0->rx_queue_cfg);
1397
-
1398
-
/*
1399
-
* Filling Tx round robin registers
1400
-
* as per the number of FIFOs for equal scheduling priority
1401
-
*/
1402
-
switch (config->tx_fifo_num) {
1403
-
case 1:
1404
-
val64 = 0x0;
1405
-
writeq(val64, &bar0->tx_w_round_robin_0);
1406
-
writeq(val64, &bar0->tx_w_round_robin_1);
1407
-
writeq(val64, &bar0->tx_w_round_robin_2);
1408
-
writeq(val64, &bar0->tx_w_round_robin_3);
1409
-
writeq(val64, &bar0->tx_w_round_robin_4);
1410
-
break;
1411
-
case 2:
1412
-
val64 = 0x0001000100010001ULL;
1413
-
writeq(val64, &bar0->tx_w_round_robin_0);
1414
-
writeq(val64, &bar0->tx_w_round_robin_1);
1415
-
writeq(val64, &bar0->tx_w_round_robin_2);
1416
-
writeq(val64, &bar0->tx_w_round_robin_3);
1417
-
val64 = 0x0001000100000000ULL;
1418
-
writeq(val64, &bar0->tx_w_round_robin_4);
1419
-
break;
1420
-
case 3:
1421
-
val64 = 0x0001020001020001ULL;
1422
-
writeq(val64, &bar0->tx_w_round_robin_0);
1423
-
val64 = 0x0200010200010200ULL;
1424
-
writeq(val64, &bar0->tx_w_round_robin_1);
1425
-
val64 = 0x0102000102000102ULL;
1426
-
writeq(val64, &bar0->tx_w_round_robin_2);
1427
-
val64 = 0x0001020001020001ULL;
1428
-
writeq(val64, &bar0->tx_w_round_robin_3);
1429
-
val64 = 0x0200010200000000ULL;
1430
-
writeq(val64, &bar0->tx_w_round_robin_4);
1431
-
break;
1432
-
case 4:
1433
-
val64 = 0x0001020300010203ULL;
1434
-
writeq(val64, &bar0->tx_w_round_robin_0);
1435
-
writeq(val64, &bar0->tx_w_round_robin_1);
1436
-
writeq(val64, &bar0->tx_w_round_robin_2);
1437
-
writeq(val64, &bar0->tx_w_round_robin_3);
1438
-
val64 = 0x0001020300000000ULL;
1439
-
writeq(val64, &bar0->tx_w_round_robin_4);
1440
-
break;
1441
-
case 5:
1442
-
val64 = 0x0001020304000102ULL;
1443
-
writeq(val64, &bar0->tx_w_round_robin_0);
1444
-
val64 = 0x0304000102030400ULL;
1445
-
writeq(val64, &bar0->tx_w_round_robin_1);
1446
-
val64 = 0x0102030400010203ULL;
1447
-
writeq(val64, &bar0->tx_w_round_robin_2);
1448
-
val64 = 0x0400010203040001ULL;
1449
-
writeq(val64, &bar0->tx_w_round_robin_3);
1450
-
val64 = 0x0203040000000000ULL;
1451
-
writeq(val64, &bar0->tx_w_round_robin_4);
1452
-
break;
1453
-
case 6:
1454
-
val64 = 0x0001020304050001ULL;
1455
-
writeq(val64, &bar0->tx_w_round_robin_0);
1456
-
val64 = 0x0203040500010203ULL;
1457
-
writeq(val64, &bar0->tx_w_round_robin_1);
1458
-
val64 = 0x0405000102030405ULL;
1459
-
writeq(val64, &bar0->tx_w_round_robin_2);
1460
-
val64 = 0x0001020304050001ULL;
1461
-
writeq(val64, &bar0->tx_w_round_robin_3);
1462
-
val64 = 0x0203040500000000ULL;
1463
-
writeq(val64, &bar0->tx_w_round_robin_4);
1464
-
break;
1465
-
case 7:
1466
-
val64 = 0x0001020304050600ULL;
1467
-
writeq(val64, &bar0->tx_w_round_robin_0);
1468
-
val64 = 0x0102030405060001ULL;
1469
-
writeq(val64, &bar0->tx_w_round_robin_1);
1470
-
val64 = 0x0203040506000102ULL;
1471
-
writeq(val64, &bar0->tx_w_round_robin_2);
1472
-
val64 = 0x0304050600010203ULL;
1473
-
writeq(val64, &bar0->tx_w_round_robin_3);
1474
-
val64 = 0x0405060000000000ULL;
1475
-
writeq(val64, &bar0->tx_w_round_robin_4);
1476
-
break;
1477
-
case 8:
1478
-
val64 = 0x0001020304050607ULL;
1479
-
writeq(val64, &bar0->tx_w_round_robin_0);
1480
-
writeq(val64, &bar0->tx_w_round_robin_1);
1481
-
writeq(val64, &bar0->tx_w_round_robin_2);
1482
-
writeq(val64, &bar0->tx_w_round_robin_3);
1483
-
val64 = 0x0001020300000000ULL;
1484
-
writeq(val64, &bar0->tx_w_round_robin_4);
1485
-
break;
1486
-
}
1487
-
1488
-
/* Enable all configured Tx FIFO partitions */
1489
-
val64 = readq(&bar0->tx_fifo_partition_0);
1490
-
val64 |= (TX_FIFO_PARTITION_EN);
1491
-
writeq(val64, &bar0->tx_fifo_partition_0);
1492
-
1493
-
/* Filling the Rx round robin registers as per the
1494
-
* number of Rings and steering based on QoS with
1495
-
* equal priority.
1496
-
*/
1497
-
switch (config->rx_ring_num) {
1498
-
case 1:
1499
-
val64 = 0x0;
1500
-
writeq(val64, &bar0->rx_w_round_robin_0);
1501
-
writeq(val64, &bar0->rx_w_round_robin_1);
1502
-
writeq(val64, &bar0->rx_w_round_robin_2);
1503
-
writeq(val64, &bar0->rx_w_round_robin_3);
1504
-
writeq(val64, &bar0->rx_w_round_robin_4);
1505
-
1506
-
val64 = 0x8080808080808080ULL;
1507
-
writeq(val64, &bar0->rts_qos_steering);
1508
-
break;
1509
-
case 2:
1510
-
val64 = 0x0001000100010001ULL;
1511
-
writeq(val64, &bar0->rx_w_round_robin_0);
1512
-
writeq(val64, &bar0->rx_w_round_robin_1);
1513
-
writeq(val64, &bar0->rx_w_round_robin_2);
1514
-
writeq(val64, &bar0->rx_w_round_robin_3);
1515
-
val64 = 0x0001000100000000ULL;
1516
-
writeq(val64, &bar0->rx_w_round_robin_4);
1517
-
1518
-
val64 = 0x8080808040404040ULL;
1519
-
writeq(val64, &bar0->rts_qos_steering);
1520
-
break;
1521
-
case 3:
1522
-
val64 = 0x0001020001020001ULL;
1523
-
writeq(val64, &bar0->rx_w_round_robin_0);
1524
-
val64 = 0x0200010200010200ULL;
1525
-
writeq(val64, &bar0->rx_w_round_robin_1);
1526
-
val64 = 0x0102000102000102ULL;
1527
-
writeq(val64, &bar0->rx_w_round_robin_2);
1528
-
val64 = 0x0001020001020001ULL;
1529
-
writeq(val64, &bar0->rx_w_round_robin_3);
1530
-
val64 = 0x0200010200000000ULL;
1531
-
writeq(val64, &bar0->rx_w_round_robin_4);
1532
-
1533
-
val64 = 0x8080804040402020ULL;
1534
-
writeq(val64, &bar0->rts_qos_steering);
1535
-
break;
1536
-
case 4:
1537
-
val64 = 0x0001020300010203ULL;
1538
-
writeq(val64, &bar0->rx_w_round_robin_0);
1539
-
writeq(val64, &bar0->rx_w_round_robin_1);
1540
-
writeq(val64, &bar0->rx_w_round_robin_2);
1541
-
writeq(val64, &bar0->rx_w_round_robin_3);
1542
-
val64 = 0x0001020300000000ULL;
1543
-
writeq(val64, &bar0->rx_w_round_robin_4);
1544
-
1545
-
val64 = 0x8080404020201010ULL;
1546
-
writeq(val64, &bar0->rts_qos_steering);
1547
-
break;
1548
-
case 5:
1549
-
val64 = 0x0001020304000102ULL;
1550
-
writeq(val64, &bar0->rx_w_round_robin_0);
1551
-
val64 = 0x0304000102030400ULL;
1552
-
writeq(val64, &bar0->rx_w_round_robin_1);
1553
-
val64 = 0x0102030400010203ULL;
1554
-
writeq(val64, &bar0->rx_w_round_robin_2);
1555
-
val64 = 0x0400010203040001ULL;
1556
-
writeq(val64, &bar0->rx_w_round_robin_3);
1557
-
val64 = 0x0203040000000000ULL;
1558
-
writeq(val64, &bar0->rx_w_round_robin_4);
1559
-
1560
-
val64 = 0x8080404020201008ULL;
1561
-
writeq(val64, &bar0->rts_qos_steering);
1562
-
break;
1563
-
case 6:
1564
-
val64 = 0x0001020304050001ULL;
1565
-
writeq(val64, &bar0->rx_w_round_robin_0);
1566
-
val64 = 0x0203040500010203ULL;
1567
-
writeq(val64, &bar0->rx_w_round_robin_1);
1568
-
val64 = 0x0405000102030405ULL;
1569
-
writeq(val64, &bar0->rx_w_round_robin_2);
1570
-
val64 = 0x0001020304050001ULL;
1571
-
writeq(val64, &bar0->rx_w_round_robin_3);
1572
-
val64 = 0x0203040500000000ULL;
1573
-
writeq(val64, &bar0->rx_w_round_robin_4);
1574
-
1575
-
val64 = 0x8080404020100804ULL;
1576
-
writeq(val64, &bar0->rts_qos_steering);
1577
-
break;
1578
-
case 7:
1579
-
val64 = 0x0001020304050600ULL;
1580
-
writeq(val64, &bar0->rx_w_round_robin_0);
1581
-
val64 = 0x0102030405060001ULL;
1582
-
writeq(val64, &bar0->rx_w_round_robin_1);
1583
-
val64 = 0x0203040506000102ULL;
1584
-
writeq(val64, &bar0->rx_w_round_robin_2);
1585
-
val64 = 0x0304050600010203ULL;
1586
-
writeq(val64, &bar0->rx_w_round_robin_3);
1587
-
val64 = 0x0405060000000000ULL;
1588
-
writeq(val64, &bar0->rx_w_round_robin_4);
1589
-
1590
-
val64 = 0x8080402010080402ULL;
1591
-
writeq(val64, &bar0->rts_qos_steering);
1592
-
break;
1593
-
case 8:
1594
-
val64 = 0x0001020304050607ULL;
1595
-
writeq(val64, &bar0->rx_w_round_robin_0);
1596
-
writeq(val64, &bar0->rx_w_round_robin_1);
1597
-
writeq(val64, &bar0->rx_w_round_robin_2);
1598
-
writeq(val64, &bar0->rx_w_round_robin_3);
1599
-
val64 = 0x0001020300000000ULL;
1600
-
writeq(val64, &bar0->rx_w_round_robin_4);
1601
-
1602
-
val64 = 0x8040201008040201ULL;
1603
-
writeq(val64, &bar0->rts_qos_steering);
1604
-
break;
1605
-
}
1606
-
1607
-
/* UDP Fix */
1608
-
val64 = 0;
1609
-
for (i = 0; i < 8; i++)
1610
-
writeq(val64, &bar0->rts_frm_len_n[i]);
1611
-
1612
-
/* Set the default rts frame length for the rings configured */
1613
-
val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1614
-
for (i = 0 ; i < config->rx_ring_num ; i++)
1615
-
writeq(val64, &bar0->rts_frm_len_n[i]);
1616
-
1617
-
/* Set the frame length for the configured rings
1618
-
* desired by the user
1619
-
*/
1620
-
for (i = 0; i < config->rx_ring_num; i++) {
1621
-
/* If rts_frm_len[i] == 0 then it is assumed that user not
1622
-
* specified frame length steering.
1623
-
* If the user provides the frame length then program
1624
-
* the rts_frm_len register for those values or else
1625
-
* leave it as it is.
1626
-
*/
1627
-
if (rts_frm_len[i] != 0) {
1628
-
writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1629
-
&bar0->rts_frm_len_n[i]);
1630
-
}
1631
-
}
1632
-
1633
-
/* Disable differentiated services steering logic */
1634
-
for (i = 0; i < 64; i++) {
1635
-
if (rts_ds_steer(nic, i, 0) == FAILURE) {
1636
-
DBG_PRINT(ERR_DBG,
1637
-
"%s: rts_ds_steer failed on codepoint %d\n",
1638
-
dev->name, i);
1639
-
return -ENODEV;
1640
-
}
1641
-
}
1642
-
1643
-
/* Program statistics memory */
1644
-
writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1645
-
1646
-
if (nic->device_type == XFRAME_II_DEVICE) {
1647
-
val64 = STAT_BC(0x320);
1648
-
writeq(val64, &bar0->stat_byte_cnt);
1649
-
}
1650
-
1651
-
/*
1652
-
* Initializing the sampling rate for the device to calculate the
1653
-
* bandwidth utilization.
1654
-
*/
1655
-
val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1656
-
MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1657
-
writeq(val64, &bar0->mac_link_util);
1658
-
1659
-
/*
1660
-
* Initializing the Transmit and Receive Traffic Interrupt
1661
-
* Scheme.
1662
-
*/
1663
-
1664
-
/* Initialize TTI */
1665
-
if (SUCCESS != init_tti(nic, nic->last_link_state, true))
1666
-
return -ENODEV;
1667
-
1668
-
/* RTI Initialization */
1669
-
if (nic->device_type == XFRAME_II_DEVICE) {
1670
-
/*
1671
-
* Programmed to generate Apprx 500 Intrs per
1672
-
* second
1673
-
*/
1674
-
int count = (nic->config.bus_speed * 125)/4;
1675
-
val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1676
-
} else
1677
-
val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1678
-
val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1679
-
RTI_DATA1_MEM_RX_URNG_B(0x10) |
1680
-
RTI_DATA1_MEM_RX_URNG_C(0x30) |
1681
-
RTI_DATA1_MEM_RX_TIMER_AC_EN;
1682
-
1683
-
writeq(val64, &bar0->rti_data1_mem);
1684
-
1685
-
val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1686
-
RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1687
-
if (nic->config.intr_type == MSI_X)
1688
-
val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1689
-
RTI_DATA2_MEM_RX_UFC_D(0x40));
1690
-
else
1691
-
val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1692
-
RTI_DATA2_MEM_RX_UFC_D(0x80));
1693
-
writeq(val64, &bar0->rti_data2_mem);
1694
-
1695
-
for (i = 0; i < config->rx_ring_num; i++) {
1696
-
val64 = RTI_CMD_MEM_WE |
1697
-
RTI_CMD_MEM_STROBE_NEW_CMD |
1698
-
RTI_CMD_MEM_OFFSET(i);
1699
-
writeq(val64, &bar0->rti_command_mem);
1700
-
1701
-
/*
1702
-
* Once the operation completes, the Strobe bit of the
1703
-
* command register will be reset. We poll for this
1704
-
* particular condition. We wait for a maximum of 500ms
1705
-
* for the operation to complete, if it's not complete
1706
-
* by then we return error.
1707
-
*/
1708
-
time = 0;
1709
-
while (true) {
1710
-
val64 = readq(&bar0->rti_command_mem);
1711
-
if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1712
-
break;
1713
-
1714
-
if (time > 10) {
1715
-
DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1716
-
dev->name);
1717
-
return -ENODEV;
1718
-
}
1719
-
time++;
1720
-
msleep(50);
1721
-
}
1722
-
}
1723
-
1724
-
/*
1725
-
* Initializing proper values as Pause threshold into all
1726
-
* the 8 Queues on Rx side.
1727
-
*/
1728
-
writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1729
-
writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1730
-
1731
-
/* Disable RMAC PAD STRIPPING */
1732
-
add = &bar0->mac_cfg;
1733
-
val64 = readq(&bar0->mac_cfg);
1734
-
val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1735
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1736
-
writel((u32) (val64), add);
1737
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1738
-
writel((u32) (val64 >> 32), (add + 4));
1739
-
val64 = readq(&bar0->mac_cfg);
1740
-
1741
-
/* Enable FCS stripping by adapter */
1742
-
add = &bar0->mac_cfg;
1743
-
val64 = readq(&bar0->mac_cfg);
1744
-
val64 |= MAC_CFG_RMAC_STRIP_FCS;
1745
-
if (nic->device_type == XFRAME_II_DEVICE)
1746
-
writeq(val64, &bar0->mac_cfg);
1747
-
else {
1748
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1749
-
writel((u32) (val64), add);
1750
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1751
-
writel((u32) (val64 >> 32), (add + 4));
1752
-
}
1753
-
1754
-
/*
1755
-
* Set the time value to be inserted in the pause frame
1756
-
* generated by xena.
1757
-
*/
1758
-
val64 = readq(&bar0->rmac_pause_cfg);
1759
-
val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1760
-
val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1761
-
writeq(val64, &bar0->rmac_pause_cfg);
1762
-
1763
-
/*
1764
-
* Set the Threshold Limit for Generating the pause frame
1765
-
* If the amount of data in any Queue exceeds ratio of
1766
-
* (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1767
-
* pause frame is generated
1768
-
*/
1769
-
val64 = 0;
1770
-
for (i = 0; i < 4; i++) {
1771
-
val64 |= (((u64)0xFF00 |
1772
-
nic->mac_control.mc_pause_threshold_q0q3)
1773
-
<< (i * 2 * 8));
1774
-
}
1775
-
writeq(val64, &bar0->mc_pause_thresh_q0q3);
1776
-
1777
-
val64 = 0;
1778
-
for (i = 0; i < 4; i++) {
1779
-
val64 |= (((u64)0xFF00 |
1780
-
nic->mac_control.mc_pause_threshold_q4q7)
1781
-
<< (i * 2 * 8));
1782
-
}
1783
-
writeq(val64, &bar0->mc_pause_thresh_q4q7);
1784
-
1785
-
/*
1786
-
* TxDMA will stop Read request if the number of read split has
1787
-
* exceeded the limit pointed by shared_splits
1788
-
*/
1789
-
val64 = readq(&bar0->pic_control);
1790
-
val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1791
-
writeq(val64, &bar0->pic_control);
1792
-
1793
-
if (nic->config.bus_speed == 266) {
1794
-
writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1795
-
writeq(0x0, &bar0->read_retry_delay);
1796
-
writeq(0x0, &bar0->write_retry_delay);
1797
-
}
1798
-
1799
-
/*
1800
-
* Programming the Herc to split every write transaction
1801
-
* that does not start on an ADB to reduce disconnects.
1802
-
*/
1803
-
if (nic->device_type == XFRAME_II_DEVICE) {
1804
-
val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1805
-
MISC_LINK_STABILITY_PRD(3);
1806
-
writeq(val64, &bar0->misc_control);
1807
-
val64 = readq(&bar0->pic_control2);
1808
-
val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1809
-
writeq(val64, &bar0->pic_control2);
1810
-
}
1811
-
if (strstr(nic->product_name, "CX4")) {
1812
-
val64 = TMAC_AVG_IPG(0x17);
1813
-
writeq(val64, &bar0->tmac_avg_ipg);
1814
-
}
1815
-
1816
-
return SUCCESS;
1817
-
}
1818
-
#define LINK_UP_DOWN_INTERRUPT 1
1819
-
#define MAC_RMAC_ERR_TIMER 2
1820
-
1821
-
static int s2io_link_fault_indication(struct s2io_nic *nic)
1822
-
{
1823
-
if (nic->device_type == XFRAME_II_DEVICE)
1824
-
return LINK_UP_DOWN_INTERRUPT;
1825
-
else
1826
-
return MAC_RMAC_ERR_TIMER;
1827
-
}
1828
-
1829
-
/**
1830
-
* do_s2io_write_bits - update alarm bits in alarm register
1831
-
* @value: alarm bits
1832
-
* @flag: interrupt status
1833
-
* @addr: address value
1834
-
* Description: update alarm bits in alarm register
1835
-
* Return Value:
1836
-
* NONE.
1837
-
*/
1838
-
static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1839
-
{
1840
-
u64 temp64;
1841
-
1842
-
temp64 = readq(addr);
1843
-
1844
-
if (flag == ENABLE_INTRS)
1845
-
temp64 &= ~((u64)value);
1846
-
else
1847
-
temp64 |= ((u64)value);
1848
-
writeq(temp64, addr);
1849
-
}
1850
-
1851
-
static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1852
-
{
1853
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
1854
-
register u64 gen_int_mask = 0;
1855
-
u64 interruptible;
1856
-
1857
-
writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1858
-
if (mask & TX_DMA_INTR) {
1859
-
gen_int_mask |= TXDMA_INT_M;
1860
-
1861
-
do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1862
-
TXDMA_PCC_INT | TXDMA_TTI_INT |
1863
-
TXDMA_LSO_INT | TXDMA_TPA_INT |
1864
-
TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1865
-
1866
-
do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1867
-
PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1868
-
PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1869
-
&bar0->pfc_err_mask);
1870
-
1871
-
do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1872
-
TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1873
-
TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1874
-
1875
-
do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1876
-
PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1877
-
PCC_N_SERR | PCC_6_COF_OV_ERR |
1878
-
PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1879
-
PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1880
-
PCC_TXB_ECC_SG_ERR,
1881
-
flag, &bar0->pcc_err_mask);
1882
-
1883
-
do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1884
-
TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1885
-
1886
-
do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1887
-
LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1888
-
LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1889
-
flag, &bar0->lso_err_mask);
1890
-
1891
-
do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1892
-
flag, &bar0->tpa_err_mask);
1893
-
1894
-
do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1895
-
}
1896
-
1897
-
if (mask & TX_MAC_INTR) {
1898
-
gen_int_mask |= TXMAC_INT_M;
1899
-
do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1900
-
&bar0->mac_int_mask);
1901
-
do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1902
-
TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1903
-
TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1904
-
flag, &bar0->mac_tmac_err_mask);
1905
-
}
1906
-
1907
-
if (mask & TX_XGXS_INTR) {
1908
-
gen_int_mask |= TXXGXS_INT_M;
1909
-
do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1910
-
&bar0->xgxs_int_mask);
1911
-
do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1912
-
TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1913
-
flag, &bar0->xgxs_txgxs_err_mask);
1914
-
}
1915
-
1916
-
if (mask & RX_DMA_INTR) {
1917
-
gen_int_mask |= RXDMA_INT_M;
1918
-
do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1919
-
RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1920
-
flag, &bar0->rxdma_int_mask);
1921
-
do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1922
-
RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1923
-
RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1924
-
RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1925
-
do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1926
-
PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1927
-
PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1928
-
&bar0->prc_pcix_err_mask);
1929
-
do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1930
-
RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1931
-
&bar0->rpa_err_mask);
1932
-
do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1933
-
RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1934
-
RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1935
-
RDA_FRM_ECC_SG_ERR |
1936
-
RDA_MISC_ERR|RDA_PCIX_ERR,
1937
-
flag, &bar0->rda_err_mask);
1938
-
do_s2io_write_bits(RTI_SM_ERR_ALARM |
1939
-
RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1940
-
flag, &bar0->rti_err_mask);
1941
-
}
1942
-
1943
-
if (mask & RX_MAC_INTR) {
1944
-
gen_int_mask |= RXMAC_INT_M;
1945
-
do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1946
-
&bar0->mac_int_mask);
1947
-
interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1948
-
RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1949
-
RMAC_DOUBLE_ECC_ERR);
1950
-
if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1951
-
interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1952
-
do_s2io_write_bits(interruptible,
1953
-
flag, &bar0->mac_rmac_err_mask);
1954
-
}
1955
-
1956
-
if (mask & RX_XGXS_INTR) {
1957
-
gen_int_mask |= RXXGXS_INT_M;
1958
-
do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1959
-
&bar0->xgxs_int_mask);
1960
-
do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1961
-
&bar0->xgxs_rxgxs_err_mask);
1962
-
}
1963
-
1964
-
if (mask & MC_INTR) {
1965
-
gen_int_mask |= MC_INT_M;
1966
-
do_s2io_write_bits(MC_INT_MASK_MC_INT,
1967
-
flag, &bar0->mc_int_mask);
1968
-
do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1969
-
MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1970
-
&bar0->mc_err_mask);
1971
-
}
1972
-
nic->general_int_mask = gen_int_mask;
1973
-
1974
-
/* Remove this line when alarm interrupts are enabled */
1975
-
nic->general_int_mask = 0;
1976
-
}
1977
-
1978
-
/**
1979
-
* en_dis_able_nic_intrs - Enable or Disable the interrupts
1980
-
* @nic: device private variable,
1981
-
* @mask: A mask indicating which Intr block must be modified and,
1982
-
* @flag: A flag indicating whether to enable or disable the Intrs.
1983
-
* Description: This function will either disable or enable the interrupts
1984
-
* depending on the flag argument. The mask argument can be used to
1985
-
* enable/disable any Intr block.
1986
-
* Return Value: NONE.
1987
-
*/
1988
-
1989
-
static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1990
-
{
1991
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
1992
-
register u64 temp64 = 0, intr_mask = 0;
1993
-
1994
-
intr_mask = nic->general_int_mask;
1995
-
1996
-
/* Top level interrupt classification */
1997
-
/* PIC Interrupts */
1998
-
if (mask & TX_PIC_INTR) {
1999
-
/* Enable PIC Intrs in the general intr mask register */
2000
-
intr_mask |= TXPIC_INT_M;
2001
-
if (flag == ENABLE_INTRS) {
2002
-
/*
2003
-
* If Hercules adapter enable GPIO otherwise
2004
-
* disable all PCIX, Flash, MDIO, IIC and GPIO
2005
-
* interrupts for now.
2006
-
* TODO
2007
-
*/
2008
-
if (s2io_link_fault_indication(nic) ==
2009
-
LINK_UP_DOWN_INTERRUPT) {
2010
-
do_s2io_write_bits(PIC_INT_GPIO, flag,
2011
-
&bar0->pic_int_mask);
2012
-
do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2013
-
&bar0->gpio_int_mask);
2014
-
} else
2015
-
writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2016
-
} else if (flag == DISABLE_INTRS) {
2017
-
/*
2018
-
* Disable PIC Intrs in the general
2019
-
* intr mask register
2020
-
*/
2021
-
writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2022
-
}
2023
-
}
2024
-
2025
-
/* Tx traffic interrupts */
2026
-
if (mask & TX_TRAFFIC_INTR) {
2027
-
intr_mask |= TXTRAFFIC_INT_M;
2028
-
if (flag == ENABLE_INTRS) {
2029
-
/*
2030
-
* Enable all the Tx side interrupts
2031
-
* writing 0 Enables all 64 TX interrupt levels
2032
-
*/
2033
-
writeq(0x0, &bar0->tx_traffic_mask);
2034
-
} else if (flag == DISABLE_INTRS) {
2035
-
/*
2036
-
* Disable Tx Traffic Intrs in the general intr mask
2037
-
* register.
2038
-
*/
2039
-
writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2040
-
}
2041
-
}
2042
-
2043
-
/* Rx traffic interrupts */
2044
-
if (mask & RX_TRAFFIC_INTR) {
2045
-
intr_mask |= RXTRAFFIC_INT_M;
2046
-
if (flag == ENABLE_INTRS) {
2047
-
/* writing 0 Enables all 8 RX interrupt levels */
2048
-
writeq(0x0, &bar0->rx_traffic_mask);
2049
-
} else if (flag == DISABLE_INTRS) {
2050
-
/*
2051
-
* Disable Rx Traffic Intrs in the general intr mask
2052
-
* register.
2053
-
*/
2054
-
writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2055
-
}
2056
-
}
2057
-
2058
-
temp64 = readq(&bar0->general_int_mask);
2059
-
if (flag == ENABLE_INTRS)
2060
-
temp64 &= ~((u64)intr_mask);
2061
-
else
2062
-
temp64 = DISABLE_ALL_INTRS;
2063
-
writeq(temp64, &bar0->general_int_mask);
2064
-
2065
-
nic->general_int_mask = readq(&bar0->general_int_mask);
2066
-
}
2067
-
2068
-
/**
2069
-
* verify_pcc_quiescent- Checks for PCC quiescent state
2070
-
* @sp : private member of the device structure, which is a pointer to the
2071
-
* s2io_nic structure.
2072
-
* @flag: boolean controlling function path
2073
-
* Return: 1 If PCC is quiescence
2074
-
* 0 If PCC is not quiescence
2075
-
*/
2076
-
static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2077
-
{
2078
-
int ret = 0, herc;
2079
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
2080
-
u64 val64 = readq(&bar0->adapter_status);
2081
-
2082
-
herc = (sp->device_type == XFRAME_II_DEVICE);
2083
-
2084
-
if (flag == false) {
2085
-
if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2086
-
if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2087
-
ret = 1;
2088
-
} else {
2089
-
if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2090
-
ret = 1;
2091
-
}
2092
-
} else {
2093
-
if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2094
-
if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2095
-
ADAPTER_STATUS_RMAC_PCC_IDLE))
2096
-
ret = 1;
2097
-
} else {
2098
-
if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2099
-
ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2100
-
ret = 1;
2101
-
}
2102
-
}
2103
-
2104
-
return ret;
2105
-
}
2106
-
/**
2107
-
* verify_xena_quiescence - Checks whether the H/W is ready
2108
-
* @sp : private member of the device structure, which is a pointer to the
2109
-
* s2io_nic structure.
2110
-
* Description: Returns whether the H/W is ready to go or not. Depending
2111
-
* on whether adapter enable bit was written or not the comparison
2112
-
* differs and the calling function passes the input argument flag to
2113
-
* indicate this.
2114
-
* Return: 1 If xena is quiescence
2115
-
* 0 If Xena is not quiescence
2116
-
*/
2117
-
2118
-
static int verify_xena_quiescence(struct s2io_nic *sp)
2119
-
{
2120
-
int mode;
2121
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
2122
-
u64 val64 = readq(&bar0->adapter_status);
2123
-
mode = s2io_verify_pci_mode(sp);
2124
-
2125
-
if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2126
-
DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2127
-
return 0;
2128
-
}
2129
-
if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2130
-
DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2131
-
return 0;
2132
-
}
2133
-
if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2134
-
DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2135
-
return 0;
2136
-
}
2137
-
if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2138
-
DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2139
-
return 0;
2140
-
}
2141
-
if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2142
-
DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2143
-
return 0;
2144
-
}
2145
-
if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2146
-
DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2147
-
return 0;
2148
-
}
2149
-
if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2150
-
DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2151
-
return 0;
2152
-
}
2153
-
if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2154
-
DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2155
-
return 0;
2156
-
}
2157
-
2158
-
/*
2159
-
* In PCI 33 mode, the P_PLL is not used, and therefore,
2160
-
* the P_PLL_LOCK bit in the adapter_status register will
2161
-
* not be asserted.
2162
-
*/
2163
-
if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2164
-
sp->device_type == XFRAME_II_DEVICE &&
2165
-
mode != PCI_MODE_PCI_33) {
2166
-
DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2167
-
return 0;
2168
-
}
2169
-
if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2170
-
ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2171
-
DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2172
-
return 0;
2173
-
}
2174
-
return 1;
2175
-
}
2176
-
2177
-
/**
2178
-
* fix_mac_address - Fix for Mac addr problem on Alpha platforms
2179
-
* @sp: Pointer to device specifc structure
2180
-
* Description :
2181
-
* New procedure to clear mac address reading problems on Alpha platforms
2182
-
*
2183
-
*/
2184
-
2185
-
static void fix_mac_address(struct s2io_nic *sp)
2186
-
{
2187
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
2188
-
int i = 0;
2189
-
2190
-
while (fix_mac[i] != END_SIGN) {
2191
-
writeq(fix_mac[i++], &bar0->gpio_control);
2192
-
udelay(10);
2193
-
(void) readq(&bar0->gpio_control);
2194
-
}
2195
-
}
2196
-
2197
-
/**
2198
-
* start_nic - Turns the device on
2199
-
* @nic : device private variable.
2200
-
* Description:
2201
-
* This function actually turns the device on. Before this function is
2202
-
* called,all Registers are configured from their reset states
2203
-
* and shared memory is allocated but the NIC is still quiescent. On
2204
-
* calling this function, the device interrupts are cleared and the NIC is
2205
-
* literally switched on by writing into the adapter control register.
2206
-
* Return Value:
2207
-
* SUCCESS on success and -1 on failure.
2208
-
*/
2209
-
2210
-
static int start_nic(struct s2io_nic *nic)
2211
-
{
2212
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
2213
-
struct net_device *dev = nic->dev;
2214
-
register u64 val64 = 0;
2215
-
u16 subid, i;
2216
-
struct config_param *config = &nic->config;
2217
-
struct mac_info *mac_control = &nic->mac_control;
2218
-
2219
-
/* PRC Initialization and configuration */
2220
-
for (i = 0; i < config->rx_ring_num; i++) {
2221
-
struct ring_info *ring = &mac_control->rings[i];
2222
-
2223
-
writeq((u64)ring->rx_blocks[0].block_dma_addr,
2224
-
&bar0->prc_rxd0_n[i]);
2225
-
2226
-
val64 = readq(&bar0->prc_ctrl_n[i]);
2227
-
if (nic->rxd_mode == RXD_MODE_1)
2228
-
val64 |= PRC_CTRL_RC_ENABLED;
2229
-
else
2230
-
val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2231
-
if (nic->device_type == XFRAME_II_DEVICE)
2232
-
val64 |= PRC_CTRL_GROUP_READS;
2233
-
val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2234
-
val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2235
-
writeq(val64, &bar0->prc_ctrl_n[i]);
2236
-
}
2237
-
2238
-
if (nic->rxd_mode == RXD_MODE_3B) {
2239
-
/* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2240
-
val64 = readq(&bar0->rx_pa_cfg);
2241
-
val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2242
-
writeq(val64, &bar0->rx_pa_cfg);
2243
-
}
2244
-
2245
-
if (vlan_tag_strip == 0) {
2246
-
val64 = readq(&bar0->rx_pa_cfg);
2247
-
val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2248
-
writeq(val64, &bar0->rx_pa_cfg);
2249
-
nic->vlan_strip_flag = 0;
2250
-
}
2251
-
2252
-
/*
2253
-
* Enabling MC-RLDRAM. After enabling the device, we timeout
2254
-
* for around 100ms, which is approximately the time required
2255
-
* for the device to be ready for operation.
2256
-
*/
2257
-
val64 = readq(&bar0->mc_rldram_mrs);
2258
-
val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2259
-
SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2260
-
val64 = readq(&bar0->mc_rldram_mrs);
2261
-
2262
-
msleep(100); /* Delay by around 100 ms. */
2263
-
2264
-
/* Enabling ECC Protection. */
2265
-
val64 = readq(&bar0->adapter_control);
2266
-
val64 &= ~ADAPTER_ECC_EN;
2267
-
writeq(val64, &bar0->adapter_control);
2268
-
2269
-
/*
2270
-
* Verify if the device is ready to be enabled, if so enable
2271
-
* it.
2272
-
*/
2273
-
val64 = readq(&bar0->adapter_status);
2274
-
if (!verify_xena_quiescence(nic)) {
2275
-
DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2276
-
"Adapter status reads: 0x%llx\n",
2277
-
dev->name, (unsigned long long)val64);
2278
-
return FAILURE;
2279
-
}
2280
-
2281
-
/*
2282
-
* With some switches, link might be already up at this point.
2283
-
* Because of this weird behavior, when we enable laser,
2284
-
* we may not get link. We need to handle this. We cannot
2285
-
* figure out which switch is misbehaving. So we are forced to
2286
-
* make a global change.
2287
-
*/
2288
-
2289
-
/* Enabling Laser. */
2290
-
val64 = readq(&bar0->adapter_control);
2291
-
val64 |= ADAPTER_EOI_TX_ON;
2292
-
writeq(val64, &bar0->adapter_control);
2293
-
2294
-
if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2295
-
/*
2296
-
* Dont see link state interrupts initially on some switches,
2297
-
* so directly scheduling the link state task here.
2298
-
*/
2299
-
schedule_work(&nic->set_link_task);
2300
-
}
2301
-
/* SXE-002: Initialize link and activity LED */
2302
-
subid = nic->pdev->subsystem_device;
2303
-
if (((subid & 0xFF) >= 0x07) &&
2304
-
(nic->device_type == XFRAME_I_DEVICE)) {
2305
-
val64 = readq(&bar0->gpio_control);
2306
-
val64 |= 0x0000800000000000ULL;
2307
-
writeq(val64, &bar0->gpio_control);
2308
-
val64 = 0x0411040400000000ULL;
2309
-
writeq(val64, (void __iomem *)bar0 + 0x2700);
2310
-
}
2311
-
2312
-
return SUCCESS;
2313
-
}
2314
-
/**
2315
-
* s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2316
-
* @fifo_data: fifo data pointer
2317
-
* @txdlp: descriptor
2318
-
* @get_off: unused
2319
-
*/
2320
-
static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2321
-
struct TxD *txdlp, int get_off)
2322
-
{
2323
-
struct s2io_nic *nic = fifo_data->nic;
2324
-
struct sk_buff *skb;
2325
-
struct TxD *txds;
2326
-
u16 j, frg_cnt;
2327
-
2328
-
txds = txdlp;
2329
-
if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2330
-
dma_unmap_single(&nic->pdev->dev,
2331
-
(dma_addr_t)txds->Buffer_Pointer,
2332
-
sizeof(u64), DMA_TO_DEVICE);
2333
-
txds++;
2334
-
}
2335
-
2336
-
skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2337
-
if (!skb) {
2338
-
memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2339
-
return NULL;
2340
-
}
2341
-
dma_unmap_single(&nic->pdev->dev, (dma_addr_t)txds->Buffer_Pointer,
2342
-
skb_headlen(skb), DMA_TO_DEVICE);
2343
-
frg_cnt = skb_shinfo(skb)->nr_frags;
2344
-
if (frg_cnt) {
2345
-
txds++;
2346
-
for (j = 0; j < frg_cnt; j++, txds++) {
2347
-
const skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2348
-
if (!txds->Buffer_Pointer)
2349
-
break;
2350
-
dma_unmap_page(&nic->pdev->dev,
2351
-
(dma_addr_t)txds->Buffer_Pointer,
2352
-
skb_frag_size(frag), DMA_TO_DEVICE);
2353
-
}
2354
-
}
2355
-
memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2356
-
return skb;
2357
-
}
2358
-
2359
-
/**
2360
-
* free_tx_buffers - Free all queued Tx buffers
2361
-
* @nic : device private variable.
2362
-
* Description:
2363
-
* Free all queued Tx buffers.
2364
-
* Return Value: void
2365
-
*/
2366
-
2367
-
static void free_tx_buffers(struct s2io_nic *nic)
2368
-
{
2369
-
struct net_device *dev = nic->dev;
2370
-
struct sk_buff *skb;
2371
-
struct TxD *txdp;
2372
-
int i, j;
2373
-
int cnt = 0;
2374
-
struct config_param *config = &nic->config;
2375
-
struct mac_info *mac_control = &nic->mac_control;
2376
-
struct stat_block *stats = mac_control->stats_info;
2377
-
struct swStat *swstats = &stats->sw_stat;
2378
-
2379
-
for (i = 0; i < config->tx_fifo_num; i++) {
2380
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2381
-
struct fifo_info *fifo = &mac_control->fifos[i];
2382
-
unsigned long flags;
2383
-
2384
-
spin_lock_irqsave(&fifo->tx_lock, flags);
2385
-
for (j = 0; j < tx_cfg->fifo_len; j++) {
2386
-
txdp = fifo->list_info[j].list_virt_addr;
2387
-
skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2388
-
if (skb) {
2389
-
swstats->mem_freed += skb->truesize;
2390
-
dev_kfree_skb_irq(skb);
2391
-
cnt++;
2392
-
}
2393
-
}
2394
-
DBG_PRINT(INTR_DBG,
2395
-
"%s: forcibly freeing %d skbs on FIFO%d\n",
2396
-
dev->name, cnt, i);
2397
-
fifo->tx_curr_get_info.offset = 0;
2398
-
fifo->tx_curr_put_info.offset = 0;
2399
-
spin_unlock_irqrestore(&fifo->tx_lock, flags);
2400
-
}
2401
-
}
2402
-
2403
-
/**
2404
-
* stop_nic - To stop the nic
2405
-
* @nic : device private variable.
2406
-
* Description:
2407
-
* This function does exactly the opposite of what the start_nic()
2408
-
* function does. This function is called to stop the device.
2409
-
* Return Value:
2410
-
* void.
2411
-
*/
2412
-
2413
-
static void stop_nic(struct s2io_nic *nic)
2414
-
{
2415
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
2416
-
register u64 val64 = 0;
2417
-
u16 interruptible;
2418
-
2419
-
/* Disable all interrupts */
2420
-
en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2421
-
interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2422
-
interruptible |= TX_PIC_INTR;
2423
-
en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2424
-
2425
-
/* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2426
-
val64 = readq(&bar0->adapter_control);
2427
-
val64 &= ~(ADAPTER_CNTL_EN);
2428
-
writeq(val64, &bar0->adapter_control);
2429
-
}
2430
-
2431
-
/**
2432
-
* fill_rx_buffers - Allocates the Rx side skbs
2433
-
* @nic : device private variable.
2434
-
* @ring: per ring structure
2435
-
* @from_card_up: If this is true, we will map the buffer to get
2436
-
* the dma address for buf0 and buf1 to give it to the card.
2437
-
* Else we will sync the already mapped buffer to give it to the card.
2438
-
* Description:
2439
-
* The function allocates Rx side skbs and puts the physical
2440
-
* address of these buffers into the RxD buffer pointers, so that the NIC
2441
-
* can DMA the received frame into these locations.
2442
-
* The NIC supports 3 receive modes, viz
2443
-
* 1. single buffer,
2444
-
* 2. three buffer and
2445
-
* 3. Five buffer modes.
2446
-
* Each mode defines how many fragments the received frame will be split
2447
-
* up into by the NIC. The frame is split into L3 header, L4 Header,
2448
-
* L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2449
-
* is split into 3 fragments. As of now only single buffer mode is
2450
-
* supported.
2451
-
* Return Value:
2452
-
* SUCCESS on success or an appropriate -ve value on failure.
2453
-
*/
2454
-
static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2455
-
int from_card_up)
2456
-
{
2457
-
struct sk_buff *skb;
2458
-
struct RxD_t *rxdp;
2459
-
int off, size, block_no, block_no1;
2460
-
u32 alloc_tab = 0;
2461
-
u32 alloc_cnt;
2462
-
u64 tmp;
2463
-
struct buffAdd *ba;
2464
-
struct RxD_t *first_rxdp = NULL;
2465
-
u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2466
-
struct RxD1 *rxdp1;
2467
-
struct RxD3 *rxdp3;
2468
-
struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2469
-
2470
-
alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2471
-
2472
-
block_no1 = ring->rx_curr_get_info.block_index;
2473
-
while (alloc_tab < alloc_cnt) {
2474
-
block_no = ring->rx_curr_put_info.block_index;
2475
-
2476
-
off = ring->rx_curr_put_info.offset;
2477
-
2478
-
rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2479
-
2480
-
if ((block_no == block_no1) &&
2481
-
(off == ring->rx_curr_get_info.offset) &&
2482
-
(rxdp->Host_Control)) {
2483
-
DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2484
-
ring->dev->name);
2485
-
goto end;
2486
-
}
2487
-
if (off && (off == ring->rxd_count)) {
2488
-
ring->rx_curr_put_info.block_index++;
2489
-
if (ring->rx_curr_put_info.block_index ==
2490
-
ring->block_count)
2491
-
ring->rx_curr_put_info.block_index = 0;
2492
-
block_no = ring->rx_curr_put_info.block_index;
2493
-
off = 0;
2494
-
ring->rx_curr_put_info.offset = off;
2495
-
rxdp = ring->rx_blocks[block_no].block_virt_addr;
2496
-
DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2497
-
ring->dev->name, rxdp);
2498
-
2499
-
}
2500
-
2501
-
if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2502
-
((ring->rxd_mode == RXD_MODE_3B) &&
2503
-
(rxdp->Control_2 & s2BIT(0)))) {
2504
-
ring->rx_curr_put_info.offset = off;
2505
-
goto end;
2506
-
}
2507
-
/* calculate size of skb based on ring mode */
2508
-
size = ring->mtu +
2509
-
HEADER_ETHERNET_II_802_3_SIZE +
2510
-
HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2511
-
if (ring->rxd_mode == RXD_MODE_1)
2512
-
size += NET_IP_ALIGN;
2513
-
else
2514
-
size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2515
-
2516
-
/* allocate skb */
2517
-
skb = netdev_alloc_skb(nic->dev, size);
2518
-
if (!skb) {
2519
-
DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2520
-
ring->dev->name);
2521
-
if (first_rxdp) {
2522
-
dma_wmb();
2523
-
first_rxdp->Control_1 |= RXD_OWN_XENA;
2524
-
}
2525
-
swstats->mem_alloc_fail_cnt++;
2526
-
2527
-
return -ENOMEM ;
2528
-
}
2529
-
swstats->mem_allocated += skb->truesize;
2530
-
2531
-
if (ring->rxd_mode == RXD_MODE_1) {
2532
-
/* 1 buffer mode - normal operation mode */
2533
-
rxdp1 = (struct RxD1 *)rxdp;
2534
-
memset(rxdp, 0, sizeof(struct RxD1));
2535
-
skb_reserve(skb, NET_IP_ALIGN);
2536
-
rxdp1->Buffer0_ptr =
2537
-
dma_map_single(&ring->pdev->dev, skb->data,
2538
-
size - NET_IP_ALIGN,
2539
-
DMA_FROM_DEVICE);
2540
-
if (dma_mapping_error(&nic->pdev->dev, rxdp1->Buffer0_ptr))
2541
-
goto pci_map_failed;
2542
-
2543
-
rxdp->Control_2 =
2544
-
SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2545
-
rxdp->Host_Control = (unsigned long)skb;
2546
-
} else if (ring->rxd_mode == RXD_MODE_3B) {
2547
-
/*
2548
-
* 2 buffer mode -
2549
-
* 2 buffer mode provides 128
2550
-
* byte aligned receive buffers.
2551
-
*/
2552
-
2553
-
rxdp3 = (struct RxD3 *)rxdp;
2554
-
/* save buffer pointers to avoid frequent dma mapping */
2555
-
Buffer0_ptr = rxdp3->Buffer0_ptr;
2556
-
Buffer1_ptr = rxdp3->Buffer1_ptr;
2557
-
memset(rxdp, 0, sizeof(struct RxD3));
2558
-
/* restore the buffer pointers for dma sync*/
2559
-
rxdp3->Buffer0_ptr = Buffer0_ptr;
2560
-
rxdp3->Buffer1_ptr = Buffer1_ptr;
2561
-
2562
-
ba = &ring->ba[block_no][off];
2563
-
skb_reserve(skb, BUF0_LEN);
2564
-
tmp = (u64)(unsigned long)skb->data;
2565
-
tmp += ALIGN_SIZE;
2566
-
tmp &= ~ALIGN_SIZE;
2567
-
skb->data = (void *) (unsigned long)tmp;
2568
-
skb_reset_tail_pointer(skb);
2569
-
2570
-
if (from_card_up) {
2571
-
rxdp3->Buffer0_ptr =
2572
-
dma_map_single(&ring->pdev->dev,
2573
-
ba->ba_0, BUF0_LEN,
2574
-
DMA_FROM_DEVICE);
2575
-
if (dma_mapping_error(&nic->pdev->dev, rxdp3->Buffer0_ptr))
2576
-
goto pci_map_failed;
2577
-
} else
2578
-
dma_sync_single_for_device(&ring->pdev->dev,
2579
-
(dma_addr_t)rxdp3->Buffer0_ptr,
2580
-
BUF0_LEN,
2581
-
DMA_FROM_DEVICE);
2582
-
2583
-
rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2584
-
if (ring->rxd_mode == RXD_MODE_3B) {
2585
-
/* Two buffer mode */
2586
-
2587
-
/*
2588
-
* Buffer2 will have L3/L4 header plus
2589
-
* L4 payload
2590
-
*/
2591
-
rxdp3->Buffer2_ptr = dma_map_single(&ring->pdev->dev,
2592
-
skb->data,
2593
-
ring->mtu + 4,
2594
-
DMA_FROM_DEVICE);
2595
-
2596
-
if (dma_mapping_error(&nic->pdev->dev, rxdp3->Buffer2_ptr))
2597
-
goto pci_map_failed;
2598
-
2599
-
if (from_card_up) {
2600
-
rxdp3->Buffer1_ptr =
2601
-
dma_map_single(&ring->pdev->dev,
2602
-
ba->ba_1,
2603
-
BUF1_LEN,
2604
-
DMA_FROM_DEVICE);
2605
-
2606
-
if (dma_mapping_error(&nic->pdev->dev,
2607
-
rxdp3->Buffer1_ptr)) {
2608
-
dma_unmap_single(&ring->pdev->dev,
2609
-
(dma_addr_t)(unsigned long)
2610
-
skb->data,
2611
-
ring->mtu + 4,
2612
-
DMA_FROM_DEVICE);
2613
-
goto pci_map_failed;
2614
-
}
2615
-
}
2616
-
rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2617
-
rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2618
-
(ring->mtu + 4);
2619
-
}
2620
-
rxdp->Control_2 |= s2BIT(0);
2621
-
rxdp->Host_Control = (unsigned long) (skb);
2622
-
}
2623
-
if (alloc_tab & ((1 << rxsync_frequency) - 1))
2624
-
rxdp->Control_1 |= RXD_OWN_XENA;
2625
-
off++;
2626
-
if (off == (ring->rxd_count + 1))
2627
-
off = 0;
2628
-
ring->rx_curr_put_info.offset = off;
2629
-
2630
-
rxdp->Control_2 |= SET_RXD_MARKER;
2631
-
if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2632
-
if (first_rxdp) {
2633
-
dma_wmb();
2634
-
first_rxdp->Control_1 |= RXD_OWN_XENA;
2635
-
}
2636
-
first_rxdp = rxdp;
2637
-
}
2638
-
ring->rx_bufs_left += 1;
2639
-
alloc_tab++;
2640
-
}
2641
-
2642
-
end:
2643
-
/* Transfer ownership of first descriptor to adapter just before
2644
-
* exiting. Before that, use memory barrier so that ownership
2645
-
* and other fields are seen by adapter correctly.
2646
-
*/
2647
-
if (first_rxdp) {
2648
-
dma_wmb();
2649
-
first_rxdp->Control_1 |= RXD_OWN_XENA;
2650
-
}
2651
-
2652
-
return SUCCESS;
2653
-
2654
-
pci_map_failed:
2655
-
swstats->pci_map_fail_cnt++;
2656
-
swstats->mem_freed += skb->truesize;
2657
-
dev_kfree_skb_irq(skb);
2658
-
return -ENOMEM;
2659
-
}
2660
-
2661
-
static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2662
-
{
2663
-
struct net_device *dev = sp->dev;
2664
-
int j;
2665
-
struct sk_buff *skb;
2666
-
struct RxD_t *rxdp;
2667
-
struct RxD1 *rxdp1;
2668
-
struct RxD3 *rxdp3;
2669
-
struct mac_info *mac_control = &sp->mac_control;
2670
-
struct stat_block *stats = mac_control->stats_info;
2671
-
struct swStat *swstats = &stats->sw_stat;
2672
-
2673
-
for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2674
-
rxdp = mac_control->rings[ring_no].
2675
-
rx_blocks[blk].rxds[j].virt_addr;
2676
-
skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2677
-
if (!skb)
2678
-
continue;
2679
-
if (sp->rxd_mode == RXD_MODE_1) {
2680
-
rxdp1 = (struct RxD1 *)rxdp;
2681
-
dma_unmap_single(&sp->pdev->dev,
2682
-
(dma_addr_t)rxdp1->Buffer0_ptr,
2683
-
dev->mtu +
2684
-
HEADER_ETHERNET_II_802_3_SIZE +
2685
-
HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2686
-
DMA_FROM_DEVICE);
2687
-
memset(rxdp, 0, sizeof(struct RxD1));
2688
-
} else if (sp->rxd_mode == RXD_MODE_3B) {
2689
-
rxdp3 = (struct RxD3 *)rxdp;
2690
-
dma_unmap_single(&sp->pdev->dev,
2691
-
(dma_addr_t)rxdp3->Buffer0_ptr,
2692
-
BUF0_LEN, DMA_FROM_DEVICE);
2693
-
dma_unmap_single(&sp->pdev->dev,
2694
-
(dma_addr_t)rxdp3->Buffer1_ptr,
2695
-
BUF1_LEN, DMA_FROM_DEVICE);
2696
-
dma_unmap_single(&sp->pdev->dev,
2697
-
(dma_addr_t)rxdp3->Buffer2_ptr,
2698
-
dev->mtu + 4, DMA_FROM_DEVICE);
2699
-
memset(rxdp, 0, sizeof(struct RxD3));
2700
-
}
2701
-
swstats->mem_freed += skb->truesize;
2702
-
dev_kfree_skb(skb);
2703
-
mac_control->rings[ring_no].rx_bufs_left -= 1;
2704
-
}
2705
-
}
2706
-
2707
-
/**
2708
-
* free_rx_buffers - Frees all Rx buffers
2709
-
* @sp: device private variable.
2710
-
* Description:
2711
-
* This function will free all Rx buffers allocated by host.
2712
-
* Return Value:
2713
-
* NONE.
2714
-
*/
2715
-
2716
-
static void free_rx_buffers(struct s2io_nic *sp)
2717
-
{
2718
-
struct net_device *dev = sp->dev;
2719
-
int i, blk = 0, buf_cnt = 0;
2720
-
struct config_param *config = &sp->config;
2721
-
struct mac_info *mac_control = &sp->mac_control;
2722
-
2723
-
for (i = 0; i < config->rx_ring_num; i++) {
2724
-
struct ring_info *ring = &mac_control->rings[i];
2725
-
2726
-
for (blk = 0; blk < rx_ring_sz[i]; blk++)
2727
-
free_rxd_blk(sp, i, blk);
2728
-
2729
-
ring->rx_curr_put_info.block_index = 0;
2730
-
ring->rx_curr_get_info.block_index = 0;
2731
-
ring->rx_curr_put_info.offset = 0;
2732
-
ring->rx_curr_get_info.offset = 0;
2733
-
ring->rx_bufs_left = 0;
2734
-
DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2735
-
dev->name, buf_cnt, i);
2736
-
}
2737
-
}
2738
-
2739
-
static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2740
-
{
2741
-
if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2742
-
DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2743
-
ring->dev->name);
2744
-
}
2745
-
return 0;
2746
-
}
2747
-
2748
-
/**
2749
-
* s2io_poll_msix - Rx interrupt handler for NAPI support
2750
-
* @napi : pointer to the napi structure.
2751
-
* @budget : The number of packets that were budgeted to be processed
2752
-
* during one pass through the 'Poll" function.
2753
-
* Description:
2754
-
* Comes into picture only if NAPI support has been incorporated. It does
2755
-
* the same thing that rx_intr_handler does, but not in a interrupt context
2756
-
* also It will process only a given number of packets.
2757
-
* Return value:
2758
-
* 0 on success and 1 if there are No Rx packets to be processed.
2759
-
*/
2760
-
2761
-
static int s2io_poll_msix(struct napi_struct *napi, int budget)
2762
-
{
2763
-
struct ring_info *ring = container_of(napi, struct ring_info, napi);
2764
-
struct net_device *dev = ring->dev;
2765
-
int pkts_processed = 0;
2766
-
u8 __iomem *addr = NULL;
2767
-
u8 val8 = 0;
2768
-
struct s2io_nic *nic = netdev_priv(dev);
2769
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
2770
-
int budget_org = budget;
2771
-
2772
-
if (unlikely(!is_s2io_card_up(nic)))
2773
-
return 0;
2774
-
2775
-
pkts_processed = rx_intr_handler(ring, budget);
2776
-
s2io_chk_rx_buffers(nic, ring);
2777
-
2778
-
if (pkts_processed < budget_org) {
2779
-
napi_complete_done(napi, pkts_processed);
2780
-
/*Re Enable MSI-Rx Vector*/
2781
-
addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2782
-
addr += 7 - ring->ring_no;
2783
-
val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2784
-
writeb(val8, addr);
2785
-
val8 = readb(addr);
2786
-
}
2787
-
return pkts_processed;
2788
-
}
2789
-
2790
-
static int s2io_poll_inta(struct napi_struct *napi, int budget)
2791
-
{
2792
-
struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2793
-
int pkts_processed = 0;
2794
-
int ring_pkts_processed, i;
2795
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
2796
-
int budget_org = budget;
2797
-
struct config_param *config = &nic->config;
2798
-
struct mac_info *mac_control = &nic->mac_control;
2799
-
2800
-
if (unlikely(!is_s2io_card_up(nic)))
2801
-
return 0;
2802
-
2803
-
for (i = 0; i < config->rx_ring_num; i++) {
2804
-
struct ring_info *ring = &mac_control->rings[i];
2805
-
ring_pkts_processed = rx_intr_handler(ring, budget);
2806
-
s2io_chk_rx_buffers(nic, ring);
2807
-
pkts_processed += ring_pkts_processed;
2808
-
budget -= ring_pkts_processed;
2809
-
if (budget <= 0)
2810
-
break;
2811
-
}
2812
-
if (pkts_processed < budget_org) {
2813
-
napi_complete_done(napi, pkts_processed);
2814
-
/* Re enable the Rx interrupts for the ring */
2815
-
writeq(0, &bar0->rx_traffic_mask);
2816
-
readl(&bar0->rx_traffic_mask);
2817
-
}
2818
-
return pkts_processed;
2819
-
}
2820
-
2821
-
#ifdef CONFIG_NET_POLL_CONTROLLER
2822
-
/**
2823
-
* s2io_netpoll - netpoll event handler entry point
2824
-
* @dev : pointer to the device structure.
2825
-
* Description:
2826
-
* This function will be called by upper layer to check for events on the
2827
-
* interface in situations where interrupts are disabled. It is used for
2828
-
* specific in-kernel networking tasks, such as remote consoles and kernel
2829
-
* debugging over the network (example netdump in RedHat).
2830
-
*/
2831
-
static void s2io_netpoll(struct net_device *dev)
2832
-
{
2833
-
struct s2io_nic *nic = netdev_priv(dev);
2834
-
const int irq = nic->pdev->irq;
2835
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
2836
-
u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2837
-
int i;
2838
-
struct config_param *config = &nic->config;
2839
-
struct mac_info *mac_control = &nic->mac_control;
2840
-
2841
-
if (pci_channel_offline(nic->pdev))
2842
-
return;
2843
-
2844
-
disable_irq(irq);
2845
-
2846
-
writeq(val64, &bar0->rx_traffic_int);
2847
-
writeq(val64, &bar0->tx_traffic_int);
2848
-
2849
-
/* we need to free up the transmitted skbufs or else netpoll will
2850
-
* run out of skbs and will fail and eventually netpoll application such
2851
-
* as netdump will fail.
2852
-
*/
2853
-
for (i = 0; i < config->tx_fifo_num; i++)
2854
-
tx_intr_handler(&mac_control->fifos[i]);
2855
-
2856
-
/* check for received packet and indicate up to network */
2857
-
for (i = 0; i < config->rx_ring_num; i++) {
2858
-
struct ring_info *ring = &mac_control->rings[i];
2859
-
2860
-
rx_intr_handler(ring, 0);
2861
-
}
2862
-
2863
-
for (i = 0; i < config->rx_ring_num; i++) {
2864
-
struct ring_info *ring = &mac_control->rings[i];
2865
-
2866
-
if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2867
-
DBG_PRINT(INFO_DBG,
2868
-
"%s: Out of memory in Rx Netpoll!!\n",
2869
-
dev->name);
2870
-
break;
2871
-
}
2872
-
}
2873
-
enable_irq(irq);
2874
-
}
2875
-
#endif
2876
-
2877
-
/**
2878
-
* rx_intr_handler - Rx interrupt handler
2879
-
* @ring_data: per ring structure.
2880
-
* @budget: budget for napi processing.
2881
-
* Description:
2882
-
* If the interrupt is because of a received frame or if the
2883
-
* receive ring contains fresh as yet un-processed frames,this function is
2884
-
* called. It picks out the RxD at which place the last Rx processing had
2885
-
* stopped and sends the skb to the OSM's Rx handler and then increments
2886
-
* the offset.
2887
-
* Return Value:
2888
-
* No. of napi packets processed.
2889
-
*/
2890
-
static int rx_intr_handler(struct ring_info *ring_data, int budget)
2891
-
{
2892
-
int get_block, put_block;
2893
-
struct rx_curr_get_info get_info, put_info;
2894
-
struct RxD_t *rxdp;
2895
-
struct sk_buff *skb;
2896
-
int pkt_cnt = 0, napi_pkts = 0;
2897
-
int i;
2898
-
struct RxD1 *rxdp1;
2899
-
struct RxD3 *rxdp3;
2900
-
2901
-
if (budget <= 0)
2902
-
return napi_pkts;
2903
-
2904
-
get_info = ring_data->rx_curr_get_info;
2905
-
get_block = get_info.block_index;
2906
-
memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2907
-
put_block = put_info.block_index;
2908
-
rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2909
-
2910
-
while (RXD_IS_UP2DT(rxdp)) {
2911
-
/*
2912
-
* If your are next to put index then it's
2913
-
* FIFO full condition
2914
-
*/
2915
-
if ((get_block == put_block) &&
2916
-
(get_info.offset + 1) == put_info.offset) {
2917
-
DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2918
-
ring_data->dev->name);
2919
-
break;
2920
-
}
2921
-
skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2922
-
if (skb == NULL) {
2923
-
DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2924
-
ring_data->dev->name);
2925
-
return 0;
2926
-
}
2927
-
if (ring_data->rxd_mode == RXD_MODE_1) {
2928
-
rxdp1 = (struct RxD1 *)rxdp;
2929
-
dma_unmap_single(&ring_data->pdev->dev,
2930
-
(dma_addr_t)rxdp1->Buffer0_ptr,
2931
-
ring_data->mtu +
2932
-
HEADER_ETHERNET_II_802_3_SIZE +
2933
-
HEADER_802_2_SIZE +
2934
-
HEADER_SNAP_SIZE,
2935
-
DMA_FROM_DEVICE);
2936
-
} else if (ring_data->rxd_mode == RXD_MODE_3B) {
2937
-
rxdp3 = (struct RxD3 *)rxdp;
2938
-
dma_sync_single_for_cpu(&ring_data->pdev->dev,
2939
-
(dma_addr_t)rxdp3->Buffer0_ptr,
2940
-
BUF0_LEN, DMA_FROM_DEVICE);
2941
-
dma_unmap_single(&ring_data->pdev->dev,
2942
-
(dma_addr_t)rxdp3->Buffer2_ptr,
2943
-
ring_data->mtu + 4, DMA_FROM_DEVICE);
2944
-
}
2945
-
prefetch(skb->data);
2946
-
rx_osm_handler(ring_data, rxdp);
2947
-
get_info.offset++;
2948
-
ring_data->rx_curr_get_info.offset = get_info.offset;
2949
-
rxdp = ring_data->rx_blocks[get_block].
2950
-
rxds[get_info.offset].virt_addr;
2951
-
if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2952
-
get_info.offset = 0;
2953
-
ring_data->rx_curr_get_info.offset = get_info.offset;
2954
-
get_block++;
2955
-
if (get_block == ring_data->block_count)
2956
-
get_block = 0;
2957
-
ring_data->rx_curr_get_info.block_index = get_block;
2958
-
rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2959
-
}
2960
-
2961
-
if (ring_data->nic->config.napi) {
2962
-
budget--;
2963
-
napi_pkts++;
2964
-
if (!budget)
2965
-
break;
2966
-
}
2967
-
pkt_cnt++;
2968
-
if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2969
-
break;
2970
-
}
2971
-
if (ring_data->lro) {
2972
-
/* Clear all LRO sessions before exiting */
2973
-
for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2974
-
struct lro *lro = &ring_data->lro0_n[i];
2975
-
if (lro->in_use) {
2976
-
update_L3L4_header(ring_data->nic, lro);
2977
-
queue_rx_frame(lro->parent, lro->vlan_tag);
2978
-
clear_lro_session(lro);
2979
-
}
2980
-
}
2981
-
}
2982
-
return napi_pkts;
2983
-
}
2984
-
2985
-
/**
2986
-
* tx_intr_handler - Transmit interrupt handler
2987
-
* @fifo_data : fifo data pointer
2988
-
* Description:
2989
-
* If an interrupt was raised to indicate DMA complete of the
2990
-
* Tx packet, this function is called. It identifies the last TxD
2991
-
* whose buffer was freed and frees all skbs whose data have already
2992
-
* DMA'ed into the NICs internal memory.
2993
-
* Return Value:
2994
-
* NONE
2995
-
*/
2996
-
2997
-
static void tx_intr_handler(struct fifo_info *fifo_data)
2998
-
{
2999
-
struct s2io_nic *nic = fifo_data->nic;
3000
-
struct tx_curr_get_info get_info, put_info;
3001
-
struct sk_buff *skb = NULL;
3002
-
struct TxD *txdlp;
3003
-
int pkt_cnt = 0;
3004
-
unsigned long flags = 0;
3005
-
u8 err_mask;
3006
-
struct stat_block *stats = nic->mac_control.stats_info;
3007
-
struct swStat *swstats = &stats->sw_stat;
3008
-
3009
-
if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3010
-
return;
3011
-
3012
-
get_info = fifo_data->tx_curr_get_info;
3013
-
memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3014
-
txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3015
-
while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3016
-
(get_info.offset != put_info.offset) &&
3017
-
(txdlp->Host_Control)) {
3018
-
/* Check for TxD errors */
3019
-
if (txdlp->Control_1 & TXD_T_CODE) {
3020
-
unsigned long long err;
3021
-
err = txdlp->Control_1 & TXD_T_CODE;
3022
-
if (err & 0x1) {
3023
-
swstats->parity_err_cnt++;
3024
-
}
3025
-
3026
-
/* update t_code statistics */
3027
-
err_mask = err >> 48;
3028
-
switch (err_mask) {
3029
-
case 2:
3030
-
swstats->tx_buf_abort_cnt++;
3031
-
break;
3032
-
3033
-
case 3:
3034
-
swstats->tx_desc_abort_cnt++;
3035
-
break;
3036
-
3037
-
case 7:
3038
-
swstats->tx_parity_err_cnt++;
3039
-
break;
3040
-
3041
-
case 10:
3042
-
swstats->tx_link_loss_cnt++;
3043
-
break;
3044
-
3045
-
case 15:
3046
-
swstats->tx_list_proc_err_cnt++;
3047
-
break;
3048
-
}
3049
-
}
3050
-
3051
-
skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3052
-
if (skb == NULL) {
3053
-
spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3054
-
DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3055
-
__func__);
3056
-
return;
3057
-
}
3058
-
pkt_cnt++;
3059
-
3060
-
/* Updating the statistics block */
3061
-
swstats->mem_freed += skb->truesize;
3062
-
dev_consume_skb_irq(skb);
3063
-
3064
-
get_info.offset++;
3065
-
if (get_info.offset == get_info.fifo_len + 1)
3066
-
get_info.offset = 0;
3067
-
txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3068
-
fifo_data->tx_curr_get_info.offset = get_info.offset;
3069
-
}
3070
-
3071
-
s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3072
-
3073
-
spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3074
-
}
3075
-
3076
-
/**
3077
-
* s2io_mdio_write - Function to write in to MDIO registers
3078
-
* @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3079
-
* @addr : address value
3080
-
* @value : data value
3081
-
* @dev : pointer to net_device structure
3082
-
* Description:
3083
-
* This function is used to write values to the MDIO registers
3084
-
* NONE
3085
-
*/
3086
-
static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3087
-
struct net_device *dev)
3088
-
{
3089
-
u64 val64;
3090
-
struct s2io_nic *sp = netdev_priv(dev);
3091
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
3092
-
3093
-
/* address transaction */
3094
-
val64 = MDIO_MMD_INDX_ADDR(addr) |
3095
-
MDIO_MMD_DEV_ADDR(mmd_type) |
3096
-
MDIO_MMS_PRT_ADDR(0x0);
3097
-
writeq(val64, &bar0->mdio_control);
3098
-
val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3099
-
writeq(val64, &bar0->mdio_control);
3100
-
udelay(100);
3101
-
3102
-
/* Data transaction */
3103
-
val64 = MDIO_MMD_INDX_ADDR(addr) |
3104
-
MDIO_MMD_DEV_ADDR(mmd_type) |
3105
-
MDIO_MMS_PRT_ADDR(0x0) |
3106
-
MDIO_MDIO_DATA(value) |
3107
-
MDIO_OP(MDIO_OP_WRITE_TRANS);
3108
-
writeq(val64, &bar0->mdio_control);
3109
-
val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3110
-
writeq(val64, &bar0->mdio_control);
3111
-
udelay(100);
3112
-
3113
-
val64 = MDIO_MMD_INDX_ADDR(addr) |
3114
-
MDIO_MMD_DEV_ADDR(mmd_type) |
3115
-
MDIO_MMS_PRT_ADDR(0x0) |
3116
-
MDIO_OP(MDIO_OP_READ_TRANS);
3117
-
writeq(val64, &bar0->mdio_control);
3118
-
val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3119
-
writeq(val64, &bar0->mdio_control);
3120
-
udelay(100);
3121
-
}
3122
-
3123
-
/**
3124
-
* s2io_mdio_read - Function to write in to MDIO registers
3125
-
* @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3126
-
* @addr : address value
3127
-
* @dev : pointer to net_device structure
3128
-
* Description:
3129
-
* This function is used to read values to the MDIO registers
3130
-
* NONE
3131
-
*/
3132
-
static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3133
-
{
3134
-
u64 val64 = 0x0;
3135
-
u64 rval64 = 0x0;
3136
-
struct s2io_nic *sp = netdev_priv(dev);
3137
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
3138
-
3139
-
/* address transaction */
3140
-
val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3141
-
| MDIO_MMD_DEV_ADDR(mmd_type)
3142
-
| MDIO_MMS_PRT_ADDR(0x0));
3143
-
writeq(val64, &bar0->mdio_control);
3144
-
val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3145
-
writeq(val64, &bar0->mdio_control);
3146
-
udelay(100);
3147
-
3148
-
/* Data transaction */
3149
-
val64 = MDIO_MMD_INDX_ADDR(addr) |
3150
-
MDIO_MMD_DEV_ADDR(mmd_type) |
3151
-
MDIO_MMS_PRT_ADDR(0x0) |
3152
-
MDIO_OP(MDIO_OP_READ_TRANS);
3153
-
writeq(val64, &bar0->mdio_control);
3154
-
val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3155
-
writeq(val64, &bar0->mdio_control);
3156
-
udelay(100);
3157
-
3158
-
/* Read the value from regs */
3159
-
rval64 = readq(&bar0->mdio_control);
3160
-
rval64 = rval64 & 0xFFFF0000;
3161
-
rval64 = rval64 >> 16;
3162
-
return rval64;
3163
-
}
3164
-
3165
-
/**
3166
-
* s2io_chk_xpak_counter - Function to check the status of the xpak counters
3167
-
* @counter : counter value to be updated
3168
-
* @regs_stat : registers status
3169
-
* @index : index
3170
-
* @flag : flag to indicate the status
3171
-
* @type : counter type
3172
-
* Description:
3173
-
* This function is to check the status of the xpak counters value
3174
-
* NONE
3175
-
*/
3176
-
3177
-
static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3178
-
u16 flag, u16 type)
3179
-
{
3180
-
u64 mask = 0x3;
3181
-
u64 val64;
3182
-
int i;
3183
-
for (i = 0; i < index; i++)
3184
-
mask = mask << 0x2;
3185
-
3186
-
if (flag > 0) {
3187
-
*counter = *counter + 1;
3188
-
val64 = *regs_stat & mask;
3189
-
val64 = val64 >> (index * 0x2);
3190
-
val64 = val64 + 1;
3191
-
if (val64 == 3) {
3192
-
switch (type) {
3193
-
case 1:
3194
-
DBG_PRINT(ERR_DBG,
3195
-
"Take Xframe NIC out of service.\n");
3196
-
DBG_PRINT(ERR_DBG,
3197
-
"Excessive temperatures may result in premature transceiver failure.\n");
3198
-
break;
3199
-
case 2:
3200
-
DBG_PRINT(ERR_DBG,
3201
-
"Take Xframe NIC out of service.\n");
3202
-
DBG_PRINT(ERR_DBG,
3203
-
"Excessive bias currents may indicate imminent laser diode failure.\n");
3204
-
break;
3205
-
case 3:
3206
-
DBG_PRINT(ERR_DBG,
3207
-
"Take Xframe NIC out of service.\n");
3208
-
DBG_PRINT(ERR_DBG,
3209
-
"Excessive laser output power may saturate far-end receiver.\n");
3210
-
break;
3211
-
default:
3212
-
DBG_PRINT(ERR_DBG,
3213
-
"Incorrect XPAK Alarm type\n");
3214
-
}
3215
-
val64 = 0x0;
3216
-
}
3217
-
val64 = val64 << (index * 0x2);
3218
-
*regs_stat = (*regs_stat & (~mask)) | (val64);
3219
-
3220
-
} else {
3221
-
*regs_stat = *regs_stat & (~mask);
3222
-
}
3223
-
}
3224
-
3225
-
/**
3226
-
* s2io_updt_xpak_counter - Function to update the xpak counters
3227
-
* @dev : pointer to net_device struct
3228
-
* Description:
3229
-
* This function is to upate the status of the xpak counters value
3230
-
* NONE
3231
-
*/
3232
-
static void s2io_updt_xpak_counter(struct net_device *dev)
3233
-
{
3234
-
u16 flag = 0x0;
3235
-
u16 type = 0x0;
3236
-
u16 val16 = 0x0;
3237
-
u64 val64 = 0x0;
3238
-
u64 addr = 0x0;
3239
-
3240
-
struct s2io_nic *sp = netdev_priv(dev);
3241
-
struct stat_block *stats = sp->mac_control.stats_info;
3242
-
struct xpakStat *xstats = &stats->xpak_stat;
3243
-
3244
-
/* Check the communication with the MDIO slave */
3245
-
addr = MDIO_CTRL1;
3246
-
val64 = 0x0;
3247
-
val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3248
-
if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3249
-
DBG_PRINT(ERR_DBG,
3250
-
"ERR: MDIO slave access failed - Returned %llx\n",
3251
-
(unsigned long long)val64);
3252
-
return;
3253
-
}
3254
-
3255
-
/* Check for the expected value of control reg 1 */
3256
-
if (val64 != MDIO_CTRL1_SPEED10G) {
3257
-
DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3258
-
"Returned: %llx- Expected: 0x%x\n",
3259
-
(unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3260
-
return;
3261
-
}
3262
-
3263
-
/* Loading the DOM register to MDIO register */
3264
-
addr = 0xA100;
3265
-
s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3266
-
val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3267
-
3268
-
/* Reading the Alarm flags */
3269
-
addr = 0xA070;
3270
-
val64 = 0x0;
3271
-
val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3272
-
3273
-
flag = CHECKBIT(val64, 0x7);
3274
-
type = 1;
3275
-
s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3276
-
&xstats->xpak_regs_stat,
3277
-
0x0, flag, type);
3278
-
3279
-
if (CHECKBIT(val64, 0x6))
3280
-
xstats->alarm_transceiver_temp_low++;
3281
-
3282
-
flag = CHECKBIT(val64, 0x3);
3283
-
type = 2;
3284
-
s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3285
-
&xstats->xpak_regs_stat,
3286
-
0x2, flag, type);
3287
-
3288
-
if (CHECKBIT(val64, 0x2))
3289
-
xstats->alarm_laser_bias_current_low++;
3290
-
3291
-
flag = CHECKBIT(val64, 0x1);
3292
-
type = 3;
3293
-
s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3294
-
&xstats->xpak_regs_stat,
3295
-
0x4, flag, type);
3296
-
3297
-
if (CHECKBIT(val64, 0x0))
3298
-
xstats->alarm_laser_output_power_low++;
3299
-
3300
-
/* Reading the Warning flags */
3301
-
addr = 0xA074;
3302
-
val64 = 0x0;
3303
-
val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3304
-
3305
-
if (CHECKBIT(val64, 0x7))
3306
-
xstats->warn_transceiver_temp_high++;
3307
-
3308
-
if (CHECKBIT(val64, 0x6))
3309
-
xstats->warn_transceiver_temp_low++;
3310
-
3311
-
if (CHECKBIT(val64, 0x3))
3312
-
xstats->warn_laser_bias_current_high++;
3313
-
3314
-
if (CHECKBIT(val64, 0x2))
3315
-
xstats->warn_laser_bias_current_low++;
3316
-
3317
-
if (CHECKBIT(val64, 0x1))
3318
-
xstats->warn_laser_output_power_high++;
3319
-
3320
-
if (CHECKBIT(val64, 0x0))
3321
-
xstats->warn_laser_output_power_low++;
3322
-
}
3323
-
3324
-
/**
3325
-
* wait_for_cmd_complete - waits for a command to complete.
3326
-
* @addr: address
3327
-
* @busy_bit: bit to check for busy
3328
-
* @bit_state: state to check
3329
-
* @may_sleep: parameter indicates if sleeping when waiting for
3330
-
* command complete
3331
-
* Description: Function that waits for a command to Write into RMAC
3332
-
* ADDR DATA registers to be completed and returns either success or
3333
-
* error depending on whether the command was complete or not.
3334
-
* Return value:
3335
-
* SUCCESS on success and FAILURE on failure.
3336
-
*/
3337
-
3338
-
static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3339
-
int bit_state, bool may_sleep)
3340
-
{
3341
-
int ret = FAILURE, cnt = 0, delay = 1;
3342
-
u64 val64;
3343
-
3344
-
if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3345
-
return FAILURE;
3346
-
3347
-
do {
3348
-
val64 = readq(addr);
3349
-
if (bit_state == S2IO_BIT_RESET) {
3350
-
if (!(val64 & busy_bit)) {
3351
-
ret = SUCCESS;
3352
-
break;
3353
-
}
3354
-
} else {
3355
-
if (val64 & busy_bit) {
3356
-
ret = SUCCESS;
3357
-
break;
3358
-
}
3359
-
}
3360
-
3361
-
if (!may_sleep)
3362
-
mdelay(delay);
3363
-
else
3364
-
msleep(delay);
3365
-
3366
-
if (++cnt >= 10)
3367
-
delay = 50;
3368
-
} while (cnt < 20);
3369
-
return ret;
3370
-
}
3371
-
/**
3372
-
* check_pci_device_id - Checks if the device id is supported
3373
-
* @id : device id
3374
-
* Description: Function to check if the pci device id is supported by driver.
3375
-
* Return value: Actual device id if supported else PCI_ANY_ID
3376
-
*/
3377
-
static u16 check_pci_device_id(u16 id)
3378
-
{
3379
-
switch (id) {
3380
-
case PCI_DEVICE_ID_HERC_WIN:
3381
-
case PCI_DEVICE_ID_HERC_UNI:
3382
-
return XFRAME_II_DEVICE;
3383
-
case PCI_DEVICE_ID_S2IO_UNI:
3384
-
case PCI_DEVICE_ID_S2IO_WIN:
3385
-
return XFRAME_I_DEVICE;
3386
-
default:
3387
-
return PCI_ANY_ID;
3388
-
}
3389
-
}
3390
-
3391
-
/**
3392
-
* s2io_reset - Resets the card.
3393
-
* @sp : private member of the device structure.
3394
-
* Description: Function to Reset the card. This function then also
3395
-
* restores the previously saved PCI configuration space registers as
3396
-
* the card reset also resets the configuration space.
3397
-
* Return value:
3398
-
* void.
3399
-
*/
3400
-
3401
-
static void s2io_reset(struct s2io_nic *sp)
3402
-
{
3403
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
3404
-
u64 val64;
3405
-
u16 subid, pci_cmd;
3406
-
int i;
3407
-
u16 val16;
3408
-
unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3409
-
unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3410
-
struct stat_block *stats;
3411
-
struct swStat *swstats;
3412
-
3413
-
DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3414
-
__func__, pci_name(sp->pdev));
3415
-
3416
-
/* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3417
-
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3418
-
3419
-
val64 = SW_RESET_ALL;
3420
-
writeq(val64, &bar0->sw_reset);
3421
-
if (strstr(sp->product_name, "CX4"))
3422
-
msleep(750);
3423
-
msleep(250);
3424
-
for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3425
-
3426
-
/* Restore the PCI state saved during initialization. */
3427
-
pci_restore_state(sp->pdev);
3428
-
pci_read_config_word(sp->pdev, 0x2, &val16);
3429
-
if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3430
-
break;
3431
-
msleep(200);
3432
-
}
3433
-
3434
-
if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3435
-
DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3436
-
3437
-
pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3438
-
3439
-
s2io_init_pci(sp);
3440
-
3441
-
/* Set swapper to enable I/O register access */
3442
-
s2io_set_swapper(sp);
3443
-
3444
-
/* restore mac_addr entries */
3445
-
do_s2io_restore_unicast_mc(sp);
3446
-
3447
-
/* Restore the MSIX table entries from local variables */
3448
-
restore_xmsi_data(sp);
3449
-
3450
-
/* Clear certain PCI/PCI-X fields after reset */
3451
-
if (sp->device_type == XFRAME_II_DEVICE) {
3452
-
/* Clear "detected parity error" bit */
3453
-
pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3454
-
3455
-
/* Clearing PCIX Ecc status register */
3456
-
pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3457
-
3458
-
/* Clearing PCI_STATUS error reflected here */
3459
-
writeq(s2BIT(62), &bar0->txpic_int_reg);
3460
-
}
3461
-
3462
-
/* Reset device statistics maintained by OS */
3463
-
memset(&sp->stats, 0, sizeof(struct net_device_stats));
3464
-
3465
-
stats = sp->mac_control.stats_info;
3466
-
swstats = &stats->sw_stat;
3467
-
3468
-
/* save link up/down time/cnt, reset/memory/watchdog cnt */
3469
-
up_cnt = swstats->link_up_cnt;
3470
-
down_cnt = swstats->link_down_cnt;
3471
-
up_time = swstats->link_up_time;
3472
-
down_time = swstats->link_down_time;
3473
-
reset_cnt = swstats->soft_reset_cnt;
3474
-
mem_alloc_cnt = swstats->mem_allocated;
3475
-
mem_free_cnt = swstats->mem_freed;
3476
-
watchdog_cnt = swstats->watchdog_timer_cnt;
3477
-
3478
-
memset(stats, 0, sizeof(struct stat_block));
3479
-
3480
-
/* restore link up/down time/cnt, reset/memory/watchdog cnt */
3481
-
swstats->link_up_cnt = up_cnt;
3482
-
swstats->link_down_cnt = down_cnt;
3483
-
swstats->link_up_time = up_time;
3484
-
swstats->link_down_time = down_time;
3485
-
swstats->soft_reset_cnt = reset_cnt;
3486
-
swstats->mem_allocated = mem_alloc_cnt;
3487
-
swstats->mem_freed = mem_free_cnt;
3488
-
swstats->watchdog_timer_cnt = watchdog_cnt;
3489
-
3490
-
/* SXE-002: Configure link and activity LED to turn it off */
3491
-
subid = sp->pdev->subsystem_device;
3492
-
if (((subid & 0xFF) >= 0x07) &&
3493
-
(sp->device_type == XFRAME_I_DEVICE)) {
3494
-
val64 = readq(&bar0->gpio_control);
3495
-
val64 |= 0x0000800000000000ULL;
3496
-
writeq(val64, &bar0->gpio_control);
3497
-
val64 = 0x0411040400000000ULL;
3498
-
writeq(val64, (void __iomem *)bar0 + 0x2700);
3499
-
}
3500
-
3501
-
/*
3502
-
* Clear spurious ECC interrupts that would have occurred on
3503
-
* XFRAME II cards after reset.
3504
-
*/
3505
-
if (sp->device_type == XFRAME_II_DEVICE) {
3506
-
val64 = readq(&bar0->pcc_err_reg);
3507
-
writeq(val64, &bar0->pcc_err_reg);
3508
-
}
3509
-
3510
-
sp->device_enabled_once = false;
3511
-
}
3512
-
3513
-
/**
3514
-
* s2io_set_swapper - to set the swapper controle on the card
3515
-
* @sp : private member of the device structure,
3516
-
* pointer to the s2io_nic structure.
3517
-
* Description: Function to set the swapper control on the card
3518
-
* correctly depending on the 'endianness' of the system.
3519
-
* Return value:
3520
-
* SUCCESS on success and FAILURE on failure.
3521
-
*/
3522
-
3523
-
static int s2io_set_swapper(struct s2io_nic *sp)
3524
-
{
3525
-
struct net_device *dev = sp->dev;
3526
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
3527
-
u64 val64, valt, valr;
3528
-
3529
-
/*
3530
-
* Set proper endian settings and verify the same by reading
3531
-
* the PIF Feed-back register.
3532
-
*/
3533
-
3534
-
val64 = readq(&bar0->pif_rd_swapper_fb);
3535
-
if (val64 != 0x0123456789ABCDEFULL) {
3536
-
int i = 0;
3537
-
static const u64 value[] = {
3538
-
0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3539
-
0x8100008181000081ULL, /* FE=1, SE=0 */
3540
-
0x4200004242000042ULL, /* FE=0, SE=1 */
3541
-
0 /* FE=0, SE=0 */
3542
-
};
3543
-
3544
-
while (i < 4) {
3545
-
writeq(value[i], &bar0->swapper_ctrl);
3546
-
val64 = readq(&bar0->pif_rd_swapper_fb);
3547
-
if (val64 == 0x0123456789ABCDEFULL)
3548
-
break;
3549
-
i++;
3550
-
}
3551
-
if (i == 4) {
3552
-
DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3553
-
"feedback read %llx\n",
3554
-
dev->name, (unsigned long long)val64);
3555
-
return FAILURE;
3556
-
}
3557
-
valr = value[i];
3558
-
} else {
3559
-
valr = readq(&bar0->swapper_ctrl);
3560
-
}
3561
-
3562
-
valt = 0x0123456789ABCDEFULL;
3563
-
writeq(valt, &bar0->xmsi_address);
3564
-
val64 = readq(&bar0->xmsi_address);
3565
-
3566
-
if (val64 != valt) {
3567
-
int i = 0;
3568
-
static const u64 value[] = {
3569
-
0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3570
-
0x0081810000818100ULL, /* FE=1, SE=0 */
3571
-
0x0042420000424200ULL, /* FE=0, SE=1 */
3572
-
0 /* FE=0, SE=0 */
3573
-
};
3574
-
3575
-
while (i < 4) {
3576
-
writeq((value[i] | valr), &bar0->swapper_ctrl);
3577
-
writeq(valt, &bar0->xmsi_address);
3578
-
val64 = readq(&bar0->xmsi_address);
3579
-
if (val64 == valt)
3580
-
break;
3581
-
i++;
3582
-
}
3583
-
if (i == 4) {
3584
-
unsigned long long x = val64;
3585
-
DBG_PRINT(ERR_DBG,
3586
-
"Write failed, Xmsi_addr reads:0x%llx\n", x);
3587
-
return FAILURE;
3588
-
}
3589
-
}
3590
-
val64 = readq(&bar0->swapper_ctrl);
3591
-
val64 &= 0xFFFF000000000000ULL;
3592
-
3593
-
#ifdef __BIG_ENDIAN
3594
-
/*
3595
-
* The device by default set to a big endian format, so a
3596
-
* big endian driver need not set anything.
3597
-
*/
3598
-
val64 |= (SWAPPER_CTRL_TXP_FE |
3599
-
SWAPPER_CTRL_TXP_SE |
3600
-
SWAPPER_CTRL_TXD_R_FE |
3601
-
SWAPPER_CTRL_TXD_W_FE |
3602
-
SWAPPER_CTRL_TXF_R_FE |
3603
-
SWAPPER_CTRL_RXD_R_FE |
3604
-
SWAPPER_CTRL_RXD_W_FE |
3605
-
SWAPPER_CTRL_RXF_W_FE |
3606
-
SWAPPER_CTRL_XMSI_FE |
3607
-
SWAPPER_CTRL_STATS_FE |
3608
-
SWAPPER_CTRL_STATS_SE);
3609
-
if (sp->config.intr_type == INTA)
3610
-
val64 |= SWAPPER_CTRL_XMSI_SE;
3611
-
writeq(val64, &bar0->swapper_ctrl);
3612
-
#else
3613
-
/*
3614
-
* Initially we enable all bits to make it accessible by the
3615
-
* driver, then we selectively enable only those bits that
3616
-
* we want to set.
3617
-
*/
3618
-
val64 |= (SWAPPER_CTRL_TXP_FE |
3619
-
SWAPPER_CTRL_TXP_SE |
3620
-
SWAPPER_CTRL_TXD_R_FE |
3621
-
SWAPPER_CTRL_TXD_R_SE |
3622
-
SWAPPER_CTRL_TXD_W_FE |
3623
-
SWAPPER_CTRL_TXD_W_SE |
3624
-
SWAPPER_CTRL_TXF_R_FE |
3625
-
SWAPPER_CTRL_RXD_R_FE |
3626
-
SWAPPER_CTRL_RXD_R_SE |
3627
-
SWAPPER_CTRL_RXD_W_FE |
3628
-
SWAPPER_CTRL_RXD_W_SE |
3629
-
SWAPPER_CTRL_RXF_W_FE |
3630
-
SWAPPER_CTRL_XMSI_FE |
3631
-
SWAPPER_CTRL_STATS_FE |
3632
-
SWAPPER_CTRL_STATS_SE);
3633
-
if (sp->config.intr_type == INTA)
3634
-
val64 |= SWAPPER_CTRL_XMSI_SE;
3635
-
writeq(val64, &bar0->swapper_ctrl);
3636
-
#endif
3637
-
val64 = readq(&bar0->swapper_ctrl);
3638
-
3639
-
/*
3640
-
* Verifying if endian settings are accurate by reading a
3641
-
* feedback register.
3642
-
*/
3643
-
val64 = readq(&bar0->pif_rd_swapper_fb);
3644
-
if (val64 != 0x0123456789ABCDEFULL) {
3645
-
/* Endian settings are incorrect, calls for another dekko. */
3646
-
DBG_PRINT(ERR_DBG,
3647
-
"%s: Endian settings are wrong, feedback read %llx\n",
3648
-
dev->name, (unsigned long long)val64);
3649
-
return FAILURE;
3650
-
}
3651
-
3652
-
return SUCCESS;
3653
-
}
3654
-
3655
-
static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3656
-
{
3657
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
3658
-
u64 val64;
3659
-
int ret = 0, cnt = 0;
3660
-
3661
-
do {
3662
-
val64 = readq(&bar0->xmsi_access);
3663
-
if (!(val64 & s2BIT(15)))
3664
-
break;
3665
-
mdelay(1);
3666
-
cnt++;
3667
-
} while (cnt < 5);
3668
-
if (cnt == 5) {
3669
-
DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3670
-
ret = 1;
3671
-
}
3672
-
3673
-
return ret;
3674
-
}
3675
-
3676
-
static void restore_xmsi_data(struct s2io_nic *nic)
3677
-
{
3678
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
3679
-
u64 val64;
3680
-
int i, msix_index;
3681
-
3682
-
if (nic->device_type == XFRAME_I_DEVICE)
3683
-
return;
3684
-
3685
-
for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3686
-
msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3687
-
writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3688
-
writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3689
-
val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3690
-
writeq(val64, &bar0->xmsi_access);
3691
-
if (wait_for_msix_trans(nic, msix_index))
3692
-
DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3693
-
__func__, msix_index);
3694
-
}
3695
-
}
3696
-
3697
-
static void store_xmsi_data(struct s2io_nic *nic)
3698
-
{
3699
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
3700
-
u64 val64, addr, data;
3701
-
int i, msix_index;
3702
-
3703
-
if (nic->device_type == XFRAME_I_DEVICE)
3704
-
return;
3705
-
3706
-
/* Store and display */
3707
-
for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3708
-
msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3709
-
val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3710
-
writeq(val64, &bar0->xmsi_access);
3711
-
if (wait_for_msix_trans(nic, msix_index)) {
3712
-
DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3713
-
__func__, msix_index);
3714
-
continue;
3715
-
}
3716
-
addr = readq(&bar0->xmsi_address);
3717
-
data = readq(&bar0->xmsi_data);
3718
-
if (addr && data) {
3719
-
nic->msix_info[i].addr = addr;
3720
-
nic->msix_info[i].data = data;
3721
-
}
3722
-
}
3723
-
}
3724
-
3725
-
static int s2io_enable_msi_x(struct s2io_nic *nic)
3726
-
{
3727
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
3728
-
u64 rx_mat;
3729
-
u16 msi_control; /* Temp variable */
3730
-
int ret, i, j, msix_indx = 1;
3731
-
int size;
3732
-
struct stat_block *stats = nic->mac_control.stats_info;
3733
-
struct swStat *swstats = &stats->sw_stat;
3734
-
3735
-
size = nic->num_entries * sizeof(struct msix_entry);
3736
-
nic->entries = kzalloc(size, GFP_KERNEL);
3737
-
if (!nic->entries) {
3738
-
DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3739
-
__func__);
3740
-
swstats->mem_alloc_fail_cnt++;
3741
-
return -ENOMEM;
3742
-
}
3743
-
swstats->mem_allocated += size;
3744
-
3745
-
size = nic->num_entries * sizeof(struct s2io_msix_entry);
3746
-
nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3747
-
if (!nic->s2io_entries) {
3748
-
DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3749
-
__func__);
3750
-
swstats->mem_alloc_fail_cnt++;
3751
-
kfree(nic->entries);
3752
-
swstats->mem_freed
3753
-
+= (nic->num_entries * sizeof(struct msix_entry));
3754
-
return -ENOMEM;
3755
-
}
3756
-
swstats->mem_allocated += size;
3757
-
3758
-
nic->entries[0].entry = 0;
3759
-
nic->s2io_entries[0].entry = 0;
3760
-
nic->s2io_entries[0].in_use = MSIX_FLG;
3761
-
nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3762
-
nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3763
-
3764
-
for (i = 1; i < nic->num_entries; i++) {
3765
-
nic->entries[i].entry = ((i - 1) * 8) + 1;
3766
-
nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3767
-
nic->s2io_entries[i].arg = NULL;
3768
-
nic->s2io_entries[i].in_use = 0;
3769
-
}
3770
-
3771
-
rx_mat = readq(&bar0->rx_mat);
3772
-
for (j = 0; j < nic->config.rx_ring_num; j++) {
3773
-
rx_mat |= RX_MAT_SET(j, msix_indx);
3774
-
nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3775
-
nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3776
-
nic->s2io_entries[j+1].in_use = MSIX_FLG;
3777
-
msix_indx += 8;
3778
-
}
3779
-
writeq(rx_mat, &bar0->rx_mat);
3780
-
readq(&bar0->rx_mat);
3781
-
3782
-
ret = pci_enable_msix_range(nic->pdev, nic->entries,
3783
-
nic->num_entries, nic->num_entries);
3784
-
/* We fail init if error or we get less vectors than min required */
3785
-
if (ret < 0) {
3786
-
DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3787
-
kfree(nic->entries);
3788
-
swstats->mem_freed += nic->num_entries *
3789
-
sizeof(struct msix_entry);
3790
-
kfree(nic->s2io_entries);
3791
-
swstats->mem_freed += nic->num_entries *
3792
-
sizeof(struct s2io_msix_entry);
3793
-
nic->entries = NULL;
3794
-
nic->s2io_entries = NULL;
3795
-
return -ENOMEM;
3796
-
}
3797
-
3798
-
/*
3799
-
* To enable MSI-X, MSI also needs to be enabled, due to a bug
3800
-
* in the herc NIC. (Temp change, needs to be removed later)
3801
-
*/
3802
-
pci_read_config_word(nic->pdev, 0x42, &msi_control);
3803
-
msi_control |= 0x1; /* Enable MSI */
3804
-
pci_write_config_word(nic->pdev, 0x42, msi_control);
3805
-
3806
-
return 0;
3807
-
}
3808
-
3809
-
/* Handle software interrupt used during MSI(X) test */
3810
-
static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3811
-
{
3812
-
struct s2io_nic *sp = dev_id;
3813
-
3814
-
sp->msi_detected = 1;
3815
-
wake_up(&sp->msi_wait);
3816
-
3817
-
return IRQ_HANDLED;
3818
-
}
3819
-
3820
-
/* Test interrupt path by forcing a software IRQ */
3821
-
static int s2io_test_msi(struct s2io_nic *sp)
3822
-
{
3823
-
struct pci_dev *pdev = sp->pdev;
3824
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
3825
-
int err;
3826
-
u64 val64, saved64;
3827
-
3828
-
err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3829
-
sp->name, sp);
3830
-
if (err) {
3831
-
DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3832
-
sp->dev->name, pci_name(pdev), pdev->irq);
3833
-
return err;
3834
-
}
3835
-
3836
-
init_waitqueue_head(&sp->msi_wait);
3837
-
sp->msi_detected = 0;
3838
-
3839
-
saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3840
-
val64 |= SCHED_INT_CTRL_ONE_SHOT;
3841
-
val64 |= SCHED_INT_CTRL_TIMER_EN;
3842
-
val64 |= SCHED_INT_CTRL_INT2MSI(1);
3843
-
writeq(val64, &bar0->scheduled_int_ctrl);
3844
-
3845
-
wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3846
-
3847
-
if (!sp->msi_detected) {
3848
-
/* MSI(X) test failed, go back to INTx mode */
3849
-
DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3850
-
"using MSI(X) during test\n",
3851
-
sp->dev->name, pci_name(pdev));
3852
-
3853
-
err = -EOPNOTSUPP;
3854
-
}
3855
-
3856
-
free_irq(sp->entries[1].vector, sp);
3857
-
3858
-
writeq(saved64, &bar0->scheduled_int_ctrl);
3859
-
3860
-
return err;
3861
-
}
3862
-
3863
-
static void remove_msix_isr(struct s2io_nic *sp)
3864
-
{
3865
-
int i;
3866
-
u16 msi_control;
3867
-
3868
-
for (i = 0; i < sp->num_entries; i++) {
3869
-
if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3870
-
int vector = sp->entries[i].vector;
3871
-
void *arg = sp->s2io_entries[i].arg;
3872
-
free_irq(vector, arg);
3873
-
}
3874
-
}
3875
-
3876
-
kfree(sp->entries);
3877
-
kfree(sp->s2io_entries);
3878
-
sp->entries = NULL;
3879
-
sp->s2io_entries = NULL;
3880
-
3881
-
pci_read_config_word(sp->pdev, 0x42, &msi_control);
3882
-
msi_control &= 0xFFFE; /* Disable MSI */
3883
-
pci_write_config_word(sp->pdev, 0x42, msi_control);
3884
-
3885
-
pci_disable_msix(sp->pdev);
3886
-
}
3887
-
3888
-
static void remove_inta_isr(struct s2io_nic *sp)
3889
-
{
3890
-
free_irq(sp->pdev->irq, sp->dev);
3891
-
}
3892
-
3893
-
/* ********************************************************* *
3894
-
* Functions defined below concern the OS part of the driver *
3895
-
* ********************************************************* */
3896
-
3897
-
/**
3898
-
* s2io_open - open entry point of the driver
3899
-
* @dev : pointer to the device structure.
3900
-
* Description:
3901
-
* This function is the open entry point of the driver. It mainly calls a
3902
-
* function to allocate Rx buffers and inserts them into the buffer
3903
-
* descriptors and then enables the Rx part of the NIC.
3904
-
* Return value:
3905
-
* 0 on success and an appropriate (-)ve integer as defined in errno.h
3906
-
* file on failure.
3907
-
*/
3908
-
3909
-
static int s2io_open(struct net_device *dev)
3910
-
{
3911
-
struct s2io_nic *sp = netdev_priv(dev);
3912
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3913
-
int err = 0;
3914
-
3915
-
/*
3916
-
* Make sure you have link off by default every time
3917
-
* Nic is initialized
3918
-
*/
3919
-
netif_carrier_off(dev);
3920
-
sp->last_link_state = 0;
3921
-
3922
-
/* Initialize H/W and enable interrupts */
3923
-
err = s2io_card_up(sp);
3924
-
if (err) {
3925
-
DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3926
-
dev->name);
3927
-
goto hw_init_failed;
3928
-
}
3929
-
3930
-
if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3931
-
DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3932
-
s2io_card_down(sp);
3933
-
err = -ENODEV;
3934
-
goto hw_init_failed;
3935
-
}
3936
-
s2io_start_all_tx_queue(sp);
3937
-
return 0;
3938
-
3939
-
hw_init_failed:
3940
-
if (sp->config.intr_type == MSI_X) {
3941
-
if (sp->entries) {
3942
-
kfree(sp->entries);
3943
-
swstats->mem_freed += sp->num_entries *
3944
-
sizeof(struct msix_entry);
3945
-
}
3946
-
if (sp->s2io_entries) {
3947
-
kfree(sp->s2io_entries);
3948
-
swstats->mem_freed += sp->num_entries *
3949
-
sizeof(struct s2io_msix_entry);
3950
-
}
3951
-
}
3952
-
return err;
3953
-
}
3954
-
3955
-
/**
3956
-
* s2io_close -close entry point of the driver
3957
-
* @dev : device pointer.
3958
-
* Description:
3959
-
* This is the stop entry point of the driver. It needs to undo exactly
3960
-
* whatever was done by the open entry point,thus it's usually referred to
3961
-
* as the close function.Among other things this function mainly stops the
3962
-
* Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3963
-
* Return value:
3964
-
* 0 on success and an appropriate (-)ve integer as defined in errno.h
3965
-
* file on failure.
3966
-
*/
3967
-
3968
-
static int s2io_close(struct net_device *dev)
3969
-
{
3970
-
struct s2io_nic *sp = netdev_priv(dev);
3971
-
struct config_param *config = &sp->config;
3972
-
u64 tmp64;
3973
-
int offset;
3974
-
3975
-
/* Return if the device is already closed *
3976
-
* Can happen when s2io_card_up failed in change_mtu *
3977
-
*/
3978
-
if (!is_s2io_card_up(sp))
3979
-
return 0;
3980
-
3981
-
s2io_stop_all_tx_queue(sp);
3982
-
/* delete all populated mac entries */
3983
-
for (offset = 1; offset < config->max_mc_addr; offset++) {
3984
-
tmp64 = do_s2io_read_unicast_mc(sp, offset);
3985
-
if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3986
-
do_s2io_delete_unicast_mc(sp, tmp64);
3987
-
}
3988
-
3989
-
s2io_card_down(sp);
3990
-
3991
-
return 0;
3992
-
}
3993
-
3994
-
/**
3995
-
* s2io_xmit - Tx entry point of te driver
3996
-
* @skb : the socket buffer containing the Tx data.
3997
-
* @dev : device pointer.
3998
-
* Description :
3999
-
* This function is the Tx entry point of the driver. S2IO NIC supports
4000
-
* certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4001
-
* NOTE: when device can't queue the pkt,just the trans_start variable will
4002
-
* not be upadted.
4003
-
* Return value:
4004
-
* 0 on success & 1 on failure.
4005
-
*/
4006
-
4007
-
static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4008
-
{
4009
-
struct s2io_nic *sp = netdev_priv(dev);
4010
-
u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4011
-
register u64 val64;
4012
-
struct TxD *txdp;
4013
-
struct TxFIFO_element __iomem *tx_fifo;
4014
-
unsigned long flags = 0;
4015
-
u16 vlan_tag = 0;
4016
-
struct fifo_info *fifo = NULL;
4017
-
int offload_type;
4018
-
int enable_per_list_interrupt = 0;
4019
-
struct config_param *config = &sp->config;
4020
-
struct mac_info *mac_control = &sp->mac_control;
4021
-
struct stat_block *stats = mac_control->stats_info;
4022
-
struct swStat *swstats = &stats->sw_stat;
4023
-
4024
-
DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4025
-
4026
-
if (unlikely(skb->len <= 0)) {
4027
-
DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4028
-
dev_kfree_skb_any(skb);
4029
-
return NETDEV_TX_OK;
4030
-
}
4031
-
4032
-
if (!is_s2io_card_up(sp)) {
4033
-
DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4034
-
dev->name);
4035
-
dev_kfree_skb_any(skb);
4036
-
return NETDEV_TX_OK;
4037
-
}
4038
-
4039
-
queue = 0;
4040
-
if (skb_vlan_tag_present(skb))
4041
-
vlan_tag = skb_vlan_tag_get(skb);
4042
-
if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4043
-
if (skb->protocol == htons(ETH_P_IP)) {
4044
-
struct iphdr *ip;
4045
-
struct tcphdr *th;
4046
-
ip = ip_hdr(skb);
4047
-
4048
-
if (!ip_is_fragment(ip)) {
4049
-
th = (struct tcphdr *)(((unsigned char *)ip) +
4050
-
ip->ihl*4);
4051
-
4052
-
if (ip->protocol == IPPROTO_TCP) {
4053
-
queue_len = sp->total_tcp_fifos;
4054
-
queue = (ntohs(th->source) +
4055
-
ntohs(th->dest)) &
4056
-
sp->fifo_selector[queue_len - 1];
4057
-
if (queue >= queue_len)
4058
-
queue = queue_len - 1;
4059
-
} else if (ip->protocol == IPPROTO_UDP) {
4060
-
queue_len = sp->total_udp_fifos;
4061
-
queue = (ntohs(th->source) +
4062
-
ntohs(th->dest)) &
4063
-
sp->fifo_selector[queue_len - 1];
4064
-
if (queue >= queue_len)
4065
-
queue = queue_len - 1;
4066
-
queue += sp->udp_fifo_idx;
4067
-
if (skb->len > 1024)
4068
-
enable_per_list_interrupt = 1;
4069
-
}
4070
-
}
4071
-
}
4072
-
} else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4073
-
/* get fifo number based on skb->priority value */
4074
-
queue = config->fifo_mapping
4075
-
[skb->priority & (MAX_TX_FIFOS - 1)];
4076
-
fifo = &mac_control->fifos[queue];
4077
-
4078
-
spin_lock_irqsave(&fifo->tx_lock, flags);
4079
-
4080
-
if (sp->config.multiq) {
4081
-
if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4082
-
spin_unlock_irqrestore(&fifo->tx_lock, flags);
4083
-
return NETDEV_TX_BUSY;
4084
-
}
4085
-
} else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4086
-
if (netif_queue_stopped(dev)) {
4087
-
spin_unlock_irqrestore(&fifo->tx_lock, flags);
4088
-
return NETDEV_TX_BUSY;
4089
-
}
4090
-
}
4091
-
4092
-
put_off = (u16)fifo->tx_curr_put_info.offset;
4093
-
get_off = (u16)fifo->tx_curr_get_info.offset;
4094
-
txdp = fifo->list_info[put_off].list_virt_addr;
4095
-
4096
-
queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4097
-
/* Avoid "put" pointer going beyond "get" pointer */
4098
-
if (txdp->Host_Control ||
4099
-
((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4100
-
DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4101
-
s2io_stop_tx_queue(sp, fifo->fifo_no);
4102
-
dev_kfree_skb_any(skb);
4103
-
spin_unlock_irqrestore(&fifo->tx_lock, flags);
4104
-
return NETDEV_TX_OK;
4105
-
}
4106
-
4107
-
offload_type = s2io_offload_type(skb);
4108
-
if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4109
-
txdp->Control_1 |= TXD_TCP_LSO_EN;
4110
-
txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4111
-
}
4112
-
if (skb->ip_summed == CHECKSUM_PARTIAL) {
4113
-
txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4114
-
TXD_TX_CKO_TCP_EN |
4115
-
TXD_TX_CKO_UDP_EN);
4116
-
}
4117
-
txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4118
-
txdp->Control_1 |= TXD_LIST_OWN_XENA;
4119
-
txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4120
-
if (enable_per_list_interrupt)
4121
-
if (put_off & (queue_len >> 5))
4122
-
txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4123
-
if (vlan_tag) {
4124
-
txdp->Control_2 |= TXD_VLAN_ENABLE;
4125
-
txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4126
-
}
4127
-
4128
-
frg_len = skb_headlen(skb);
4129
-
txdp->Buffer_Pointer = dma_map_single(&sp->pdev->dev, skb->data,
4130
-
frg_len, DMA_TO_DEVICE);
4131
-
if (dma_mapping_error(&sp->pdev->dev, txdp->Buffer_Pointer))
4132
-
goto pci_map_failed;
4133
-
4134
-
txdp->Host_Control = (unsigned long)skb;
4135
-
txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4136
-
4137
-
frg_cnt = skb_shinfo(skb)->nr_frags;
4138
-
/* For fragmented SKB. */
4139
-
for (i = 0; i < frg_cnt; i++) {
4140
-
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4141
-
/* A '0' length fragment will be ignored */
4142
-
if (!skb_frag_size(frag))
4143
-
continue;
4144
-
txdp++;
4145
-
txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev,
4146
-
frag, 0,
4147
-
skb_frag_size(frag),
4148
-
DMA_TO_DEVICE);
4149
-
txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag));
4150
-
}
4151
-
txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4152
-
4153
-
tx_fifo = mac_control->tx_FIFO_start[queue];
4154
-
val64 = fifo->list_info[put_off].list_phy_addr;
4155
-
writeq(val64, &tx_fifo->TxDL_Pointer);
4156
-
4157
-
val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4158
-
TX_FIFO_LAST_LIST);
4159
-
if (offload_type)
4160
-
val64 |= TX_FIFO_SPECIAL_FUNC;
4161
-
4162
-
writeq(val64, &tx_fifo->List_Control);
4163
-
4164
-
put_off++;
4165
-
if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4166
-
put_off = 0;
4167
-
fifo->tx_curr_put_info.offset = put_off;
4168
-
4169
-
/* Avoid "put" pointer going beyond "get" pointer */
4170
-
if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4171
-
swstats->fifo_full_cnt++;
4172
-
DBG_PRINT(TX_DBG,
4173
-
"No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4174
-
put_off, get_off);
4175
-
s2io_stop_tx_queue(sp, fifo->fifo_no);
4176
-
}
4177
-
swstats->mem_allocated += skb->truesize;
4178
-
spin_unlock_irqrestore(&fifo->tx_lock, flags);
4179
-
4180
-
if (sp->config.intr_type == MSI_X)
4181
-
tx_intr_handler(fifo);
4182
-
4183
-
return NETDEV_TX_OK;
4184
-
4185
-
pci_map_failed:
4186
-
swstats->pci_map_fail_cnt++;
4187
-
s2io_stop_tx_queue(sp, fifo->fifo_no);
4188
-
swstats->mem_freed += skb->truesize;
4189
-
dev_kfree_skb_any(skb);
4190
-
spin_unlock_irqrestore(&fifo->tx_lock, flags);
4191
-
return NETDEV_TX_OK;
4192
-
}
4193
-
4194
-
static void
4195
-
s2io_alarm_handle(struct timer_list *t)
4196
-
{
4197
-
struct s2io_nic *sp = timer_container_of(sp, t, alarm_timer);
4198
-
struct net_device *dev = sp->dev;
4199
-
4200
-
s2io_handle_errors(dev);
4201
-
mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4202
-
}
4203
-
4204
-
static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4205
-
{
4206
-
struct ring_info *ring = (struct ring_info *)dev_id;
4207
-
struct s2io_nic *sp = ring->nic;
4208
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4209
-
4210
-
if (unlikely(!is_s2io_card_up(sp)))
4211
-
return IRQ_HANDLED;
4212
-
4213
-
if (sp->config.napi) {
4214
-
u8 __iomem *addr = NULL;
4215
-
u8 val8 = 0;
4216
-
4217
-
addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4218
-
addr += (7 - ring->ring_no);
4219
-
val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4220
-
writeb(val8, addr);
4221
-
val8 = readb(addr);
4222
-
napi_schedule(&ring->napi);
4223
-
} else {
4224
-
rx_intr_handler(ring, 0);
4225
-
s2io_chk_rx_buffers(sp, ring);
4226
-
}
4227
-
4228
-
return IRQ_HANDLED;
4229
-
}
4230
-
4231
-
static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4232
-
{
4233
-
int i;
4234
-
struct fifo_info *fifos = (struct fifo_info *)dev_id;
4235
-
struct s2io_nic *sp = fifos->nic;
4236
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4237
-
struct config_param *config = &sp->config;
4238
-
u64 reason;
4239
-
4240
-
if (unlikely(!is_s2io_card_up(sp)))
4241
-
return IRQ_NONE;
4242
-
4243
-
reason = readq(&bar0->general_int_status);
4244
-
if (unlikely(reason == S2IO_MINUS_ONE))
4245
-
/* Nothing much can be done. Get out */
4246
-
return IRQ_HANDLED;
4247
-
4248
-
if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4249
-
writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4250
-
4251
-
if (reason & GEN_INTR_TXPIC)
4252
-
s2io_txpic_intr_handle(sp);
4253
-
4254
-
if (reason & GEN_INTR_TXTRAFFIC)
4255
-
writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4256
-
4257
-
for (i = 0; i < config->tx_fifo_num; i++)
4258
-
tx_intr_handler(&fifos[i]);
4259
-
4260
-
writeq(sp->general_int_mask, &bar0->general_int_mask);
4261
-
readl(&bar0->general_int_status);
4262
-
return IRQ_HANDLED;
4263
-
}
4264
-
/* The interrupt was not raised by us */
4265
-
return IRQ_NONE;
4266
-
}
4267
-
4268
-
static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4269
-
{
4270
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4271
-
u64 val64;
4272
-
4273
-
val64 = readq(&bar0->pic_int_status);
4274
-
if (val64 & PIC_INT_GPIO) {
4275
-
val64 = readq(&bar0->gpio_int_reg);
4276
-
if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4277
-
(val64 & GPIO_INT_REG_LINK_UP)) {
4278
-
/*
4279
-
* This is unstable state so clear both up/down
4280
-
* interrupt and adapter to re-evaluate the link state.
4281
-
*/
4282
-
val64 |= GPIO_INT_REG_LINK_DOWN;
4283
-
val64 |= GPIO_INT_REG_LINK_UP;
4284
-
writeq(val64, &bar0->gpio_int_reg);
4285
-
val64 = readq(&bar0->gpio_int_mask);
4286
-
val64 &= ~(GPIO_INT_MASK_LINK_UP |
4287
-
GPIO_INT_MASK_LINK_DOWN);
4288
-
writeq(val64, &bar0->gpio_int_mask);
4289
-
} else if (val64 & GPIO_INT_REG_LINK_UP) {
4290
-
val64 = readq(&bar0->adapter_status);
4291
-
/* Enable Adapter */
4292
-
val64 = readq(&bar0->adapter_control);
4293
-
val64 |= ADAPTER_CNTL_EN;
4294
-
writeq(val64, &bar0->adapter_control);
4295
-
val64 |= ADAPTER_LED_ON;
4296
-
writeq(val64, &bar0->adapter_control);
4297
-
if (!sp->device_enabled_once)
4298
-
sp->device_enabled_once = 1;
4299
-
4300
-
s2io_link(sp, LINK_UP);
4301
-
/*
4302
-
* unmask link down interrupt and mask link-up
4303
-
* intr
4304
-
*/
4305
-
val64 = readq(&bar0->gpio_int_mask);
4306
-
val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4307
-
val64 |= GPIO_INT_MASK_LINK_UP;
4308
-
writeq(val64, &bar0->gpio_int_mask);
4309
-
4310
-
} else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4311
-
val64 = readq(&bar0->adapter_status);
4312
-
s2io_link(sp, LINK_DOWN);
4313
-
/* Link is down so unmaks link up interrupt */
4314
-
val64 = readq(&bar0->gpio_int_mask);
4315
-
val64 &= ~GPIO_INT_MASK_LINK_UP;
4316
-
val64 |= GPIO_INT_MASK_LINK_DOWN;
4317
-
writeq(val64, &bar0->gpio_int_mask);
4318
-
4319
-
/* turn off LED */
4320
-
val64 = readq(&bar0->adapter_control);
4321
-
val64 = val64 & (~ADAPTER_LED_ON);
4322
-
writeq(val64, &bar0->adapter_control);
4323
-
}
4324
-
}
4325
-
val64 = readq(&bar0->gpio_int_mask);
4326
-
}
4327
-
4328
-
/**
4329
-
* do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4330
-
* @value: alarm bits
4331
-
* @addr: address value
4332
-
* @cnt: counter variable
4333
-
* Description: Check for alarm and increment the counter
4334
-
* Return Value:
4335
-
* 1 - if alarm bit set
4336
-
* 0 - if alarm bit is not set
4337
-
*/
4338
-
static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4339
-
unsigned long long *cnt)
4340
-
{
4341
-
u64 val64;
4342
-
val64 = readq(addr);
4343
-
if (val64 & value) {
4344
-
writeq(val64, addr);
4345
-
(*cnt)++;
4346
-
return 1;
4347
-
}
4348
-
return 0;
4349
-
4350
-
}
4351
-
4352
-
/**
4353
-
* s2io_handle_errors - Xframe error indication handler
4354
-
* @dev_id: opaque handle to dev
4355
-
* Description: Handle alarms such as loss of link, single or
4356
-
* double ECC errors, critical and serious errors.
4357
-
* Return Value:
4358
-
* NONE
4359
-
*/
4360
-
static void s2io_handle_errors(void *dev_id)
4361
-
{
4362
-
struct net_device *dev = (struct net_device *)dev_id;
4363
-
struct s2io_nic *sp = netdev_priv(dev);
4364
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4365
-
u64 temp64 = 0, val64 = 0;
4366
-
int i = 0;
4367
-
4368
-
struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4369
-
struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4370
-
4371
-
if (!is_s2io_card_up(sp))
4372
-
return;
4373
-
4374
-
if (pci_channel_offline(sp->pdev))
4375
-
return;
4376
-
4377
-
memset(&sw_stat->ring_full_cnt, 0,
4378
-
sizeof(sw_stat->ring_full_cnt));
4379
-
4380
-
/* Handling the XPAK counters update */
4381
-
if (stats->xpak_timer_count < 72000) {
4382
-
/* waiting for an hour */
4383
-
stats->xpak_timer_count++;
4384
-
} else {
4385
-
s2io_updt_xpak_counter(dev);
4386
-
/* reset the count to zero */
4387
-
stats->xpak_timer_count = 0;
4388
-
}
4389
-
4390
-
/* Handling link status change error Intr */
4391
-
if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4392
-
val64 = readq(&bar0->mac_rmac_err_reg);
4393
-
writeq(val64, &bar0->mac_rmac_err_reg);
4394
-
if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4395
-
schedule_work(&sp->set_link_task);
4396
-
}
4397
-
4398
-
/* In case of a serious error, the device will be Reset. */
4399
-
if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4400
-
&sw_stat->serious_err_cnt))
4401
-
goto reset;
4402
-
4403
-
/* Check for data parity error */
4404
-
if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4405
-
&sw_stat->parity_err_cnt))
4406
-
goto reset;
4407
-
4408
-
/* Check for ring full counter */
4409
-
if (sp->device_type == XFRAME_II_DEVICE) {
4410
-
val64 = readq(&bar0->ring_bump_counter1);
4411
-
for (i = 0; i < 4; i++) {
4412
-
temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4413
-
temp64 >>= 64 - ((i+1)*16);
4414
-
sw_stat->ring_full_cnt[i] += temp64;
4415
-
}
4416
-
4417
-
val64 = readq(&bar0->ring_bump_counter2);
4418
-
for (i = 0; i < 4; i++) {
4419
-
temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4420
-
temp64 >>= 64 - ((i+1)*16);
4421
-
sw_stat->ring_full_cnt[i+4] += temp64;
4422
-
}
4423
-
}
4424
-
4425
-
val64 = readq(&bar0->txdma_int_status);
4426
-
/*check for pfc_err*/
4427
-
if (val64 & TXDMA_PFC_INT) {
4428
-
if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4429
-
PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4430
-
PFC_PCIX_ERR,
4431
-
&bar0->pfc_err_reg,
4432
-
&sw_stat->pfc_err_cnt))
4433
-
goto reset;
4434
-
do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4435
-
&bar0->pfc_err_reg,
4436
-
&sw_stat->pfc_err_cnt);
4437
-
}
4438
-
4439
-
/*check for tda_err*/
4440
-
if (val64 & TXDMA_TDA_INT) {
4441
-
if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4442
-
TDA_SM0_ERR_ALARM |
4443
-
TDA_SM1_ERR_ALARM,
4444
-
&bar0->tda_err_reg,
4445
-
&sw_stat->tda_err_cnt))
4446
-
goto reset;
4447
-
do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4448
-
&bar0->tda_err_reg,
4449
-
&sw_stat->tda_err_cnt);
4450
-
}
4451
-
/*check for pcc_err*/
4452
-
if (val64 & TXDMA_PCC_INT) {
4453
-
if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4454
-
PCC_N_SERR | PCC_6_COF_OV_ERR |
4455
-
PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4456
-
PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4457
-
PCC_TXB_ECC_DB_ERR,
4458
-
&bar0->pcc_err_reg,
4459
-
&sw_stat->pcc_err_cnt))
4460
-
goto reset;
4461
-
do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4462
-
&bar0->pcc_err_reg,
4463
-
&sw_stat->pcc_err_cnt);
4464
-
}
4465
-
4466
-
/*check for tti_err*/
4467
-
if (val64 & TXDMA_TTI_INT) {
4468
-
if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4469
-
&bar0->tti_err_reg,
4470
-
&sw_stat->tti_err_cnt))
4471
-
goto reset;
4472
-
do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4473
-
&bar0->tti_err_reg,
4474
-
&sw_stat->tti_err_cnt);
4475
-
}
4476
-
4477
-
/*check for lso_err*/
4478
-
if (val64 & TXDMA_LSO_INT) {
4479
-
if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4480
-
LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4481
-
&bar0->lso_err_reg,
4482
-
&sw_stat->lso_err_cnt))
4483
-
goto reset;
4484
-
do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4485
-
&bar0->lso_err_reg,
4486
-
&sw_stat->lso_err_cnt);
4487
-
}
4488
-
4489
-
/*check for tpa_err*/
4490
-
if (val64 & TXDMA_TPA_INT) {
4491
-
if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4492
-
&bar0->tpa_err_reg,
4493
-
&sw_stat->tpa_err_cnt))
4494
-
goto reset;
4495
-
do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4496
-
&bar0->tpa_err_reg,
4497
-
&sw_stat->tpa_err_cnt);
4498
-
}
4499
-
4500
-
/*check for sm_err*/
4501
-
if (val64 & TXDMA_SM_INT) {
4502
-
if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4503
-
&bar0->sm_err_reg,
4504
-
&sw_stat->sm_err_cnt))
4505
-
goto reset;
4506
-
}
4507
-
4508
-
val64 = readq(&bar0->mac_int_status);
4509
-
if (val64 & MAC_INT_STATUS_TMAC_INT) {
4510
-
if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4511
-
&bar0->mac_tmac_err_reg,
4512
-
&sw_stat->mac_tmac_err_cnt))
4513
-
goto reset;
4514
-
do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4515
-
TMAC_DESC_ECC_SG_ERR |
4516
-
TMAC_DESC_ECC_DB_ERR,
4517
-
&bar0->mac_tmac_err_reg,
4518
-
&sw_stat->mac_tmac_err_cnt);
4519
-
}
4520
-
4521
-
val64 = readq(&bar0->xgxs_int_status);
4522
-
if (val64 & XGXS_INT_STATUS_TXGXS) {
4523
-
if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4524
-
&bar0->xgxs_txgxs_err_reg,
4525
-
&sw_stat->xgxs_txgxs_err_cnt))
4526
-
goto reset;
4527
-
do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4528
-
&bar0->xgxs_txgxs_err_reg,
4529
-
&sw_stat->xgxs_txgxs_err_cnt);
4530
-
}
4531
-
4532
-
val64 = readq(&bar0->rxdma_int_status);
4533
-
if (val64 & RXDMA_INT_RC_INT_M) {
4534
-
if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4535
-
RC_FTC_ECC_DB_ERR |
4536
-
RC_PRCn_SM_ERR_ALARM |
4537
-
RC_FTC_SM_ERR_ALARM,
4538
-
&bar0->rc_err_reg,
4539
-
&sw_stat->rc_err_cnt))
4540
-
goto reset;
4541
-
do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4542
-
RC_FTC_ECC_SG_ERR |
4543
-
RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4544
-
&sw_stat->rc_err_cnt);
4545
-
if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4546
-
PRC_PCI_AB_WR_Rn |
4547
-
PRC_PCI_AB_F_WR_Rn,
4548
-
&bar0->prc_pcix_err_reg,
4549
-
&sw_stat->prc_pcix_err_cnt))
4550
-
goto reset;
4551
-
do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4552
-
PRC_PCI_DP_WR_Rn |
4553
-
PRC_PCI_DP_F_WR_Rn,
4554
-
&bar0->prc_pcix_err_reg,
4555
-
&sw_stat->prc_pcix_err_cnt);
4556
-
}
4557
-
4558
-
if (val64 & RXDMA_INT_RPA_INT_M) {
4559
-
if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4560
-
&bar0->rpa_err_reg,
4561
-
&sw_stat->rpa_err_cnt))
4562
-
goto reset;
4563
-
do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4564
-
&bar0->rpa_err_reg,
4565
-
&sw_stat->rpa_err_cnt);
4566
-
}
4567
-
4568
-
if (val64 & RXDMA_INT_RDA_INT_M) {
4569
-
if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4570
-
RDA_FRM_ECC_DB_N_AERR |
4571
-
RDA_SM1_ERR_ALARM |
4572
-
RDA_SM0_ERR_ALARM |
4573
-
RDA_RXD_ECC_DB_SERR,
4574
-
&bar0->rda_err_reg,
4575
-
&sw_stat->rda_err_cnt))
4576
-
goto reset;
4577
-
do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4578
-
RDA_FRM_ECC_SG_ERR |
4579
-
RDA_MISC_ERR |
4580
-
RDA_PCIX_ERR,
4581
-
&bar0->rda_err_reg,
4582
-
&sw_stat->rda_err_cnt);
4583
-
}
4584
-
4585
-
if (val64 & RXDMA_INT_RTI_INT_M) {
4586
-
if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4587
-
&bar0->rti_err_reg,
4588
-
&sw_stat->rti_err_cnt))
4589
-
goto reset;
4590
-
do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4591
-
&bar0->rti_err_reg,
4592
-
&sw_stat->rti_err_cnt);
4593
-
}
4594
-
4595
-
val64 = readq(&bar0->mac_int_status);
4596
-
if (val64 & MAC_INT_STATUS_RMAC_INT) {
4597
-
if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4598
-
&bar0->mac_rmac_err_reg,
4599
-
&sw_stat->mac_rmac_err_cnt))
4600
-
goto reset;
4601
-
do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4602
-
RMAC_SINGLE_ECC_ERR |
4603
-
RMAC_DOUBLE_ECC_ERR,
4604
-
&bar0->mac_rmac_err_reg,
4605
-
&sw_stat->mac_rmac_err_cnt);
4606
-
}
4607
-
4608
-
val64 = readq(&bar0->xgxs_int_status);
4609
-
if (val64 & XGXS_INT_STATUS_RXGXS) {
4610
-
if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4611
-
&bar0->xgxs_rxgxs_err_reg,
4612
-
&sw_stat->xgxs_rxgxs_err_cnt))
4613
-
goto reset;
4614
-
}
4615
-
4616
-
val64 = readq(&bar0->mc_int_status);
4617
-
if (val64 & MC_INT_STATUS_MC_INT) {
4618
-
if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4619
-
&bar0->mc_err_reg,
4620
-
&sw_stat->mc_err_cnt))
4621
-
goto reset;
4622
-
4623
-
/* Handling Ecc errors */
4624
-
if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4625
-
writeq(val64, &bar0->mc_err_reg);
4626
-
if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4627
-
sw_stat->double_ecc_errs++;
4628
-
if (sp->device_type != XFRAME_II_DEVICE) {
4629
-
/*
4630
-
* Reset XframeI only if critical error
4631
-
*/
4632
-
if (val64 &
4633
-
(MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4634
-
MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4635
-
goto reset;
4636
-
}
4637
-
} else
4638
-
sw_stat->single_ecc_errs++;
4639
-
}
4640
-
}
4641
-
return;
4642
-
4643
-
reset:
4644
-
s2io_stop_all_tx_queue(sp);
4645
-
schedule_work(&sp->rst_timer_task);
4646
-
sw_stat->soft_reset_cnt++;
4647
-
}
4648
-
4649
-
/**
4650
-
* s2io_isr - ISR handler of the device .
4651
-
* @irq: the irq of the device.
4652
-
* @dev_id: a void pointer to the dev structure of the NIC.
4653
-
* Description: This function is the ISR handler of the device. It
4654
-
* identifies the reason for the interrupt and calls the relevant
4655
-
* service routines. As a contongency measure, this ISR allocates the
4656
-
* recv buffers, if their numbers are below the panic value which is
4657
-
* presently set to 25% of the original number of rcv buffers allocated.
4658
-
* Return value:
4659
-
* IRQ_HANDLED: will be returned if IRQ was handled by this routine
4660
-
* IRQ_NONE: will be returned if interrupt is not from our device
4661
-
*/
4662
-
static irqreturn_t s2io_isr(int irq, void *dev_id)
4663
-
{
4664
-
struct net_device *dev = (struct net_device *)dev_id;
4665
-
struct s2io_nic *sp = netdev_priv(dev);
4666
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4667
-
int i;
4668
-
u64 reason = 0;
4669
-
struct mac_info *mac_control;
4670
-
struct config_param *config;
4671
-
4672
-
/* Pretend we handled any irq's from a disconnected card */
4673
-
if (pci_channel_offline(sp->pdev))
4674
-
return IRQ_NONE;
4675
-
4676
-
if (!is_s2io_card_up(sp))
4677
-
return IRQ_NONE;
4678
-
4679
-
config = &sp->config;
4680
-
mac_control = &sp->mac_control;
4681
-
4682
-
/*
4683
-
* Identify the cause for interrupt and call the appropriate
4684
-
* interrupt handler. Causes for the interrupt could be;
4685
-
* 1. Rx of packet.
4686
-
* 2. Tx complete.
4687
-
* 3. Link down.
4688
-
*/
4689
-
reason = readq(&bar0->general_int_status);
4690
-
4691
-
if (unlikely(reason == S2IO_MINUS_ONE))
4692
-
return IRQ_HANDLED; /* Nothing much can be done. Get out */
4693
-
4694
-
if (reason &
4695
-
(GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4696
-
writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4697
-
4698
-
if (config->napi) {
4699
-
if (reason & GEN_INTR_RXTRAFFIC) {
4700
-
napi_schedule(&sp->napi);
4701
-
writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4702
-
writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4703
-
readl(&bar0->rx_traffic_int);
4704
-
}
4705
-
} else {
4706
-
/*
4707
-
* rx_traffic_int reg is an R1 register, writing all 1's
4708
-
* will ensure that the actual interrupt causing bit
4709
-
* gets cleared and hence a read can be avoided.
4710
-
*/
4711
-
if (reason & GEN_INTR_RXTRAFFIC)
4712
-
writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4713
-
4714
-
for (i = 0; i < config->rx_ring_num; i++) {
4715
-
struct ring_info *ring = &mac_control->rings[i];
4716
-
4717
-
rx_intr_handler(ring, 0);
4718
-
}
4719
-
}
4720
-
4721
-
/*
4722
-
* tx_traffic_int reg is an R1 register, writing all 1's
4723
-
* will ensure that the actual interrupt causing bit gets
4724
-
* cleared and hence a read can be avoided.
4725
-
*/
4726
-
if (reason & GEN_INTR_TXTRAFFIC)
4727
-
writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4728
-
4729
-
for (i = 0; i < config->tx_fifo_num; i++)
4730
-
tx_intr_handler(&mac_control->fifos[i]);
4731
-
4732
-
if (reason & GEN_INTR_TXPIC)
4733
-
s2io_txpic_intr_handle(sp);
4734
-
4735
-
/*
4736
-
* Reallocate the buffers from the interrupt handler itself.
4737
-
*/
4738
-
if (!config->napi) {
4739
-
for (i = 0; i < config->rx_ring_num; i++) {
4740
-
struct ring_info *ring = &mac_control->rings[i];
4741
-
4742
-
s2io_chk_rx_buffers(sp, ring);
4743
-
}
4744
-
}
4745
-
writeq(sp->general_int_mask, &bar0->general_int_mask);
4746
-
readl(&bar0->general_int_status);
4747
-
4748
-
return IRQ_HANDLED;
4749
-
4750
-
} else if (!reason) {
4751
-
/* The interrupt was not raised by us */
4752
-
return IRQ_NONE;
4753
-
}
4754
-
4755
-
return IRQ_HANDLED;
4756
-
}
4757
-
4758
-
/*
4759
-
* s2io_updt_stats -
4760
-
*/
4761
-
static void s2io_updt_stats(struct s2io_nic *sp)
4762
-
{
4763
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4764
-
u64 val64;
4765
-
int cnt = 0;
4766
-
4767
-
if (is_s2io_card_up(sp)) {
4768
-
/* Apprx 30us on a 133 MHz bus */
4769
-
val64 = SET_UPDT_CLICKS(10) |
4770
-
STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4771
-
writeq(val64, &bar0->stat_cfg);
4772
-
do {
4773
-
udelay(100);
4774
-
val64 = readq(&bar0->stat_cfg);
4775
-
if (!(val64 & s2BIT(0)))
4776
-
break;
4777
-
cnt++;
4778
-
if (cnt == 5)
4779
-
break; /* Updt failed */
4780
-
} while (1);
4781
-
}
4782
-
}
4783
-
4784
-
/**
4785
-
* s2io_get_stats - Updates the device statistics structure.
4786
-
* @dev : pointer to the device structure.
4787
-
* Description:
4788
-
* This function updates the device statistics structure in the s2io_nic
4789
-
* structure and returns a pointer to the same.
4790
-
* Return value:
4791
-
* pointer to the updated net_device_stats structure.
4792
-
*/
4793
-
static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4794
-
{
4795
-
struct s2io_nic *sp = netdev_priv(dev);
4796
-
struct mac_info *mac_control = &sp->mac_control;
4797
-
struct stat_block *stats = mac_control->stats_info;
4798
-
u64 delta;
4799
-
4800
-
/* Configure Stats for immediate updt */
4801
-
s2io_updt_stats(sp);
4802
-
4803
-
/* A device reset will cause the on-adapter statistics to be zero'ed.
4804
-
* This can be done while running by changing the MTU. To prevent the
4805
-
* system from having the stats zero'ed, the driver keeps a copy of the
4806
-
* last update to the system (which is also zero'ed on reset). This
4807
-
* enables the driver to accurately know the delta between the last
4808
-
* update and the current update.
4809
-
*/
4810
-
delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4811
-
le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4812
-
sp->stats.rx_packets += delta;
4813
-
dev->stats.rx_packets += delta;
4814
-
4815
-
delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4816
-
le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4817
-
sp->stats.tx_packets += delta;
4818
-
dev->stats.tx_packets += delta;
4819
-
4820
-
delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4821
-
le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4822
-
sp->stats.rx_bytes += delta;
4823
-
dev->stats.rx_bytes += delta;
4824
-
4825
-
delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4826
-
le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4827
-
sp->stats.tx_bytes += delta;
4828
-
dev->stats.tx_bytes += delta;
4829
-
4830
-
delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4831
-
sp->stats.rx_errors += delta;
4832
-
dev->stats.rx_errors += delta;
4833
-
4834
-
delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4835
-
le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4836
-
sp->stats.tx_errors += delta;
4837
-
dev->stats.tx_errors += delta;
4838
-
4839
-
delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4840
-
sp->stats.rx_dropped += delta;
4841
-
dev->stats.rx_dropped += delta;
4842
-
4843
-
delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4844
-
sp->stats.tx_dropped += delta;
4845
-
dev->stats.tx_dropped += delta;
4846
-
4847
-
/* The adapter MAC interprets pause frames as multicast packets, but
4848
-
* does not pass them up. This erroneously increases the multicast
4849
-
* packet count and needs to be deducted when the multicast frame count
4850
-
* is queried.
4851
-
*/
4852
-
delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4853
-
le32_to_cpu(stats->rmac_vld_mcst_frms);
4854
-
delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4855
-
delta -= sp->stats.multicast;
4856
-
sp->stats.multicast += delta;
4857
-
dev->stats.multicast += delta;
4858
-
4859
-
delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4860
-
le32_to_cpu(stats->rmac_usized_frms)) +
4861
-
le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4862
-
sp->stats.rx_length_errors += delta;
4863
-
dev->stats.rx_length_errors += delta;
4864
-
4865
-
delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4866
-
sp->stats.rx_crc_errors += delta;
4867
-
dev->stats.rx_crc_errors += delta;
4868
-
4869
-
return &dev->stats;
4870
-
}
4871
-
4872
-
/**
4873
-
* s2io_set_multicast - entry point for multicast address enable/disable.
4874
-
* @dev : pointer to the device structure
4875
-
* @may_sleep: parameter indicates if sleeping when waiting for command
4876
-
* complete
4877
-
* Description:
4878
-
* This function is a driver entry point which gets called by the kernel
4879
-
* whenever multicast addresses must be enabled/disabled. This also gets
4880
-
* called to set/reset promiscuous mode. Depending on the deivce flag, we
4881
-
* determine, if multicast address must be enabled or if promiscuous mode
4882
-
* is to be disabled etc.
4883
-
* Return value:
4884
-
* void.
4885
-
*/
4886
-
static void s2io_set_multicast(struct net_device *dev, bool may_sleep)
4887
-
{
4888
-
int i, j, prev_cnt;
4889
-
struct netdev_hw_addr *ha;
4890
-
struct s2io_nic *sp = netdev_priv(dev);
4891
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
4892
-
u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4893
-
0xfeffffffffffULL;
4894
-
u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4895
-
void __iomem *add;
4896
-
struct config_param *config = &sp->config;
4897
-
4898
-
if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4899
-
/* Enable all Multicast addresses */
4900
-
writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4901
-
&bar0->rmac_addr_data0_mem);
4902
-
writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4903
-
&bar0->rmac_addr_data1_mem);
4904
-
val64 = RMAC_ADDR_CMD_MEM_WE |
4905
-
RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4906
-
RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4907
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
4908
-
/* Wait till command completes */
4909
-
wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4910
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4911
-
S2IO_BIT_RESET, may_sleep);
4912
-
4913
-
sp->m_cast_flg = 1;
4914
-
sp->all_multi_pos = config->max_mc_addr - 1;
4915
-
} else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4916
-
/* Disable all Multicast addresses */
4917
-
writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4918
-
&bar0->rmac_addr_data0_mem);
4919
-
writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4920
-
&bar0->rmac_addr_data1_mem);
4921
-
val64 = RMAC_ADDR_CMD_MEM_WE |
4922
-
RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4923
-
RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4924
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
4925
-
/* Wait till command completes */
4926
-
wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4927
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4928
-
S2IO_BIT_RESET, may_sleep);
4929
-
4930
-
sp->m_cast_flg = 0;
4931
-
sp->all_multi_pos = 0;
4932
-
}
4933
-
4934
-
if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4935
-
/* Put the NIC into promiscuous mode */
4936
-
add = &bar0->mac_cfg;
4937
-
val64 = readq(&bar0->mac_cfg);
4938
-
val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4939
-
4940
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4941
-
writel((u32)val64, add);
4942
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4943
-
writel((u32) (val64 >> 32), (add + 4));
4944
-
4945
-
if (vlan_tag_strip != 1) {
4946
-
val64 = readq(&bar0->rx_pa_cfg);
4947
-
val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4948
-
writeq(val64, &bar0->rx_pa_cfg);
4949
-
sp->vlan_strip_flag = 0;
4950
-
}
4951
-
4952
-
val64 = readq(&bar0->mac_cfg);
4953
-
sp->promisc_flg = 1;
4954
-
DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4955
-
dev->name);
4956
-
} else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4957
-
/* Remove the NIC from promiscuous mode */
4958
-
add = &bar0->mac_cfg;
4959
-
val64 = readq(&bar0->mac_cfg);
4960
-
val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4961
-
4962
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4963
-
writel((u32)val64, add);
4964
-
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4965
-
writel((u32) (val64 >> 32), (add + 4));
4966
-
4967
-
if (vlan_tag_strip != 0) {
4968
-
val64 = readq(&bar0->rx_pa_cfg);
4969
-
val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4970
-
writeq(val64, &bar0->rx_pa_cfg);
4971
-
sp->vlan_strip_flag = 1;
4972
-
}
4973
-
4974
-
val64 = readq(&bar0->mac_cfg);
4975
-
sp->promisc_flg = 0;
4976
-
DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
4977
-
}
4978
-
4979
-
/* Update individual M_CAST address list */
4980
-
if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
4981
-
if (netdev_mc_count(dev) >
4982
-
(config->max_mc_addr - config->max_mac_addr)) {
4983
-
DBG_PRINT(ERR_DBG,
4984
-
"%s: No more Rx filters can be added - "
4985
-
"please enable ALL_MULTI instead\n",
4986
-
dev->name);
4987
-
return;
4988
-
}
4989
-
4990
-
prev_cnt = sp->mc_addr_count;
4991
-
sp->mc_addr_count = netdev_mc_count(dev);
4992
-
4993
-
/* Clear out the previous list of Mc in the H/W. */
4994
-
for (i = 0; i < prev_cnt; i++) {
4995
-
writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4996
-
&bar0->rmac_addr_data0_mem);
4997
-
writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4998
-
&bar0->rmac_addr_data1_mem);
4999
-
val64 = RMAC_ADDR_CMD_MEM_WE |
5000
-
RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5001
-
RMAC_ADDR_CMD_MEM_OFFSET
5002
-
(config->mc_start_offset + i);
5003
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
5004
-
5005
-
/* Wait for command completes */
5006
-
if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5007
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5008
-
S2IO_BIT_RESET, may_sleep)) {
5009
-
DBG_PRINT(ERR_DBG,
5010
-
"%s: Adding Multicasts failed\n",
5011
-
dev->name);
5012
-
return;
5013
-
}
5014
-
}
5015
-
5016
-
/* Create the new Rx filter list and update the same in H/W. */
5017
-
i = 0;
5018
-
netdev_for_each_mc_addr(ha, dev) {
5019
-
mac_addr = 0;
5020
-
for (j = 0; j < ETH_ALEN; j++) {
5021
-
mac_addr |= ha->addr[j];
5022
-
mac_addr <<= 8;
5023
-
}
5024
-
mac_addr >>= 8;
5025
-
writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5026
-
&bar0->rmac_addr_data0_mem);
5027
-
writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5028
-
&bar0->rmac_addr_data1_mem);
5029
-
val64 = RMAC_ADDR_CMD_MEM_WE |
5030
-
RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031
-
RMAC_ADDR_CMD_MEM_OFFSET
5032
-
(i + config->mc_start_offset);
5033
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
5034
-
5035
-
/* Wait for command completes */
5036
-
if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5037
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5038
-
S2IO_BIT_RESET, may_sleep)) {
5039
-
DBG_PRINT(ERR_DBG,
5040
-
"%s: Adding Multicasts failed\n",
5041
-
dev->name);
5042
-
return;
5043
-
}
5044
-
i++;
5045
-
}
5046
-
}
5047
-
}
5048
-
5049
-
/* NDO wrapper for s2io_set_multicast */
5050
-
static void s2io_ndo_set_multicast(struct net_device *dev)
5051
-
{
5052
-
s2io_set_multicast(dev, false);
5053
-
}
5054
-
5055
-
/* read from CAM unicast & multicast addresses and store it in
5056
-
* def_mac_addr structure
5057
-
*/
5058
-
static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5059
-
{
5060
-
int offset;
5061
-
u64 mac_addr = 0x0;
5062
-
struct config_param *config = &sp->config;
5063
-
5064
-
/* store unicast & multicast mac addresses */
5065
-
for (offset = 0; offset < config->max_mc_addr; offset++) {
5066
-
mac_addr = do_s2io_read_unicast_mc(sp, offset);
5067
-
/* if read fails disable the entry */
5068
-
if (mac_addr == FAILURE)
5069
-
mac_addr = S2IO_DISABLE_MAC_ENTRY;
5070
-
do_s2io_copy_mac_addr(sp, offset, mac_addr);
5071
-
}
5072
-
}
5073
-
5074
-
/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5075
-
static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5076
-
{
5077
-
int offset;
5078
-
struct config_param *config = &sp->config;
5079
-
/* restore unicast mac address */
5080
-
for (offset = 0; offset < config->max_mac_addr; offset++)
5081
-
do_s2io_prog_unicast(sp->dev,
5082
-
sp->def_mac_addr[offset].mac_addr);
5083
-
5084
-
/* restore multicast mac address */
5085
-
for (offset = config->mc_start_offset;
5086
-
offset < config->max_mc_addr; offset++)
5087
-
do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5088
-
}
5089
-
5090
-
/* add a multicast MAC address to CAM */
5091
-
static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5092
-
{
5093
-
int i;
5094
-
u64 mac_addr;
5095
-
struct config_param *config = &sp->config;
5096
-
5097
-
mac_addr = ether_addr_to_u64(addr);
5098
-
if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5099
-
return SUCCESS;
5100
-
5101
-
/* check if the multicast mac already preset in CAM */
5102
-
for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5103
-
u64 tmp64;
5104
-
tmp64 = do_s2io_read_unicast_mc(sp, i);
5105
-
if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5106
-
break;
5107
-
5108
-
if (tmp64 == mac_addr)
5109
-
return SUCCESS;
5110
-
}
5111
-
if (i == config->max_mc_addr) {
5112
-
DBG_PRINT(ERR_DBG,
5113
-
"CAM full no space left for multicast MAC\n");
5114
-
return FAILURE;
5115
-
}
5116
-
/* Update the internal structure with this new mac address */
5117
-
do_s2io_copy_mac_addr(sp, i, mac_addr);
5118
-
5119
-
return do_s2io_add_mac(sp, mac_addr, i);
5120
-
}
5121
-
5122
-
/* add MAC address to CAM */
5123
-
static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5124
-
{
5125
-
u64 val64;
5126
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5127
-
5128
-
writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5129
-
&bar0->rmac_addr_data0_mem);
5130
-
5131
-
val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5132
-
RMAC_ADDR_CMD_MEM_OFFSET(off);
5133
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
5134
-
5135
-
/* Wait till command completes */
5136
-
if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5137
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5138
-
S2IO_BIT_RESET, true)) {
5139
-
DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5140
-
return FAILURE;
5141
-
}
5142
-
return SUCCESS;
5143
-
}
5144
-
/* deletes a specified unicast/multicast mac entry from CAM */
5145
-
static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5146
-
{
5147
-
int offset;
5148
-
u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5149
-
struct config_param *config = &sp->config;
5150
-
5151
-
for (offset = 1;
5152
-
offset < config->max_mc_addr; offset++) {
5153
-
tmp64 = do_s2io_read_unicast_mc(sp, offset);
5154
-
if (tmp64 == addr) {
5155
-
/* disable the entry by writing 0xffffffffffffULL */
5156
-
if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5157
-
return FAILURE;
5158
-
/* store the new mac list from CAM */
5159
-
do_s2io_store_unicast_mc(sp);
5160
-
return SUCCESS;
5161
-
}
5162
-
}
5163
-
DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5164
-
(unsigned long long)addr);
5165
-
return FAILURE;
5166
-
}
5167
-
5168
-
/* read mac entries from CAM */
5169
-
static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5170
-
{
5171
-
u64 tmp64, val64;
5172
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5173
-
5174
-
/* read mac addr */
5175
-
val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5176
-
RMAC_ADDR_CMD_MEM_OFFSET(offset);
5177
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
5178
-
5179
-
/* Wait till command completes */
5180
-
if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5181
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5182
-
S2IO_BIT_RESET, true)) {
5183
-
DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5184
-
return FAILURE;
5185
-
}
5186
-
tmp64 = readq(&bar0->rmac_addr_data0_mem);
5187
-
5188
-
return tmp64 >> 16;
5189
-
}
5190
-
5191
-
/*
5192
-
* s2io_set_mac_addr - driver entry point
5193
-
*/
5194
-
5195
-
static int s2io_set_mac_addr(struct net_device *dev, void *p)
5196
-
{
5197
-
struct sockaddr *addr = p;
5198
-
5199
-
if (!is_valid_ether_addr(addr->sa_data))
5200
-
return -EADDRNOTAVAIL;
5201
-
5202
-
eth_hw_addr_set(dev, addr->sa_data);
5203
-
5204
-
/* store the MAC address in CAM */
5205
-
return do_s2io_prog_unicast(dev, dev->dev_addr);
5206
-
}
5207
-
/**
5208
-
* do_s2io_prog_unicast - Programs the Xframe mac address
5209
-
* @dev : pointer to the device structure.
5210
-
* @addr: a uchar pointer to the new mac address which is to be set.
5211
-
* Description : This procedure will program the Xframe to receive
5212
-
* frames with new Mac Address
5213
-
* Return value: SUCCESS on success and an appropriate (-)ve integer
5214
-
* as defined in errno.h file on failure.
5215
-
*/
5216
-
5217
-
static int do_s2io_prog_unicast(struct net_device *dev, const u8 *addr)
5218
-
{
5219
-
struct s2io_nic *sp = netdev_priv(dev);
5220
-
register u64 mac_addr, perm_addr;
5221
-
int i;
5222
-
u64 tmp64;
5223
-
struct config_param *config = &sp->config;
5224
-
5225
-
/*
5226
-
* Set the new MAC address as the new unicast filter and reflect this
5227
-
* change on the device address registered with the OS. It will be
5228
-
* at offset 0.
5229
-
*/
5230
-
mac_addr = ether_addr_to_u64(addr);
5231
-
perm_addr = ether_addr_to_u64(sp->def_mac_addr[0].mac_addr);
5232
-
5233
-
/* check if the dev_addr is different than perm_addr */
5234
-
if (mac_addr == perm_addr)
5235
-
return SUCCESS;
5236
-
5237
-
/* check if the mac already preset in CAM */
5238
-
for (i = 1; i < config->max_mac_addr; i++) {
5239
-
tmp64 = do_s2io_read_unicast_mc(sp, i);
5240
-
if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5241
-
break;
5242
-
5243
-
if (tmp64 == mac_addr) {
5244
-
DBG_PRINT(INFO_DBG,
5245
-
"MAC addr:0x%llx already present in CAM\n",
5246
-
(unsigned long long)mac_addr);
5247
-
return SUCCESS;
5248
-
}
5249
-
}
5250
-
if (i == config->max_mac_addr) {
5251
-
DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5252
-
return FAILURE;
5253
-
}
5254
-
/* Update the internal structure with this new mac address */
5255
-
do_s2io_copy_mac_addr(sp, i, mac_addr);
5256
-
5257
-
return do_s2io_add_mac(sp, mac_addr, i);
5258
-
}
5259
-
5260
-
/**
5261
-
* s2io_ethtool_set_link_ksettings - Sets different link parameters.
5262
-
* @dev : pointer to netdev
5263
-
* @cmd: pointer to the structure with parameters given by ethtool to set
5264
-
* link information.
5265
-
* Description:
5266
-
* The function sets different link parameters provided by the user onto
5267
-
* the NIC.
5268
-
* Return value:
5269
-
* 0 on success.
5270
-
*/
5271
-
5272
-
static int
5273
-
s2io_ethtool_set_link_ksettings(struct net_device *dev,
5274
-
const struct ethtool_link_ksettings *cmd)
5275
-
{
5276
-
struct s2io_nic *sp = netdev_priv(dev);
5277
-
if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
5278
-
(cmd->base.speed != SPEED_10000) ||
5279
-
(cmd->base.duplex != DUPLEX_FULL))
5280
-
return -EINVAL;
5281
-
else {
5282
-
s2io_close(sp->dev);
5283
-
s2io_open(sp->dev);
5284
-
}
5285
-
5286
-
return 0;
5287
-
}
5288
-
5289
-
/**
5290
-
* s2io_ethtool_get_link_ksettings - Return link specific information.
5291
-
* @dev: pointer to netdev
5292
-
* @cmd : pointer to the structure with parameters given by ethtool
5293
-
* to return link information.
5294
-
* Description:
5295
-
* Returns link specific information like speed, duplex etc.. to ethtool.
5296
-
* Return value :
5297
-
* return 0 on success.
5298
-
*/
5299
-
5300
-
static int
5301
-
s2io_ethtool_get_link_ksettings(struct net_device *dev,
5302
-
struct ethtool_link_ksettings *cmd)
5303
-
{
5304
-
struct s2io_nic *sp = netdev_priv(dev);
5305
-
5306
-
ethtool_link_ksettings_zero_link_mode(cmd, supported);
5307
-
ethtool_link_ksettings_add_link_mode(cmd, supported, 10000baseT_Full);
5308
-
ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
5309
-
5310
-
ethtool_link_ksettings_zero_link_mode(cmd, advertising);
5311
-
ethtool_link_ksettings_add_link_mode(cmd, advertising, 10000baseT_Full);
5312
-
ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
5313
-
5314
-
cmd->base.port = PORT_FIBRE;
5315
-
5316
-
if (netif_carrier_ok(sp->dev)) {
5317
-
cmd->base.speed = SPEED_10000;
5318
-
cmd->base.duplex = DUPLEX_FULL;
5319
-
} else {
5320
-
cmd->base.speed = SPEED_UNKNOWN;
5321
-
cmd->base.duplex = DUPLEX_UNKNOWN;
5322
-
}
5323
-
5324
-
cmd->base.autoneg = AUTONEG_DISABLE;
5325
-
return 0;
5326
-
}
5327
-
5328
-
/**
5329
-
* s2io_ethtool_gdrvinfo - Returns driver specific information.
5330
-
* @dev: pointer to netdev
5331
-
* @info : pointer to the structure with parameters given by ethtool to
5332
-
* return driver information.
5333
-
* Description:
5334
-
* Returns driver specefic information like name, version etc.. to ethtool.
5335
-
* Return value:
5336
-
* void
5337
-
*/
5338
-
5339
-
static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5340
-
struct ethtool_drvinfo *info)
5341
-
{
5342
-
struct s2io_nic *sp = netdev_priv(dev);
5343
-
5344
-
strscpy(info->driver, s2io_driver_name, sizeof(info->driver));
5345
-
strscpy(info->version, s2io_driver_version, sizeof(info->version));
5346
-
strscpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5347
-
}
5348
-
5349
-
/**
5350
-
* s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5351
-
* @dev: pointer to netdev
5352
-
* @regs : pointer to the structure with parameters given by ethtool for
5353
-
* dumping the registers.
5354
-
* @space: The input argument into which all the registers are dumped.
5355
-
* Description:
5356
-
* Dumps the entire register space of xFrame NIC into the user given
5357
-
* buffer area.
5358
-
* Return value :
5359
-
* void .
5360
-
*/
5361
-
5362
-
static void s2io_ethtool_gregs(struct net_device *dev,
5363
-
struct ethtool_regs *regs, void *space)
5364
-
{
5365
-
int i;
5366
-
u64 reg;
5367
-
u8 *reg_space = (u8 *)space;
5368
-
struct s2io_nic *sp = netdev_priv(dev);
5369
-
5370
-
regs->len = XENA_REG_SPACE;
5371
-
regs->version = sp->pdev->subsystem_device;
5372
-
5373
-
for (i = 0; i < regs->len; i += 8) {
5374
-
reg = readq(sp->bar0 + i);
5375
-
memcpy((reg_space + i), ®, 8);
5376
-
}
5377
-
}
5378
-
5379
-
/*
5380
-
* s2io_set_led - control NIC led
5381
-
*/
5382
-
static void s2io_set_led(struct s2io_nic *sp, bool on)
5383
-
{
5384
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5385
-
u16 subid = sp->pdev->subsystem_device;
5386
-
u64 val64;
5387
-
5388
-
if ((sp->device_type == XFRAME_II_DEVICE) ||
5389
-
((subid & 0xFF) >= 0x07)) {
5390
-
val64 = readq(&bar0->gpio_control);
5391
-
if (on)
5392
-
val64 |= GPIO_CTRL_GPIO_0;
5393
-
else
5394
-
val64 &= ~GPIO_CTRL_GPIO_0;
5395
-
5396
-
writeq(val64, &bar0->gpio_control);
5397
-
} else {
5398
-
val64 = readq(&bar0->adapter_control);
5399
-
if (on)
5400
-
val64 |= ADAPTER_LED_ON;
5401
-
else
5402
-
val64 &= ~ADAPTER_LED_ON;
5403
-
5404
-
writeq(val64, &bar0->adapter_control);
5405
-
}
5406
-
5407
-
}
5408
-
5409
-
/**
5410
-
* s2io_ethtool_set_led - To physically identify the nic on the system.
5411
-
* @dev : network device
5412
-
* @state: led setting
5413
-
*
5414
-
* Description: Used to physically identify the NIC on the system.
5415
-
* The Link LED will blink for a time specified by the user for
5416
-
* identification.
5417
-
* NOTE: The Link has to be Up to be able to blink the LED. Hence
5418
-
* identification is possible only if it's link is up.
5419
-
*/
5420
-
5421
-
static int s2io_ethtool_set_led(struct net_device *dev,
5422
-
enum ethtool_phys_id_state state)
5423
-
{
5424
-
struct s2io_nic *sp = netdev_priv(dev);
5425
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5426
-
u16 subid = sp->pdev->subsystem_device;
5427
-
5428
-
if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5429
-
u64 val64 = readq(&bar0->adapter_control);
5430
-
if (!(val64 & ADAPTER_CNTL_EN)) {
5431
-
pr_err("Adapter Link down, cannot blink LED\n");
5432
-
return -EAGAIN;
5433
-
}
5434
-
}
5435
-
5436
-
switch (state) {
5437
-
case ETHTOOL_ID_ACTIVE:
5438
-
sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5439
-
return 1; /* cycle on/off once per second */
5440
-
5441
-
case ETHTOOL_ID_ON:
5442
-
s2io_set_led(sp, true);
5443
-
break;
5444
-
5445
-
case ETHTOOL_ID_OFF:
5446
-
s2io_set_led(sp, false);
5447
-
break;
5448
-
5449
-
case ETHTOOL_ID_INACTIVE:
5450
-
if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5451
-
writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5452
-
}
5453
-
5454
-
return 0;
5455
-
}
5456
-
5457
-
static void
5458
-
s2io_ethtool_gringparam(struct net_device *dev,
5459
-
struct ethtool_ringparam *ering,
5460
-
struct kernel_ethtool_ringparam *kernel_ering,
5461
-
struct netlink_ext_ack *extack)
5462
-
{
5463
-
struct s2io_nic *sp = netdev_priv(dev);
5464
-
int i, tx_desc_count = 0, rx_desc_count = 0;
5465
-
5466
-
if (sp->rxd_mode == RXD_MODE_1) {
5467
-
ering->rx_max_pending = MAX_RX_DESC_1;
5468
-
ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5469
-
} else {
5470
-
ering->rx_max_pending = MAX_RX_DESC_2;
5471
-
ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5472
-
}
5473
-
5474
-
ering->tx_max_pending = MAX_TX_DESC;
5475
-
5476
-
for (i = 0; i < sp->config.rx_ring_num; i++)
5477
-
rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5478
-
ering->rx_pending = rx_desc_count;
5479
-
ering->rx_jumbo_pending = rx_desc_count;
5480
-
5481
-
for (i = 0; i < sp->config.tx_fifo_num; i++)
5482
-
tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5483
-
ering->tx_pending = tx_desc_count;
5484
-
DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5485
-
}
5486
-
5487
-
/**
5488
-
* s2io_ethtool_getpause_data -Pause frame generation and reception.
5489
-
* @dev: pointer to netdev
5490
-
* @ep : pointer to the structure with pause parameters given by ethtool.
5491
-
* Description:
5492
-
* Returns the Pause frame generation and reception capability of the NIC.
5493
-
* Return value:
5494
-
* void
5495
-
*/
5496
-
static void s2io_ethtool_getpause_data(struct net_device *dev,
5497
-
struct ethtool_pauseparam *ep)
5498
-
{
5499
-
u64 val64;
5500
-
struct s2io_nic *sp = netdev_priv(dev);
5501
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5502
-
5503
-
val64 = readq(&bar0->rmac_pause_cfg);
5504
-
if (val64 & RMAC_PAUSE_GEN_ENABLE)
5505
-
ep->tx_pause = true;
5506
-
if (val64 & RMAC_PAUSE_RX_ENABLE)
5507
-
ep->rx_pause = true;
5508
-
ep->autoneg = false;
5509
-
}
5510
-
5511
-
/**
5512
-
* s2io_ethtool_setpause_data - set/reset pause frame generation.
5513
-
* @dev: pointer to netdev
5514
-
* @ep : pointer to the structure with pause parameters given by ethtool.
5515
-
* Description:
5516
-
* It can be used to set or reset Pause frame generation or reception
5517
-
* support of the NIC.
5518
-
* Return value:
5519
-
* int, returns 0 on Success
5520
-
*/
5521
-
5522
-
static int s2io_ethtool_setpause_data(struct net_device *dev,
5523
-
struct ethtool_pauseparam *ep)
5524
-
{
5525
-
u64 val64;
5526
-
struct s2io_nic *sp = netdev_priv(dev);
5527
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5528
-
5529
-
val64 = readq(&bar0->rmac_pause_cfg);
5530
-
if (ep->tx_pause)
5531
-
val64 |= RMAC_PAUSE_GEN_ENABLE;
5532
-
else
5533
-
val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5534
-
if (ep->rx_pause)
5535
-
val64 |= RMAC_PAUSE_RX_ENABLE;
5536
-
else
5537
-
val64 &= ~RMAC_PAUSE_RX_ENABLE;
5538
-
writeq(val64, &bar0->rmac_pause_cfg);
5539
-
return 0;
5540
-
}
5541
-
5542
-
#define S2IO_DEV_ID 5
5543
-
/**
5544
-
* read_eeprom - reads 4 bytes of data from user given offset.
5545
-
* @sp : private member of the device structure, which is a pointer to the
5546
-
* s2io_nic structure.
5547
-
* @off : offset at which the data must be written
5548
-
* @data : Its an output parameter where the data read at the given
5549
-
* offset is stored.
5550
-
* Description:
5551
-
* Will read 4 bytes of data from the user given offset and return the
5552
-
* read data.
5553
-
* NOTE: Will allow to read only part of the EEPROM visible through the
5554
-
* I2C bus.
5555
-
* Return value:
5556
-
* -1 on failure and 0 on success.
5557
-
*/
5558
-
static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5559
-
{
5560
-
int ret = -1;
5561
-
u32 exit_cnt = 0;
5562
-
u64 val64;
5563
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5564
-
5565
-
if (sp->device_type == XFRAME_I_DEVICE) {
5566
-
val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5567
-
I2C_CONTROL_ADDR(off) |
5568
-
I2C_CONTROL_BYTE_CNT(0x3) |
5569
-
I2C_CONTROL_READ |
5570
-
I2C_CONTROL_CNTL_START;
5571
-
SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5572
-
5573
-
while (exit_cnt < 5) {
5574
-
val64 = readq(&bar0->i2c_control);
5575
-
if (I2C_CONTROL_CNTL_END(val64)) {
5576
-
*data = I2C_CONTROL_GET_DATA(val64);
5577
-
ret = 0;
5578
-
break;
5579
-
}
5580
-
msleep(50);
5581
-
exit_cnt++;
5582
-
}
5583
-
}
5584
-
5585
-
if (sp->device_type == XFRAME_II_DEVICE) {
5586
-
val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5587
-
SPI_CONTROL_BYTECNT(0x3) |
5588
-
SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5589
-
SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5590
-
val64 |= SPI_CONTROL_REQ;
5591
-
SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5592
-
while (exit_cnt < 5) {
5593
-
val64 = readq(&bar0->spi_control);
5594
-
if (val64 & SPI_CONTROL_NACK) {
5595
-
ret = 1;
5596
-
break;
5597
-
} else if (val64 & SPI_CONTROL_DONE) {
5598
-
*data = readq(&bar0->spi_data);
5599
-
*data &= 0xffffff;
5600
-
ret = 0;
5601
-
break;
5602
-
}
5603
-
msleep(50);
5604
-
exit_cnt++;
5605
-
}
5606
-
}
5607
-
return ret;
5608
-
}
5609
-
5610
-
/**
5611
-
* write_eeprom - actually writes the relevant part of the data value.
5612
-
* @sp : private member of the device structure, which is a pointer to the
5613
-
* s2io_nic structure.
5614
-
* @off : offset at which the data must be written
5615
-
* @data : The data that is to be written
5616
-
* @cnt : Number of bytes of the data that are actually to be written into
5617
-
* the Eeprom. (max of 3)
5618
-
* Description:
5619
-
* Actually writes the relevant part of the data value into the Eeprom
5620
-
* through the I2C bus.
5621
-
* Return value:
5622
-
* 0 on success, -1 on failure.
5623
-
*/
5624
-
5625
-
static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5626
-
{
5627
-
int exit_cnt = 0, ret = -1;
5628
-
u64 val64;
5629
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5630
-
5631
-
if (sp->device_type == XFRAME_I_DEVICE) {
5632
-
val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5633
-
I2C_CONTROL_ADDR(off) |
5634
-
I2C_CONTROL_BYTE_CNT(cnt) |
5635
-
I2C_CONTROL_SET_DATA((u32)data) |
5636
-
I2C_CONTROL_CNTL_START;
5637
-
SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5638
-
5639
-
while (exit_cnt < 5) {
5640
-
val64 = readq(&bar0->i2c_control);
5641
-
if (I2C_CONTROL_CNTL_END(val64)) {
5642
-
if (!(val64 & I2C_CONTROL_NACK))
5643
-
ret = 0;
5644
-
break;
5645
-
}
5646
-
msleep(50);
5647
-
exit_cnt++;
5648
-
}
5649
-
}
5650
-
5651
-
if (sp->device_type == XFRAME_II_DEVICE) {
5652
-
int write_cnt = (cnt == 8) ? 0 : cnt;
5653
-
writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5654
-
5655
-
val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5656
-
SPI_CONTROL_BYTECNT(write_cnt) |
5657
-
SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5658
-
SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5659
-
val64 |= SPI_CONTROL_REQ;
5660
-
SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5661
-
while (exit_cnt < 5) {
5662
-
val64 = readq(&bar0->spi_control);
5663
-
if (val64 & SPI_CONTROL_NACK) {
5664
-
ret = 1;
5665
-
break;
5666
-
} else if (val64 & SPI_CONTROL_DONE) {
5667
-
ret = 0;
5668
-
break;
5669
-
}
5670
-
msleep(50);
5671
-
exit_cnt++;
5672
-
}
5673
-
}
5674
-
return ret;
5675
-
}
5676
-
static void s2io_vpd_read(struct s2io_nic *nic)
5677
-
{
5678
-
u8 *vpd_data;
5679
-
u8 data;
5680
-
int i = 0, cnt, len, fail = 0;
5681
-
int vpd_addr = 0x80;
5682
-
struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5683
-
5684
-
if (nic->device_type == XFRAME_II_DEVICE) {
5685
-
strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5686
-
vpd_addr = 0x80;
5687
-
} else {
5688
-
strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5689
-
vpd_addr = 0x50;
5690
-
}
5691
-
strcpy(nic->serial_num, "NOT AVAILABLE");
5692
-
5693
-
vpd_data = kmalloc(256, GFP_KERNEL);
5694
-
if (!vpd_data) {
5695
-
swstats->mem_alloc_fail_cnt++;
5696
-
return;
5697
-
}
5698
-
swstats->mem_allocated += 256;
5699
-
5700
-
for (i = 0; i < 256; i += 4) {
5701
-
pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5702
-
pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5703
-
pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5704
-
for (cnt = 0; cnt < 5; cnt++) {
5705
-
msleep(2);
5706
-
pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5707
-
if (data == 0x80)
5708
-
break;
5709
-
}
5710
-
if (cnt >= 5) {
5711
-
DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5712
-
fail = 1;
5713
-
break;
5714
-
}
5715
-
pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5716
-
(u32 *)&vpd_data[i]);
5717
-
}
5718
-
5719
-
if (!fail) {
5720
-
/* read serial number of adapter */
5721
-
for (cnt = 0; cnt < 252; cnt++) {
5722
-
if ((vpd_data[cnt] == 'S') &&
5723
-
(vpd_data[cnt+1] == 'N')) {
5724
-
len = vpd_data[cnt+2];
5725
-
if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5726
-
memcpy(nic->serial_num,
5727
-
&vpd_data[cnt + 3],
5728
-
len);
5729
-
memset(nic->serial_num+len,
5730
-
0,
5731
-
VPD_STRING_LEN-len);
5732
-
break;
5733
-
}
5734
-
}
5735
-
}
5736
-
}
5737
-
5738
-
if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5739
-
len = vpd_data[1];
5740
-
memcpy(nic->product_name, &vpd_data[3], len);
5741
-
nic->product_name[len] = 0;
5742
-
}
5743
-
kfree(vpd_data);
5744
-
swstats->mem_freed += 256;
5745
-
}
5746
-
5747
-
/**
5748
-
* s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5749
-
* @dev: pointer to netdev
5750
-
* @eeprom : pointer to the user level structure provided by ethtool,
5751
-
* containing all relevant information.
5752
-
* @data_buf : user defined value to be written into Eeprom.
5753
-
* Description: Reads the values stored in the Eeprom at given offset
5754
-
* for a given length. Stores these values int the input argument data
5755
-
* buffer 'data_buf' and returns these to the caller (ethtool.)
5756
-
* Return value:
5757
-
* int 0 on success
5758
-
*/
5759
-
5760
-
static int s2io_ethtool_geeprom(struct net_device *dev,
5761
-
struct ethtool_eeprom *eeprom, u8 * data_buf)
5762
-
{
5763
-
u32 i, valid;
5764
-
u64 data;
5765
-
struct s2io_nic *sp = netdev_priv(dev);
5766
-
5767
-
eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5768
-
5769
-
if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5770
-
eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5771
-
5772
-
for (i = 0; i < eeprom->len; i += 4) {
5773
-
if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5774
-
DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5775
-
return -EFAULT;
5776
-
}
5777
-
valid = INV(data);
5778
-
memcpy((data_buf + i), &valid, 4);
5779
-
}
5780
-
return 0;
5781
-
}
5782
-
5783
-
/**
5784
-
* s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5785
-
* @dev: pointer to netdev
5786
-
* @eeprom : pointer to the user level structure provided by ethtool,
5787
-
* containing all relevant information.
5788
-
* @data_buf : user defined value to be written into Eeprom.
5789
-
* Description:
5790
-
* Tries to write the user provided value in the Eeprom, at the offset
5791
-
* given by the user.
5792
-
* Return value:
5793
-
* 0 on success, -EFAULT on failure.
5794
-
*/
5795
-
5796
-
static int s2io_ethtool_seeprom(struct net_device *dev,
5797
-
struct ethtool_eeprom *eeprom,
5798
-
u8 *data_buf)
5799
-
{
5800
-
int len = eeprom->len, cnt = 0;
5801
-
u64 valid = 0, data;
5802
-
struct s2io_nic *sp = netdev_priv(dev);
5803
-
5804
-
if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5805
-
DBG_PRINT(ERR_DBG,
5806
-
"ETHTOOL_WRITE_EEPROM Err: "
5807
-
"Magic value is wrong, it is 0x%x should be 0x%x\n",
5808
-
(sp->pdev->vendor | (sp->pdev->device << 16)),
5809
-
eeprom->magic);
5810
-
return -EFAULT;
5811
-
}
5812
-
5813
-
while (len) {
5814
-
data = (u32)data_buf[cnt] & 0x000000FF;
5815
-
if (data)
5816
-
valid = (u32)(data << 24);
5817
-
else
5818
-
valid = data;
5819
-
5820
-
if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5821
-
DBG_PRINT(ERR_DBG,
5822
-
"ETHTOOL_WRITE_EEPROM Err: "
5823
-
"Cannot write into the specified offset\n");
5824
-
return -EFAULT;
5825
-
}
5826
-
cnt++;
5827
-
len--;
5828
-
}
5829
-
5830
-
return 0;
5831
-
}
5832
-
5833
-
/**
5834
-
* s2io_register_test - reads and writes into all clock domains.
5835
-
* @sp : private member of the device structure, which is a pointer to the
5836
-
* s2io_nic structure.
5837
-
* @data : variable that returns the result of each of the test conducted b
5838
-
* by the driver.
5839
-
* Description:
5840
-
* Read and write into all clock domains. The NIC has 3 clock domains,
5841
-
* see that registers in all the three regions are accessible.
5842
-
* Return value:
5843
-
* 0 on success.
5844
-
*/
5845
-
5846
-
static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5847
-
{
5848
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
5849
-
u64 val64 = 0, exp_val;
5850
-
int fail = 0;
5851
-
5852
-
val64 = readq(&bar0->pif_rd_swapper_fb);
5853
-
if (val64 != 0x123456789abcdefULL) {
5854
-
fail = 1;
5855
-
DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5856
-
}
5857
-
5858
-
val64 = readq(&bar0->rmac_pause_cfg);
5859
-
if (val64 != 0xc000ffff00000000ULL) {
5860
-
fail = 1;
5861
-
DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5862
-
}
5863
-
5864
-
val64 = readq(&bar0->rx_queue_cfg);
5865
-
if (sp->device_type == XFRAME_II_DEVICE)
5866
-
exp_val = 0x0404040404040404ULL;
5867
-
else
5868
-
exp_val = 0x0808080808080808ULL;
5869
-
if (val64 != exp_val) {
5870
-
fail = 1;
5871
-
DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5872
-
}
5873
-
5874
-
val64 = readq(&bar0->xgxs_efifo_cfg);
5875
-
if (val64 != 0x000000001923141EULL) {
5876
-
fail = 1;
5877
-
DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5878
-
}
5879
-
5880
-
val64 = 0x5A5A5A5A5A5A5A5AULL;
5881
-
writeq(val64, &bar0->xmsi_data);
5882
-
val64 = readq(&bar0->xmsi_data);
5883
-
if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5884
-
fail = 1;
5885
-
DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5886
-
}
5887
-
5888
-
val64 = 0xA5A5A5A5A5A5A5A5ULL;
5889
-
writeq(val64, &bar0->xmsi_data);
5890
-
val64 = readq(&bar0->xmsi_data);
5891
-
if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5892
-
fail = 1;
5893
-
DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5894
-
}
5895
-
5896
-
*data = fail;
5897
-
return fail;
5898
-
}
5899
-
5900
-
/**
5901
-
* s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5902
-
* @sp : private member of the device structure, which is a pointer to the
5903
-
* s2io_nic structure.
5904
-
* @data:variable that returns the result of each of the test conducted by
5905
-
* the driver.
5906
-
* Description:
5907
-
* Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5908
-
* register.
5909
-
* Return value:
5910
-
* 0 on success.
5911
-
*/
5912
-
5913
-
static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5914
-
{
5915
-
int fail = 0;
5916
-
u64 ret_data, org_4F0, org_7F0;
5917
-
u8 saved_4F0 = 0, saved_7F0 = 0;
5918
-
struct net_device *dev = sp->dev;
5919
-
5920
-
/* Test Write Error at offset 0 */
5921
-
/* Note that SPI interface allows write access to all areas
5922
-
* of EEPROM. Hence doing all negative testing only for Xframe I.
5923
-
*/
5924
-
if (sp->device_type == XFRAME_I_DEVICE)
5925
-
if (!write_eeprom(sp, 0, 0, 3))
5926
-
fail = 1;
5927
-
5928
-
/* Save current values at offsets 0x4F0 and 0x7F0 */
5929
-
if (!read_eeprom(sp, 0x4F0, &org_4F0))
5930
-
saved_4F0 = 1;
5931
-
if (!read_eeprom(sp, 0x7F0, &org_7F0))
5932
-
saved_7F0 = 1;
5933
-
5934
-
/* Test Write at offset 4f0 */
5935
-
if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5936
-
fail = 1;
5937
-
if (read_eeprom(sp, 0x4F0, &ret_data))
5938
-
fail = 1;
5939
-
5940
-
if (ret_data != 0x012345) {
5941
-
DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5942
-
"Data written %llx Data read %llx\n",
5943
-
dev->name, (unsigned long long)0x12345,
5944
-
(unsigned long long)ret_data);
5945
-
fail = 1;
5946
-
}
5947
-
5948
-
/* Reset the EEPROM data go FFFF */
5949
-
write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5950
-
5951
-
/* Test Write Request Error at offset 0x7c */
5952
-
if (sp->device_type == XFRAME_I_DEVICE)
5953
-
if (!write_eeprom(sp, 0x07C, 0, 3))
5954
-
fail = 1;
5955
-
5956
-
/* Test Write Request at offset 0x7f0 */
5957
-
if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5958
-
fail = 1;
5959
-
if (read_eeprom(sp, 0x7F0, &ret_data))
5960
-
fail = 1;
5961
-
5962
-
if (ret_data != 0x012345) {
5963
-
DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5964
-
"Data written %llx Data read %llx\n",
5965
-
dev->name, (unsigned long long)0x12345,
5966
-
(unsigned long long)ret_data);
5967
-
fail = 1;
5968
-
}
5969
-
5970
-
/* Reset the EEPROM data go FFFF */
5971
-
write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5972
-
5973
-
if (sp->device_type == XFRAME_I_DEVICE) {
5974
-
/* Test Write Error at offset 0x80 */
5975
-
if (!write_eeprom(sp, 0x080, 0, 3))
5976
-
fail = 1;
5977
-
5978
-
/* Test Write Error at offset 0xfc */
5979
-
if (!write_eeprom(sp, 0x0FC, 0, 3))
5980
-
fail = 1;
5981
-
5982
-
/* Test Write Error at offset 0x100 */
5983
-
if (!write_eeprom(sp, 0x100, 0, 3))
5984
-
fail = 1;
5985
-
5986
-
/* Test Write Error at offset 4ec */
5987
-
if (!write_eeprom(sp, 0x4EC, 0, 3))
5988
-
fail = 1;
5989
-
}
5990
-
5991
-
/* Restore values at offsets 0x4F0 and 0x7F0 */
5992
-
if (saved_4F0)
5993
-
write_eeprom(sp, 0x4F0, org_4F0, 3);
5994
-
if (saved_7F0)
5995
-
write_eeprom(sp, 0x7F0, org_7F0, 3);
5996
-
5997
-
*data = fail;
5998
-
return fail;
5999
-
}
6000
-
6001
-
/**
6002
-
* s2io_bist_test - invokes the MemBist test of the card .
6003
-
* @sp : private member of the device structure, which is a pointer to the
6004
-
* s2io_nic structure.
6005
-
* @data:variable that returns the result of each of the test conducted by
6006
-
* the driver.
6007
-
* Description:
6008
-
* This invokes the MemBist test of the card. We give around
6009
-
* 2 secs time for the Test to complete. If it's still not complete
6010
-
* within this peiod, we consider that the test failed.
6011
-
* Return value:
6012
-
* 0 on success and -1 on failure.
6013
-
*/
6014
-
6015
-
static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6016
-
{
6017
-
u8 bist = 0;
6018
-
int cnt = 0, ret = -1;
6019
-
6020
-
pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6021
-
bist |= PCI_BIST_START;
6022
-
pci_write_config_word(sp->pdev, PCI_BIST, bist);
6023
-
6024
-
while (cnt < 20) {
6025
-
pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6026
-
if (!(bist & PCI_BIST_START)) {
6027
-
*data = (bist & PCI_BIST_CODE_MASK);
6028
-
ret = 0;
6029
-
break;
6030
-
}
6031
-
msleep(100);
6032
-
cnt++;
6033
-
}
6034
-
6035
-
return ret;
6036
-
}
6037
-
6038
-
/**
6039
-
* s2io_link_test - verifies the link state of the nic
6040
-
* @sp: private member of the device structure, which is a pointer to the
6041
-
* s2io_nic structure.
6042
-
* @data: variable that returns the result of each of the test conducted by
6043
-
* the driver.
6044
-
* Description:
6045
-
* The function verifies the link state of the NIC and updates the input
6046
-
* argument 'data' appropriately.
6047
-
* Return value:
6048
-
* 0 on success.
6049
-
*/
6050
-
6051
-
static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6052
-
{
6053
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
6054
-
u64 val64;
6055
-
6056
-
val64 = readq(&bar0->adapter_status);
6057
-
if (!(LINK_IS_UP(val64)))
6058
-
*data = 1;
6059
-
else
6060
-
*data = 0;
6061
-
6062
-
return *data;
6063
-
}
6064
-
6065
-
/**
6066
-
* s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6067
-
* @sp: private member of the device structure, which is a pointer to the
6068
-
* s2io_nic structure.
6069
-
* @data: variable that returns the result of each of the test
6070
-
* conducted by the driver.
6071
-
* Description:
6072
-
* This is one of the offline test that tests the read and write
6073
-
* access to the RldRam chip on the NIC.
6074
-
* Return value:
6075
-
* 0 on success.
6076
-
*/
6077
-
6078
-
static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6079
-
{
6080
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
6081
-
u64 val64;
6082
-
int cnt, iteration = 0, test_fail = 0;
6083
-
6084
-
val64 = readq(&bar0->adapter_control);
6085
-
val64 &= ~ADAPTER_ECC_EN;
6086
-
writeq(val64, &bar0->adapter_control);
6087
-
6088
-
val64 = readq(&bar0->mc_rldram_test_ctrl);
6089
-
val64 |= MC_RLDRAM_TEST_MODE;
6090
-
SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6091
-
6092
-
val64 = readq(&bar0->mc_rldram_mrs);
6093
-
val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6094
-
SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6095
-
6096
-
val64 |= MC_RLDRAM_MRS_ENABLE;
6097
-
SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6098
-
6099
-
while (iteration < 2) {
6100
-
val64 = 0x55555555aaaa0000ULL;
6101
-
if (iteration == 1)
6102
-
val64 ^= 0xFFFFFFFFFFFF0000ULL;
6103
-
writeq(val64, &bar0->mc_rldram_test_d0);
6104
-
6105
-
val64 = 0xaaaa5a5555550000ULL;
6106
-
if (iteration == 1)
6107
-
val64 ^= 0xFFFFFFFFFFFF0000ULL;
6108
-
writeq(val64, &bar0->mc_rldram_test_d1);
6109
-
6110
-
val64 = 0x55aaaaaaaa5a0000ULL;
6111
-
if (iteration == 1)
6112
-
val64 ^= 0xFFFFFFFFFFFF0000ULL;
6113
-
writeq(val64, &bar0->mc_rldram_test_d2);
6114
-
6115
-
val64 = (u64) (0x0000003ffffe0100ULL);
6116
-
writeq(val64, &bar0->mc_rldram_test_add);
6117
-
6118
-
val64 = MC_RLDRAM_TEST_MODE |
6119
-
MC_RLDRAM_TEST_WRITE |
6120
-
MC_RLDRAM_TEST_GO;
6121
-
SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6122
-
6123
-
for (cnt = 0; cnt < 5; cnt++) {
6124
-
val64 = readq(&bar0->mc_rldram_test_ctrl);
6125
-
if (val64 & MC_RLDRAM_TEST_DONE)
6126
-
break;
6127
-
msleep(200);
6128
-
}
6129
-
6130
-
if (cnt == 5)
6131
-
break;
6132
-
6133
-
val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6134
-
SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6135
-
6136
-
for (cnt = 0; cnt < 5; cnt++) {
6137
-
val64 = readq(&bar0->mc_rldram_test_ctrl);
6138
-
if (val64 & MC_RLDRAM_TEST_DONE)
6139
-
break;
6140
-
msleep(500);
6141
-
}
6142
-
6143
-
if (cnt == 5)
6144
-
break;
6145
-
6146
-
val64 = readq(&bar0->mc_rldram_test_ctrl);
6147
-
if (!(val64 & MC_RLDRAM_TEST_PASS))
6148
-
test_fail = 1;
6149
-
6150
-
iteration++;
6151
-
}
6152
-
6153
-
*data = test_fail;
6154
-
6155
-
/* Bring the adapter out of test mode */
6156
-
SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6157
-
6158
-
return test_fail;
6159
-
}
6160
-
6161
-
/**
6162
-
* s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6163
-
* @dev: pointer to netdev
6164
-
* @ethtest : pointer to a ethtool command specific structure that will be
6165
-
* returned to the user.
6166
-
* @data : variable that returns the result of each of the test
6167
-
* conducted by the driver.
6168
-
* Description:
6169
-
* This function conducts 6 tests ( 4 offline and 2 online) to determine
6170
-
* the health of the card.
6171
-
* Return value:
6172
-
* void
6173
-
*/
6174
-
6175
-
static void s2io_ethtool_test(struct net_device *dev,
6176
-
struct ethtool_test *ethtest,
6177
-
uint64_t *data)
6178
-
{
6179
-
struct s2io_nic *sp = netdev_priv(dev);
6180
-
int orig_state = netif_running(sp->dev);
6181
-
6182
-
if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6183
-
/* Offline Tests. */
6184
-
if (orig_state)
6185
-
s2io_close(sp->dev);
6186
-
6187
-
if (s2io_register_test(sp, &data[0]))
6188
-
ethtest->flags |= ETH_TEST_FL_FAILED;
6189
-
6190
-
s2io_reset(sp);
6191
-
6192
-
if (s2io_rldram_test(sp, &data[3]))
6193
-
ethtest->flags |= ETH_TEST_FL_FAILED;
6194
-
6195
-
s2io_reset(sp);
6196
-
6197
-
if (s2io_eeprom_test(sp, &data[1]))
6198
-
ethtest->flags |= ETH_TEST_FL_FAILED;
6199
-
6200
-
if (s2io_bist_test(sp, &data[4]))
6201
-
ethtest->flags |= ETH_TEST_FL_FAILED;
6202
-
6203
-
if (orig_state)
6204
-
s2io_open(sp->dev);
6205
-
6206
-
data[2] = 0;
6207
-
} else {
6208
-
/* Online Tests. */
6209
-
if (!orig_state) {
6210
-
DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6211
-
dev->name);
6212
-
data[0] = -1;
6213
-
data[1] = -1;
6214
-
data[2] = -1;
6215
-
data[3] = -1;
6216
-
data[4] = -1;
6217
-
}
6218
-
6219
-
if (s2io_link_test(sp, &data[2]))
6220
-
ethtest->flags |= ETH_TEST_FL_FAILED;
6221
-
6222
-
data[0] = 0;
6223
-
data[1] = 0;
6224
-
data[3] = 0;
6225
-
data[4] = 0;
6226
-
}
6227
-
}
6228
-
6229
-
static void s2io_get_ethtool_stats(struct net_device *dev,
6230
-
struct ethtool_stats *estats,
6231
-
u64 *tmp_stats)
6232
-
{
6233
-
int i = 0, k;
6234
-
struct s2io_nic *sp = netdev_priv(dev);
6235
-
struct stat_block *stats = sp->mac_control.stats_info;
6236
-
struct swStat *swstats = &stats->sw_stat;
6237
-
struct xpakStat *xstats = &stats->xpak_stat;
6238
-
6239
-
s2io_updt_stats(sp);
6240
-
tmp_stats[i++] =
6241
-
(u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6242
-
le32_to_cpu(stats->tmac_frms);
6243
-
tmp_stats[i++] =
6244
-
(u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6245
-
le32_to_cpu(stats->tmac_data_octets);
6246
-
tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6247
-
tmp_stats[i++] =
6248
-
(u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6249
-
le32_to_cpu(stats->tmac_mcst_frms);
6250
-
tmp_stats[i++] =
6251
-
(u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6252
-
le32_to_cpu(stats->tmac_bcst_frms);
6253
-
tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6254
-
tmp_stats[i++] =
6255
-
(u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6256
-
le32_to_cpu(stats->tmac_ttl_octets);
6257
-
tmp_stats[i++] =
6258
-
(u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6259
-
le32_to_cpu(stats->tmac_ucst_frms);
6260
-
tmp_stats[i++] =
6261
-
(u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6262
-
le32_to_cpu(stats->tmac_nucst_frms);
6263
-
tmp_stats[i++] =
6264
-
(u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6265
-
le32_to_cpu(stats->tmac_any_err_frms);
6266
-
tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6267
-
tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6268
-
tmp_stats[i++] =
6269
-
(u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6270
-
le32_to_cpu(stats->tmac_vld_ip);
6271
-
tmp_stats[i++] =
6272
-
(u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6273
-
le32_to_cpu(stats->tmac_drop_ip);
6274
-
tmp_stats[i++] =
6275
-
(u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6276
-
le32_to_cpu(stats->tmac_icmp);
6277
-
tmp_stats[i++] =
6278
-
(u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6279
-
le32_to_cpu(stats->tmac_rst_tcp);
6280
-
tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6281
-
tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6282
-
le32_to_cpu(stats->tmac_udp);
6283
-
tmp_stats[i++] =
6284
-
(u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6285
-
le32_to_cpu(stats->rmac_vld_frms);
6286
-
tmp_stats[i++] =
6287
-
(u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6288
-
le32_to_cpu(stats->rmac_data_octets);
6289
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6290
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6291
-
tmp_stats[i++] =
6292
-
(u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6293
-
le32_to_cpu(stats->rmac_vld_mcst_frms);
6294
-
tmp_stats[i++] =
6295
-
(u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6296
-
le32_to_cpu(stats->rmac_vld_bcst_frms);
6297
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6298
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6299
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6300
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6301
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6302
-
tmp_stats[i++] =
6303
-
(u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6304
-
le32_to_cpu(stats->rmac_ttl_octets);
6305
-
tmp_stats[i++] =
6306
-
(u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6307
-
| le32_to_cpu(stats->rmac_accepted_ucst_frms);
6308
-
tmp_stats[i++] =
6309
-
(u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6310
-
<< 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6311
-
tmp_stats[i++] =
6312
-
(u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6313
-
le32_to_cpu(stats->rmac_discarded_frms);
6314
-
tmp_stats[i++] =
6315
-
(u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6316
-
<< 32 | le32_to_cpu(stats->rmac_drop_events);
6317
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6318
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6319
-
tmp_stats[i++] =
6320
-
(u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6321
-
le32_to_cpu(stats->rmac_usized_frms);
6322
-
tmp_stats[i++] =
6323
-
(u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6324
-
le32_to_cpu(stats->rmac_osized_frms);
6325
-
tmp_stats[i++] =
6326
-
(u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6327
-
le32_to_cpu(stats->rmac_frag_frms);
6328
-
tmp_stats[i++] =
6329
-
(u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6330
-
le32_to_cpu(stats->rmac_jabber_frms);
6331
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6332
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6333
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6334
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6335
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6336
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6337
-
tmp_stats[i++] =
6338
-
(u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6339
-
le32_to_cpu(stats->rmac_ip);
6340
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6341
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6342
-
tmp_stats[i++] =
6343
-
(u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6344
-
le32_to_cpu(stats->rmac_drop_ip);
6345
-
tmp_stats[i++] =
6346
-
(u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6347
-
le32_to_cpu(stats->rmac_icmp);
6348
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6349
-
tmp_stats[i++] =
6350
-
(u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6351
-
le32_to_cpu(stats->rmac_udp);
6352
-
tmp_stats[i++] =
6353
-
(u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6354
-
le32_to_cpu(stats->rmac_err_drp_udp);
6355
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6356
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6357
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6358
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6359
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6360
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6361
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6362
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6363
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6364
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6365
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6366
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6367
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6368
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6369
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6370
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6371
-
tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6372
-
tmp_stats[i++] =
6373
-
(u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6374
-
le32_to_cpu(stats->rmac_pause_cnt);
6375
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6376
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6377
-
tmp_stats[i++] =
6378
-
(u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6379
-
le32_to_cpu(stats->rmac_accepted_ip);
6380
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6381
-
tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6382
-
tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6383
-
tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6384
-
tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6385
-
tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6386
-
tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6387
-
tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6388
-
tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6389
-
tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6390
-
tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6391
-
tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6392
-
tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6393
-
tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6394
-
tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6395
-
tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6396
-
tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6397
-
tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6398
-
tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6399
-
6400
-
/* Enhanced statistics exist only for Hercules */
6401
-
if (sp->device_type == XFRAME_II_DEVICE) {
6402
-
tmp_stats[i++] =
6403
-
le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6404
-
tmp_stats[i++] =
6405
-
le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6406
-
tmp_stats[i++] =
6407
-
le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6408
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6409
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6410
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6411
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6412
-
tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6413
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6414
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6415
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6416
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6417
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6418
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6419
-
tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6420
-
tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6421
-
}
6422
-
6423
-
tmp_stats[i++] = 0;
6424
-
tmp_stats[i++] = swstats->single_ecc_errs;
6425
-
tmp_stats[i++] = swstats->double_ecc_errs;
6426
-
tmp_stats[i++] = swstats->parity_err_cnt;
6427
-
tmp_stats[i++] = swstats->serious_err_cnt;
6428
-
tmp_stats[i++] = swstats->soft_reset_cnt;
6429
-
tmp_stats[i++] = swstats->fifo_full_cnt;
6430
-
for (k = 0; k < MAX_RX_RINGS; k++)
6431
-
tmp_stats[i++] = swstats->ring_full_cnt[k];
6432
-
tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6433
-
tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6434
-
tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6435
-
tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6436
-
tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6437
-
tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6438
-
tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6439
-
tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6440
-
tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6441
-
tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6442
-
tmp_stats[i++] = xstats->warn_laser_output_power_high;
6443
-
tmp_stats[i++] = xstats->warn_laser_output_power_low;
6444
-
tmp_stats[i++] = swstats->clubbed_frms_cnt;
6445
-
tmp_stats[i++] = swstats->sending_both;
6446
-
tmp_stats[i++] = swstats->outof_sequence_pkts;
6447
-
tmp_stats[i++] = swstats->flush_max_pkts;
6448
-
if (swstats->num_aggregations) {
6449
-
u64 tmp = swstats->sum_avg_pkts_aggregated;
6450
-
int count = 0;
6451
-
/*
6452
-
* Since 64-bit divide does not work on all platforms,
6453
-
* do repeated subtraction.
6454
-
*/
6455
-
while (tmp >= swstats->num_aggregations) {
6456
-
tmp -= swstats->num_aggregations;
6457
-
count++;
6458
-
}
6459
-
tmp_stats[i++] = count;
6460
-
} else
6461
-
tmp_stats[i++] = 0;
6462
-
tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6463
-
tmp_stats[i++] = swstats->pci_map_fail_cnt;
6464
-
tmp_stats[i++] = swstats->watchdog_timer_cnt;
6465
-
tmp_stats[i++] = swstats->mem_allocated;
6466
-
tmp_stats[i++] = swstats->mem_freed;
6467
-
tmp_stats[i++] = swstats->link_up_cnt;
6468
-
tmp_stats[i++] = swstats->link_down_cnt;
6469
-
tmp_stats[i++] = swstats->link_up_time;
6470
-
tmp_stats[i++] = swstats->link_down_time;
6471
-
6472
-
tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6473
-
tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6474
-
tmp_stats[i++] = swstats->tx_parity_err_cnt;
6475
-
tmp_stats[i++] = swstats->tx_link_loss_cnt;
6476
-
tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6477
-
6478
-
tmp_stats[i++] = swstats->rx_parity_err_cnt;
6479
-
tmp_stats[i++] = swstats->rx_abort_cnt;
6480
-
tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6481
-
tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6482
-
tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6483
-
tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6484
-
tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6485
-
tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6486
-
tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6487
-
tmp_stats[i++] = swstats->tda_err_cnt;
6488
-
tmp_stats[i++] = swstats->pfc_err_cnt;
6489
-
tmp_stats[i++] = swstats->pcc_err_cnt;
6490
-
tmp_stats[i++] = swstats->tti_err_cnt;
6491
-
tmp_stats[i++] = swstats->tpa_err_cnt;
6492
-
tmp_stats[i++] = swstats->sm_err_cnt;
6493
-
tmp_stats[i++] = swstats->lso_err_cnt;
6494
-
tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6495
-
tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6496
-
tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6497
-
tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6498
-
tmp_stats[i++] = swstats->rc_err_cnt;
6499
-
tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6500
-
tmp_stats[i++] = swstats->rpa_err_cnt;
6501
-
tmp_stats[i++] = swstats->rda_err_cnt;
6502
-
tmp_stats[i++] = swstats->rti_err_cnt;
6503
-
tmp_stats[i++] = swstats->mc_err_cnt;
6504
-
}
6505
-
6506
-
static int s2io_ethtool_get_regs_len(struct net_device *dev)
6507
-
{
6508
-
return XENA_REG_SPACE;
6509
-
}
6510
-
6511
-
6512
-
static int s2io_get_eeprom_len(struct net_device *dev)
6513
-
{
6514
-
return XENA_EEPROM_SPACE;
6515
-
}
6516
-
6517
-
static int s2io_get_sset_count(struct net_device *dev, int sset)
6518
-
{
6519
-
struct s2io_nic *sp = netdev_priv(dev);
6520
-
6521
-
switch (sset) {
6522
-
case ETH_SS_TEST:
6523
-
return S2IO_TEST_LEN;
6524
-
case ETH_SS_STATS:
6525
-
switch (sp->device_type) {
6526
-
case XFRAME_I_DEVICE:
6527
-
return XFRAME_I_STAT_LEN;
6528
-
case XFRAME_II_DEVICE:
6529
-
return XFRAME_II_STAT_LEN;
6530
-
default:
6531
-
return 0;
6532
-
}
6533
-
default:
6534
-
return -EOPNOTSUPP;
6535
-
}
6536
-
}
6537
-
6538
-
static void s2io_ethtool_get_strings(struct net_device *dev,
6539
-
u32 stringset, u8 *data)
6540
-
{
6541
-
int stat_size = 0;
6542
-
struct s2io_nic *sp = netdev_priv(dev);
6543
-
6544
-
switch (stringset) {
6545
-
case ETH_SS_TEST:
6546
-
memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6547
-
break;
6548
-
case ETH_SS_STATS:
6549
-
stat_size = sizeof(ethtool_xena_stats_keys);
6550
-
memcpy(data, ðtool_xena_stats_keys, stat_size);
6551
-
if (sp->device_type == XFRAME_II_DEVICE) {
6552
-
memcpy(data + stat_size,
6553
-
ðtool_enhanced_stats_keys,
6554
-
sizeof(ethtool_enhanced_stats_keys));
6555
-
stat_size += sizeof(ethtool_enhanced_stats_keys);
6556
-
}
6557
-
6558
-
memcpy(data + stat_size, ðtool_driver_stats_keys,
6559
-
sizeof(ethtool_driver_stats_keys));
6560
-
}
6561
-
}
6562
-
6563
-
static int s2io_set_features(struct net_device *dev, netdev_features_t features)
6564
-
{
6565
-
struct s2io_nic *sp = netdev_priv(dev);
6566
-
netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO;
6567
-
6568
-
if (changed && netif_running(dev)) {
6569
-
int rc;
6570
-
6571
-
s2io_stop_all_tx_queue(sp);
6572
-
s2io_card_down(sp);
6573
-
dev->features = features;
6574
-
rc = s2io_card_up(sp);
6575
-
if (rc)
6576
-
s2io_reset(sp);
6577
-
else
6578
-
s2io_start_all_tx_queue(sp);
6579
-
6580
-
return rc ? rc : 1;
6581
-
}
6582
-
6583
-
return 0;
6584
-
}
6585
-
6586
-
static const struct ethtool_ops netdev_ethtool_ops = {
6587
-
.get_drvinfo = s2io_ethtool_gdrvinfo,
6588
-
.get_regs_len = s2io_ethtool_get_regs_len,
6589
-
.get_regs = s2io_ethtool_gregs,
6590
-
.get_link = ethtool_op_get_link,
6591
-
.get_eeprom_len = s2io_get_eeprom_len,
6592
-
.get_eeprom = s2io_ethtool_geeprom,
6593
-
.set_eeprom = s2io_ethtool_seeprom,
6594
-
.get_ringparam = s2io_ethtool_gringparam,
6595
-
.get_pauseparam = s2io_ethtool_getpause_data,
6596
-
.set_pauseparam = s2io_ethtool_setpause_data,
6597
-
.self_test = s2io_ethtool_test,
6598
-
.get_strings = s2io_ethtool_get_strings,
6599
-
.set_phys_id = s2io_ethtool_set_led,
6600
-
.get_ethtool_stats = s2io_get_ethtool_stats,
6601
-
.get_sset_count = s2io_get_sset_count,
6602
-
.get_link_ksettings = s2io_ethtool_get_link_ksettings,
6603
-
.set_link_ksettings = s2io_ethtool_set_link_ksettings,
6604
-
};
6605
-
6606
-
/**
6607
-
* s2io_ioctl - Entry point for the Ioctl
6608
-
* @dev : Device pointer.
6609
-
* @rq : An IOCTL specefic structure, that can contain a pointer to
6610
-
* a proprietary structure used to pass information to the driver.
6611
-
* @cmd : This is used to distinguish between the different commands that
6612
-
* can be passed to the IOCTL functions.
6613
-
* Description:
6614
-
* Currently there are no special functionality supported in IOCTL, hence
6615
-
* function always return EOPNOTSUPPORTED
6616
-
*/
6617
-
6618
-
static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6619
-
{
6620
-
return -EOPNOTSUPP;
6621
-
}
6622
-
6623
-
/**
6624
-
* s2io_change_mtu - entry point to change MTU size for the device.
6625
-
* @dev : device pointer.
6626
-
* @new_mtu : the new MTU size for the device.
6627
-
* Description: A driver entry point to change MTU size for the device.
6628
-
* Before changing the MTU the device must be stopped.
6629
-
* Return value:
6630
-
* 0 on success and an appropriate (-)ve integer as defined in errno.h
6631
-
* file on failure.
6632
-
*/
6633
-
6634
-
static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6635
-
{
6636
-
struct s2io_nic *sp = netdev_priv(dev);
6637
-
int ret = 0;
6638
-
6639
-
WRITE_ONCE(dev->mtu, new_mtu);
6640
-
if (netif_running(dev)) {
6641
-
s2io_stop_all_tx_queue(sp);
6642
-
s2io_card_down(sp);
6643
-
ret = s2io_card_up(sp);
6644
-
if (ret) {
6645
-
DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6646
-
__func__);
6647
-
return ret;
6648
-
}
6649
-
s2io_wake_all_tx_queue(sp);
6650
-
} else { /* Device is down */
6651
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
6652
-
u64 val64 = new_mtu;
6653
-
6654
-
writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6655
-
}
6656
-
6657
-
return ret;
6658
-
}
6659
-
6660
-
/**
6661
-
* s2io_set_link - Set the LInk status
6662
-
* @work: work struct containing a pointer to device private structure
6663
-
* Description: Sets the link status for the adapter
6664
-
*/
6665
-
6666
-
static void s2io_set_link(struct work_struct *work)
6667
-
{
6668
-
struct s2io_nic *nic = container_of(work, struct s2io_nic,
6669
-
set_link_task);
6670
-
struct net_device *dev = nic->dev;
6671
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
6672
-
register u64 val64;
6673
-
u16 subid;
6674
-
6675
-
rtnl_lock();
6676
-
6677
-
if (!netif_running(dev))
6678
-
goto out_unlock;
6679
-
6680
-
if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6681
-
/* The card is being reset, no point doing anything */
6682
-
goto out_unlock;
6683
-
}
6684
-
6685
-
subid = nic->pdev->subsystem_device;
6686
-
if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6687
-
/*
6688
-
* Allow a small delay for the NICs self initiated
6689
-
* cleanup to complete.
6690
-
*/
6691
-
msleep(100);
6692
-
}
6693
-
6694
-
val64 = readq(&bar0->adapter_status);
6695
-
if (LINK_IS_UP(val64)) {
6696
-
if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6697
-
if (verify_xena_quiescence(nic)) {
6698
-
val64 = readq(&bar0->adapter_control);
6699
-
val64 |= ADAPTER_CNTL_EN;
6700
-
writeq(val64, &bar0->adapter_control);
6701
-
if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6702
-
nic->device_type, subid)) {
6703
-
val64 = readq(&bar0->gpio_control);
6704
-
val64 |= GPIO_CTRL_GPIO_0;
6705
-
writeq(val64, &bar0->gpio_control);
6706
-
val64 = readq(&bar0->gpio_control);
6707
-
} else {
6708
-
val64 |= ADAPTER_LED_ON;
6709
-
writeq(val64, &bar0->adapter_control);
6710
-
}
6711
-
nic->device_enabled_once = true;
6712
-
} else {
6713
-
DBG_PRINT(ERR_DBG,
6714
-
"%s: Error: device is not Quiescent\n",
6715
-
dev->name);
6716
-
s2io_stop_all_tx_queue(nic);
6717
-
}
6718
-
}
6719
-
val64 = readq(&bar0->adapter_control);
6720
-
val64 |= ADAPTER_LED_ON;
6721
-
writeq(val64, &bar0->adapter_control);
6722
-
s2io_link(nic, LINK_UP);
6723
-
} else {
6724
-
if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6725
-
subid)) {
6726
-
val64 = readq(&bar0->gpio_control);
6727
-
val64 &= ~GPIO_CTRL_GPIO_0;
6728
-
writeq(val64, &bar0->gpio_control);
6729
-
val64 = readq(&bar0->gpio_control);
6730
-
}
6731
-
/* turn off LED */
6732
-
val64 = readq(&bar0->adapter_control);
6733
-
val64 = val64 & (~ADAPTER_LED_ON);
6734
-
writeq(val64, &bar0->adapter_control);
6735
-
s2io_link(nic, LINK_DOWN);
6736
-
}
6737
-
clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6738
-
6739
-
out_unlock:
6740
-
rtnl_unlock();
6741
-
}
6742
-
6743
-
static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6744
-
struct buffAdd *ba,
6745
-
struct sk_buff **skb, u64 *temp0, u64 *temp1,
6746
-
u64 *temp2, int size)
6747
-
{
6748
-
struct net_device *dev = sp->dev;
6749
-
struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6750
-
6751
-
if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6752
-
struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6753
-
/* allocate skb */
6754
-
if (*skb) {
6755
-
DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6756
-
/*
6757
-
* As Rx frame are not going to be processed,
6758
-
* using same mapped address for the Rxd
6759
-
* buffer pointer
6760
-
*/
6761
-
rxdp1->Buffer0_ptr = *temp0;
6762
-
} else {
6763
-
*skb = netdev_alloc_skb(dev, size);
6764
-
if (!(*skb)) {
6765
-
DBG_PRINT(INFO_DBG,
6766
-
"%s: Out of memory to allocate %s\n",
6767
-
dev->name, "1 buf mode SKBs");
6768
-
stats->mem_alloc_fail_cnt++;
6769
-
return -ENOMEM ;
6770
-
}
6771
-
stats->mem_allocated += (*skb)->truesize;
6772
-
/* storing the mapped addr in a temp variable
6773
-
* such it will be used for next rxd whose
6774
-
* Host Control is NULL
6775
-
*/
6776
-
rxdp1->Buffer0_ptr = *temp0 =
6777
-
dma_map_single(&sp->pdev->dev, (*skb)->data,
6778
-
size - NET_IP_ALIGN,
6779
-
DMA_FROM_DEVICE);
6780
-
if (dma_mapping_error(&sp->pdev->dev, rxdp1->Buffer0_ptr))
6781
-
goto memalloc_failed;
6782
-
rxdp->Host_Control = (unsigned long) (*skb);
6783
-
}
6784
-
} else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6785
-
struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6786
-
/* Two buffer Mode */
6787
-
if (*skb) {
6788
-
rxdp3->Buffer2_ptr = *temp2;
6789
-
rxdp3->Buffer0_ptr = *temp0;
6790
-
rxdp3->Buffer1_ptr = *temp1;
6791
-
} else {
6792
-
*skb = netdev_alloc_skb(dev, size);
6793
-
if (!(*skb)) {
6794
-
DBG_PRINT(INFO_DBG,
6795
-
"%s: Out of memory to allocate %s\n",
6796
-
dev->name,
6797
-
"2 buf mode SKBs");
6798
-
stats->mem_alloc_fail_cnt++;
6799
-
return -ENOMEM;
6800
-
}
6801
-
stats->mem_allocated += (*skb)->truesize;
6802
-
rxdp3->Buffer2_ptr = *temp2 =
6803
-
dma_map_single(&sp->pdev->dev, (*skb)->data,
6804
-
dev->mtu + 4, DMA_FROM_DEVICE);
6805
-
if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer2_ptr))
6806
-
goto memalloc_failed;
6807
-
rxdp3->Buffer0_ptr = *temp0 =
6808
-
dma_map_single(&sp->pdev->dev, ba->ba_0,
6809
-
BUF0_LEN, DMA_FROM_DEVICE);
6810
-
if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer0_ptr)) {
6811
-
dma_unmap_single(&sp->pdev->dev,
6812
-
(dma_addr_t)rxdp3->Buffer2_ptr,
6813
-
dev->mtu + 4,
6814
-
DMA_FROM_DEVICE);
6815
-
goto memalloc_failed;
6816
-
}
6817
-
rxdp->Host_Control = (unsigned long) (*skb);
6818
-
6819
-
/* Buffer-1 will be dummy buffer not used */
6820
-
rxdp3->Buffer1_ptr = *temp1 =
6821
-
dma_map_single(&sp->pdev->dev, ba->ba_1,
6822
-
BUF1_LEN, DMA_FROM_DEVICE);
6823
-
if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer1_ptr)) {
6824
-
dma_unmap_single(&sp->pdev->dev,
6825
-
(dma_addr_t)rxdp3->Buffer0_ptr,
6826
-
BUF0_LEN, DMA_FROM_DEVICE);
6827
-
dma_unmap_single(&sp->pdev->dev,
6828
-
(dma_addr_t)rxdp3->Buffer2_ptr,
6829
-
dev->mtu + 4,
6830
-
DMA_FROM_DEVICE);
6831
-
goto memalloc_failed;
6832
-
}
6833
-
}
6834
-
}
6835
-
return 0;
6836
-
6837
-
memalloc_failed:
6838
-
stats->pci_map_fail_cnt++;
6839
-
stats->mem_freed += (*skb)->truesize;
6840
-
dev_kfree_skb(*skb);
6841
-
return -ENOMEM;
6842
-
}
6843
-
6844
-
static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6845
-
int size)
6846
-
{
6847
-
struct net_device *dev = sp->dev;
6848
-
if (sp->rxd_mode == RXD_MODE_1) {
6849
-
rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6850
-
} else if (sp->rxd_mode == RXD_MODE_3B) {
6851
-
rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6852
-
rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6853
-
rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6854
-
}
6855
-
}
6856
-
6857
-
static int rxd_owner_bit_reset(struct s2io_nic *sp)
6858
-
{
6859
-
int i, j, k, blk_cnt = 0, size;
6860
-
struct config_param *config = &sp->config;
6861
-
struct mac_info *mac_control = &sp->mac_control;
6862
-
struct net_device *dev = sp->dev;
6863
-
struct RxD_t *rxdp = NULL;
6864
-
struct sk_buff *skb = NULL;
6865
-
struct buffAdd *ba = NULL;
6866
-
u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6867
-
6868
-
/* Calculate the size based on ring mode */
6869
-
size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6870
-
HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6871
-
if (sp->rxd_mode == RXD_MODE_1)
6872
-
size += NET_IP_ALIGN;
6873
-
else if (sp->rxd_mode == RXD_MODE_3B)
6874
-
size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6875
-
6876
-
for (i = 0; i < config->rx_ring_num; i++) {
6877
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6878
-
struct ring_info *ring = &mac_control->rings[i];
6879
-
6880
-
blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6881
-
6882
-
for (j = 0; j < blk_cnt; j++) {
6883
-
for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6884
-
rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6885
-
if (sp->rxd_mode == RXD_MODE_3B)
6886
-
ba = &ring->ba[j][k];
6887
-
if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6888
-
&temp0_64,
6889
-
&temp1_64,
6890
-
&temp2_64,
6891
-
size) == -ENOMEM) {
6892
-
return 0;
6893
-
}
6894
-
6895
-
set_rxd_buffer_size(sp, rxdp, size);
6896
-
dma_wmb();
6897
-
/* flip the Ownership bit to Hardware */
6898
-
rxdp->Control_1 |= RXD_OWN_XENA;
6899
-
}
6900
-
}
6901
-
}
6902
-
return 0;
6903
-
6904
-
}
6905
-
6906
-
static int s2io_add_isr(struct s2io_nic *sp)
6907
-
{
6908
-
int ret = 0;
6909
-
struct net_device *dev = sp->dev;
6910
-
int err = 0;
6911
-
6912
-
if (sp->config.intr_type == MSI_X)
6913
-
ret = s2io_enable_msi_x(sp);
6914
-
if (ret) {
6915
-
DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6916
-
sp->config.intr_type = INTA;
6917
-
}
6918
-
6919
-
/*
6920
-
* Store the values of the MSIX table in
6921
-
* the struct s2io_nic structure
6922
-
*/
6923
-
store_xmsi_data(sp);
6924
-
6925
-
/* After proper initialization of H/W, register ISR */
6926
-
if (sp->config.intr_type == MSI_X) {
6927
-
int i, msix_rx_cnt = 0;
6928
-
6929
-
for (i = 0; i < sp->num_entries; i++) {
6930
-
if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6931
-
if (sp->s2io_entries[i].type ==
6932
-
MSIX_RING_TYPE) {
6933
-
snprintf(sp->desc[i],
6934
-
sizeof(sp->desc[i]),
6935
-
"%s:MSI-X-%d-RX",
6936
-
dev->name, i);
6937
-
err = request_irq(sp->entries[i].vector,
6938
-
s2io_msix_ring_handle,
6939
-
0,
6940
-
sp->desc[i],
6941
-
sp->s2io_entries[i].arg);
6942
-
} else if (sp->s2io_entries[i].type ==
6943
-
MSIX_ALARM_TYPE) {
6944
-
snprintf(sp->desc[i],
6945
-
sizeof(sp->desc[i]),
6946
-
"%s:MSI-X-%d-TX",
6947
-
dev->name, i);
6948
-
err = request_irq(sp->entries[i].vector,
6949
-
s2io_msix_fifo_handle,
6950
-
0,
6951
-
sp->desc[i],
6952
-
sp->s2io_entries[i].arg);
6953
-
6954
-
}
6955
-
/* if either data or addr is zero print it. */
6956
-
if (!(sp->msix_info[i].addr &&
6957
-
sp->msix_info[i].data)) {
6958
-
DBG_PRINT(ERR_DBG,
6959
-
"%s @Addr:0x%llx Data:0x%llx\n",
6960
-
sp->desc[i],
6961
-
(unsigned long long)
6962
-
sp->msix_info[i].addr,
6963
-
(unsigned long long)
6964
-
ntohl(sp->msix_info[i].data));
6965
-
} else
6966
-
msix_rx_cnt++;
6967
-
if (err) {
6968
-
remove_msix_isr(sp);
6969
-
6970
-
DBG_PRINT(ERR_DBG,
6971
-
"%s:MSI-X-%d registration "
6972
-
"failed\n", dev->name, i);
6973
-
6974
-
DBG_PRINT(ERR_DBG,
6975
-
"%s: Defaulting to INTA\n",
6976
-
dev->name);
6977
-
sp->config.intr_type = INTA;
6978
-
break;
6979
-
}
6980
-
sp->s2io_entries[i].in_use =
6981
-
MSIX_REGISTERED_SUCCESS;
6982
-
}
6983
-
}
6984
-
if (!err) {
6985
-
pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
6986
-
DBG_PRINT(INFO_DBG,
6987
-
"MSI-X-TX entries enabled through alarm vector\n");
6988
-
}
6989
-
}
6990
-
if (sp->config.intr_type == INTA) {
6991
-
err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED,
6992
-
sp->name, dev);
6993
-
if (err) {
6994
-
DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6995
-
dev->name);
6996
-
return -1;
6997
-
}
6998
-
}
6999
-
return 0;
7000
-
}
7001
-
7002
-
static void s2io_rem_isr(struct s2io_nic *sp)
7003
-
{
7004
-
if (sp->config.intr_type == MSI_X)
7005
-
remove_msix_isr(sp);
7006
-
else
7007
-
remove_inta_isr(sp);
7008
-
}
7009
-
7010
-
static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7011
-
{
7012
-
int cnt = 0;
7013
-
struct XENA_dev_config __iomem *bar0 = sp->bar0;
7014
-
register u64 val64 = 0;
7015
-
struct config_param *config;
7016
-
config = &sp->config;
7017
-
7018
-
if (!is_s2io_card_up(sp))
7019
-
return;
7020
-
7021
-
timer_delete_sync(&sp->alarm_timer);
7022
-
/* If s2io_set_link task is executing, wait till it completes. */
7023
-
while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7024
-
msleep(50);
7025
-
clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7026
-
7027
-
/* Disable napi */
7028
-
if (sp->config.napi) {
7029
-
int off = 0;
7030
-
if (config->intr_type == MSI_X) {
7031
-
for (; off < sp->config.rx_ring_num; off++)
7032
-
napi_disable(&sp->mac_control.rings[off].napi);
7033
-
}
7034
-
else
7035
-
napi_disable(&sp->napi);
7036
-
}
7037
-
7038
-
/* disable Tx and Rx traffic on the NIC */
7039
-
if (do_io)
7040
-
stop_nic(sp);
7041
-
7042
-
s2io_rem_isr(sp);
7043
-
7044
-
/* stop the tx queue, indicate link down */
7045
-
s2io_link(sp, LINK_DOWN);
7046
-
7047
-
/* Check if the device is Quiescent and then Reset the NIC */
7048
-
while (do_io) {
7049
-
/* As per the HW requirement we need to replenish the
7050
-
* receive buffer to avoid the ring bump. Since there is
7051
-
* no intention of processing the Rx frame at this pointwe are
7052
-
* just setting the ownership bit of rxd in Each Rx
7053
-
* ring to HW and set the appropriate buffer size
7054
-
* based on the ring mode
7055
-
*/
7056
-
rxd_owner_bit_reset(sp);
7057
-
7058
-
val64 = readq(&bar0->adapter_status);
7059
-
if (verify_xena_quiescence(sp)) {
7060
-
if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7061
-
break;
7062
-
}
7063
-
7064
-
msleep(50);
7065
-
cnt++;
7066
-
if (cnt == 10) {
7067
-
DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7068
-
"adapter status reads 0x%llx\n",
7069
-
(unsigned long long)val64);
7070
-
break;
7071
-
}
7072
-
}
7073
-
if (do_io)
7074
-
s2io_reset(sp);
7075
-
7076
-
/* Free all Tx buffers */
7077
-
free_tx_buffers(sp);
7078
-
7079
-
/* Free all Rx buffers */
7080
-
free_rx_buffers(sp);
7081
-
7082
-
clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7083
-
}
7084
-
7085
-
static void s2io_card_down(struct s2io_nic *sp)
7086
-
{
7087
-
do_s2io_card_down(sp, 1);
7088
-
}
7089
-
7090
-
static int s2io_card_up(struct s2io_nic *sp)
7091
-
{
7092
-
int i, ret = 0;
7093
-
struct config_param *config;
7094
-
struct mac_info *mac_control;
7095
-
struct net_device *dev = sp->dev;
7096
-
u16 interruptible;
7097
-
7098
-
/* Initialize the H/W I/O registers */
7099
-
ret = init_nic(sp);
7100
-
if (ret != 0) {
7101
-
DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7102
-
dev->name);
7103
-
if (ret != -EIO)
7104
-
s2io_reset(sp);
7105
-
return ret;
7106
-
}
7107
-
7108
-
/*
7109
-
* Initializing the Rx buffers. For now we are considering only 1
7110
-
* Rx ring and initializing buffers into 30 Rx blocks
7111
-
*/
7112
-
config = &sp->config;
7113
-
mac_control = &sp->mac_control;
7114
-
7115
-
for (i = 0; i < config->rx_ring_num; i++) {
7116
-
struct ring_info *ring = &mac_control->rings[i];
7117
-
7118
-
ring->mtu = dev->mtu;
7119
-
ring->lro = !!(dev->features & NETIF_F_LRO);
7120
-
ret = fill_rx_buffers(sp, ring, 1);
7121
-
if (ret) {
7122
-
DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7123
-
dev->name);
7124
-
ret = -ENOMEM;
7125
-
goto err_fill_buff;
7126
-
}
7127
-
DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7128
-
ring->rx_bufs_left);
7129
-
}
7130
-
7131
-
/* Initialise napi */
7132
-
if (config->napi) {
7133
-
if (config->intr_type == MSI_X) {
7134
-
for (i = 0; i < sp->config.rx_ring_num; i++)
7135
-
napi_enable(&sp->mac_control.rings[i].napi);
7136
-
} else {
7137
-
napi_enable(&sp->napi);
7138
-
}
7139
-
}
7140
-
7141
-
/* Maintain the state prior to the open */
7142
-
if (sp->promisc_flg)
7143
-
sp->promisc_flg = 0;
7144
-
if (sp->m_cast_flg) {
7145
-
sp->m_cast_flg = 0;
7146
-
sp->all_multi_pos = 0;
7147
-
}
7148
-
7149
-
/* Setting its receive mode */
7150
-
s2io_set_multicast(dev, true);
7151
-
7152
-
if (dev->features & NETIF_F_LRO) {
7153
-
/* Initialize max aggregatable pkts per session based on MTU */
7154
-
sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7155
-
/* Check if we can use (if specified) user provided value */
7156
-
if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7157
-
sp->lro_max_aggr_per_sess = lro_max_pkts;
7158
-
}
7159
-
7160
-
/* Enable Rx Traffic and interrupts on the NIC */
7161
-
if (start_nic(sp)) {
7162
-
DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7163
-
ret = -ENODEV;
7164
-
goto err_out;
7165
-
}
7166
-
7167
-
/* Add interrupt service routine */
7168
-
if (s2io_add_isr(sp) != 0) {
7169
-
if (sp->config.intr_type == MSI_X)
7170
-
s2io_rem_isr(sp);
7171
-
ret = -ENODEV;
7172
-
goto err_out;
7173
-
}
7174
-
7175
-
timer_setup(&sp->alarm_timer, s2io_alarm_handle, 0);
7176
-
mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
7177
-
7178
-
set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7179
-
7180
-
/* Enable select interrupts */
7181
-
en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7182
-
if (sp->config.intr_type != INTA) {
7183
-
interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7184
-
en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7185
-
} else {
7186
-
interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7187
-
interruptible |= TX_PIC_INTR;
7188
-
en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7189
-
}
7190
-
7191
-
return 0;
7192
-
7193
-
err_out:
7194
-
if (config->napi) {
7195
-
if (config->intr_type == MSI_X) {
7196
-
for (i = 0; i < sp->config.rx_ring_num; i++)
7197
-
napi_disable(&sp->mac_control.rings[i].napi);
7198
-
} else {
7199
-
napi_disable(&sp->napi);
7200
-
}
7201
-
}
7202
-
err_fill_buff:
7203
-
s2io_reset(sp);
7204
-
free_rx_buffers(sp);
7205
-
return ret;
7206
-
}
7207
-
7208
-
/**
7209
-
* s2io_restart_nic - Resets the NIC.
7210
-
* @work : work struct containing a pointer to the device private structure
7211
-
* Description:
7212
-
* This function is scheduled to be run by the s2io_tx_watchdog
7213
-
* function after 0.5 secs to reset the NIC. The idea is to reduce
7214
-
* the run time of the watch dog routine which is run holding a
7215
-
* spin lock.
7216
-
*/
7217
-
7218
-
static void s2io_restart_nic(struct work_struct *work)
7219
-
{
7220
-
struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7221
-
struct net_device *dev = sp->dev;
7222
-
7223
-
rtnl_lock();
7224
-
7225
-
if (!netif_running(dev))
7226
-
goto out_unlock;
7227
-
7228
-
s2io_card_down(sp);
7229
-
if (s2io_card_up(sp)) {
7230
-
DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7231
-
}
7232
-
s2io_wake_all_tx_queue(sp);
7233
-
DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7234
-
out_unlock:
7235
-
rtnl_unlock();
7236
-
}
7237
-
7238
-
/**
7239
-
* s2io_tx_watchdog - Watchdog for transmit side.
7240
-
* @dev : Pointer to net device structure
7241
-
* @txqueue: index of the hanging queue
7242
-
* Description:
7243
-
* This function is triggered if the Tx Queue is stopped
7244
-
* for a pre-defined amount of time when the Interface is still up.
7245
-
* If the Interface is jammed in such a situation, the hardware is
7246
-
* reset (by s2io_close) and restarted again (by s2io_open) to
7247
-
* overcome any problem that might have been caused in the hardware.
7248
-
* Return value:
7249
-
* void
7250
-
*/
7251
-
7252
-
static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue)
7253
-
{
7254
-
struct s2io_nic *sp = netdev_priv(dev);
7255
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7256
-
7257
-
if (netif_carrier_ok(dev)) {
7258
-
swstats->watchdog_timer_cnt++;
7259
-
schedule_work(&sp->rst_timer_task);
7260
-
swstats->soft_reset_cnt++;
7261
-
}
7262
-
}
7263
-
7264
-
/**
7265
-
* rx_osm_handler - To perform some OS related operations on SKB.
7266
-
* @ring_data : the ring from which this RxD was extracted.
7267
-
* @rxdp: descriptor
7268
-
* Description:
7269
-
* This function is called by the Rx interrupt serivce routine to perform
7270
-
* some OS related operations on the SKB before passing it to the upper
7271
-
* layers. It mainly checks if the checksum is OK, if so adds it to the
7272
-
* SKBs cksum variable, increments the Rx packet count and passes the SKB
7273
-
* to the upper layer. If the checksum is wrong, it increments the Rx
7274
-
* packet error count, frees the SKB and returns error.
7275
-
* Return value:
7276
-
* SUCCESS on success and -1 on failure.
7277
-
*/
7278
-
static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7279
-
{
7280
-
struct s2io_nic *sp = ring_data->nic;
7281
-
struct net_device *dev = ring_data->dev;
7282
-
struct sk_buff *skb = (struct sk_buff *)
7283
-
((unsigned long)rxdp->Host_Control);
7284
-
int ring_no = ring_data->ring_no;
7285
-
u16 l3_csum, l4_csum;
7286
-
unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7287
-
struct lro *lro;
7288
-
u8 err_mask;
7289
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7290
-
7291
-
skb->dev = dev;
7292
-
7293
-
if (err) {
7294
-
/* Check for parity error */
7295
-
if (err & 0x1)
7296
-
swstats->parity_err_cnt++;
7297
-
7298
-
err_mask = err >> 48;
7299
-
switch (err_mask) {
7300
-
case 1:
7301
-
swstats->rx_parity_err_cnt++;
7302
-
break;
7303
-
7304
-
case 2:
7305
-
swstats->rx_abort_cnt++;
7306
-
break;
7307
-
7308
-
case 3:
7309
-
swstats->rx_parity_abort_cnt++;
7310
-
break;
7311
-
7312
-
case 4:
7313
-
swstats->rx_rda_fail_cnt++;
7314
-
break;
7315
-
7316
-
case 5:
7317
-
swstats->rx_unkn_prot_cnt++;
7318
-
break;
7319
-
7320
-
case 6:
7321
-
swstats->rx_fcs_err_cnt++;
7322
-
break;
7323
-
7324
-
case 7:
7325
-
swstats->rx_buf_size_err_cnt++;
7326
-
break;
7327
-
7328
-
case 8:
7329
-
swstats->rx_rxd_corrupt_cnt++;
7330
-
break;
7331
-
7332
-
case 15:
7333
-
swstats->rx_unkn_err_cnt++;
7334
-
break;
7335
-
}
7336
-
/*
7337
-
* Drop the packet if bad transfer code. Exception being
7338
-
* 0x5, which could be due to unsupported IPv6 extension header.
7339
-
* In this case, we let stack handle the packet.
7340
-
* Note that in this case, since checksum will be incorrect,
7341
-
* stack will validate the same.
7342
-
*/
7343
-
if (err_mask != 0x5) {
7344
-
DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7345
-
dev->name, err_mask);
7346
-
dev->stats.rx_crc_errors++;
7347
-
swstats->mem_freed
7348
-
+= skb->truesize;
7349
-
dev_kfree_skb(skb);
7350
-
ring_data->rx_bufs_left -= 1;
7351
-
rxdp->Host_Control = 0;
7352
-
return 0;
7353
-
}
7354
-
}
7355
-
7356
-
rxdp->Host_Control = 0;
7357
-
if (sp->rxd_mode == RXD_MODE_1) {
7358
-
int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7359
-
7360
-
skb_put(skb, len);
7361
-
} else if (sp->rxd_mode == RXD_MODE_3B) {
7362
-
int get_block = ring_data->rx_curr_get_info.block_index;
7363
-
int get_off = ring_data->rx_curr_get_info.offset;
7364
-
int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7365
-
int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7366
-
7367
-
struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7368
-
skb_put_data(skb, ba->ba_0, buf0_len);
7369
-
skb_put(skb, buf2_len);
7370
-
}
7371
-
7372
-
if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7373
-
((!ring_data->lro) ||
7374
-
(!(rxdp->Control_1 & RXD_FRAME_IP_FRAG))) &&
7375
-
(dev->features & NETIF_F_RXCSUM)) {
7376
-
l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7377
-
l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7378
-
if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7379
-
/*
7380
-
* NIC verifies if the Checksum of the received
7381
-
* frame is Ok or not and accordingly returns
7382
-
* a flag in the RxD.
7383
-
*/
7384
-
skb->ip_summed = CHECKSUM_UNNECESSARY;
7385
-
if (ring_data->lro) {
7386
-
u32 tcp_len = 0;
7387
-
u8 *tcp;
7388
-
int ret = 0;
7389
-
7390
-
ret = s2io_club_tcp_session(ring_data,
7391
-
skb->data, &tcp,
7392
-
&tcp_len, &lro,
7393
-
rxdp, sp);
7394
-
switch (ret) {
7395
-
case 3: /* Begin anew */
7396
-
lro->parent = skb;
7397
-
goto aggregate;
7398
-
case 1: /* Aggregate */
7399
-
lro_append_pkt(sp, lro, skb, tcp_len);
7400
-
goto aggregate;
7401
-
case 4: /* Flush session */
7402
-
lro_append_pkt(sp, lro, skb, tcp_len);
7403
-
queue_rx_frame(lro->parent,
7404
-
lro->vlan_tag);
7405
-
clear_lro_session(lro);
7406
-
swstats->flush_max_pkts++;
7407
-
goto aggregate;
7408
-
case 2: /* Flush both */
7409
-
lro->parent->data_len = lro->frags_len;
7410
-
swstats->sending_both++;
7411
-
queue_rx_frame(lro->parent,
7412
-
lro->vlan_tag);
7413
-
clear_lro_session(lro);
7414
-
goto send_up;
7415
-
case 0: /* sessions exceeded */
7416
-
case -1: /* non-TCP or not L2 aggregatable */
7417
-
case 5: /*
7418
-
* First pkt in session not
7419
-
* L3/L4 aggregatable
7420
-
*/
7421
-
break;
7422
-
default:
7423
-
DBG_PRINT(ERR_DBG,
7424
-
"%s: Samadhana!!\n",
7425
-
__func__);
7426
-
BUG();
7427
-
}
7428
-
}
7429
-
} else {
7430
-
/*
7431
-
* Packet with erroneous checksum, let the
7432
-
* upper layers deal with it.
7433
-
*/
7434
-
skb_checksum_none_assert(skb);
7435
-
}
7436
-
} else
7437
-
skb_checksum_none_assert(skb);
7438
-
7439
-
swstats->mem_freed += skb->truesize;
7440
-
send_up:
7441
-
skb_record_rx_queue(skb, ring_no);
7442
-
queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7443
-
aggregate:
7444
-
sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7445
-
return SUCCESS;
7446
-
}
7447
-
7448
-
/**
7449
-
* s2io_link - stops/starts the Tx queue.
7450
-
* @sp : private member of the device structure, which is a pointer to the
7451
-
* s2io_nic structure.
7452
-
* @link : inidicates whether link is UP/DOWN.
7453
-
* Description:
7454
-
* This function stops/starts the Tx queue depending on whether the link
7455
-
* status of the NIC is down or up. This is called by the Alarm
7456
-
* interrupt handler whenever a link change interrupt comes up.
7457
-
* Return value:
7458
-
* void.
7459
-
*/
7460
-
7461
-
static void s2io_link(struct s2io_nic *sp, int link)
7462
-
{
7463
-
struct net_device *dev = sp->dev;
7464
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7465
-
7466
-
if (link != sp->last_link_state) {
7467
-
init_tti(sp, link, false);
7468
-
if (link == LINK_DOWN) {
7469
-
DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7470
-
s2io_stop_all_tx_queue(sp);
7471
-
netif_carrier_off(dev);
7472
-
if (swstats->link_up_cnt)
7473
-
swstats->link_up_time =
7474
-
jiffies - sp->start_time;
7475
-
swstats->link_down_cnt++;
7476
-
} else {
7477
-
DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7478
-
if (swstats->link_down_cnt)
7479
-
swstats->link_down_time =
7480
-
jiffies - sp->start_time;
7481
-
swstats->link_up_cnt++;
7482
-
netif_carrier_on(dev);
7483
-
s2io_wake_all_tx_queue(sp);
7484
-
}
7485
-
}
7486
-
sp->last_link_state = link;
7487
-
sp->start_time = jiffies;
7488
-
}
7489
-
7490
-
/**
7491
-
* s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7492
-
* @sp : private member of the device structure, which is a pointer to the
7493
-
* s2io_nic structure.
7494
-
* Description:
7495
-
* This function initializes a few of the PCI and PCI-X configuration registers
7496
-
* with recommended values.
7497
-
* Return value:
7498
-
* void
7499
-
*/
7500
-
7501
-
static void s2io_init_pci(struct s2io_nic *sp)
7502
-
{
7503
-
u16 pci_cmd = 0, pcix_cmd = 0;
7504
-
7505
-
/* Enable Data Parity Error Recovery in PCI-X command register. */
7506
-
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7507
-
&(pcix_cmd));
7508
-
pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7509
-
(pcix_cmd | 1));
7510
-
pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7511
-
&(pcix_cmd));
7512
-
7513
-
/* Set the PErr Response bit in PCI command register. */
7514
-
pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7515
-
pci_write_config_word(sp->pdev, PCI_COMMAND,
7516
-
(pci_cmd | PCI_COMMAND_PARITY));
7517
-
pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7518
-
}
7519
-
7520
-
static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7521
-
u8 *dev_multiq)
7522
-
{
7523
-
int i;
7524
-
7525
-
if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7526
-
DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7527
-
"(%d) not supported\n", tx_fifo_num);
7528
-
7529
-
if (tx_fifo_num < 1)
7530
-
tx_fifo_num = 1;
7531
-
else
7532
-
tx_fifo_num = MAX_TX_FIFOS;
7533
-
7534
-
DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7535
-
}
7536
-
7537
-
if (multiq)
7538
-
*dev_multiq = multiq;
7539
-
7540
-
if (tx_steering_type && (1 == tx_fifo_num)) {
7541
-
if (tx_steering_type != TX_DEFAULT_STEERING)
7542
-
DBG_PRINT(ERR_DBG,
7543
-
"Tx steering is not supported with "
7544
-
"one fifo. Disabling Tx steering.\n");
7545
-
tx_steering_type = NO_STEERING;
7546
-
}
7547
-
7548
-
if ((tx_steering_type < NO_STEERING) ||
7549
-
(tx_steering_type > TX_DEFAULT_STEERING)) {
7550
-
DBG_PRINT(ERR_DBG,
7551
-
"Requested transmit steering not supported\n");
7552
-
DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7553
-
tx_steering_type = NO_STEERING;
7554
-
}
7555
-
7556
-
if (rx_ring_num > MAX_RX_RINGS) {
7557
-
DBG_PRINT(ERR_DBG,
7558
-
"Requested number of rx rings not supported\n");
7559
-
DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7560
-
MAX_RX_RINGS);
7561
-
rx_ring_num = MAX_RX_RINGS;
7562
-
}
7563
-
7564
-
if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7565
-
DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7566
-
"Defaulting to INTA\n");
7567
-
*dev_intr_type = INTA;
7568
-
}
7569
-
7570
-
if ((*dev_intr_type == MSI_X) &&
7571
-
((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7572
-
(pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7573
-
DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7574
-
"Defaulting to INTA\n");
7575
-
*dev_intr_type = INTA;
7576
-
}
7577
-
7578
-
if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7579
-
DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7580
-
DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7581
-
rx_ring_mode = 1;
7582
-
}
7583
-
7584
-
for (i = 0; i < MAX_RX_RINGS; i++)
7585
-
if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7586
-
DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7587
-
"supported\nDefaulting to %d\n",
7588
-
MAX_RX_BLOCKS_PER_RING);
7589
-
rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7590
-
}
7591
-
7592
-
return SUCCESS;
7593
-
}
7594
-
7595
-
/**
7596
-
* rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS or Traffic class respectively.
7597
-
* @nic: device private variable
7598
-
* @ds_codepoint: data
7599
-
* @ring: ring index
7600
-
* Description: The function configures the receive steering to
7601
-
* desired receive ring.
7602
-
* Return Value: SUCCESS on success and
7603
-
* '-1' on failure (endian settings incorrect).
7604
-
*/
7605
-
static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7606
-
{
7607
-
struct XENA_dev_config __iomem *bar0 = nic->bar0;
7608
-
register u64 val64 = 0;
7609
-
7610
-
if (ds_codepoint > 63)
7611
-
return FAILURE;
7612
-
7613
-
val64 = RTS_DS_MEM_DATA(ring);
7614
-
writeq(val64, &bar0->rts_ds_mem_data);
7615
-
7616
-
val64 = RTS_DS_MEM_CTRL_WE |
7617
-
RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7618
-
RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7619
-
7620
-
writeq(val64, &bar0->rts_ds_mem_ctrl);
7621
-
7622
-
return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7623
-
RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7624
-
S2IO_BIT_RESET, true);
7625
-
}
7626
-
7627
-
static const struct net_device_ops s2io_netdev_ops = {
7628
-
.ndo_open = s2io_open,
7629
-
.ndo_stop = s2io_close,
7630
-
.ndo_get_stats = s2io_get_stats,
7631
-
.ndo_start_xmit = s2io_xmit,
7632
-
.ndo_validate_addr = eth_validate_addr,
7633
-
.ndo_set_rx_mode = s2io_ndo_set_multicast,
7634
-
.ndo_eth_ioctl = s2io_ioctl,
7635
-
.ndo_set_mac_address = s2io_set_mac_addr,
7636
-
.ndo_change_mtu = s2io_change_mtu,
7637
-
.ndo_set_features = s2io_set_features,
7638
-
.ndo_tx_timeout = s2io_tx_watchdog,
7639
-
#ifdef CONFIG_NET_POLL_CONTROLLER
7640
-
.ndo_poll_controller = s2io_netpoll,
7641
-
#endif
7642
-
};
7643
-
7644
-
/**
7645
-
* s2io_init_nic - Initialization of the adapter .
7646
-
* @pdev : structure containing the PCI related information of the device.
7647
-
* @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7648
-
* Description:
7649
-
* The function initializes an adapter identified by the pci_dec structure.
7650
-
* All OS related initialization including memory and device structure and
7651
-
* initlaization of the device private variable is done. Also the swapper
7652
-
* control register is initialized to enable read and write into the I/O
7653
-
* registers of the device.
7654
-
* Return value:
7655
-
* returns 0 on success and negative on failure.
7656
-
*/
7657
-
7658
-
static int
7659
-
s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7660
-
{
7661
-
struct s2io_nic *sp;
7662
-
struct net_device *dev;
7663
-
int i, j, ret;
7664
-
u32 mac_up, mac_down;
7665
-
u64 val64 = 0, tmp64 = 0;
7666
-
struct XENA_dev_config __iomem *bar0 = NULL;
7667
-
u16 subid;
7668
-
struct config_param *config;
7669
-
struct mac_info *mac_control;
7670
-
int mode;
7671
-
u8 dev_intr_type = intr_type;
7672
-
u8 dev_multiq = 0;
7673
-
7674
-
ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7675
-
if (ret)
7676
-
return ret;
7677
-
7678
-
ret = pci_enable_device(pdev);
7679
-
if (ret) {
7680
-
DBG_PRINT(ERR_DBG,
7681
-
"%s: pci_enable_device failed\n", __func__);
7682
-
return ret;
7683
-
}
7684
-
7685
-
if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7686
-
DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7687
-
} else {
7688
-
pci_disable_device(pdev);
7689
-
return -ENOMEM;
7690
-
}
7691
-
ret = pci_request_regions(pdev, s2io_driver_name);
7692
-
if (ret) {
7693
-
DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7694
-
__func__, ret);
7695
-
pci_disable_device(pdev);
7696
-
return -ENODEV;
7697
-
}
7698
-
if (dev_multiq)
7699
-
dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7700
-
else
7701
-
dev = alloc_etherdev(sizeof(struct s2io_nic));
7702
-
if (dev == NULL) {
7703
-
pci_disable_device(pdev);
7704
-
pci_release_regions(pdev);
7705
-
return -ENODEV;
7706
-
}
7707
-
7708
-
pci_set_master(pdev);
7709
-
pci_set_drvdata(pdev, dev);
7710
-
SET_NETDEV_DEV(dev, &pdev->dev);
7711
-
7712
-
/* Private member variable initialized to s2io NIC structure */
7713
-
sp = netdev_priv(dev);
7714
-
sp->dev = dev;
7715
-
sp->pdev = pdev;
7716
-
sp->device_enabled_once = false;
7717
-
if (rx_ring_mode == 1)
7718
-
sp->rxd_mode = RXD_MODE_1;
7719
-
if (rx_ring_mode == 2)
7720
-
sp->rxd_mode = RXD_MODE_3B;
7721
-
7722
-
sp->config.intr_type = dev_intr_type;
7723
-
7724
-
if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7725
-
(pdev->device == PCI_DEVICE_ID_HERC_UNI))
7726
-
sp->device_type = XFRAME_II_DEVICE;
7727
-
else
7728
-
sp->device_type = XFRAME_I_DEVICE;
7729
-
7730
-
7731
-
/* Initialize some PCI/PCI-X fields of the NIC. */
7732
-
s2io_init_pci(sp);
7733
-
7734
-
/*
7735
-
* Setting the device configuration parameters.
7736
-
* Most of these parameters can be specified by the user during
7737
-
* module insertion as they are module loadable parameters. If
7738
-
* these parameters are not specified during load time, they
7739
-
* are initialized with default values.
7740
-
*/
7741
-
config = &sp->config;
7742
-
mac_control = &sp->mac_control;
7743
-
7744
-
config->napi = napi;
7745
-
config->tx_steering_type = tx_steering_type;
7746
-
7747
-
/* Tx side parameters. */
7748
-
if (config->tx_steering_type == TX_PRIORITY_STEERING)
7749
-
config->tx_fifo_num = MAX_TX_FIFOS;
7750
-
else
7751
-
config->tx_fifo_num = tx_fifo_num;
7752
-
7753
-
/* Initialize the fifos used for tx steering */
7754
-
if (config->tx_fifo_num < 5) {
7755
-
if (config->tx_fifo_num == 1)
7756
-
sp->total_tcp_fifos = 1;
7757
-
else
7758
-
sp->total_tcp_fifos = config->tx_fifo_num - 1;
7759
-
sp->udp_fifo_idx = config->tx_fifo_num - 1;
7760
-
sp->total_udp_fifos = 1;
7761
-
sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7762
-
} else {
7763
-
sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7764
-
FIFO_OTHER_MAX_NUM);
7765
-
sp->udp_fifo_idx = sp->total_tcp_fifos;
7766
-
sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7767
-
sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7768
-
}
7769
-
7770
-
config->multiq = dev_multiq;
7771
-
for (i = 0; i < config->tx_fifo_num; i++) {
7772
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7773
-
7774
-
tx_cfg->fifo_len = tx_fifo_len[i];
7775
-
tx_cfg->fifo_priority = i;
7776
-
}
7777
-
7778
-
/* mapping the QoS priority to the configured fifos */
7779
-
for (i = 0; i < MAX_TX_FIFOS; i++)
7780
-
config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7781
-
7782
-
/* map the hashing selector table to the configured fifos */
7783
-
for (i = 0; i < config->tx_fifo_num; i++)
7784
-
sp->fifo_selector[i] = fifo_selector[i];
7785
-
7786
-
7787
-
config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7788
-
for (i = 0; i < config->tx_fifo_num; i++) {
7789
-
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7790
-
7791
-
tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7792
-
if (tx_cfg->fifo_len < 65) {
7793
-
config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7794
-
break;
7795
-
}
7796
-
}
7797
-
/* + 2 because one Txd for skb->data and one Txd for UFO */
7798
-
config->max_txds = MAX_SKB_FRAGS + 2;
7799
-
7800
-
/* Rx side parameters. */
7801
-
config->rx_ring_num = rx_ring_num;
7802
-
for (i = 0; i < config->rx_ring_num; i++) {
7803
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7804
-
struct ring_info *ring = &mac_control->rings[i];
7805
-
7806
-
rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7807
-
rx_cfg->ring_priority = i;
7808
-
ring->rx_bufs_left = 0;
7809
-
ring->rxd_mode = sp->rxd_mode;
7810
-
ring->rxd_count = rxd_count[sp->rxd_mode];
7811
-
ring->pdev = sp->pdev;
7812
-
ring->dev = sp->dev;
7813
-
}
7814
-
7815
-
for (i = 0; i < rx_ring_num; i++) {
7816
-
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7817
-
7818
-
rx_cfg->ring_org = RING_ORG_BUFF1;
7819
-
rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7820
-
}
7821
-
7822
-
/* Setting Mac Control parameters */
7823
-
mac_control->rmac_pause_time = rmac_pause_time;
7824
-
mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7825
-
mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7826
-
7827
-
7828
-
/* initialize the shared memory used by the NIC and the host */
7829
-
if (init_shared_mem(sp)) {
7830
-
DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7831
-
ret = -ENOMEM;
7832
-
goto mem_alloc_failed;
7833
-
}
7834
-
7835
-
sp->bar0 = pci_ioremap_bar(pdev, 0);
7836
-
if (!sp->bar0) {
7837
-
DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7838
-
dev->name);
7839
-
ret = -ENOMEM;
7840
-
goto bar0_remap_failed;
7841
-
}
7842
-
7843
-
sp->bar1 = pci_ioremap_bar(pdev, 2);
7844
-
if (!sp->bar1) {
7845
-
DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7846
-
dev->name);
7847
-
ret = -ENOMEM;
7848
-
goto bar1_remap_failed;
7849
-
}
7850
-
7851
-
/* Initializing the BAR1 address as the start of the FIFO pointer. */
7852
-
for (j = 0; j < MAX_TX_FIFOS; j++) {
7853
-
mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7854
-
}
7855
-
7856
-
/* Driver entry points */
7857
-
dev->netdev_ops = &s2io_netdev_ops;
7858
-
dev->ethtool_ops = &netdev_ethtool_ops;
7859
-
dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7860
-
NETIF_F_TSO | NETIF_F_TSO6 |
7861
-
NETIF_F_RXCSUM | NETIF_F_LRO;
7862
-
dev->features |= dev->hw_features |
7863
-
NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
7864
-
NETIF_F_HIGHDMA;
7865
-
dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7866
-
INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7867
-
INIT_WORK(&sp->set_link_task, s2io_set_link);
7868
-
7869
-
pci_save_state(sp->pdev);
7870
-
7871
-
/* Setting swapper control on the NIC, for proper reset operation */
7872
-
if (s2io_set_swapper(sp)) {
7873
-
DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7874
-
dev->name);
7875
-
ret = -EAGAIN;
7876
-
goto set_swap_failed;
7877
-
}
7878
-
7879
-
/* Verify if the Herc works on the slot its placed into */
7880
-
if (sp->device_type & XFRAME_II_DEVICE) {
7881
-
mode = s2io_verify_pci_mode(sp);
7882
-
if (mode < 0) {
7883
-
DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7884
-
__func__);
7885
-
ret = -EBADSLT;
7886
-
goto set_swap_failed;
7887
-
}
7888
-
}
7889
-
7890
-
if (sp->config.intr_type == MSI_X) {
7891
-
sp->num_entries = config->rx_ring_num + 1;
7892
-
ret = s2io_enable_msi_x(sp);
7893
-
7894
-
if (!ret) {
7895
-
ret = s2io_test_msi(sp);
7896
-
/* rollback MSI-X, will re-enable during add_isr() */
7897
-
remove_msix_isr(sp);
7898
-
}
7899
-
if (ret) {
7900
-
7901
-
DBG_PRINT(ERR_DBG,
7902
-
"MSI-X requested but failed to enable\n");
7903
-
sp->config.intr_type = INTA;
7904
-
}
7905
-
}
7906
-
7907
-
if (config->intr_type == MSI_X) {
7908
-
for (i = 0; i < config->rx_ring_num ; i++) {
7909
-
struct ring_info *ring = &mac_control->rings[i];
7910
-
7911
-
netif_napi_add(dev, &ring->napi, s2io_poll_msix);
7912
-
}
7913
-
} else {
7914
-
netif_napi_add(dev, &sp->napi, s2io_poll_inta);
7915
-
}
7916
-
7917
-
/* Not needed for Herc */
7918
-
if (sp->device_type & XFRAME_I_DEVICE) {
7919
-
/*
7920
-
* Fix for all "FFs" MAC address problems observed on
7921
-
* Alpha platforms
7922
-
*/
7923
-
fix_mac_address(sp);
7924
-
s2io_reset(sp);
7925
-
}
7926
-
7927
-
/*
7928
-
* MAC address initialization.
7929
-
* For now only one mac address will be read and used.
7930
-
*/
7931
-
bar0 = sp->bar0;
7932
-
val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7933
-
RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
7934
-
writeq(val64, &bar0->rmac_addr_cmd_mem);
7935
-
wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7936
-
RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
7937
-
S2IO_BIT_RESET, true);
7938
-
tmp64 = readq(&bar0->rmac_addr_data0_mem);
7939
-
mac_down = (u32)tmp64;
7940
-
mac_up = (u32) (tmp64 >> 32);
7941
-
7942
-
sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7943
-
sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7944
-
sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7945
-
sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7946
-
sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7947
-
sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7948
-
7949
-
/* Set the factory defined MAC address initially */
7950
-
dev->addr_len = ETH_ALEN;
7951
-
eth_hw_addr_set(dev, sp->def_mac_addr[0].mac_addr);
7952
-
7953
-
/* initialize number of multicast & unicast MAC entries variables */
7954
-
if (sp->device_type == XFRAME_I_DEVICE) {
7955
-
config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7956
-
config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7957
-
config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7958
-
} else if (sp->device_type == XFRAME_II_DEVICE) {
7959
-
config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7960
-
config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7961
-
config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7962
-
}
7963
-
7964
-
/* MTU range: 46 - 9600 */
7965
-
dev->min_mtu = MIN_MTU;
7966
-
dev->max_mtu = S2IO_JUMBO_SIZE;
7967
-
7968
-
/* store mac addresses from CAM to s2io_nic structure */
7969
-
do_s2io_store_unicast_mc(sp);
7970
-
7971
-
/* Configure MSIX vector for number of rings configured plus one */
7972
-
if ((sp->device_type == XFRAME_II_DEVICE) &&
7973
-
(config->intr_type == MSI_X))
7974
-
sp->num_entries = config->rx_ring_num + 1;
7975
-
7976
-
/* Store the values of the MSIX table in the s2io_nic structure */
7977
-
store_xmsi_data(sp);
7978
-
/* reset Nic and bring it to known state */
7979
-
s2io_reset(sp);
7980
-
7981
-
/*
7982
-
* Initialize link state flags
7983
-
* and the card state parameter
7984
-
*/
7985
-
sp->state = 0;
7986
-
7987
-
/* Initialize spinlocks */
7988
-
for (i = 0; i < sp->config.tx_fifo_num; i++) {
7989
-
struct fifo_info *fifo = &mac_control->fifos[i];
7990
-
7991
-
spin_lock_init(&fifo->tx_lock);
7992
-
}
7993
-
7994
-
/*
7995
-
* SXE-002: Configure link and activity LED to init state
7996
-
* on driver load.
7997
-
*/
7998
-
subid = sp->pdev->subsystem_device;
7999
-
if ((subid & 0xFF) >= 0x07) {
8000
-
val64 = readq(&bar0->gpio_control);
8001
-
val64 |= 0x0000800000000000ULL;
8002
-
writeq(val64, &bar0->gpio_control);
8003
-
val64 = 0x0411040400000000ULL;
8004
-
writeq(val64, (void __iomem *)bar0 + 0x2700);
8005
-
val64 = readq(&bar0->gpio_control);
8006
-
}
8007
-
8008
-
sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8009
-
8010
-
if (register_netdev(dev)) {
8011
-
DBG_PRINT(ERR_DBG, "Device registration failed\n");
8012
-
ret = -ENODEV;
8013
-
goto register_failed;
8014
-
}
8015
-
s2io_vpd_read(sp);
8016
-
DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8017
-
DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8018
-
sp->product_name, pdev->revision);
8019
-
DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8020
-
s2io_driver_version);
8021
-
DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8022
-
DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8023
-
if (sp->device_type & XFRAME_II_DEVICE) {
8024
-
mode = s2io_print_pci_mode(sp);
8025
-
if (mode < 0) {
8026
-
ret = -EBADSLT;
8027
-
unregister_netdev(dev);
8028
-
goto set_swap_failed;
8029
-
}
8030
-
}
8031
-
switch (sp->rxd_mode) {
8032
-
case RXD_MODE_1:
8033
-
DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8034
-
dev->name);
8035
-
break;
8036
-
case RXD_MODE_3B:
8037
-
DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8038
-
dev->name);
8039
-
break;
8040
-
}
8041
-
8042
-
switch (sp->config.napi) {
8043
-
case 0:
8044
-
DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8045
-
break;
8046
-
case 1:
8047
-
DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8048
-
break;
8049
-
}
8050
-
8051
-
DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8052
-
sp->config.tx_fifo_num);
8053
-
8054
-
DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8055
-
sp->config.rx_ring_num);
8056
-
8057
-
switch (sp->config.intr_type) {
8058
-
case INTA:
8059
-
DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8060
-
break;
8061
-
case MSI_X:
8062
-
DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8063
-
break;
8064
-
}
8065
-
if (sp->config.multiq) {
8066
-
for (i = 0; i < sp->config.tx_fifo_num; i++) {
8067
-
struct fifo_info *fifo = &mac_control->fifos[i];
8068
-
8069
-
fifo->multiq = config->multiq;
8070
-
}
8071
-
DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8072
-
dev->name);
8073
-
} else
8074
-
DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8075
-
dev->name);
8076
-
8077
-
switch (sp->config.tx_steering_type) {
8078
-
case NO_STEERING:
8079
-
DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8080
-
dev->name);
8081
-
break;
8082
-
case TX_PRIORITY_STEERING:
8083
-
DBG_PRINT(ERR_DBG,
8084
-
"%s: Priority steering enabled for transmit\n",
8085
-
dev->name);
8086
-
break;
8087
-
case TX_DEFAULT_STEERING:
8088
-
DBG_PRINT(ERR_DBG,
8089
-
"%s: Default steering enabled for transmit\n",
8090
-
dev->name);
8091
-
}
8092
-
8093
-
DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8094
-
dev->name);
8095
-
/* Initialize device name */
8096
-
snprintf(sp->name, sizeof(sp->name), "%s Neterion %s", dev->name,
8097
-
sp->product_name);
8098
-
8099
-
if (vlan_tag_strip)
8100
-
sp->vlan_strip_flag = 1;
8101
-
else
8102
-
sp->vlan_strip_flag = 0;
8103
-
8104
-
/*
8105
-
* Make Link state as off at this point, when the Link change
8106
-
* interrupt comes the state will be automatically changed to
8107
-
* the right state.
8108
-
*/
8109
-
netif_carrier_off(dev);
8110
-
8111
-
return 0;
8112
-
8113
-
register_failed:
8114
-
set_swap_failed:
8115
-
iounmap(sp->bar1);
8116
-
bar1_remap_failed:
8117
-
iounmap(sp->bar0);
8118
-
bar0_remap_failed:
8119
-
mem_alloc_failed:
8120
-
free_shared_mem(sp);
8121
-
pci_disable_device(pdev);
8122
-
pci_release_regions(pdev);
8123
-
free_netdev(dev);
8124
-
8125
-
return ret;
8126
-
}
8127
-
8128
-
/**
8129
-
* s2io_rem_nic - Free the PCI device
8130
-
* @pdev: structure containing the PCI related information of the device.
8131
-
* Description: This function is called by the Pci subsystem to release a
8132
-
* PCI device and free up all resource held up by the device. This could
8133
-
* be in response to a Hot plug event or when the driver is to be removed
8134
-
* from memory.
8135
-
*/
8136
-
8137
-
static void s2io_rem_nic(struct pci_dev *pdev)
8138
-
{
8139
-
struct net_device *dev = pci_get_drvdata(pdev);
8140
-
struct s2io_nic *sp;
8141
-
8142
-
if (dev == NULL) {
8143
-
DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8144
-
return;
8145
-
}
8146
-
8147
-
sp = netdev_priv(dev);
8148
-
8149
-
cancel_work_sync(&sp->rst_timer_task);
8150
-
cancel_work_sync(&sp->set_link_task);
8151
-
8152
-
unregister_netdev(dev);
8153
-
8154
-
free_shared_mem(sp);
8155
-
iounmap(sp->bar0);
8156
-
iounmap(sp->bar1);
8157
-
pci_release_regions(pdev);
8158
-
free_netdev(dev);
8159
-
pci_disable_device(pdev);
8160
-
}
8161
-
8162
-
module_pci_driver(s2io_driver);
8163
-
8164
-
static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8165
-
struct tcphdr **tcp, struct RxD_t *rxdp,
8166
-
struct s2io_nic *sp)
8167
-
{
8168
-
int ip_off;
8169
-
u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8170
-
8171
-
if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8172
-
DBG_PRINT(INIT_DBG,
8173
-
"%s: Non-TCP frames not supported for LRO\n",
8174
-
__func__);
8175
-
return -1;
8176
-
}
8177
-
8178
-
/* Checking for DIX type or DIX type with VLAN */
8179
-
if ((l2_type == 0) || (l2_type == 4)) {
8180
-
ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8181
-
/*
8182
-
* If vlan stripping is disabled and the frame is VLAN tagged,
8183
-
* shift the offset by the VLAN header size bytes.
8184
-
*/
8185
-
if ((!sp->vlan_strip_flag) &&
8186
-
(rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8187
-
ip_off += HEADER_VLAN_SIZE;
8188
-
} else {
8189
-
/* LLC, SNAP etc are considered non-mergeable */
8190
-
return -1;
8191
-
}
8192
-
8193
-
*ip = (struct iphdr *)(buffer + ip_off);
8194
-
ip_len = (u8)((*ip)->ihl);
8195
-
ip_len <<= 2;
8196
-
*tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8197
-
8198
-
return 0;
8199
-
}
8200
-
8201
-
static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8202
-
struct tcphdr *tcp)
8203
-
{
8204
-
DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8205
-
if ((lro->iph->saddr != ip->saddr) ||
8206
-
(lro->iph->daddr != ip->daddr) ||
8207
-
(lro->tcph->source != tcp->source) ||
8208
-
(lro->tcph->dest != tcp->dest))
8209
-
return -1;
8210
-
return 0;
8211
-
}
8212
-
8213
-
static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8214
-
{
8215
-
return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8216
-
}
8217
-
8218
-
static void initiate_new_session(struct lro *lro, u8 *l2h,
8219
-
struct iphdr *ip, struct tcphdr *tcp,
8220
-
u32 tcp_pyld_len, u16 vlan_tag)
8221
-
{
8222
-
DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8223
-
lro->l2h = l2h;
8224
-
lro->iph = ip;
8225
-
lro->tcph = tcp;
8226
-
lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8227
-
lro->tcp_ack = tcp->ack_seq;
8228
-
lro->sg_num = 1;
8229
-
lro->total_len = ntohs(ip->tot_len);
8230
-
lro->frags_len = 0;
8231
-
lro->vlan_tag = vlan_tag;
8232
-
/*
8233
-
* Check if we saw TCP timestamp.
8234
-
* Other consistency checks have already been done.
8235
-
*/
8236
-
if (tcp->doff == 8) {
8237
-
__be32 *ptr;
8238
-
ptr = (__be32 *)(tcp+1);
8239
-
lro->saw_ts = 1;
8240
-
lro->cur_tsval = ntohl(*(ptr+1));
8241
-
lro->cur_tsecr = *(ptr+2);
8242
-
}
8243
-
lro->in_use = 1;
8244
-
}
8245
-
8246
-
static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8247
-
{
8248
-
struct iphdr *ip = lro->iph;
8249
-
struct tcphdr *tcp = lro->tcph;
8250
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8251
-
8252
-
DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8253
-
8254
-
/* Update L3 header */
8255
-
csum_replace2(&ip->check, ip->tot_len, htons(lro->total_len));
8256
-
ip->tot_len = htons(lro->total_len);
8257
-
8258
-
/* Update L4 header */
8259
-
tcp->ack_seq = lro->tcp_ack;
8260
-
tcp->window = lro->window;
8261
-
8262
-
/* Update tsecr field if this session has timestamps enabled */
8263
-
if (lro->saw_ts) {
8264
-
__be32 *ptr = (__be32 *)(tcp + 1);
8265
-
*(ptr+2) = lro->cur_tsecr;
8266
-
}
8267
-
8268
-
/* Update counters required for calculation of
8269
-
* average no. of packets aggregated.
8270
-
*/
8271
-
swstats->sum_avg_pkts_aggregated += lro->sg_num;
8272
-
swstats->num_aggregations++;
8273
-
}
8274
-
8275
-
static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8276
-
struct tcphdr *tcp, u32 l4_pyld)
8277
-
{
8278
-
DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8279
-
lro->total_len += l4_pyld;
8280
-
lro->frags_len += l4_pyld;
8281
-
lro->tcp_next_seq += l4_pyld;
8282
-
lro->sg_num++;
8283
-
8284
-
/* Update ack seq no. and window ad(from this pkt) in LRO object */
8285
-
lro->tcp_ack = tcp->ack_seq;
8286
-
lro->window = tcp->window;
8287
-
8288
-
if (lro->saw_ts) {
8289
-
__be32 *ptr;
8290
-
/* Update tsecr and tsval from this packet */
8291
-
ptr = (__be32 *)(tcp+1);
8292
-
lro->cur_tsval = ntohl(*(ptr+1));
8293
-
lro->cur_tsecr = *(ptr + 2);
8294
-
}
8295
-
}
8296
-
8297
-
static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8298
-
struct tcphdr *tcp, u32 tcp_pyld_len)
8299
-
{
8300
-
u8 *ptr;
8301
-
8302
-
DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8303
-
8304
-
if (!tcp_pyld_len) {
8305
-
/* Runt frame or a pure ack */
8306
-
return -1;
8307
-
}
8308
-
8309
-
if (ip->ihl != 5) /* IP has options */
8310
-
return -1;
8311
-
8312
-
/* If we see CE codepoint in IP header, packet is not mergeable */
8313
-
if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8314
-
return -1;
8315
-
8316
-
/* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8317
-
if (tcp->urg || tcp->psh || tcp->rst ||
8318
-
tcp->syn || tcp->fin ||
8319
-
tcp->ece || tcp->cwr || !tcp->ack) {
8320
-
/*
8321
-
* Currently recognize only the ack control word and
8322
-
* any other control field being set would result in
8323
-
* flushing the LRO session
8324
-
*/
8325
-
return -1;
8326
-
}
8327
-
8328
-
/*
8329
-
* Allow only one TCP timestamp option. Don't aggregate if
8330
-
* any other options are detected.
8331
-
*/
8332
-
if (tcp->doff != 5 && tcp->doff != 8)
8333
-
return -1;
8334
-
8335
-
if (tcp->doff == 8) {
8336
-
ptr = (u8 *)(tcp + 1);
8337
-
while (*ptr == TCPOPT_NOP)
8338
-
ptr++;
8339
-
if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8340
-
return -1;
8341
-
8342
-
/* Ensure timestamp value increases monotonically */
8343
-
if (l_lro)
8344
-
if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8345
-
return -1;
8346
-
8347
-
/* timestamp echo reply should be non-zero */
8348
-
if (*((__be32 *)(ptr+6)) == 0)
8349
-
return -1;
8350
-
}
8351
-
8352
-
return 0;
8353
-
}
8354
-
8355
-
static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8356
-
u8 **tcp, u32 *tcp_len, struct lro **lro,
8357
-
struct RxD_t *rxdp, struct s2io_nic *sp)
8358
-
{
8359
-
struct iphdr *ip;
8360
-
struct tcphdr *tcph;
8361
-
int ret = 0, i;
8362
-
u16 vlan_tag = 0;
8363
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8364
-
8365
-
ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8366
-
rxdp, sp);
8367
-
if (ret)
8368
-
return ret;
8369
-
8370
-
DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8371
-
8372
-
vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8373
-
tcph = (struct tcphdr *)*tcp;
8374
-
*tcp_len = get_l4_pyld_length(ip, tcph);
8375
-
for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8376
-
struct lro *l_lro = &ring_data->lro0_n[i];
8377
-
if (l_lro->in_use) {
8378
-
if (check_for_socket_match(l_lro, ip, tcph))
8379
-
continue;
8380
-
/* Sock pair matched */
8381
-
*lro = l_lro;
8382
-
8383
-
if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8384
-
DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8385
-
"expected 0x%x, actual 0x%x\n",
8386
-
__func__,
8387
-
(*lro)->tcp_next_seq,
8388
-
ntohl(tcph->seq));
8389
-
8390
-
swstats->outof_sequence_pkts++;
8391
-
ret = 2;
8392
-
break;
8393
-
}
8394
-
8395
-
if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8396
-
*tcp_len))
8397
-
ret = 1; /* Aggregate */
8398
-
else
8399
-
ret = 2; /* Flush both */
8400
-
break;
8401
-
}
8402
-
}
8403
-
8404
-
if (ret == 0) {
8405
-
/* Before searching for available LRO objects,
8406
-
* check if the pkt is L3/L4 aggregatable. If not
8407
-
* don't create new LRO session. Just send this
8408
-
* packet up.
8409
-
*/
8410
-
if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8411
-
return 5;
8412
-
8413
-
for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8414
-
struct lro *l_lro = &ring_data->lro0_n[i];
8415
-
if (!(l_lro->in_use)) {
8416
-
*lro = l_lro;
8417
-
ret = 3; /* Begin anew */
8418
-
break;
8419
-
}
8420
-
}
8421
-
}
8422
-
8423
-
if (ret == 0) { /* sessions exceeded */
8424
-
DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8425
-
__func__);
8426
-
*lro = NULL;
8427
-
return ret;
8428
-
}
8429
-
8430
-
switch (ret) {
8431
-
case 3:
8432
-
initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8433
-
vlan_tag);
8434
-
break;
8435
-
case 2:
8436
-
update_L3L4_header(sp, *lro);
8437
-
break;
8438
-
case 1:
8439
-
aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8440
-
if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8441
-
update_L3L4_header(sp, *lro);
8442
-
ret = 4; /* Flush the LRO */
8443
-
}
8444
-
break;
8445
-
default:
8446
-
DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8447
-
break;
8448
-
}
8449
-
8450
-
return ret;
8451
-
}
8452
-
8453
-
static void clear_lro_session(struct lro *lro)
8454
-
{
8455
-
static u16 lro_struct_size = sizeof(struct lro);
8456
-
8457
-
memset(lro, 0, lro_struct_size);
8458
-
}
8459
-
8460
-
static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8461
-
{
8462
-
struct net_device *dev = skb->dev;
8463
-
struct s2io_nic *sp = netdev_priv(dev);
8464
-
8465
-
skb->protocol = eth_type_trans(skb, dev);
8466
-
if (vlan_tag && sp->vlan_strip_flag)
8467
-
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
8468
-
if (sp->config.napi)
8469
-
netif_receive_skb(skb);
8470
-
else
8471
-
netif_rx(skb);
8472
-
}
8473
-
8474
-
static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8475
-
struct sk_buff *skb, u32 tcp_len)
8476
-
{
8477
-
struct sk_buff *first = lro->parent;
8478
-
struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8479
-
8480
-
first->len += tcp_len;
8481
-
first->data_len = lro->frags_len;
8482
-
skb_pull(skb, (skb->len - tcp_len));
8483
-
if (skb_shinfo(first)->frag_list)
8484
-
lro->last_frag->next = skb;
8485
-
else
8486
-
skb_shinfo(first)->frag_list = skb;
8487
-
first->truesize += skb->truesize;
8488
-
lro->last_frag = skb;
8489
-
swstats->clubbed_frms_cnt++;
8490
-
}
8491
-
8492
-
/**
8493
-
* s2io_io_error_detected - called when PCI error is detected
8494
-
* @pdev: Pointer to PCI device
8495
-
* @state: The current pci connection state
8496
-
*
8497
-
* This function is called after a PCI bus error affecting
8498
-
* this device has been detected.
8499
-
*/
8500
-
static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8501
-
pci_channel_state_t state)
8502
-
{
8503
-
struct net_device *netdev = pci_get_drvdata(pdev);
8504
-
struct s2io_nic *sp = netdev_priv(netdev);
8505
-
8506
-
netif_device_detach(netdev);
8507
-
8508
-
if (state == pci_channel_io_perm_failure)
8509
-
return PCI_ERS_RESULT_DISCONNECT;
8510
-
8511
-
if (netif_running(netdev)) {
8512
-
/* Bring down the card, while avoiding PCI I/O */
8513
-
do_s2io_card_down(sp, 0);
8514
-
}
8515
-
pci_disable_device(pdev);
8516
-
8517
-
return PCI_ERS_RESULT_NEED_RESET;
8518
-
}
8519
-
8520
-
/**
8521
-
* s2io_io_slot_reset - called after the pci bus has been reset.
8522
-
* @pdev: Pointer to PCI device
8523
-
*
8524
-
* Restart the card from scratch, as if from a cold-boot.
8525
-
* At this point, the card has experienced a hard reset,
8526
-
* followed by fixups by BIOS, and has its config space
8527
-
* set up identically to what it was at cold boot.
8528
-
*/
8529
-
static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8530
-
{
8531
-
struct net_device *netdev = pci_get_drvdata(pdev);
8532
-
struct s2io_nic *sp = netdev_priv(netdev);
8533
-
8534
-
if (pci_enable_device(pdev)) {
8535
-
pr_err("Cannot re-enable PCI device after reset.\n");
8536
-
return PCI_ERS_RESULT_DISCONNECT;
8537
-
}
8538
-
8539
-
pci_set_master(pdev);
8540
-
s2io_reset(sp);
8541
-
8542
-
return PCI_ERS_RESULT_RECOVERED;
8543
-
}
8544
-
8545
-
/**
8546
-
* s2io_io_resume - called when traffic can start flowing again.
8547
-
* @pdev: Pointer to PCI device
8548
-
*
8549
-
* This callback is called when the error recovery driver tells
8550
-
* us that its OK to resume normal operation.
8551
-
*/
8552
-
static void s2io_io_resume(struct pci_dev *pdev)
8553
-
{
8554
-
struct net_device *netdev = pci_get_drvdata(pdev);
8555
-
struct s2io_nic *sp = netdev_priv(netdev);
8556
-
8557
-
if (netif_running(netdev)) {
8558
-
if (s2io_card_up(sp)) {
8559
-
pr_err("Can't bring device back up after reset.\n");
8560
-
return;
8561
-
}
8562
-
8563
-
if (do_s2io_prog_unicast(netdev, netdev->dev_addr) == FAILURE) {
8564
-
s2io_card_down(sp);
8565
-
pr_err("Can't restore mac addr after reset.\n");
8566
-
return;
8567
-
}
8568
-
}
8569
-
8570
-
netif_device_attach(netdev);
8571
-
netif_tx_wake_all_queues(netdev);
8572
-
}
-1124
drivers/net/ethernet/neterion/s2io.h
-1124
drivers/net/ethernet/neterion/s2io.h
···
1
-
/************************************************************************
2
-
* s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3
-
* Copyright(c) 2002-2010 Exar Corp.
4
-
5
-
* This software may be used and distributed according to the terms of
6
-
* the GNU General Public License (GPL), incorporated herein by reference.
7
-
* Drivers based on or derived from this code fall under the GPL and must
8
-
* retain the authorship, copyright and license notice. This file is not
9
-
* a complete program and may only be used when the entire operating
10
-
* system is licensed under the GPL.
11
-
* See the file COPYING in this distribution for more information.
12
-
************************************************************************/
13
-
#include <linux/io-64-nonatomic-lo-hi.h>
14
-
#ifndef _S2IO_H
15
-
#define _S2IO_H
16
-
17
-
#define TBD 0
18
-
#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
19
-
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
20
-
#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
21
-
22
-
#undef SUCCESS
23
-
#define SUCCESS 0
24
-
#define FAILURE -1
25
-
#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
26
-
#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
27
-
#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
28
-
#define S2IO_BIT_RESET 1
29
-
#define S2IO_BIT_SET 2
30
-
#define CHECKBIT(value, nbit) (value & (1 << nbit))
31
-
32
-
/* Maximum time to flicker LED when asked to identify NIC using ethtool */
33
-
#define MAX_FLICKER_TIME 60000 /* 60 Secs */
34
-
35
-
/* Maximum outstanding splits to be configured into xena. */
36
-
enum {
37
-
XENA_ONE_SPLIT_TRANSACTION = 0,
38
-
XENA_TWO_SPLIT_TRANSACTION = 1,
39
-
XENA_THREE_SPLIT_TRANSACTION = 2,
40
-
XENA_FOUR_SPLIT_TRANSACTION = 3,
41
-
XENA_EIGHT_SPLIT_TRANSACTION = 4,
42
-
XENA_TWELVE_SPLIT_TRANSACTION = 5,
43
-
XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
44
-
XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
45
-
};
46
-
#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
47
-
48
-
/* OS concerned variables and constants */
49
-
#define WATCH_DOG_TIMEOUT 15*HZ
50
-
#define EFILL 0x1234
51
-
#define ALIGN_SIZE 127
52
-
#define PCIX_COMMAND_REGISTER 0x62
53
-
54
-
/*
55
-
* Debug related variables.
56
-
*/
57
-
/* different debug levels. */
58
-
#define ERR_DBG 0
59
-
#define INIT_DBG 1
60
-
#define INFO_DBG 2
61
-
#define TX_DBG 3
62
-
#define INTR_DBG 4
63
-
64
-
/* Global variable that defines the present debug level of the driver. */
65
-
static int debug_level = ERR_DBG;
66
-
67
-
/* DEBUG message print. */
68
-
#define DBG_PRINT(dbg_level, fmt, args...) do { \
69
-
if (dbg_level <= debug_level) \
70
-
pr_info(fmt, ##args); \
71
-
} while (0)
72
-
73
-
/* Protocol assist features of the NIC */
74
-
#define L3_CKSUM_OK 0xFFFF
75
-
#define L4_CKSUM_OK 0xFFFF
76
-
#define S2IO_JUMBO_SIZE 9600
77
-
78
-
/* Driver statistics maintained by driver */
79
-
struct swStat {
80
-
unsigned long long single_ecc_errs;
81
-
unsigned long long double_ecc_errs;
82
-
unsigned long long parity_err_cnt;
83
-
unsigned long long serious_err_cnt;
84
-
unsigned long long soft_reset_cnt;
85
-
unsigned long long fifo_full_cnt;
86
-
unsigned long long ring_full_cnt[8];
87
-
/* LRO statistics */
88
-
unsigned long long clubbed_frms_cnt;
89
-
unsigned long long sending_both;
90
-
unsigned long long outof_sequence_pkts;
91
-
unsigned long long flush_max_pkts;
92
-
unsigned long long sum_avg_pkts_aggregated;
93
-
unsigned long long num_aggregations;
94
-
/* Other statistics */
95
-
unsigned long long mem_alloc_fail_cnt;
96
-
unsigned long long pci_map_fail_cnt;
97
-
unsigned long long watchdog_timer_cnt;
98
-
unsigned long long mem_allocated;
99
-
unsigned long long mem_freed;
100
-
unsigned long long link_up_cnt;
101
-
unsigned long long link_down_cnt;
102
-
unsigned long long link_up_time;
103
-
unsigned long long link_down_time;
104
-
105
-
/* Transfer Code statistics */
106
-
unsigned long long tx_buf_abort_cnt;
107
-
unsigned long long tx_desc_abort_cnt;
108
-
unsigned long long tx_parity_err_cnt;
109
-
unsigned long long tx_link_loss_cnt;
110
-
unsigned long long tx_list_proc_err_cnt;
111
-
112
-
unsigned long long rx_parity_err_cnt;
113
-
unsigned long long rx_abort_cnt;
114
-
unsigned long long rx_parity_abort_cnt;
115
-
unsigned long long rx_rda_fail_cnt;
116
-
unsigned long long rx_unkn_prot_cnt;
117
-
unsigned long long rx_fcs_err_cnt;
118
-
unsigned long long rx_buf_size_err_cnt;
119
-
unsigned long long rx_rxd_corrupt_cnt;
120
-
unsigned long long rx_unkn_err_cnt;
121
-
122
-
/* Error/alarm statistics*/
123
-
unsigned long long tda_err_cnt;
124
-
unsigned long long pfc_err_cnt;
125
-
unsigned long long pcc_err_cnt;
126
-
unsigned long long tti_err_cnt;
127
-
unsigned long long lso_err_cnt;
128
-
unsigned long long tpa_err_cnt;
129
-
unsigned long long sm_err_cnt;
130
-
unsigned long long mac_tmac_err_cnt;
131
-
unsigned long long mac_rmac_err_cnt;
132
-
unsigned long long xgxs_txgxs_err_cnt;
133
-
unsigned long long xgxs_rxgxs_err_cnt;
134
-
unsigned long long rc_err_cnt;
135
-
unsigned long long prc_pcix_err_cnt;
136
-
unsigned long long rpa_err_cnt;
137
-
unsigned long long rda_err_cnt;
138
-
unsigned long long rti_err_cnt;
139
-
unsigned long long mc_err_cnt;
140
-
141
-
};
142
-
143
-
/* Xpak releated alarm and warnings */
144
-
struct xpakStat {
145
-
u64 alarm_transceiver_temp_high;
146
-
u64 alarm_transceiver_temp_low;
147
-
u64 alarm_laser_bias_current_high;
148
-
u64 alarm_laser_bias_current_low;
149
-
u64 alarm_laser_output_power_high;
150
-
u64 alarm_laser_output_power_low;
151
-
u64 warn_transceiver_temp_high;
152
-
u64 warn_transceiver_temp_low;
153
-
u64 warn_laser_bias_current_high;
154
-
u64 warn_laser_bias_current_low;
155
-
u64 warn_laser_output_power_high;
156
-
u64 warn_laser_output_power_low;
157
-
u64 xpak_regs_stat;
158
-
u32 xpak_timer_count;
159
-
};
160
-
161
-
162
-
/* The statistics block of Xena */
163
-
struct stat_block {
164
-
/* Tx MAC statistics counters. */
165
-
__le32 tmac_data_octets;
166
-
__le32 tmac_frms;
167
-
__le64 tmac_drop_frms;
168
-
__le32 tmac_bcst_frms;
169
-
__le32 tmac_mcst_frms;
170
-
__le64 tmac_pause_ctrl_frms;
171
-
__le32 tmac_ucst_frms;
172
-
__le32 tmac_ttl_octets;
173
-
__le32 tmac_any_err_frms;
174
-
__le32 tmac_nucst_frms;
175
-
__le64 tmac_ttl_less_fb_octets;
176
-
__le64 tmac_vld_ip_octets;
177
-
__le32 tmac_drop_ip;
178
-
__le32 tmac_vld_ip;
179
-
__le32 tmac_rst_tcp;
180
-
__le32 tmac_icmp;
181
-
__le64 tmac_tcp;
182
-
__le32 reserved_0;
183
-
__le32 tmac_udp;
184
-
185
-
/* Rx MAC Statistics counters. */
186
-
__le32 rmac_data_octets;
187
-
__le32 rmac_vld_frms;
188
-
__le64 rmac_fcs_err_frms;
189
-
__le64 rmac_drop_frms;
190
-
__le32 rmac_vld_bcst_frms;
191
-
__le32 rmac_vld_mcst_frms;
192
-
__le32 rmac_out_rng_len_err_frms;
193
-
__le32 rmac_in_rng_len_err_frms;
194
-
__le64 rmac_long_frms;
195
-
__le64 rmac_pause_ctrl_frms;
196
-
__le64 rmac_unsup_ctrl_frms;
197
-
__le32 rmac_accepted_ucst_frms;
198
-
__le32 rmac_ttl_octets;
199
-
__le32 rmac_discarded_frms;
200
-
__le32 rmac_accepted_nucst_frms;
201
-
__le32 reserved_1;
202
-
__le32 rmac_drop_events;
203
-
__le64 rmac_ttl_less_fb_octets;
204
-
__le64 rmac_ttl_frms;
205
-
__le64 reserved_2;
206
-
__le32 rmac_usized_frms;
207
-
__le32 reserved_3;
208
-
__le32 rmac_frag_frms;
209
-
__le32 rmac_osized_frms;
210
-
__le32 reserved_4;
211
-
__le32 rmac_jabber_frms;
212
-
__le64 rmac_ttl_64_frms;
213
-
__le64 rmac_ttl_65_127_frms;
214
-
__le64 reserved_5;
215
-
__le64 rmac_ttl_128_255_frms;
216
-
__le64 rmac_ttl_256_511_frms;
217
-
__le64 reserved_6;
218
-
__le64 rmac_ttl_512_1023_frms;
219
-
__le64 rmac_ttl_1024_1518_frms;
220
-
__le32 rmac_ip;
221
-
__le32 reserved_7;
222
-
__le64 rmac_ip_octets;
223
-
__le32 rmac_drop_ip;
224
-
__le32 rmac_hdr_err_ip;
225
-
__le32 reserved_8;
226
-
__le32 rmac_icmp;
227
-
__le64 rmac_tcp;
228
-
__le32 rmac_err_drp_udp;
229
-
__le32 rmac_udp;
230
-
__le64 rmac_xgmii_err_sym;
231
-
__le64 rmac_frms_q0;
232
-
__le64 rmac_frms_q1;
233
-
__le64 rmac_frms_q2;
234
-
__le64 rmac_frms_q3;
235
-
__le64 rmac_frms_q4;
236
-
__le64 rmac_frms_q5;
237
-
__le64 rmac_frms_q6;
238
-
__le64 rmac_frms_q7;
239
-
__le16 rmac_full_q3;
240
-
__le16 rmac_full_q2;
241
-
__le16 rmac_full_q1;
242
-
__le16 rmac_full_q0;
243
-
__le16 rmac_full_q7;
244
-
__le16 rmac_full_q6;
245
-
__le16 rmac_full_q5;
246
-
__le16 rmac_full_q4;
247
-
__le32 reserved_9;
248
-
__le32 rmac_pause_cnt;
249
-
__le64 rmac_xgmii_data_err_cnt;
250
-
__le64 rmac_xgmii_ctrl_err_cnt;
251
-
__le32 rmac_err_tcp;
252
-
__le32 rmac_accepted_ip;
253
-
254
-
/* PCI/PCI-X Read transaction statistics. */
255
-
__le32 new_rd_req_cnt;
256
-
__le32 rd_req_cnt;
257
-
__le32 rd_rtry_cnt;
258
-
__le32 new_rd_req_rtry_cnt;
259
-
260
-
/* PCI/PCI-X Write/Read transaction statistics. */
261
-
__le32 wr_req_cnt;
262
-
__le32 wr_rtry_rd_ack_cnt;
263
-
__le32 new_wr_req_rtry_cnt;
264
-
__le32 new_wr_req_cnt;
265
-
__le32 wr_disc_cnt;
266
-
__le32 wr_rtry_cnt;
267
-
268
-
/* PCI/PCI-X Write / DMA Transaction statistics. */
269
-
__le32 txp_wr_cnt;
270
-
__le32 rd_rtry_wr_ack_cnt;
271
-
__le32 txd_wr_cnt;
272
-
__le32 txd_rd_cnt;
273
-
__le32 rxd_wr_cnt;
274
-
__le32 rxd_rd_cnt;
275
-
__le32 rxf_wr_cnt;
276
-
__le32 txf_rd_cnt;
277
-
278
-
/* Tx MAC statistics overflow counters. */
279
-
__le32 tmac_data_octets_oflow;
280
-
__le32 tmac_frms_oflow;
281
-
__le32 tmac_bcst_frms_oflow;
282
-
__le32 tmac_mcst_frms_oflow;
283
-
__le32 tmac_ucst_frms_oflow;
284
-
__le32 tmac_ttl_octets_oflow;
285
-
__le32 tmac_any_err_frms_oflow;
286
-
__le32 tmac_nucst_frms_oflow;
287
-
__le64 tmac_vlan_frms;
288
-
__le32 tmac_drop_ip_oflow;
289
-
__le32 tmac_vld_ip_oflow;
290
-
__le32 tmac_rst_tcp_oflow;
291
-
__le32 tmac_icmp_oflow;
292
-
__le32 tpa_unknown_protocol;
293
-
__le32 tmac_udp_oflow;
294
-
__le32 reserved_10;
295
-
__le32 tpa_parse_failure;
296
-
297
-
/* Rx MAC Statistics overflow counters. */
298
-
__le32 rmac_data_octets_oflow;
299
-
__le32 rmac_vld_frms_oflow;
300
-
__le32 rmac_vld_bcst_frms_oflow;
301
-
__le32 rmac_vld_mcst_frms_oflow;
302
-
__le32 rmac_accepted_ucst_frms_oflow;
303
-
__le32 rmac_ttl_octets_oflow;
304
-
__le32 rmac_discarded_frms_oflow;
305
-
__le32 rmac_accepted_nucst_frms_oflow;
306
-
__le32 rmac_usized_frms_oflow;
307
-
__le32 rmac_drop_events_oflow;
308
-
__le32 rmac_frag_frms_oflow;
309
-
__le32 rmac_osized_frms_oflow;
310
-
__le32 rmac_ip_oflow;
311
-
__le32 rmac_jabber_frms_oflow;
312
-
__le32 rmac_icmp_oflow;
313
-
__le32 rmac_drop_ip_oflow;
314
-
__le32 rmac_err_drp_udp_oflow;
315
-
__le32 rmac_udp_oflow;
316
-
__le32 reserved_11;
317
-
__le32 rmac_pause_cnt_oflow;
318
-
__le64 rmac_ttl_1519_4095_frms;
319
-
__le64 rmac_ttl_4096_8191_frms;
320
-
__le64 rmac_ttl_8192_max_frms;
321
-
__le64 rmac_ttl_gt_max_frms;
322
-
__le64 rmac_osized_alt_frms;
323
-
__le64 rmac_jabber_alt_frms;
324
-
__le64 rmac_gt_max_alt_frms;
325
-
__le64 rmac_vlan_frms;
326
-
__le32 rmac_len_discard;
327
-
__le32 rmac_fcs_discard;
328
-
__le32 rmac_pf_discard;
329
-
__le32 rmac_da_discard;
330
-
__le32 rmac_red_discard;
331
-
__le32 rmac_rts_discard;
332
-
__le32 reserved_12;
333
-
__le32 rmac_ingm_full_discard;
334
-
__le32 reserved_13;
335
-
__le32 rmac_accepted_ip_oflow;
336
-
__le32 reserved_14;
337
-
__le32 link_fault_cnt;
338
-
u8 buffer[20];
339
-
struct swStat sw_stat;
340
-
struct xpakStat xpak_stat;
341
-
};
342
-
343
-
/* Default value for 'vlan_strip_tag' configuration parameter */
344
-
#define NO_STRIP_IN_PROMISC 2
345
-
346
-
/*
347
-
* Structures representing different init time configuration
348
-
* parameters of the NIC.
349
-
*/
350
-
351
-
#define MAX_TX_FIFOS 8
352
-
#define MAX_RX_RINGS 8
353
-
354
-
#define FIFO_DEFAULT_NUM 5
355
-
#define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */
356
-
#define FIFO_OTHER_MAX_NUM 1
357
-
358
-
359
-
#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128)
360
-
#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86)
361
-
#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
362
-
363
-
/* FIFO mappings for all possible number of fifos configured */
364
-
static const int fifo_map[][MAX_TX_FIFOS] = {
365
-
{0, 0, 0, 0, 0, 0, 0, 0},
366
-
{0, 0, 0, 0, 1, 1, 1, 1},
367
-
{0, 0, 0, 1, 1, 1, 2, 2},
368
-
{0, 0, 1, 1, 2, 2, 3, 3},
369
-
{0, 0, 1, 1, 2, 2, 3, 4},
370
-
{0, 0, 1, 1, 2, 3, 4, 5},
371
-
{0, 0, 1, 2, 3, 4, 5, 6},
372
-
{0, 1, 2, 3, 4, 5, 6, 7},
373
-
};
374
-
375
-
static const u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
376
-
377
-
/* Maintains Per FIFO related information. */
378
-
struct tx_fifo_config {
379
-
#define MAX_AVAILABLE_TXDS 8192
380
-
u32 fifo_len; /* specifies len of FIFO up to 8192, ie no of TxDLs */
381
-
/* Priority definition */
382
-
#define TX_FIFO_PRI_0 0 /*Highest */
383
-
#define TX_FIFO_PRI_1 1
384
-
#define TX_FIFO_PRI_2 2
385
-
#define TX_FIFO_PRI_3 3
386
-
#define TX_FIFO_PRI_4 4
387
-
#define TX_FIFO_PRI_5 5
388
-
#define TX_FIFO_PRI_6 6
389
-
#define TX_FIFO_PRI_7 7 /*lowest */
390
-
u8 fifo_priority; /* specifies pointer level for FIFO */
391
-
/* user should not set twos fifos with same pri */
392
-
u8 f_no_snoop;
393
-
#define NO_SNOOP_TXD 0x01
394
-
#define NO_SNOOP_TXD_BUFFER 0x02
395
-
};
396
-
397
-
398
-
/* Maintains per Ring related information */
399
-
struct rx_ring_config {
400
-
u32 num_rxd; /*No of RxDs per Rx Ring */
401
-
#define RX_RING_PRI_0 0 /* highest */
402
-
#define RX_RING_PRI_1 1
403
-
#define RX_RING_PRI_2 2
404
-
#define RX_RING_PRI_3 3
405
-
#define RX_RING_PRI_4 4
406
-
#define RX_RING_PRI_5 5
407
-
#define RX_RING_PRI_6 6
408
-
#define RX_RING_PRI_7 7 /* lowest */
409
-
410
-
u8 ring_priority; /*Specifies service priority of ring */
411
-
/* OSM should not set any two rings with same priority */
412
-
u8 ring_org; /*Organization of ring */
413
-
#define RING_ORG_BUFF1 0x01
414
-
#define RX_RING_ORG_BUFF3 0x03
415
-
#define RX_RING_ORG_BUFF5 0x05
416
-
417
-
u8 f_no_snoop;
418
-
#define NO_SNOOP_RXD 0x01
419
-
#define NO_SNOOP_RXD_BUFFER 0x02
420
-
};
421
-
422
-
/* This structure provides contains values of the tunable parameters
423
-
* of the H/W
424
-
*/
425
-
struct config_param {
426
-
/* Tx Side */
427
-
u32 tx_fifo_num; /*Number of Tx FIFOs */
428
-
429
-
/* 0-No steering, 1-Priority steering, 2-Default fifo map */
430
-
#define NO_STEERING 0
431
-
#define TX_PRIORITY_STEERING 0x1
432
-
#define TX_DEFAULT_STEERING 0x2
433
-
u8 tx_steering_type;
434
-
435
-
u8 fifo_mapping[MAX_TX_FIFOS];
436
-
struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
437
-
u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
438
-
u64 tx_intr_type;
439
-
#define INTA 0
440
-
#define MSI_X 2
441
-
u8 intr_type;
442
-
u8 napi;
443
-
444
-
/* Specifies if Tx Intr is UTILZ or PER_LIST type. */
445
-
446
-
/* Rx Side */
447
-
u32 rx_ring_num; /*Number of receive rings */
448
-
#define MAX_RX_BLOCKS_PER_RING 150
449
-
450
-
struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
451
-
452
-
#define HEADER_ETHERNET_II_802_3_SIZE 14
453
-
#define HEADER_802_2_SIZE 3
454
-
#define HEADER_SNAP_SIZE 5
455
-
#define HEADER_VLAN_SIZE 4
456
-
457
-
#define MIN_MTU 46
458
-
#define MAX_PYLD 1500
459
-
#define MAX_MTU (MAX_PYLD+18)
460
-
#define MAX_MTU_VLAN (MAX_PYLD+22)
461
-
#define MAX_PYLD_JUMBO 9600
462
-
#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
463
-
#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
464
-
u16 bus_speed;
465
-
int max_mc_addr; /* xena=64 herc=256 */
466
-
int max_mac_addr; /* xena=16 herc=64 */
467
-
int mc_start_offset; /* xena=16 herc=64 */
468
-
u8 multiq;
469
-
};
470
-
471
-
/* Structure representing MAC Addrs */
472
-
struct mac_addr {
473
-
u8 mac_addr[ETH_ALEN];
474
-
};
475
-
476
-
/* Structure that represent every FIFO element in the BAR1
477
-
* Address location.
478
-
*/
479
-
struct TxFIFO_element {
480
-
u64 TxDL_Pointer;
481
-
482
-
u64 List_Control;
483
-
#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
484
-
#define TX_FIFO_FIRST_LIST s2BIT(14)
485
-
#define TX_FIFO_LAST_LIST s2BIT(15)
486
-
#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
487
-
#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
488
-
#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
489
-
#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
490
-
};
491
-
492
-
/* Tx descriptor structure */
493
-
struct TxD {
494
-
u64 Control_1;
495
-
/* bit mask */
496
-
#define TXD_LIST_OWN_XENA s2BIT(7)
497
-
#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
498
-
#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
499
-
#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
500
-
#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
501
-
#define TXD_GATHER_CODE_FIRST s2BIT(22)
502
-
#define TXD_GATHER_CODE_LAST s2BIT(23)
503
-
#define TXD_TCP_LSO_EN s2BIT(30)
504
-
#define TXD_UDP_COF_EN s2BIT(31)
505
-
#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
506
-
#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
507
-
#define TXD_UFO_MSS(val) vBIT(val,34,14)
508
-
#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
509
-
510
-
u64 Control_2;
511
-
#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
512
-
#define TXD_TX_CKO_IPV4_EN s2BIT(5)
513
-
#define TXD_TX_CKO_TCP_EN s2BIT(6)
514
-
#define TXD_TX_CKO_UDP_EN s2BIT(7)
515
-
#define TXD_VLAN_ENABLE s2BIT(15)
516
-
#define TXD_VLAN_TAG(val) vBIT(val,16,16)
517
-
#define TXD_INT_NUMBER(val) vBIT(val,34,6)
518
-
#define TXD_INT_TYPE_PER_LIST s2BIT(47)
519
-
#define TXD_INT_TYPE_UTILZ s2BIT(46)
520
-
#define TXD_SET_MARKER vBIT(0x6,0,4)
521
-
522
-
u64 Buffer_Pointer;
523
-
u64 Host_Control; /* reserved for host */
524
-
};
525
-
526
-
/* Structure to hold the phy and virt addr of every TxDL. */
527
-
struct list_info_hold {
528
-
dma_addr_t list_phy_addr;
529
-
void *list_virt_addr;
530
-
};
531
-
532
-
/* Rx descriptor structure for 1 buffer mode */
533
-
struct RxD_t {
534
-
u64 Host_Control; /* reserved for host */
535
-
u64 Control_1;
536
-
#define RXD_OWN_XENA s2BIT(7)
537
-
#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
538
-
#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
539
-
#define RXD_FRAME_VLAN_TAG s2BIT(24)
540
-
#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
541
-
#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
542
-
#define RXD_FRAME_IP_FRAG s2BIT(29)
543
-
#define RXD_FRAME_PROTO_TCP s2BIT(30)
544
-
#define RXD_FRAME_PROTO_UDP s2BIT(31)
545
-
#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
546
-
#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
547
-
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
548
-
549
-
u64 Control_2;
550
-
#define THE_RXD_MARK 0x3
551
-
#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
552
-
#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
553
-
554
-
#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
555
-
#define SET_VLAN_TAG(val) vBIT(val,48,16)
556
-
#define SET_NUM_TAG(val) vBIT(val,16,32)
557
-
558
-
559
-
};
560
-
/* Rx descriptor structure for 1 buffer mode */
561
-
struct RxD1 {
562
-
struct RxD_t h;
563
-
564
-
#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
565
-
#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
566
-
#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
567
-
(u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
568
-
u64 Buffer0_ptr;
569
-
};
570
-
/* Rx descriptor structure for 3 or 2 buffer mode */
571
-
572
-
struct RxD3 {
573
-
struct RxD_t h;
574
-
575
-
#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
576
-
#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
577
-
#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
578
-
#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
579
-
#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
580
-
#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
581
-
#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
582
-
(u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
583
-
#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
584
-
(u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
585
-
#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
586
-
(u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
587
-
#define BUF0_LEN 40
588
-
#define BUF1_LEN 1
589
-
590
-
u64 Buffer0_ptr;
591
-
u64 Buffer1_ptr;
592
-
u64 Buffer2_ptr;
593
-
};
594
-
595
-
596
-
/* Structure that represents the Rx descriptor block which contains
597
-
* 128 Rx descriptors.
598
-
*/
599
-
struct RxD_block {
600
-
#define MAX_RXDS_PER_BLOCK_1 127
601
-
struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
602
-
603
-
u64 reserved_0;
604
-
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
605
-
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
606
-
* Rxd in this blk */
607
-
u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
608
-
u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
609
-
* the upper 32 bits should
610
-
* be 0 */
611
-
};
612
-
613
-
#define SIZE_OF_BLOCK 4096
614
-
615
-
#define RXD_MODE_1 0 /* One Buffer mode */
616
-
#define RXD_MODE_3B 1 /* Two Buffer mode */
617
-
618
-
/* Structure to hold virtual addresses of Buf0 and Buf1 in
619
-
* 2buf mode. */
620
-
struct buffAdd {
621
-
void *ba_0_org;
622
-
void *ba_1_org;
623
-
void *ba_0;
624
-
void *ba_1;
625
-
};
626
-
627
-
/* Structure which stores all the MAC control parameters */
628
-
629
-
/* This structure stores the offset of the RxD in the ring
630
-
* from which the Rx Interrupt processor can start picking
631
-
* up the RxDs for processing.
632
-
*/
633
-
struct rx_curr_get_info {
634
-
u32 block_index;
635
-
u32 offset;
636
-
u32 ring_len;
637
-
};
638
-
639
-
struct rx_curr_put_info {
640
-
u32 block_index;
641
-
u32 offset;
642
-
u32 ring_len;
643
-
};
644
-
645
-
/* This structure stores the offset of the TxDl in the FIFO
646
-
* from which the Tx Interrupt processor can start picking
647
-
* up the TxDLs for send complete interrupt processing.
648
-
*/
649
-
struct tx_curr_get_info {
650
-
u32 offset;
651
-
u32 fifo_len;
652
-
};
653
-
654
-
struct tx_curr_put_info {
655
-
u32 offset;
656
-
u32 fifo_len;
657
-
};
658
-
659
-
struct rxd_info {
660
-
void *virt_addr;
661
-
dma_addr_t dma_addr;
662
-
};
663
-
664
-
/* Structure that holds the Phy and virt addresses of the Blocks */
665
-
struct rx_block_info {
666
-
void *block_virt_addr;
667
-
dma_addr_t block_dma_addr;
668
-
struct rxd_info *rxds;
669
-
};
670
-
671
-
/* Data structure to represent a LRO session */
672
-
struct lro {
673
-
struct sk_buff *parent;
674
-
struct sk_buff *last_frag;
675
-
u8 *l2h;
676
-
struct iphdr *iph;
677
-
struct tcphdr *tcph;
678
-
u32 tcp_next_seq;
679
-
__be32 tcp_ack;
680
-
int total_len;
681
-
int frags_len;
682
-
int sg_num;
683
-
int in_use;
684
-
__be16 window;
685
-
u16 vlan_tag;
686
-
u32 cur_tsval;
687
-
__be32 cur_tsecr;
688
-
u8 saw_ts;
689
-
} ____cacheline_aligned;
690
-
691
-
/* Ring specific structure */
692
-
struct ring_info {
693
-
/* The ring number */
694
-
int ring_no;
695
-
696
-
/* per-ring buffer counter */
697
-
u32 rx_bufs_left;
698
-
699
-
#define MAX_LRO_SESSIONS 32
700
-
struct lro lro0_n[MAX_LRO_SESSIONS];
701
-
u8 lro;
702
-
703
-
/* copy of sp->rxd_mode flag */
704
-
int rxd_mode;
705
-
706
-
/* Number of rxds per block for the rxd_mode */
707
-
int rxd_count;
708
-
709
-
/* copy of sp pointer */
710
-
struct s2io_nic *nic;
711
-
712
-
/* copy of sp->dev pointer */
713
-
struct net_device *dev;
714
-
715
-
/* copy of sp->pdev pointer */
716
-
struct pci_dev *pdev;
717
-
718
-
/* Per ring napi struct */
719
-
struct napi_struct napi;
720
-
721
-
unsigned long interrupt_count;
722
-
723
-
/*
724
-
* Place holders for the virtual and physical addresses of
725
-
* all the Rx Blocks
726
-
*/
727
-
struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
728
-
int block_count;
729
-
int pkt_cnt;
730
-
731
-
/*
732
-
* Put pointer info which indictes which RxD has to be replenished
733
-
* with a new buffer.
734
-
*/
735
-
struct rx_curr_put_info rx_curr_put_info;
736
-
737
-
/*
738
-
* Get pointer info which indictes which is the last RxD that was
739
-
* processed by the driver.
740
-
*/
741
-
struct rx_curr_get_info rx_curr_get_info;
742
-
743
-
/* interface MTU value */
744
-
unsigned mtu;
745
-
746
-
/* Buffer Address store. */
747
-
struct buffAdd **ba;
748
-
} ____cacheline_aligned;
749
-
750
-
/* Fifo specific structure */
751
-
struct fifo_info {
752
-
/* FIFO number */
753
-
int fifo_no;
754
-
755
-
/* Maximum TxDs per TxDL */
756
-
int max_txds;
757
-
758
-
/* Place holder of all the TX List's Phy and Virt addresses. */
759
-
struct list_info_hold *list_info;
760
-
761
-
/*
762
-
* Current offset within the tx FIFO where driver would write
763
-
* new Tx frame
764
-
*/
765
-
struct tx_curr_put_info tx_curr_put_info;
766
-
767
-
/*
768
-
* Current offset within tx FIFO from where the driver would start freeing
769
-
* the buffers
770
-
*/
771
-
struct tx_curr_get_info tx_curr_get_info;
772
-
#define FIFO_QUEUE_START 0
773
-
#define FIFO_QUEUE_STOP 1
774
-
int queue_state;
775
-
776
-
/* copy of sp->dev pointer */
777
-
struct net_device *dev;
778
-
779
-
/* copy of multiq status */
780
-
u8 multiq;
781
-
782
-
/* Per fifo lock */
783
-
spinlock_t tx_lock;
784
-
785
-
/* Per fifo UFO in band structure */
786
-
u64 *ufo_in_band_v;
787
-
788
-
struct s2io_nic *nic;
789
-
} ____cacheline_aligned;
790
-
791
-
/* Information related to the Tx and Rx FIFOs and Rings of Xena
792
-
* is maintained in this structure.
793
-
*/
794
-
struct mac_info {
795
-
/* tx side stuff */
796
-
/* logical pointer of start of each Tx FIFO */
797
-
struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
798
-
799
-
/* Fifo specific structure */
800
-
struct fifo_info fifos[MAX_TX_FIFOS];
801
-
802
-
/* Save virtual address of TxD page with zero DMA addr(if any) */
803
-
void *zerodma_virt_addr;
804
-
805
-
/* rx side stuff */
806
-
/* Ring specific structure */
807
-
struct ring_info rings[MAX_RX_RINGS];
808
-
809
-
u16 rmac_pause_time;
810
-
u16 mc_pause_threshold_q0q3;
811
-
u16 mc_pause_threshold_q4q7;
812
-
813
-
void *stats_mem; /* orignal pointer to allocated mem */
814
-
dma_addr_t stats_mem_phy; /* Physical address of the stat block */
815
-
u32 stats_mem_sz;
816
-
struct stat_block *stats_info; /* Logical address of the stat block */
817
-
};
818
-
819
-
/* Default Tunable parameters of the NIC. */
820
-
#define DEFAULT_FIFO_0_LEN 4096
821
-
#define DEFAULT_FIFO_1_7_LEN 512
822
-
#define SMALL_BLK_CNT 30
823
-
#define LARGE_BLK_CNT 100
824
-
825
-
/*
826
-
* Structure to keep track of the MSI-X vectors and the corresponding
827
-
* argument registered against each vector
828
-
*/
829
-
#define MAX_REQUESTED_MSI_X 9
830
-
struct s2io_msix_entry
831
-
{
832
-
u16 vector;
833
-
u16 entry;
834
-
void *arg;
835
-
836
-
u8 type;
837
-
#define MSIX_ALARM_TYPE 1
838
-
#define MSIX_RING_TYPE 2
839
-
840
-
u8 in_use;
841
-
#define MSIX_REGISTERED_SUCCESS 0xAA
842
-
};
843
-
844
-
struct msix_info_st {
845
-
u64 addr;
846
-
u64 data;
847
-
};
848
-
849
-
/* These flags represent the devices temporary state */
850
-
enum s2io_device_state_t
851
-
{
852
-
__S2IO_STATE_LINK_TASK=0,
853
-
__S2IO_STATE_CARD_UP
854
-
};
855
-
856
-
/* Structure representing one instance of the NIC */
857
-
struct s2io_nic {
858
-
int rxd_mode;
859
-
/*
860
-
* Count of packets to be processed in a given iteration, it will be indicated
861
-
* by the quota field of the device structure when NAPI is enabled.
862
-
*/
863
-
int pkts_to_process;
864
-
struct net_device *dev;
865
-
struct mac_info mac_control;
866
-
struct config_param config;
867
-
struct pci_dev *pdev;
868
-
void __iomem *bar0;
869
-
void __iomem *bar1;
870
-
#define MAX_MAC_SUPPORTED 16
871
-
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
872
-
873
-
struct mac_addr def_mac_addr[256];
874
-
875
-
struct net_device_stats stats;
876
-
int device_enabled_once;
877
-
878
-
char name[60];
879
-
880
-
/* Timer that handles I/O errors/exceptions */
881
-
struct timer_list alarm_timer;
882
-
883
-
/* Space to back up the PCI config space */
884
-
u32 config_space[256 / sizeof(u32)];
885
-
886
-
#define PROMISC 1
887
-
#define ALL_MULTI 2
888
-
889
-
#define MAX_ADDRS_SUPPORTED 64
890
-
u16 mc_addr_count;
891
-
892
-
u16 m_cast_flg;
893
-
u16 all_multi_pos;
894
-
u16 promisc_flg;
895
-
896
-
/* Restart timer, used to restart NIC if the device is stuck and
897
-
* a schedule task that will set the correct Link state once the
898
-
* NIC's PHY has stabilized after a state change.
899
-
*/
900
-
struct work_struct rst_timer_task;
901
-
struct work_struct set_link_task;
902
-
903
-
/* Flag that can be used to turn on or turn off the Rx checksum
904
-
* offload feature.
905
-
*/
906
-
int rx_csum;
907
-
908
-
/* Below variables are used for fifo selection to transmit a packet */
909
-
u16 fifo_selector[MAX_TX_FIFOS];
910
-
911
-
/* Total fifos for tcp packets */
912
-
u8 total_tcp_fifos;
913
-
914
-
/*
915
-
* Beginning index of udp for udp packets
916
-
* Value will be equal to
917
-
* (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
918
-
*/
919
-
u8 udp_fifo_idx;
920
-
921
-
u8 total_udp_fifos;
922
-
923
-
/*
924
-
* Beginning index of fifo for all other packets
925
-
* Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
926
-
*/
927
-
u8 other_fifo_idx;
928
-
929
-
struct napi_struct napi;
930
-
/* after blink, the adapter must be restored with original
931
-
* values.
932
-
*/
933
-
u64 adapt_ctrl_org;
934
-
935
-
/* Last known link state. */
936
-
u16 last_link_state;
937
-
#define LINK_DOWN 1
938
-
#define LINK_UP 2
939
-
940
-
int task_flag;
941
-
unsigned long long start_time;
942
-
int vlan_strip_flag;
943
-
#define MSIX_FLG 0xA5
944
-
int num_entries;
945
-
struct msix_entry *entries;
946
-
int msi_detected;
947
-
wait_queue_head_t msi_wait;
948
-
struct s2io_msix_entry *s2io_entries;
949
-
char desc[MAX_REQUESTED_MSI_X][25];
950
-
951
-
int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
952
-
953
-
struct msix_info_st msix_info[0x3f];
954
-
955
-
#define XFRAME_I_DEVICE 1
956
-
#define XFRAME_II_DEVICE 2
957
-
u8 device_type;
958
-
959
-
unsigned long clubbed_frms_cnt;
960
-
unsigned long sending_both;
961
-
u16 lro_max_aggr_per_sess;
962
-
volatile unsigned long state;
963
-
u64 general_int_mask;
964
-
965
-
#define VPD_STRING_LEN 80
966
-
u8 product_name[VPD_STRING_LEN];
967
-
u8 serial_num[VPD_STRING_LEN];
968
-
};
969
-
970
-
#define RESET_ERROR 1
971
-
#define CMD_ERROR 2
972
-
973
-
/*
974
-
* Some registers have to be written in a particular order to
975
-
* expect correct hardware operation. The macro SPECIAL_REG_WRITE
976
-
* is used to perform such ordered writes. Defines UF (Upper First)
977
-
* and LF (Lower First) will be used to specify the required write order.
978
-
*/
979
-
#define UF 1
980
-
#define LF 2
981
-
static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
982
-
{
983
-
if (order == LF) {
984
-
writel((u32) (val), addr);
985
-
(void) readl(addr);
986
-
writel((u32) (val >> 32), (addr + 4));
987
-
(void) readl(addr + 4);
988
-
} else {
989
-
writel((u32) (val >> 32), (addr + 4));
990
-
(void) readl(addr + 4);
991
-
writel((u32) (val), addr);
992
-
(void) readl(addr);
993
-
}
994
-
}
995
-
996
-
/* Interrupt related values of Xena */
997
-
998
-
#define ENABLE_INTRS 1
999
-
#define DISABLE_INTRS 2
1000
-
1001
-
/* Highest level interrupt blocks */
1002
-
#define TX_PIC_INTR (0x0001<<0)
1003
-
#define TX_DMA_INTR (0x0001<<1)
1004
-
#define TX_MAC_INTR (0x0001<<2)
1005
-
#define TX_XGXS_INTR (0x0001<<3)
1006
-
#define TX_TRAFFIC_INTR (0x0001<<4)
1007
-
#define RX_PIC_INTR (0x0001<<5)
1008
-
#define RX_DMA_INTR (0x0001<<6)
1009
-
#define RX_MAC_INTR (0x0001<<7)
1010
-
#define RX_XGXS_INTR (0x0001<<8)
1011
-
#define RX_TRAFFIC_INTR (0x0001<<9)
1012
-
#define MC_INTR (0x0001<<10)
1013
-
#define ENA_ALL_INTRS ( TX_PIC_INTR | \
1014
-
TX_DMA_INTR | \
1015
-
TX_MAC_INTR | \
1016
-
TX_XGXS_INTR | \
1017
-
TX_TRAFFIC_INTR | \
1018
-
RX_PIC_INTR | \
1019
-
RX_DMA_INTR | \
1020
-
RX_MAC_INTR | \
1021
-
RX_XGXS_INTR | \
1022
-
RX_TRAFFIC_INTR | \
1023
-
MC_INTR )
1024
-
1025
-
/* Interrupt masks for the general interrupt mask register */
1026
-
#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1027
-
1028
-
#define TXPIC_INT_M s2BIT(0)
1029
-
#define TXDMA_INT_M s2BIT(1)
1030
-
#define TXMAC_INT_M s2BIT(2)
1031
-
#define TXXGXS_INT_M s2BIT(3)
1032
-
#define TXTRAFFIC_INT_M s2BIT(8)
1033
-
#define PIC_RX_INT_M s2BIT(32)
1034
-
#define RXDMA_INT_M s2BIT(33)
1035
-
#define RXMAC_INT_M s2BIT(34)
1036
-
#define MC_INT_M s2BIT(35)
1037
-
#define RXXGXS_INT_M s2BIT(36)
1038
-
#define RXTRAFFIC_INT_M s2BIT(40)
1039
-
1040
-
/* PIC level Interrupts TODO*/
1041
-
1042
-
/* DMA level Inressupts */
1043
-
#define TXDMA_PFC_INT_M s2BIT(0)
1044
-
#define TXDMA_PCC_INT_M s2BIT(2)
1045
-
1046
-
/* PFC block interrupts */
1047
-
#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1048
-
1049
-
/* PCC block interrupts. */
1050
-
#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1051
-
PCC_FB_ECC Error. */
1052
-
1053
-
#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1054
-
/*
1055
-
* Prototype declaration.
1056
-
*/
1057
-
static int s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre);
1058
-
static void s2io_rem_nic(struct pci_dev *pdev);
1059
-
static int init_shared_mem(struct s2io_nic *sp);
1060
-
static void free_shared_mem(struct s2io_nic *sp);
1061
-
static int init_nic(struct s2io_nic *nic);
1062
-
static int rx_intr_handler(struct ring_info *ring_data, int budget);
1063
-
static void s2io_txpic_intr_handle(struct s2io_nic *sp);
1064
-
static void tx_intr_handler(struct fifo_info *fifo_data);
1065
-
static void s2io_handle_errors(void * dev_id);
1066
-
1067
-
static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue);
1068
-
static void s2io_set_multicast(struct net_device *dev, bool may_sleep);
1069
-
static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1070
-
static void s2io_link(struct s2io_nic * sp, int link);
1071
-
static void s2io_reset(struct s2io_nic * sp);
1072
-
static int s2io_poll_msix(struct napi_struct *napi, int budget);
1073
-
static int s2io_poll_inta(struct napi_struct *napi, int budget);
1074
-
static void s2io_init_pci(struct s2io_nic * sp);
1075
-
static int do_s2io_prog_unicast(struct net_device *dev, const u8 *addr);
1076
-
static void s2io_alarm_handle(struct timer_list *t);
1077
-
static irqreturn_t
1078
-
s2io_msix_ring_handle(int irq, void *dev_id);
1079
-
static irqreturn_t
1080
-
s2io_msix_fifo_handle(int irq, void *dev_id);
1081
-
static irqreturn_t s2io_isr(int irq, void *dev_id);
1082
-
static int verify_xena_quiescence(struct s2io_nic *sp);
1083
-
static const struct ethtool_ops netdev_ethtool_ops;
1084
-
static void s2io_set_link(struct work_struct *work);
1085
-
static int s2io_set_swapper(struct s2io_nic * sp);
1086
-
static void s2io_card_down(struct s2io_nic *nic);
1087
-
static int s2io_card_up(struct s2io_nic *nic);
1088
-
static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1089
-
int bit_state, bool may_sleep);
1090
-
static int s2io_add_isr(struct s2io_nic * sp);
1091
-
static void s2io_rem_isr(struct s2io_nic * sp);
1092
-
1093
-
static void restore_xmsi_data(struct s2io_nic *nic);
1094
-
static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1095
-
static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1096
-
static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1097
-
static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1098
-
static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1099
-
static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
1100
-
1101
-
static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
1102
-
u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
1103
-
struct s2io_nic *sp);
1104
-
static void clear_lro_session(struct lro *lro);
1105
-
static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
1106
-
static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1107
-
static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1108
-
struct sk_buff *skb, u32 tcp_len);
1109
-
static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
1110
-
1111
-
static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1112
-
pci_channel_state_t state);
1113
-
static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1114
-
static void s2io_io_resume(struct pci_dev *pdev);
1115
-
1116
-
#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1117
-
#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1118
-
#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1119
-
1120
-
#define S2IO_PARM_INT(X, def_val) \
1121
-
static unsigned int X = def_val;\
1122
-
module_param(X , uint, 0);
1123
-
1124
-
#endif /* _S2IO_H */