Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"One small build fix, a couple do_div() fixes, and a fix for the gpio
basic clock type are the major changes here. There's also a couple
fixes for the TI, sunxi, and scpi clock drivers"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: sunxi: pll2: Fix clock running too fast
clk: scpi: add missing of_node_put
clk: qoriq: fix memory leak
imx/clk-pllv2: fix wrong do_div() usage
imx/clk-pllv1: fix wrong do_div() usage
clk: mmp: add linux/clk.h includes
clk: ti: drop locking code from mux/divider drivers
clk: ti816x: Add missing dmtimer clkdev entries
clk: ti: fapll: fix wrong do_div() usage
clk: ti: clkt_dpll: fix wrong do_div() usage
clk: gpio: Get parent clk names in of_gpio_clk_setup()
+53
-75
+17
-16
drivers/clk/clk-gpio.c
+17
-16
drivers/clk/clk-gpio.c
···
209
209
210
210
struct clk_gpio_delayed_register_data {
211
211
const char *gpio_name;
212
+
int num_parents;
213
+
const char **parent_names;
212
214
struct device_node *node;
213
215
struct mutex lock;
214
216
struct clk *clk;
···
224
222
{
225
223
struct clk_gpio_delayed_register_data *data = _data;
226
224
struct clk *clk;
227
-
const char **parent_names;
228
-
int i, num_parents;
229
225
int gpio;
230
226
enum of_gpio_flags of_flags;
231
227
···
248
248
return ERR_PTR(gpio);
249
249
}
250
250
251
-
num_parents = of_clk_get_parent_count(data->node);
252
-
253
-
parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
254
-
if (!parent_names) {
255
-
clk = ERR_PTR(-ENOMEM);
256
-
goto out;
257
-
}
258
-
259
-
for (i = 0; i < num_parents; i++)
260
-
parent_names[i] = of_clk_get_parent_name(data->node, i);
261
-
262
-
clk = data->clk_register_get(data->node->name, parent_names,
263
-
num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW);
251
+
clk = data->clk_register_get(data->node->name, data->parent_names,
252
+
data->num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW);
264
253
if (IS_ERR(clk))
265
254
goto out;
266
255
267
256
data->clk = clk;
268
257
out:
269
258
mutex_unlock(&data->lock);
270
-
kfree(parent_names);
271
259
272
260
return clk;
273
261
}
···
284
296
unsigned gpio, bool active_low))
285
297
{
286
298
struct clk_gpio_delayed_register_data *data;
299
+
const char **parent_names;
300
+
int i, num_parents;
287
301
288
302
data = kzalloc(sizeof(*data), GFP_KERNEL);
289
303
if (!data)
290
304
return;
291
305
306
+
num_parents = of_clk_get_parent_count(node);
307
+
308
+
parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
309
+
if (!parent_names)
310
+
return;
311
+
312
+
for (i = 0; i < num_parents; i++)
313
+
parent_names[i] = of_clk_get_parent_name(node, i);
314
+
315
+
data->num_parents = num_parents;
316
+
data->parent_names = parent_names;
292
317
data->node = node;
293
318
data->gpio_name = gpio_name;
294
319
data->clk_register_get = clk_register_get;
+3
-1
drivers/clk/clk-qoriq.c
+3
-1
drivers/clk/clk-qoriq.c
+1
drivers/clk/clk-scpi.c
+1
drivers/clk/clk-scpi.c
+7
-7
drivers/clk/imx/clk-pllv1.c
+7
-7
drivers/clk/imx/clk-pllv1.c
···
52
52
unsigned long parent_rate)
53
53
{
54
54
struct clk_pllv1 *pll = to_clk_pllv1(hw);
55
-
long long ll;
55
+
unsigned long long ull;
56
56
int mfn_abs;
57
57
unsigned int mfi, mfn, mfd, pd;
58
58
u32 reg;
···
94
94
rate = parent_rate * 2;
95
95
rate /= pd + 1;
96
96
97
-
ll = (unsigned long long)rate * mfn_abs;
97
+
ull = (unsigned long long)rate * mfn_abs;
98
98
99
-
do_div(ll, mfd + 1);
99
+
do_div(ull, mfd + 1);
100
100
101
101
if (mfn_is_negative(pll, mfn))
102
-
ll = -ll;
102
+
ull = (rate * mfi) - ull;
103
+
else
104
+
ull = (rate * mfi) + ull;
103
105
104
-
ll = (rate * mfi) + ll;
105
-
106
-
return ll;
106
+
return ull;
107
107
}
108
108
109
109
static struct clk_ops clk_pllv1_ops = {
+5
-4
drivers/clk/imx/clk-pllv2.c
+5
-4
drivers/clk/imx/clk-pllv2.c
···
79
79
{
80
80
long mfi, mfn, mfd, pdf, ref_clk;
81
81
unsigned long dbl;
82
-
s64 temp;
82
+
u64 temp;
83
83
84
84
dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
85
85
···
98
98
temp = (u64) ref_clk * abs(mfn);
99
99
do_div(temp, mfd + 1);
100
100
if (mfn < 0)
101
-
temp = -temp;
102
-
temp = (ref_clk * mfi) + temp;
101
+
temp = (ref_clk * mfi) - temp;
102
+
else
103
+
temp = (ref_clk * mfi) + temp;
103
104
104
105
return temp;
105
106
}
···
127
126
{
128
127
u32 reg;
129
128
long mfi, pdf, mfn, mfd = 999999;
130
-
s64 temp64;
129
+
u64 temp64;
131
130
unsigned long quad_parent_rate;
132
131
133
132
quad_parent_rate = 4 * parent_rate;
+1
drivers/clk/mmp/clk-mmp2.c
+1
drivers/clk/mmp/clk-mmp2.c
+1
drivers/clk/mmp/clk-pxa168.c
+1
drivers/clk/mmp/clk-pxa168.c
+1
drivers/clk/mmp/clk-pxa910.c
+1
drivers/clk/mmp/clk-pxa910.c
+5
-18
drivers/clk/sunxi/clk-a10-pll2.c
+5
-18
drivers/clk/sunxi/clk-a10-pll2.c
···
41
41
42
42
#define SUN4I_PLL2_OUTPUTS 4
43
43
44
-
struct sun4i_pll2_data {
45
-
u32 post_div_offset;
46
-
u32 pre_div_flags;
47
-
};
48
-
49
44
static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
50
45
51
46
static void __init sun4i_pll2_setup(struct device_node *node,
52
-
struct sun4i_pll2_data *data)
47
+
int post_div_offset)
53
48
{
54
49
const char *clk_name = node->name, *parent;
55
50
struct clk **clks, *base_clk, *prediv_clk;
···
71
76
parent, 0, reg,
72
77
SUN4I_PLL2_PRE_DIV_SHIFT,
73
78
SUN4I_PLL2_PRE_DIV_WIDTH,
74
-
data->pre_div_flags,
79
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
75
80
&sun4i_a10_pll2_lock);
76
81
if (!prediv_clk) {
77
82
pr_err("Couldn't register the prediv clock\n");
···
122
127
*/
123
128
val = readl(reg);
124
129
val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
125
-
val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
130
+
val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
126
131
writel(val, reg);
127
132
128
133
of_property_read_string_index(node, "clock-output-names",
···
186
191
iounmap(reg);
187
192
}
188
193
189
-
static struct sun4i_pll2_data sun4i_a10_pll2_data = {
190
-
.pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
191
-
};
192
-
193
194
static void __init sun4i_a10_pll2_setup(struct device_node *node)
194
195
{
195
-
sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
196
+
sun4i_pll2_setup(node, 0);
196
197
}
197
198
198
199
CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
199
200
sun4i_a10_pll2_setup);
200
201
201
-
static struct sun4i_pll2_data sun5i_a13_pll2_data = {
202
-
.post_div_offset = 1,
203
-
};
204
-
205
202
static void __init sun5i_a13_pll2_setup(struct device_node *node)
206
203
{
207
-
sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
204
+
sun4i_pll2_setup(node, 1);
208
205
}
209
206
210
207
CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
+2
drivers/clk/ti/clk-816x.c
+2
drivers/clk/ti/clk-816x.c
···
20
20
DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
21
21
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
22
22
DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
23
+
DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
24
+
DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
23
25
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
24
26
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
25
27
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
+2
-2
drivers/clk/ti/clkt_dpll.c
+2
-2
drivers/clk/ti/clkt_dpll.c
···
240
240
*/
241
241
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
242
242
{
243
-
long long dpll_clk;
243
+
u64 dpll_clk;
244
244
u32 dpll_mult, dpll_div, v;
245
245
struct dpll_data *dd;
246
246
···
262
262
dpll_div = v & dd->div1_mask;
263
263
dpll_div >>= __ffs(dd->div1_mask);
264
264
265
-
dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult;
265
+
dpll_clk = (u64)clk_get_rate(dd->clk_ref) * dpll_mult;
266
266
do_div(dpll_clk, dpll_div + 1);
267
267
268
268
return dpll_clk;
+3
-13
drivers/clk/ti/divider.c
+3
-13
drivers/clk/ti/divider.c
···
214
214
{
215
215
struct clk_divider *divider;
216
216
unsigned int div, value;
217
-
unsigned long flags = 0;
218
217
u32 val;
219
218
220
219
if (!hw || !rate)
···
227
228
if (value > div_mask(divider))
228
229
value = div_mask(divider);
229
230
230
-
if (divider->lock)
231
-
spin_lock_irqsave(divider->lock, flags);
232
-
233
231
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
234
232
val = div_mask(divider) << (divider->shift + 16);
235
233
} else {
···
235
239
}
236
240
val |= value << divider->shift;
237
241
ti_clk_ll_ops->clk_writel(val, divider->reg);
238
-
239
-
if (divider->lock)
240
-
spin_unlock_irqrestore(divider->lock, flags);
241
242
242
243
return 0;
243
244
}
···
249
256
const char *parent_name,
250
257
unsigned long flags, void __iomem *reg,
251
258
u8 shift, u8 width, u8 clk_divider_flags,
252
-
const struct clk_div_table *table,
253
-
spinlock_t *lock)
259
+
const struct clk_div_table *table)
254
260
{
255
261
struct clk_divider *div;
256
262
struct clk *clk;
···
280
288
div->shift = shift;
281
289
div->width = width;
282
290
div->flags = clk_divider_flags;
283
-
div->lock = lock;
284
291
div->hw.init = &init;
285
292
div->table = table;
286
293
···
412
421
413
422
clk = _register_divider(NULL, setup->name, div->parent,
414
423
flags, (void __iomem *)reg, div->bit_shift,
415
-
width, div_flags, table, NULL);
424
+
width, div_flags, table);
416
425
417
426
if (IS_ERR(clk))
418
427
kfree(table);
···
575
584
goto cleanup;
576
585
577
586
clk = _register_divider(NULL, node->name, parent_name, flags, reg,
578
-
shift, width, clk_divider_flags, table,
579
-
NULL);
587
+
shift, width, clk_divider_flags, table);
580
588
581
589
if (!IS_ERR(clk)) {
582
590
of_clk_add_provider(node, of_clk_src_simple_get, clk);
+2
-2
drivers/clk/ti/fapll.c
+2
-2
drivers/clk/ti/fapll.c
···
168
168
{
169
169
struct fapll_data *fd = to_fapll(hw);
170
170
u32 fapll_n, fapll_p, v;
171
-
long long rate;
171
+
u64 rate;
172
172
173
173
if (ti_fapll_clock_is_bypass(fd))
174
174
return parent_rate;
···
314
314
{
315
315
struct fapll_synth *synth = to_synth(hw);
316
316
u32 synth_div_m;
317
-
long long rate;
317
+
u64 rate;
318
318
319
319
/* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
320
320
if (!synth->div)
+3
-12
drivers/clk/ti/mux.c
+3
-12
drivers/clk/ti/mux.c
···
69
69
{
70
70
struct clk_mux *mux = to_clk_mux(hw);
71
71
u32 val;
72
-
unsigned long flags = 0;
73
72
74
73
if (mux->table) {
75
74
index = mux->table[index];
···
80
81
index++;
81
82
}
82
83
83
-
if (mux->lock)
84
-
spin_lock_irqsave(mux->lock, flags);
85
-
86
84
if (mux->flags & CLK_MUX_HIWORD_MASK) {
87
85
val = mux->mask << (mux->shift + 16);
88
86
} else {
···
88
92
}
89
93
val |= index << mux->shift;
90
94
ti_clk_ll_ops->clk_writel(val, mux->reg);
91
-
92
-
if (mux->lock)
93
-
spin_unlock_irqrestore(mux->lock, flags);
94
95
95
96
return 0;
96
97
}
···
102
109
const char **parent_names, u8 num_parents,
103
110
unsigned long flags, void __iomem *reg,
104
111
u8 shift, u32 mask, u8 clk_mux_flags,
105
-
u32 *table, spinlock_t *lock)
112
+
u32 *table)
106
113
{
107
114
struct clk_mux *mux;
108
115
struct clk *clk;
···
126
133
mux->shift = shift;
127
134
mux->mask = mask;
128
135
mux->flags = clk_mux_flags;
129
-
mux->lock = lock;
130
136
mux->table = table;
131
137
mux->hw.init = &init;
132
138
···
167
175
168
176
return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
169
177
flags, (void __iomem *)reg, mux->bit_shift, mask,
170
-
mux_flags, NULL, NULL);
178
+
mux_flags, NULL);
171
179
}
172
180
173
181
/**
···
219
227
mask = (1 << fls(mask)) - 1;
220
228
221
229
clk = _register_mux(NULL, node->name, parent_names, num_parents,
222
-
flags, reg, shift, mask, clk_mux_flags, NULL,
223
-
NULL);
230
+
flags, reg, shift, mask, clk_mux_flags, NULL);
224
231
225
232
if (!IS_ERR(clk))
226
233
of_clk_add_provider(node, of_clk_src_simple_get, clk);