tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:
"Mostly PMU fixes and a reworking of the pseudo-NMI disabling on broken
MediaTek firmware:

- Move the MediaTek GIC quirk handling from irqchip to core. Before
the merging window commit 44bd78dd2b88 ("irqchip/gic-v3: Disable
pseudo NMIs on MediaTek devices w/ firmware issues") temporarily
addressed this issue. Fixed now at a deeper level in the arch code

- Reject events meant for other PMUs in the CoreSight PMU driver,
otherwise some of the core PMU events would disappear

- Fix the Armv8 PMUv3 driver driver to not truncate 64-bit registers,
causing some events to be invisible

- Remove duplicate declaration of __arm64_sys##name following the
patch to avoid prototype warning for syscalls

- Typos in the elf_hwcap documentation"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/syscall: Remove duplicate declaration
Revert "arm64: smp: avoid NMI IPIs with broken MediaTek FW"
arm64: Move MediaTek GIC quirk handling from irqchip to core
arm64/arm: arm_pmuv3: perf: Don't truncate 64-bit registers
perf: arm_cspmu: Reject events meant for other PMUs
Documentation/arm64: Fix typos in elf_hwcaps

Linus Torvalds ac347a06 e1d809b3

+78 -86
+3 -3
Documentation/arch/arm64/elf_hwcaps.rst
··· 174 174 Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. 175 175 176 176 HWCAP2_SVE2 177 - Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001. 177 + Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001. 178 178 179 179 HWCAP2_SVEAES 180 180 Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001. ··· 222 222 Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001. 223 223 224 224 HWCAP2_BTI 225 - Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001. 225 + Functionality implied by ID_AA64PFR1_EL1.BT == 0b0001. 226 226 227 227 HWCAP2_MTE 228 228 Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described ··· 232 232 Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001. 233 233 234 234 HWCAP2_AFP 235 - Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001. 235 + Functionality implied by ID_AA64MMFR1_EL1.AFP == 0b0001. 236 236 237 237 HWCAP2_RPRES 238 238 Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
+23 -25
arch/arm/include/asm/arm_pmuv3.h
··· 23 23 #define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0) 24 24 #define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1) 25 25 #define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2) 26 + #define PMCEID2 __ACCESS_CP15(c9, 0, c14, 4) 27 + #define PMCEID3 __ACCESS_CP15(c9, 0, c14, 5) 26 28 #define PMMIR __ACCESS_CP15(c9, 0, c14, 6) 27 29 #define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7) 28 30 ··· 152 150 return read_sysreg(PMCCNTR); 153 151 } 154 152 155 - static inline void write_pmxevcntr(u32 val) 156 - { 157 - write_sysreg(val, PMXEVCNTR); 158 - } 159 - 160 - static inline u32 read_pmxevcntr(void) 161 - { 162 - return read_sysreg(PMXEVCNTR); 163 - } 164 - 165 - static inline void write_pmxevtyper(u32 val) 166 - { 167 - write_sysreg(val, PMXEVTYPER); 168 - } 169 - 170 153 static inline void write_pmcntenset(u32 val) 171 154 { 172 155 write_sysreg(val, PMCNTENSET); ··· 192 205 write_sysreg(val, PMUSERENR); 193 206 } 194 207 195 - static inline u32 read_pmceid0(void) 196 - { 197 - return read_sysreg(PMCEID0); 198 - } 199 - 200 - static inline u32 read_pmceid1(void) 201 - { 202 - return read_sysreg(PMCEID1); 203 - } 204 - 205 208 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 206 209 static inline void kvm_clr_pmu_events(u32 clr) {} 207 210 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) ··· 208 231 209 232 /* PMU Version in DFR Register */ 210 233 #define ARMV8_PMU_DFR_VER_NI 0 234 + #define ARMV8_PMU_DFR_VER_V3P1 0x4 211 235 #define ARMV8_PMU_DFR_VER_V3P4 0x5 212 236 #define ARMV8_PMU_DFR_VER_V3P5 0x6 213 237 #define ARMV8_PMU_DFR_VER_IMP_DEF 0xF ··· 227 249 static inline bool is_pmuv3p5(int pmuver) 228 250 { 229 251 return pmuver >= ARMV8_PMU_DFR_VER_V3P5; 252 + } 253 + 254 + static inline u64 read_pmceid0(void) 255 + { 256 + u64 val = read_sysreg(PMCEID0); 257 + 258 + if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1) 259 + val |= (u64)read_sysreg(PMCEID2) << 32; 260 + 261 + return val; 262 + } 263 + 264 + static inline u64 read_pmceid1(void) 265 + { 266 + u64 val = read_sysreg(PMCEID1); 267 + 268 + if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1) 269 + val |= (u64)read_sysreg(PMCEID3) << 32; 270 + 271 + return val; 230 272 } 231 273 232 274 #endif
+5 -20
arch/arm64/include/asm/arm_pmuv3.h
··· 46 46 ID_AA64DFR0_EL1_PMUVer_SHIFT); 47 47 } 48 48 49 - static inline void write_pmcr(u32 val) 49 + static inline void write_pmcr(u64 val) 50 50 { 51 51 write_sysreg(val, pmcr_el0); 52 52 } 53 53 54 - static inline u32 read_pmcr(void) 54 + static inline u64 read_pmcr(void) 55 55 { 56 56 return read_sysreg(pmcr_el0); 57 57 } ··· 69 69 static inline u64 read_pmccntr(void) 70 70 { 71 71 return read_sysreg(pmccntr_el0); 72 - } 73 - 74 - static inline void write_pmxevcntr(u32 val) 75 - { 76 - write_sysreg(val, pmxevcntr_el0); 77 - } 78 - 79 - static inline u32 read_pmxevcntr(void) 80 - { 81 - return read_sysreg(pmxevcntr_el0); 82 - } 83 - 84 - static inline void write_pmxevtyper(u32 val) 85 - { 86 - write_sysreg(val, pmxevtyper_el0); 87 72 } 88 73 89 74 static inline void write_pmcntenset(u32 val) ··· 91 106 write_sysreg(val, pmintenclr_el1); 92 107 } 93 108 94 - static inline void write_pmccfiltr(u32 val) 109 + static inline void write_pmccfiltr(u64 val) 95 110 { 96 111 write_sysreg(val, pmccfiltr_el0); 97 112 } ··· 111 126 write_sysreg(val, pmuserenr_el0); 112 127 } 113 128 114 - static inline u32 read_pmceid0(void) 129 + static inline u64 read_pmceid0(void) 115 130 { 116 131 return read_sysreg(pmceid0_el0); 117 132 } 118 133 119 - static inline u32 read_pmceid1(void) 134 + static inline u64 read_pmceid1(void) 120 135 { 121 136 return read_sysreg(pmceid1_el0); 122 137 }
-1
arch/arm64/include/asm/syscall_wrapper.h
··· 54 54 ALLOW_ERROR_INJECTION(__arm64_sys##name, ERRNO); \ 55 55 static long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)); \ 56 56 static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)); \ 57 - asmlinkage long __arm64_sys##name(const struct pt_regs *regs); \ 58 57 asmlinkage long __arm64_sys##name(const struct pt_regs *regs) \ 59 58 { \ 60 59 return __se_sys##name(SC_ARM64_REGS_TO_ARGS(x,__VA_ARGS__)); \
+38 -8
arch/arm64/kernel/cpufeature.c
··· 999 999 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1000 1000 } 1001 1001 1002 + #ifdef CONFIG_ARM64_PSEUDO_NMI 1003 + static bool enable_pseudo_nmi; 1004 + 1005 + static int __init early_enable_pseudo_nmi(char *p) 1006 + { 1007 + return kstrtobool(p, &enable_pseudo_nmi); 1008 + } 1009 + early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1010 + 1011 + static __init void detect_system_supports_pseudo_nmi(void) 1012 + { 1013 + struct device_node *np; 1014 + 1015 + if (!enable_pseudo_nmi) 1016 + return; 1017 + 1018 + /* 1019 + * Detect broken MediaTek firmware that doesn't properly save and 1020 + * restore GIC priorities. 1021 + */ 1022 + np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1023 + if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1024 + pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1025 + enable_pseudo_nmi = false; 1026 + } 1027 + of_node_put(np); 1028 + } 1029 + #else /* CONFIG_ARM64_PSEUDO_NMI */ 1030 + static inline void detect_system_supports_pseudo_nmi(void) { } 1031 + #endif 1032 + 1002 1033 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1003 1034 { 1004 1035 /* Before we start using the tables, make sure it is sorted */ ··· 1087 1056 * handle the boot CPU below. 1088 1057 */ 1089 1058 init_cpucap_indirect_list(); 1059 + 1060 + /* 1061 + * Detect broken pseudo-NMI. Must be called _before_ the call to 1062 + * setup_boot_cpu_capabilities() since it interacts with 1063 + * can_use_gic_priorities(). 1064 + */ 1065 + detect_system_supports_pseudo_nmi(); 1090 1066 1091 1067 /* 1092 1068 * Detect and enable early CPU capabilities based on the boot CPU, ··· 2123 2085 #endif /* CONFIG_ARM64_E0PD */ 2124 2086 2125 2087 #ifdef CONFIG_ARM64_PSEUDO_NMI 2126 - static bool enable_pseudo_nmi; 2127 - 2128 - static int __init early_enable_pseudo_nmi(char *p) 2129 - { 2130 - return kstrtobool(p, &enable_pseudo_nmi); 2131 - } 2132 - early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2133 - 2134 2088 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2135 2089 int scope) 2136 2090 {
+1 -4
arch/arm64/kernel/smp.c
··· 965 965 966 966 static bool ipi_should_be_nmi(enum ipi_msg_type ipi) 967 967 { 968 - DECLARE_STATIC_KEY_FALSE(supports_pseudo_nmis); 969 - 970 - if (!system_uses_irq_prio_masking() || 971 - !static_branch_likely(&supports_pseudo_nmis)) 968 + if (!system_uses_irq_prio_masking()) 972 969 return false; 973 970 974 971 switch (ipi) {
+2 -22
drivers/irqchip/irq-gic-v3.c
··· 39 39 40 40 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) 41 41 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) 42 - #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) 43 - #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) 42 + #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2) 44 43 45 44 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 46 45 ··· 105 106 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 106 107 * interrupt. 107 108 */ 108 - DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 109 + static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); 109 110 110 111 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); 111 112 EXPORT_SYMBOL(gic_nonsecure_priorities); ··· 1778 1779 return true; 1779 1780 } 1780 1781 1781 - static bool gic_enable_quirk_mtk_gicr(void *data) 1782 - { 1783 - struct gic_chip_data *d = data; 1784 - 1785 - d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE; 1786 - 1787 - return true; 1788 - } 1789 - 1790 1782 static bool gic_enable_quirk_cavium_38539(void *data) 1791 1783 { 1792 1784 struct gic_chip_data *d = data; ··· 1879 1889 .init = gic_enable_quirk_asr8601, 1880 1890 }, 1881 1891 { 1882 - .desc = "GICv3: Mediatek Chromebook GICR save problem", 1883 - .property = "mediatek,broken-save-restore-fw", 1884 - .init = gic_enable_quirk_mtk_gicr, 1885 - }, 1886 - { 1887 1892 .desc = "GICv3: HIP06 erratum 161010803", 1888 1893 .iidr = 0x0204043b, 1889 1894 .mask = 0xffffffff, ··· 1943 1958 1944 1959 if (!gic_prio_masking_enabled()) 1945 1960 return; 1946 - 1947 - if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) { 1948 - pr_warn("Skipping NMI enable due to firmware issues\n"); 1949 - return; 1950 - } 1951 1961 1952 1962 rdist_nmi_refs = kcalloc(gic_data.ppi_nr + SGI_NR, 1953 1963 sizeof(*rdist_nmi_refs), GFP_KERNEL);
+3
drivers/perf/arm_cspmu/arm_cspmu.c
··· 676 676 677 677 cspmu = to_arm_cspmu(event->pmu); 678 678 679 + if (event->attr.type != event->pmu->type) 680 + return -ENOENT; 681 + 679 682 /* 680 683 * Following other "uncore" PMUs, we do not support sampling mode or 681 684 * attach to a task (per-process mode).
+3 -3
drivers/perf/arm_pmuv3.c
··· 428 428 #define ARMV8_IDX_TO_COUNTER(x) \ 429 429 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK) 430 430 431 - static inline u32 armv8pmu_pmcr_read(void) 431 + static inline u64 armv8pmu_pmcr_read(void) 432 432 { 433 433 return read_pmcr(); 434 434 } 435 435 436 - static inline void armv8pmu_pmcr_write(u32 val) 436 + static inline void armv8pmu_pmcr_write(u64 val) 437 437 { 438 438 val &= ARMV8_PMU_PMCR_MASK; 439 439 isb(); ··· 957 957 static void armv8pmu_reset(void *info) 958 958 { 959 959 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 960 - u32 pmcr; 960 + u64 pmcr; 961 961 962 962 /* The counter and interrupt enable registers are unknown at reset. */ 963 963 armv8pmu_disable_counter(U32_MAX);