+1 -1

MAINTAINERS

reviewed

··· 7923 7923 S: Maintained 7924 7924 7925 7925 MARDUK (CREATOR CI40) DEVICE TREE SUPPORT 7926 7926 - M: Rahul Bedarkar <rahul.bedarkar@imgtec.com> 7926 7926 + M: Rahul Bedarkar <rahulbedarkar89@gmail.com> 7927 7927 L: linux-mips@linux-mips.org 7928 7928 S: Maintained 7929 7929 F: arch/mips/boot/dts/img/pistachio_marduk.dts

+2

arch/mips/Kbuild

reviewed

··· 1 1 # Fail on warnings - also for files referenced in subdirs 2 2 # -Werror can be disabled for specific files using: 3 3 # CFLAGS_<file.o> := -Wno-error 4 4 + ifeq ($(W),) 4 5 subdir-ccflags-y := -Werror 6 6 + endif 5 7 6 8 # platform specific definitions 7 9 include arch/mips/Kbuild.platforms

+11 -13

arch/mips/Kconfig

reviewed

··· 46 46 select ARCH_DISCARD_MEMBLOCK 47 47 select GENERIC_SMP_IDLE_THREAD 48 48 select BUILDTIME_EXTABLE_SORT 49 49 + select GENERIC_CPU_AUTOPROBE 49 50 select GENERIC_CLOCKEVENTS 50 51 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC 51 52 select GENERIC_CMOS_UPDATE ··· 69 68 select HANDLE_DOMAIN_IRQ 70 69 select HAVE_EXIT_THREAD 71 70 select HAVE_REGS_AND_STACK_ACCESS_API 71 71 + select HAVE_COPY_THREAD_TLS 72 72 73 73 menu "Machine selection" 74 74 ··· 1041 1039 config RWSEM_XCHGADD_ALGORITHM 1042 1040 bool 1043 1041 1044 1044 - config ARCH_HAS_ILOG2_U32 1045 1045 - bool 1046 1046 - default n 1047 1047 - 1048 1048 - config ARCH_HAS_ILOG2_U64 1049 1049 - bool 1050 1050 - default n 1051 1051 - 1052 1042 config GENERIC_HWEIGHT 1053 1043 bool 1054 1044 default y ··· 1366 1372 select WEAK_ORDERING 1367 1373 select WEAK_REORDERING_BEYOND_LLSC 1368 1374 select MIPS_PGD_C0_CONTEXT 1375 1375 + select MIPS_L1_CACHE_SHIFT_6 1369 1376 select GPIOLIB 1370 1377 help 1371 1378 The Loongson 3 processor implements the MIPS64R2 instruction ··· 2115 2120 bool "48 bits virtual memory" 2116 2121 depends on 64BIT 2117 2122 help 2118 2118 - Support a maximum at least 48 bits of application virtual memory. 2119 2119 - Default is 40 bits or less, depending on the CPU. 2120 2120 - This option result in a small memory overhead for page tables. 2121 2121 - This option is only supported with 16k and 64k page sizes. 2123 2123 + Support a maximum at least 48 bits of application virtual 2124 2124 + memory. Default is 40 bits or less, depending on the CPU. 2125 2125 + For page sizes 16k and above, this option results in a small 2126 2126 + memory overhead for page tables. For 4k page size, a fourth 2127 2127 + level of page tables is added which imposes both a memory 2128 2128 + overhead as well as slower TLB fault handling. 2129 2129 + 2122 2130 If unsure, say N. 2123 2131 2124 2132 choice ··· 2131 2133 config PAGE_SIZE_4KB 2132 2134 bool "4kB" 2133 2135 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3 2134 2134 - depends on !MIPS_VA_BITS_48 2135 2136 help 2136 2137 This option select the standard 4kB Linux page size. On some 2137 2138 R3000-family processors this is the only available page size. Using ··· 2979 2982 2980 2983 config PGTABLE_LEVELS 2981 2984 int 2985 2985 + default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48 2982 2986 default 3 if 64BIT && !PAGE_SIZE_64KB 2983 2987 default 2 2984 2988

+1 -1

arch/mips/Kconfig.debug

reviewed

··· 82 82 config SB1XXX_CORELIS 83 83 bool "Corelis Debugger" 84 84 depends on SIBYTE_SB1xxx_SOC 85 85 - select DEBUG_INFO 85 85 + select DEBUG_INFO if !COMPILE_TEST 86 86 help 87 87 Select compile flags that produce code that can be processed by the 88 88 Corelis mksym utility and UDB Emulator.

-9

arch/mips/cavium-octeon/Kconfig

reviewed

··· 25 25 26 26 if CAVIUM_OCTEON_SOC 27 27 28 28 - config CAVIUM_OCTEON_2ND_KERNEL 29 29 - bool "Build the kernel to be used as a 2nd kernel on the same chip" 30 30 - default "n" 31 31 - help 32 32 - This option configures this kernel to be linked at a different 33 33 - address and use the 2nd uart for output. This allows a kernel built 34 34 - with this option to be run at the same time as one built without this 35 35 - option. 36 36 - 37 28 config CAVIUM_OCTEON_LOCK_L2 38 29 bool "Lock often used kernel code in the L2" 39 30 default "y"

-4

arch/mips/cavium-octeon/Platform

reviewed

··· 4 4 platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/ 5 5 cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \ 6 6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon 7 7 - ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 8 8 - load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000 9 9 - else 10 7 load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000 11 11 - endif

+56 -83

arch/mips/cavium-octeon/executive/cvmx-l2c.c

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2010 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 239 239 else { 240 240 uint64_t counter = 0; 241 241 int tad; 242 242 + 242 243 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 243 244 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad)); 244 245 return counter; ··· 250 249 else { 251 250 uint64_t counter = 0; 252 251 int tad; 252 252 + 253 253 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 254 254 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad)); 255 255 return counter; ··· 261 259 else { 262 260 uint64_t counter = 0; 263 261 int tad; 262 262 + 264 263 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 265 264 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad)); 266 265 return counter; ··· 273 270 else { 274 271 uint64_t counter = 0; 275 272 int tad; 273 273 + 276 274 for (tad = 0; tad < CVMX_L2C_TADS; tad++) 277 275 counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad)); 278 276 return counter; ··· 305 301 */ 306 302 CVMX_DCACHE_INVALIDATE; 307 303 while (len > 0) { 308 308 - ACCESS_ONCE(*ptr); 304 304 + READ_ONCE(*ptr); 309 305 len -= CVMX_CACHE_LINE_SIZE; 310 306 ptr += CVMX_CACHE_LINE_SIZE; 311 307 } ··· 379 375 if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) { 380 376 int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1; 381 377 uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS; 378 378 + 382 379 lckbase.s.lck_base = addr_tmp >> 7; 380 380 + 383 381 } else { 384 382 lckbase.s.lck_base = addr >> 7; 385 383 } ··· 441 435 /* These may look like constants, but they aren't... */ 442 436 int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT; 443 437 int set_shift = CVMX_L2C_IDX_ADDR_SHIFT; 438 438 + 444 439 for (set = 0; set < n_set; set++) { 445 440 for (assoc = 0; assoc < n_assoc; assoc++) { 446 441 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, ··· 526 519 union __cvmx_l2c_tag { 527 520 uint64_t u64; 528 521 struct cvmx_l2c_tag_cn50xx { 529 529 - #ifdef __BIG_ENDIAN_BITFIELD 530 530 - uint64_t reserved:40; 531 531 - uint64_t V:1; /* Line valid */ 532 532 - uint64_t D:1; /* Line dirty */ 533 533 - uint64_t L:1; /* Line locked */ 534 534 - uint64_t U:1; /* Use, LRU eviction */ 535 535 - uint64_t addr:20; /* Phys mem addr (33..14) */ 536 536 - #else 537 537 - uint64_t addr:20; /* Phys mem addr (33..14) */ 538 538 - uint64_t U:1; /* Use, LRU eviction */ 539 539 - uint64_t L:1; /* Line locked */ 540 540 - uint64_t D:1; /* Line dirty */ 541 541 - uint64_t V:1; /* Line valid */ 542 542 - uint64_t reserved:40; 543 543 - #endif 522 522 + __BITFIELD_FIELD(uint64_t reserved:40, 523 523 + __BITFIELD_FIELD(uint64_t V:1, /* Line valid */ 524 524 + __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */ 525 525 + __BITFIELD_FIELD(uint64_t L:1, /* Line locked */ 526 526 + __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */ 527 527 + __BITFIELD_FIELD(uint64_t addr:20, /* Phys addr (33..14) */ 528 528 + ;)))))) 544 529 } cn50xx; 545 530 struct cvmx_l2c_tag_cn30xx { 546 546 - #ifdef __BIG_ENDIAN_BITFIELD 547 547 - uint64_t reserved:41; 548 548 - uint64_t V:1; /* Line valid */ 549 549 - uint64_t D:1; /* Line dirty */ 550 550 - uint64_t L:1; /* Line locked */ 551 551 - uint64_t U:1; /* Use, LRU eviction */ 552 552 - uint64_t addr:19; /* Phys mem addr (33..15) */ 553 553 - #else 554 554 - uint64_t addr:19; /* Phys mem addr (33..15) */ 555 555 - uint64_t U:1; /* Use, LRU eviction */ 556 556 - uint64_t L:1; /* Line locked */ 557 557 - uint64_t D:1; /* Line dirty */ 558 558 - uint64_t V:1; /* Line valid */ 559 559 - uint64_t reserved:41; 560 560 - #endif 531 531 + __BITFIELD_FIELD(uint64_t reserved:41, 532 532 + __BITFIELD_FIELD(uint64_t V:1, /* Line valid */ 533 533 + __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */ 534 534 + __BITFIELD_FIELD(uint64_t L:1, /* Line locked */ 535 535 + __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */ 536 536 + __BITFIELD_FIELD(uint64_t addr:19, /* Phys addr (33..15) */ 537 537 + ;)))))) 561 538 } cn30xx; 562 539 struct cvmx_l2c_tag_cn31xx { 563 563 - #ifdef __BIG_ENDIAN_BITFIELD 564 564 - uint64_t reserved:42; 565 565 - uint64_t V:1; /* Line valid */ 566 566 - uint64_t D:1; /* Line dirty */ 567 567 - uint64_t L:1; /* Line locked */ 568 568 - uint64_t U:1; /* Use, LRU eviction */ 569 569 - uint64_t addr:18; /* Phys mem addr (33..16) */ 570 570 - #else 571 571 - uint64_t addr:18; /* Phys mem addr (33..16) */ 572 572 - uint64_t U:1; /* Use, LRU eviction */ 573 573 - uint64_t L:1; /* Line locked */ 574 574 - uint64_t D:1; /* Line dirty */ 575 575 - uint64_t V:1; /* Line valid */ 576 576 - uint64_t reserved:42; 577 577 - #endif 540 540 + __BITFIELD_FIELD(uint64_t reserved:42, 541 541 + __BITFIELD_FIELD(uint64_t V:1, /* Line valid */ 542 542 + __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */ 543 543 + __BITFIELD_FIELD(uint64_t L:1, /* Line locked */ 544 544 + __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */ 545 545 + __BITFIELD_FIELD(uint64_t addr:18, /* Phys addr (33..16) */ 546 546 + ;)))))) 578 547 } cn31xx; 579 548 struct cvmx_l2c_tag_cn38xx { 580 580 - #ifdef __BIG_ENDIAN_BITFIELD 581 581 - uint64_t reserved:43; 582 582 - uint64_t V:1; /* Line valid */ 583 583 - uint64_t D:1; /* Line dirty */ 584 584 - uint64_t L:1; /* Line locked */ 585 585 - uint64_t U:1; /* Use, LRU eviction */ 586 586 - uint64_t addr:17; /* Phys mem addr (33..17) */ 587 587 - #else 588 588 - uint64_t addr:17; /* Phys mem addr (33..17) */ 589 589 - uint64_t U:1; /* Use, LRU eviction */ 590 590 - uint64_t L:1; /* Line locked */ 591 591 - uint64_t D:1; /* Line dirty */ 592 592 - uint64_t V:1; /* Line valid */ 593 593 - uint64_t reserved:43; 594 594 - #endif 549 549 + __BITFIELD_FIELD(uint64_t reserved:43, 550 550 + __BITFIELD_FIELD(uint64_t V:1, /* Line valid */ 551 551 + __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */ 552 552 + __BITFIELD_FIELD(uint64_t L:1, /* Line locked */ 553 553 + __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */ 554 554 + __BITFIELD_FIELD(uint64_t addr:17, /* Phys addr (33..17) */ 555 555 + ;)))))) 595 556 } cn38xx; 596 557 struct cvmx_l2c_tag_cn58xx { 597 597 - #ifdef __BIG_ENDIAN_BITFIELD 598 598 - uint64_t reserved:44; 599 599 - uint64_t V:1; /* Line valid */ 600 600 - uint64_t D:1; /* Line dirty */ 601 601 - uint64_t L:1; /* Line locked */ 602 602 - uint64_t U:1; /* Use, LRU eviction */ 603 603 - uint64_t addr:16; /* Phys mem addr (33..18) */ 604 604 - #else 605 605 - uint64_t addr:16; /* Phys mem addr (33..18) */ 606 606 - uint64_t U:1; /* Use, LRU eviction */ 607 607 - uint64_t L:1; /* Line locked */ 608 608 - uint64_t D:1; /* Line dirty */ 609 609 - uint64_t V:1; /* Line valid */ 610 610 - uint64_t reserved:44; 611 611 - #endif 558 558 + __BITFIELD_FIELD(uint64_t reserved:44, 559 559 + __BITFIELD_FIELD(uint64_t V:1, /* Line valid */ 560 560 + __BITFIELD_FIELD(uint64_t D:1, /* Line dirty */ 561 561 + __BITFIELD_FIELD(uint64_t L:1, /* Line locked */ 562 562 + __BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */ 563 563 + __BITFIELD_FIELD(uint64_t addr:16, /* Phys addr (33..18) */ 564 564 + ;)))))) 612 565 } cn58xx; 613 566 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */ 614 567 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */ ··· 596 629 union __cvmx_l2c_tag tag_val; 597 630 uint64_t dbg_addr = CVMX_L2C_DBG; 598 631 unsigned long flags; 599 599 - 600 632 union cvmx_l2c_dbg debug_val; 633 633 + 601 634 debug_val.u64 = 0; 602 635 /* 603 636 * For low core count parts, the core number is always small ··· 650 683 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) 651 684 { 652 685 union cvmx_l2c_tag tag; 653 653 - tag.u64 = 0; 654 686 687 687 + tag.u64 = 0; 655 688 if ((int)association >= cvmx_l2c_get_num_assoc()) { 656 689 cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n"); 657 690 return tag; ··· 734 767 735 768 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 736 769 union cvmx_l2c_ctl l2c_ctl; 770 770 + 737 771 l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL); 738 772 indxalias = !l2c_ctl.s.disidxalias; 739 773 } else { 740 774 union cvmx_l2c_cfg l2c_cfg; 775 775 + 741 776 l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); 742 777 indxalias = l2c_cfg.s.idxalias; 743 778 } ··· 747 778 if (indxalias) { 748 779 if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { 749 780 uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7; 781 781 + 750 782 idx ^= idx / cvmx_l2c_get_num_sets(); 751 783 idx ^= a_14_12; 752 784 } else { ··· 771 801 int cvmx_l2c_get_set_bits(void) 772 802 { 773 803 int l2_set_bits; 804 804 + 774 805 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) 775 806 l2_set_bits = 11; /* 2048 sets */ 776 807 else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) ··· 799 828 int cvmx_l2c_get_num_assoc(void) 800 829 { 801 830 int l2_assoc; 831 831 + 802 832 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || 803 833 OCTEON_IS_MODEL(OCTEON_CN52XX) || 804 834 OCTEON_IS_MODEL(OCTEON_CN58XX) || ··· 841 869 else if (mio_fus_dat3.s.l2c_crip == 1) 842 870 l2_assoc = 12; 843 871 } else { 844 844 - union cvmx_l2d_fus3 val; 845 845 - val.u64 = cvmx_read_csr(CVMX_L2D_FUS3); 872 872 + uint64_t l2d_fus3; 873 873 + 874 874 + l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3); 846 875 /* 847 876 * Using shifts here, as bit position names are 848 877 * different for each model but they all mean the 849 878 * same. 850 879 */ 851 851 - if ((val.u64 >> 35) & 0x1) 880 880 + if ((l2d_fus3 >> 35) & 0x1) 852 881 l2_assoc = l2_assoc >> 2; 853 853 - else if ((val.u64 >> 34) & 0x1) 882 882 + else if ((l2d_fus3 >> 34) & 0x1) 854 883 l2_assoc = l2_assoc >> 1; 855 884 } 856 885 return l2_assoc;

+10 -11

arch/mips/cavium-octeon/executive/octeon-model.c

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2010 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 63 63 char pass[4]; 64 64 int clock_mhz; 65 65 const char *suffix; 66 66 - union cvmx_l2d_fus3 fus3; 67 66 int num_cores; 68 67 union cvmx_mio_fus_dat2 fus_dat2; 69 68 union cvmx_mio_fus_dat3 fus_dat3; 70 69 char fuse_model[10]; 71 70 uint32_t fuse_data = 0; 71 71 + uint64_t l2d_fus3 = 0; 72 72 73 73 - fus3.u64 = 0; 74 73 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) 75 75 - fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); 74 74 + l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3; 76 75 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); 77 76 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); 78 77 num_cores = cvmx_octeon_num_cores(); ··· 191 192 /* Now figure out the family, the first two digits */ 192 193 switch ((chip_id >> 8) & 0xff) { 193 194 case 0: /* CN38XX, CN37XX or CN36XX */ 194 194 - if (fus3.cn38xx.crip_512k) { 195 195 + if (l2d_fus3) { 195 196 /* 196 197 * For some unknown reason, the 16 core one is 197 198 * called 37 instead of 36. ··· 222 223 } 223 224 break; 224 225 case 1: /* CN31XX or CN3020 */ 225 225 - if ((chip_id & 0x10) || fus3.cn31xx.crip_128k) 226 226 + if ((chip_id & 0x10) || l2d_fus3) 226 227 family = "30"; 227 228 else 228 229 family = "31"; ··· 245 246 case 2: /* CN3010 or CN3005 */ 246 247 family = "30"; 247 248 /* A chip with half cache is an 05 */ 248 248 - if (fus3.cn30xx.crip_64k) 249 249 + if (l2d_fus3) 249 250 core_model = "05"; 250 251 /* 251 252 * This series of chips didn't follow the standard ··· 266 267 case 3: /* CN58XX */ 267 268 family = "58"; 268 269 /* Special case. 4 core, half cache (CP with half cache) */ 269 269 - if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2)) 270 270 + if ((num_cores == 4) && l2d_fus3 && !strncmp(suffix, "CP", 2)) 270 271 core_model = "29"; 271 272 272 273 /* Pass 1 uses different encodings for pass numbers */ ··· 289 290 break; 290 291 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */ 291 292 if (fus_dat2.cn56xx.raid_en) { 292 292 - if (fus3.cn56xx.crip_1024k) 293 293 + if (l2d_fus3) 293 294 family = "55"; 294 295 else 295 296 family = "57"; ··· 308 309 if (fus_dat3.cn56xx.bar2_en) 309 310 suffix = "NSPB2"; 310 311 } 311 311 - if (fus3.cn56xx.crip_1024k) 312 312 + if (l2d_fus3) 312 313 family = "54"; 313 314 else 314 315 family = "56"; ··· 318 319 family = "50"; 319 320 break; 320 321 case 7: /* CN52XX */ 321 321 - if (fus3.cn52xx.crip_256k) 322 322 + if (l2d_fus3) 322 323 family = "51"; 323 324 else 324 325 family = "52";

+61 -52

arch/mips/cavium-octeon/octeon-platform.c

reviewed

··· 3 3 * License. See the file "COPYING" in the main directory of this archive 4 4 * for more details. 5 5 * 6 6 - * Copyright (C) 2004-2016 Cavium Networks 6 6 + * Copyright (C) 2004-2017 Cavium, Inc. 7 7 * Copyright (C) 2008 Wind River Systems 8 8 */ 9 9 10 10 - #include <linux/init.h> 11 11 - #include <linux/delay.h> 12 10 #include <linux/etherdevice.h> 13 11 #include <linux/of_platform.h> 14 12 #include <linux/of_fdt.h> 15 13 #include <linux/libfdt.h> 16 16 - #include <linux/usb/ehci_def.h> 17 17 - #include <linux/usb/ehci_pdriver.h> 18 18 - #include <linux/usb/ohci_pdriver.h> 19 14 20 15 #include <asm/octeon/octeon.h> 21 16 #include <asm/octeon/cvmx-helper-board.h> 17 17 + 18 18 + #ifdef CONFIG_USB 19 19 + #include <linux/usb/ehci_def.h> 20 20 + #include <linux/usb/ehci_pdriver.h> 21 21 + #include <linux/usb/ohci_pdriver.h> 22 22 #include <asm/octeon/cvmx-uctlx-defs.h> 23 23 24 24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) 25 25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) 26 26 - 27 27 - /* Octeon Random Number Generator. */ 28 28 - static int __init octeon_rng_device_init(void) 29 29 - { 30 30 - struct platform_device *pd; 31 31 - int ret = 0; 32 32 - 33 33 - struct resource rng_resources[] = { 34 34 - { 35 35 - .flags = IORESOURCE_MEM, 36 36 - .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), 37 37 - .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf 38 38 - }, { 39 39 - .flags = IORESOURCE_MEM, 40 40 - .start = cvmx_build_io_address(8, 0), 41 41 - .end = cvmx_build_io_address(8, 0) + 0x7 42 42 - } 43 43 - }; 44 44 - 45 45 - pd = platform_device_alloc("octeon_rng", -1); 46 46 - if (!pd) { 47 47 - ret = -ENOMEM; 48 48 - goto out; 49 49 - } 50 50 - 51 51 - ret = platform_device_add_resources(pd, rng_resources, 52 52 - ARRAY_SIZE(rng_resources)); 53 53 - if (ret) 54 54 - goto fail; 55 55 - 56 56 - ret = platform_device_add(pd); 57 57 - if (ret) 58 58 - goto fail; 59 59 - 60 60 - return ret; 61 61 - fail: 62 62 - platform_device_put(pd); 63 63 - 64 64 - out: 65 65 - return ret; 66 66 - } 67 67 - device_initcall(octeon_rng_device_init); 68 68 - 69 69 - #ifdef CONFIG_USB 70 26 71 27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex); 72 28 ··· 396 440 397 441 #endif /* CONFIG_USB */ 398 442 443 443 + /* Octeon Random Number Generator. */ 444 444 + static int __init octeon_rng_device_init(void) 445 445 + { 446 446 + struct platform_device *pd; 447 447 + int ret = 0; 399 448 400 400 - static struct of_device_id __initdata octeon_ids[] = { 449 449 + struct resource rng_resources[] = { 450 450 + { 451 451 + .flags = IORESOURCE_MEM, 452 452 + .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), 453 453 + .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf 454 454 + }, { 455 455 + .flags = IORESOURCE_MEM, 456 456 + .start = cvmx_build_io_address(8, 0), 457 457 + .end = cvmx_build_io_address(8, 0) + 0x7 458 458 + } 459 459 + }; 460 460 + 461 461 + pd = platform_device_alloc("octeon_rng", -1); 462 462 + if (!pd) { 463 463 + ret = -ENOMEM; 464 464 + goto out; 465 465 + } 466 466 + 467 467 + ret = platform_device_add_resources(pd, rng_resources, 468 468 + ARRAY_SIZE(rng_resources)); 469 469 + if (ret) 470 470 + goto fail; 471 471 + 472 472 + ret = platform_device_add(pd); 473 473 + if (ret) 474 474 + goto fail; 475 475 + 476 476 + return ret; 477 477 + fail: 478 478 + platform_device_put(pd); 479 479 + 480 480 + out: 481 481 + return ret; 482 482 + } 483 483 + device_initcall(octeon_rng_device_init); 484 484 + 485 485 + const struct of_device_id octeon_ids[] __initconst = { 401 486 { .compatible = "simple-bus", }, 402 487 { .compatible = "cavium,octeon-6335-uctl", }, 403 488 { .compatible = "cavium,octeon-5750-usbn", }, ··· 478 481 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); 479 482 if (alt_phy_handle) { 480 483 u32 alt_phandle = be32_to_cpup(alt_phy_handle); 484 484 + 481 485 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); 482 486 } else { 483 487 alt_phy = -1; ··· 577 579 if (phy_handle) { 578 580 u32 ph = be32_to_cpup(phy_handle); 579 581 int p = fdt_node_offset_by_phandle(initial_boot_params, ph); 582 582 + 580 583 if (p >= 0) 581 584 fdt_nop_node(initial_boot_params, p); 582 585 } ··· 727 728 728 729 for (i = 0; i < 2; i++) { 729 730 int mgmt; 731 731 + 730 732 snprintf(name_buffer, sizeof(name_buffer), 731 733 "mix%d", i); 732 734 alias_prop = fdt_getprop(initial_boot_params, aliases, ··· 743 743 name_buffer); 744 744 } else { 745 745 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); 746 746 + 746 747 octeon_fdt_set_phy(mgmt, phy_addr); 747 748 } 748 749 } ··· 752 751 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 753 752 if (pip_path) { 754 753 int pip = fdt_path_offset(initial_boot_params, pip_path); 754 754 + 755 755 if (pip >= 0) 756 756 for (i = 0; i <= 4; i++) 757 757 octeon_fdt_pip_iface(pip, i); ··· 769 767 770 768 for (i = 0; i < 2; i++) { 771 769 int i2c; 770 770 + 772 771 snprintf(name_buffer, sizeof(name_buffer), 773 772 "twsi%d", i); 774 773 alias_prop = fdt_getprop(initial_boot_params, aliases, ··· 800 797 801 798 for (i = 0; i < 2; i++) { 802 799 int i2c; 800 800 + 803 801 snprintf(name_buffer, sizeof(name_buffer), 804 802 "smi%d", i); 805 803 alias_prop = fdt_getprop(initial_boot_params, aliases, 806 804 name_buffer, NULL); 807 807 - 808 805 if (alias_prop) { 809 806 i2c = fdt_path_offset(initial_boot_params, alias_prop); 810 807 if (i2c < 0) ··· 827 824 828 825 for (i = 0; i < 3; i++) { 829 826 int uart; 827 827 + 830 828 snprintf(name_buffer, sizeof(name_buffer), 831 829 "uart%d", i); 832 830 alias_prop = fdt_getprop(initial_boot_params, aliases, ··· 867 863 int len; 868 864 869 865 int cf = fdt_path_offset(initial_boot_params, alias_prop); 866 866 + 870 867 base_ptr = 0; 871 868 if (octeon_bootinfo->major_version == 1 872 869 && octeon_bootinfo->minor_version >= 1) { ··· 917 912 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); 918 913 if (!is_16bit) { 919 914 __be32 width = cpu_to_be32(8); 915 915 + 920 916 fdt_setprop_inplace(initial_boot_params, cf, 921 917 "cavium,bus-width", &width, sizeof(width)); 922 918 } ··· 1010 1004 ; 1011 1005 } 1012 1006 1007 1007 + #ifdef CONFIG_USB 1013 1008 /* OHCI/UHCI USB */ 1014 1009 alias_prop = fdt_getprop(initial_boot_params, aliases, 1015 1010 "uctl", NULL); ··· 1043 1036 } else { 1044 1037 __be32 new_f[1]; 1045 1038 enum cvmx_helper_board_usb_clock_types c; 1039 1039 + 1046 1040 c = __cvmx_helper_board_usb_get_clock_type(); 1047 1041 switch (c) { 1048 1042 case USB_CLOCK_TYPE_REF_48: ··· 1060 1052 } 1061 1053 } 1062 1054 } 1055 1055 + #endif 1063 1056 1064 1057 return 0; 1065 1058 }

+1 -11

arch/mips/cavium-octeon/setup.c

reviewed

··· 374 374 */ 375 375 int octeon_get_boot_uart(void) 376 376 { 377 377 - int uart; 378 378 - #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 379 379 - uart = 1; 380 380 - #else 381 381 - uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 377 377 + return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 382 378 1 : 0; 383 383 - #endif 384 384 - return uart; 385 379 } 386 380 387 381 /** ··· 895 901 } 896 902 897 903 if (strstr(arcs_cmdline, "console=") == NULL) { 898 898 - #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 899 899 - strcat(arcs_cmdline, " console=ttyS0,115200"); 900 900 - #else 901 904 if (octeon_uart == 1) 902 905 strcat(arcs_cmdline, " console=ttyS1,115200"); 903 906 else 904 907 strcat(arcs_cmdline, " console=ttyS0,115200"); 905 905 - #endif 906 908 } 907 909 908 910 mips_hpt_frequency = octeon_get_clock_rate();

+3

arch/mips/configs/generic_defconfig

reviewed

··· 36 36 CONFIG_PACKET=y 37 37 CONFIG_UNIX=y 38 38 CONFIG_INET=y 39 39 + CONFIG_IP_PNP=y 40 40 + CONFIG_IP_PNP_DHCP=y 39 41 CONFIG_NETFILTER=y 40 42 # CONFIG_WIRELESS is not set 41 43 CONFIG_DEVTMPFS=y ··· 82 80 CONFIG_NFS_V4=y 83 81 CONFIG_NFS_V4_1=y 84 82 CONFIG_NFS_V4_2=y 83 83 + CONFIG_ROOT_NFS=y 85 84 CONFIG_PRINTK_TIME=y 86 85 CONFIG_DEBUG_INFO=y 87 86 CONFIG_DEBUG_INFO_REDUCED=y

-5

arch/mips/include/asm/cache.h

reviewed

··· 9 9 #ifndef _ASM_CACHE_H 10 10 #define _ASM_CACHE_H 11 11 12 12 - #include <kmalloc.h> 13 13 - 14 12 #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 15 13 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 16 16 - 17 17 - #define SMP_CACHE_SHIFT L1_CACHE_SHIFT 18 18 - #define SMP_CACHE_BYTES L1_CACHE_BYTES 19 14 20 15 #define __read_mostly __attribute__((__section__(".data..read_mostly"))) 21 16

+1 -2

arch/mips/include/asm/cpu-info.h

reviewed

··· 12 12 #ifndef __ASM_CPU_INFO_H 13 13 #define __ASM_CPU_INFO_H 14 14 15 15 + #include <linux/cache.h> 15 16 #include <linux/types.h> 16 16 - 17 17 - #include <asm/cache.h> 18 17 19 18 /* 20 19 * Descriptor for a cache

+26

arch/mips/include/asm/cpufeature.h

reviewed

··· 1 1 + /* 2 2 + * CPU feature definitions for module loading, used by 3 3 + * module_cpu_feature_match(), see uapi/asm/hwcap.h for MIPS CPU features. 4 4 + * 5 5 + * This program is free software; you can redistribute it and/or 6 6 + * modify it under the terms of the GNU General Public License 7 7 + * as published by the Free Software Foundation; either version 8 8 + * 2 of the License, or (at your option) any later version. 9 9 + */ 10 10 + 11 11 + #ifndef __ASM_CPUFEATURE_H 12 12 + #define __ASM_CPUFEATURE_H 13 13 + 14 14 + #include <uapi/asm/hwcap.h> 15 15 + #include <asm/elf.h> 16 16 + 17 17 + #define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) 18 18 + 19 19 + #define cpu_feature(x) ilog2(HWCAP_ ## x) 20 20 + 21 21 + static inline bool cpu_have_feature(unsigned int num) 22 22 + { 23 23 + return elf_hwcap & (1UL << num); 24 24 + } 25 25 + 26 26 + #endif /* __ASM_CPUFEATURE_H */

-2

arch/mips/include/asm/mach-rm/cpu-feature-overrides.h

reviewed

··· 10 10 #ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H 11 11 #define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H 12 12 13 13 - #include <cpu-feature-overrides.h> 14 14 - 15 13 #define cpu_has_tlb 1 16 14 #define cpu_has_4kex 1 17 15 #define cpu_has_4k_cache 1

+116 -3079

arch/mips/include/asm/octeon/cvmx-l2c-defs.h

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2012 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 28 28 #ifndef __CVMX_L2C_DEFS_H__ 29 29 #define __CVMX_L2C_DEFS_H__ 30 30 31 31 - #define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull)) 32 32 - #define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull)) 33 33 - #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull)) 34 34 - #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull)) 35 35 - #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull)) 36 36 - #define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull) 37 37 - #define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull) 38 38 - #define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull) 39 39 - #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) 40 40 - #define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8) 41 41 - #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) 31 31 + #include <uapi/asm/bitfield.h> 32 32 + 42 33 #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) 43 43 - #define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull)) 44 44 - #define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8) 45 45 - #define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) 46 46 - #define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) 47 47 - #define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull) 48 48 - #define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull)) 49 49 - #define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull)) 50 50 - #define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull)) 51 51 - #define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull)) 52 52 - #define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull)) 53 53 - #define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull)) 54 54 - #define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull)) 55 55 - #define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull)) 56 56 - #define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull)) 34 34 + #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) 35 35 + #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) 57 36 #define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull)) 58 37 #define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull)) 59 59 - #define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull)) 60 60 - #define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull)) 61 61 - #define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull)) 62 62 - #define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull)) 63 63 - #define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull)) 64 64 - #define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull)) 65 65 - #define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull)) 66 66 - #define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull)) 38 38 + #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) 39 39 + #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + \ 40 40 + ((offset) & 3) * 8) 67 41 #define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0) 68 42 #define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1) 69 43 #define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2) 70 44 #define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3) 71 71 - #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) 72 72 - #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8) 73 73 - #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull)) 74 74 - #define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8) 75 75 - #define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8) 76 76 - #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull)) 77 77 - #define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64) 78 78 - #define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64) 79 45 #define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) 80 46 #define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) 81 47 #define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) 82 48 #define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) 83 49 #define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) 84 84 - #define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull) 85 85 - #define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull) 86 86 - #define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull) 87 87 - #define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull) 88 88 - #define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull) 89 89 - #define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull) 90 90 - #define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull) 91 91 - #define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull) 92 92 - #define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull) 93 93 - #define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull) 94 94 - #define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull)) 95 95 - #define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull)) 96 96 - #define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull)) 97 97 - #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull)) 98 98 - #define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8) 99 99 - #define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8) 100 100 - #define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull)) 101 101 - #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8) 102 102 - #define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8) 103 103 - #define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8) 104 104 - #define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64) 105 105 - #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull)) 106 106 - #define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64) 50 50 + #define CVMX_L2C_TADX_PFCX(offset, block_id) \ 51 51 + (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + (((offset) & 3) + \ 52 52 + ((block_id) & 7) * 0x8000ull) * 8) 53 53 + #define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + \ 54 54 + ((block_id) & 3) * 0x40000ull) 55 55 + #define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + \ 56 56 + ((block_id) & 3) * 0x40000ull) 57 57 + #define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + \ 58 58 + ((block_id) & 3) * 0x40000ull) 59 59 + #define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + \ 60 60 + ((block_id) & 3) * 0x40000ull) 61 61 + #define CVMX_L2C_TADX_PRF(offset) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + \ 62 62 + ((offset) & 7) * 0x40000ull) 63 63 + #define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + \ 64 64 + ((block_id) & 3) * 0x40000ull) 65 65 + #define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + \ 66 66 + ((offset) & 1) * 8) 67 67 + #define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \ 68 68 + ((offset) & 31) * 8) 69 69 + #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) 107 70 108 108 - union cvmx_l2c_big_ctl { 109 109 - uint64_t u64; 110 110 - struct cvmx_l2c_big_ctl_s { 111 111 - #ifdef __BIG_ENDIAN_BITFIELD 112 112 - uint64_t reserved_8_63:56; 113 113 - uint64_t maxdram:4; 114 114 - uint64_t reserved_1_3:3; 115 115 - uint64_t disable:1; 116 116 - #else 117 117 - uint64_t disable:1; 118 118 - uint64_t reserved_1_3:3; 119 119 - uint64_t maxdram:4; 120 120 - uint64_t reserved_8_63:56; 121 121 - #endif 122 122 - } s; 123 123 - struct cvmx_l2c_big_ctl_s cn61xx; 124 124 - struct cvmx_l2c_big_ctl_s cn63xx; 125 125 - struct cvmx_l2c_big_ctl_s cn66xx; 126 126 - struct cvmx_l2c_big_ctl_s cn68xx; 127 127 - struct cvmx_l2c_big_ctl_s cn68xxp1; 128 128 - struct cvmx_l2c_big_ctl_s cnf71xx; 129 129 - }; 130 130 - 131 131 - union cvmx_l2c_bst { 132 132 - uint64_t u64; 133 133 - struct cvmx_l2c_bst_s { 134 134 - #ifdef __BIG_ENDIAN_BITFIELD 135 135 - uint64_t dutfl:32; 136 136 - uint64_t rbffl:4; 137 137 - uint64_t xbffl:4; 138 138 - uint64_t tdpfl:4; 139 139 - uint64_t ioccmdfl:4; 140 140 - uint64_t iocdatfl:4; 141 141 - uint64_t dutresfl:4; 142 142 - uint64_t vrtfl:4; 143 143 - uint64_t tdffl:4; 144 144 - #else 145 145 - uint64_t tdffl:4; 146 146 - uint64_t vrtfl:4; 147 147 - uint64_t dutresfl:4; 148 148 - uint64_t iocdatfl:4; 149 149 - uint64_t ioccmdfl:4; 150 150 - uint64_t tdpfl:4; 151 151 - uint64_t xbffl:4; 152 152 - uint64_t rbffl:4; 153 153 - uint64_t dutfl:32; 154 154 - #endif 155 155 - } s; 156 156 - struct cvmx_l2c_bst_cn61xx { 157 157 - #ifdef __BIG_ENDIAN_BITFIELD 158 158 - uint64_t reserved_36_63:28; 159 159 - uint64_t dutfl:4; 160 160 - uint64_t reserved_17_31:15; 161 161 - uint64_t ioccmdfl:1; 162 162 - uint64_t reserved_13_15:3; 163 163 - uint64_t iocdatfl:1; 164 164 - uint64_t reserved_9_11:3; 165 165 - uint64_t dutresfl:1; 166 166 - uint64_t reserved_5_7:3; 167 167 - uint64_t vrtfl:1; 168 168 - uint64_t reserved_1_3:3; 169 169 - uint64_t tdffl:1; 170 170 - #else 171 171 - uint64_t tdffl:1; 172 172 - uint64_t reserved_1_3:3; 173 173 - uint64_t vrtfl:1; 174 174 - uint64_t reserved_5_7:3; 175 175 - uint64_t dutresfl:1; 176 176 - uint64_t reserved_9_11:3; 177 177 - uint64_t iocdatfl:1; 178 178 - uint64_t reserved_13_15:3; 179 179 - uint64_t ioccmdfl:1; 180 180 - uint64_t reserved_17_31:15; 181 181 - uint64_t dutfl:4; 182 182 - uint64_t reserved_36_63:28; 183 183 - #endif 184 184 - } cn61xx; 185 185 - struct cvmx_l2c_bst_cn63xx { 186 186 - #ifdef __BIG_ENDIAN_BITFIELD 187 187 - uint64_t reserved_38_63:26; 188 188 - uint64_t dutfl:6; 189 189 - uint64_t reserved_17_31:15; 190 190 - uint64_t ioccmdfl:1; 191 191 - uint64_t reserved_13_15:3; 192 192 - uint64_t iocdatfl:1; 193 193 - uint64_t reserved_9_11:3; 194 194 - uint64_t dutresfl:1; 195 195 - uint64_t reserved_5_7:3; 196 196 - uint64_t vrtfl:1; 197 197 - uint64_t reserved_1_3:3; 198 198 - uint64_t tdffl:1; 199 199 - #else 200 200 - uint64_t tdffl:1; 201 201 - uint64_t reserved_1_3:3; 202 202 - uint64_t vrtfl:1; 203 203 - uint64_t reserved_5_7:3; 204 204 - uint64_t dutresfl:1; 205 205 - uint64_t reserved_9_11:3; 206 206 - uint64_t iocdatfl:1; 207 207 - uint64_t reserved_13_15:3; 208 208 - uint64_t ioccmdfl:1; 209 209 - uint64_t reserved_17_31:15; 210 210 - uint64_t dutfl:6; 211 211 - uint64_t reserved_38_63:26; 212 212 - #endif 213 213 - } cn63xx; 214 214 - struct cvmx_l2c_bst_cn63xx cn63xxp1; 215 215 - struct cvmx_l2c_bst_cn66xx { 216 216 - #ifdef __BIG_ENDIAN_BITFIELD 217 217 - uint64_t reserved_42_63:22; 218 218 - uint64_t dutfl:10; 219 219 - uint64_t reserved_17_31:15; 220 220 - uint64_t ioccmdfl:1; 221 221 - uint64_t reserved_13_15:3; 222 222 - uint64_t iocdatfl:1; 223 223 - uint64_t reserved_9_11:3; 224 224 - uint64_t dutresfl:1; 225 225 - uint64_t reserved_5_7:3; 226 226 - uint64_t vrtfl:1; 227 227 - uint64_t reserved_1_3:3; 228 228 - uint64_t tdffl:1; 229 229 - #else 230 230 - uint64_t tdffl:1; 231 231 - uint64_t reserved_1_3:3; 232 232 - uint64_t vrtfl:1; 233 233 - uint64_t reserved_5_7:3; 234 234 - uint64_t dutresfl:1; 235 235 - uint64_t reserved_9_11:3; 236 236 - uint64_t iocdatfl:1; 237 237 - uint64_t reserved_13_15:3; 238 238 - uint64_t ioccmdfl:1; 239 239 - uint64_t reserved_17_31:15; 240 240 - uint64_t dutfl:10; 241 241 - uint64_t reserved_42_63:22; 242 242 - #endif 243 243 - } cn66xx; 244 244 - struct cvmx_l2c_bst_s cn68xx; 245 245 - struct cvmx_l2c_bst_s cn68xxp1; 246 246 - struct cvmx_l2c_bst_cn61xx cnf71xx; 247 247 - }; 248 248 - 249 249 - union cvmx_l2c_bst0 { 250 250 - uint64_t u64; 251 251 - struct cvmx_l2c_bst0_s { 252 252 - #ifdef __BIG_ENDIAN_BITFIELD 253 253 - uint64_t reserved_24_63:40; 254 254 - uint64_t dtbnk:1; 255 255 - uint64_t wlb_msk:4; 256 256 - uint64_t dtcnt:13; 257 257 - uint64_t dt:1; 258 258 - uint64_t stin_msk:1; 259 259 - uint64_t wlb_dat:4; 260 260 - #else 261 261 - uint64_t wlb_dat:4; 262 262 - uint64_t stin_msk:1; 263 263 - uint64_t dt:1; 264 264 - uint64_t dtcnt:13; 265 265 - uint64_t wlb_msk:4; 266 266 - uint64_t dtbnk:1; 267 267 - uint64_t reserved_24_63:40; 268 268 - #endif 269 269 - } s; 270 270 - struct cvmx_l2c_bst0_cn30xx { 271 271 - #ifdef __BIG_ENDIAN_BITFIELD 272 272 - uint64_t reserved_23_63:41; 273 273 - uint64_t wlb_msk:4; 274 274 - uint64_t reserved_15_18:4; 275 275 - uint64_t dtcnt:9; 276 276 - uint64_t dt:1; 277 277 - uint64_t reserved_4_4:1; 278 278 - uint64_t wlb_dat:4; 279 279 - #else 280 280 - uint64_t wlb_dat:4; 281 281 - uint64_t reserved_4_4:1; 282 282 - uint64_t dt:1; 283 283 - uint64_t dtcnt:9; 284 284 - uint64_t reserved_15_18:4; 285 285 - uint64_t wlb_msk:4; 286 286 - uint64_t reserved_23_63:41; 287 287 - #endif 288 288 - } cn30xx; 289 289 - struct cvmx_l2c_bst0_cn31xx { 290 290 - #ifdef __BIG_ENDIAN_BITFIELD 291 291 - uint64_t reserved_23_63:41; 292 292 - uint64_t wlb_msk:4; 293 293 - uint64_t reserved_16_18:3; 294 294 - uint64_t dtcnt:10; 295 295 - uint64_t dt:1; 296 296 - uint64_t stin_msk:1; 297 297 - uint64_t wlb_dat:4; 298 298 - #else 299 299 - uint64_t wlb_dat:4; 300 300 - uint64_t stin_msk:1; 301 301 - uint64_t dt:1; 302 302 - uint64_t dtcnt:10; 303 303 - uint64_t reserved_16_18:3; 304 304 - uint64_t wlb_msk:4; 305 305 - uint64_t reserved_23_63:41; 306 306 - #endif 307 307 - } cn31xx; 308 308 - struct cvmx_l2c_bst0_cn38xx { 309 309 - #ifdef __BIG_ENDIAN_BITFIELD 310 310 - uint64_t reserved_19_63:45; 311 311 - uint64_t dtcnt:13; 312 312 - uint64_t dt:1; 313 313 - uint64_t stin_msk:1; 314 314 - uint64_t wlb_dat:4; 315 315 - #else 316 316 - uint64_t wlb_dat:4; 317 317 - uint64_t stin_msk:1; 318 318 - uint64_t dt:1; 319 319 - uint64_t dtcnt:13; 320 320 - uint64_t reserved_19_63:45; 321 321 - #endif 322 322 - } cn38xx; 323 323 - struct cvmx_l2c_bst0_cn38xx cn38xxp2; 324 324 - struct cvmx_l2c_bst0_cn50xx { 325 325 - #ifdef __BIG_ENDIAN_BITFIELD 326 326 - uint64_t reserved_24_63:40; 327 327 - uint64_t dtbnk:1; 328 328 - uint64_t wlb_msk:4; 329 329 - uint64_t reserved_16_18:3; 330 330 - uint64_t dtcnt:10; 331 331 - uint64_t dt:1; 332 332 - uint64_t stin_msk:1; 333 333 - uint64_t wlb_dat:4; 334 334 - #else 335 335 - uint64_t wlb_dat:4; 336 336 - uint64_t stin_msk:1; 337 337 - uint64_t dt:1; 338 338 - uint64_t dtcnt:10; 339 339 - uint64_t reserved_16_18:3; 340 340 - uint64_t wlb_msk:4; 341 341 - uint64_t dtbnk:1; 342 342 - uint64_t reserved_24_63:40; 343 343 - #endif 344 344 - } cn50xx; 345 345 - struct cvmx_l2c_bst0_cn50xx cn52xx; 346 346 - struct cvmx_l2c_bst0_cn50xx cn52xxp1; 347 347 - struct cvmx_l2c_bst0_s cn56xx; 348 348 - struct cvmx_l2c_bst0_s cn56xxp1; 349 349 - struct cvmx_l2c_bst0_s cn58xx; 350 350 - struct cvmx_l2c_bst0_s cn58xxp1; 351 351 - }; 352 352 - 353 353 - union cvmx_l2c_bst1 { 354 354 - uint64_t u64; 355 355 - struct cvmx_l2c_bst1_s { 356 356 - #ifdef __BIG_ENDIAN_BITFIELD 357 357 - uint64_t reserved_9_63:55; 358 358 - uint64_t l2t:9; 359 359 - #else 360 360 - uint64_t l2t:9; 361 361 - uint64_t reserved_9_63:55; 362 362 - #endif 363 363 - } s; 364 364 - struct cvmx_l2c_bst1_cn30xx { 365 365 - #ifdef __BIG_ENDIAN_BITFIELD 366 366 - uint64_t reserved_16_63:48; 367 367 - uint64_t vwdf:4; 368 368 - uint64_t lrf:2; 369 369 - uint64_t vab_vwcf:1; 370 370 - uint64_t reserved_5_8:4; 371 371 - uint64_t l2t:5; 372 372 - #else 373 373 - uint64_t l2t:5; 374 374 - uint64_t reserved_5_8:4; 375 375 - uint64_t vab_vwcf:1; 376 376 - uint64_t lrf:2; 377 377 - uint64_t vwdf:4; 378 378 - uint64_t reserved_16_63:48; 379 379 - #endif 380 380 - } cn30xx; 381 381 - struct cvmx_l2c_bst1_cn30xx cn31xx; 382 382 - struct cvmx_l2c_bst1_cn38xx { 383 383 - #ifdef __BIG_ENDIAN_BITFIELD 384 384 - uint64_t reserved_16_63:48; 385 385 - uint64_t vwdf:4; 386 386 - uint64_t lrf:2; 387 387 - uint64_t vab_vwcf:1; 388 388 - uint64_t l2t:9; 389 389 - #else 390 390 - uint64_t l2t:9; 391 391 - uint64_t vab_vwcf:1; 392 392 - uint64_t lrf:2; 393 393 - uint64_t vwdf:4; 394 394 - uint64_t reserved_16_63:48; 395 395 - #endif 396 396 - } cn38xx; 397 397 - struct cvmx_l2c_bst1_cn38xx cn38xxp2; 398 398 - struct cvmx_l2c_bst1_cn38xx cn50xx; 399 399 - struct cvmx_l2c_bst1_cn52xx { 400 400 - #ifdef __BIG_ENDIAN_BITFIELD 401 401 - uint64_t reserved_19_63:45; 402 402 - uint64_t plc2:1; 403 403 - uint64_t plc1:1; 404 404 - uint64_t plc0:1; 405 405 - uint64_t vwdf:4; 406 406 - uint64_t reserved_11_11:1; 407 407 - uint64_t ilc:1; 408 408 - uint64_t vab_vwcf:1; 409 409 - uint64_t l2t:9; 410 410 - #else 411 411 - uint64_t l2t:9; 412 412 - uint64_t vab_vwcf:1; 413 413 - uint64_t ilc:1; 414 414 - uint64_t reserved_11_11:1; 415 415 - uint64_t vwdf:4; 416 416 - uint64_t plc0:1; 417 417 - uint64_t plc1:1; 418 418 - uint64_t plc2:1; 419 419 - uint64_t reserved_19_63:45; 420 420 - #endif 421 421 - } cn52xx; 422 422 - struct cvmx_l2c_bst1_cn52xx cn52xxp1; 423 423 - struct cvmx_l2c_bst1_cn56xx { 424 424 - #ifdef __BIG_ENDIAN_BITFIELD 425 425 - uint64_t reserved_24_63:40; 426 426 - uint64_t plc2:1; 427 427 - uint64_t plc1:1; 428 428 - uint64_t plc0:1; 429 429 - uint64_t ilc:1; 430 430 - uint64_t vwdf1:4; 431 431 - uint64_t vwdf0:4; 432 432 - uint64_t vab_vwcf1:1; 433 433 - uint64_t reserved_10_10:1; 434 434 - uint64_t vab_vwcf0:1; 435 435 - uint64_t l2t:9; 436 436 - #else 437 437 - uint64_t l2t:9; 438 438 - uint64_t vab_vwcf0:1; 439 439 - uint64_t reserved_10_10:1; 440 440 - uint64_t vab_vwcf1:1; 441 441 - uint64_t vwdf0:4; 442 442 - uint64_t vwdf1:4; 443 443 - uint64_t ilc:1; 444 444 - uint64_t plc0:1; 445 445 - uint64_t plc1:1; 446 446 - uint64_t plc2:1; 447 447 - uint64_t reserved_24_63:40; 448 448 - #endif 449 449 - } cn56xx; 450 450 - struct cvmx_l2c_bst1_cn56xx cn56xxp1; 451 451 - struct cvmx_l2c_bst1_cn38xx cn58xx; 452 452 - struct cvmx_l2c_bst1_cn38xx cn58xxp1; 453 453 - }; 454 454 - 455 455 - union cvmx_l2c_bst2 { 456 456 - uint64_t u64; 457 457 - struct cvmx_l2c_bst2_s { 458 458 - #ifdef __BIG_ENDIAN_BITFIELD 459 459 - uint64_t reserved_16_63:48; 460 460 - uint64_t mrb:4; 461 461 - uint64_t reserved_4_11:8; 462 462 - uint64_t ipcbst:1; 463 463 - uint64_t picbst:1; 464 464 - uint64_t xrdmsk:1; 465 465 - uint64_t xrddat:1; 466 466 - #else 467 467 - uint64_t xrddat:1; 468 468 - uint64_t xrdmsk:1; 469 469 - uint64_t picbst:1; 470 470 - uint64_t ipcbst:1; 471 471 - uint64_t reserved_4_11:8; 472 472 - uint64_t mrb:4; 473 473 - uint64_t reserved_16_63:48; 474 474 - #endif 475 475 - } s; 476 476 - struct cvmx_l2c_bst2_cn30xx { 477 477 - #ifdef __BIG_ENDIAN_BITFIELD 478 478 - uint64_t reserved_16_63:48; 479 479 - uint64_t mrb:4; 480 480 - uint64_t rmdf:4; 481 481 - uint64_t reserved_4_7:4; 482 482 - uint64_t ipcbst:1; 483 483 - uint64_t reserved_2_2:1; 484 484 - uint64_t xrdmsk:1; 485 485 - uint64_t xrddat:1; 486 486 - #else 487 487 - uint64_t xrddat:1; 488 488 - uint64_t xrdmsk:1; 489 489 - uint64_t reserved_2_2:1; 490 490 - uint64_t ipcbst:1; 491 491 - uint64_t reserved_4_7:4; 492 492 - uint64_t rmdf:4; 493 493 - uint64_t mrb:4; 494 494 - uint64_t reserved_16_63:48; 495 495 - #endif 496 496 - } cn30xx; 497 497 - struct cvmx_l2c_bst2_cn30xx cn31xx; 498 498 - struct cvmx_l2c_bst2_cn38xx { 499 499 - #ifdef __BIG_ENDIAN_BITFIELD 500 500 - uint64_t reserved_16_63:48; 501 501 - uint64_t mrb:4; 502 502 - uint64_t rmdf:4; 503 503 - uint64_t rhdf:4; 504 504 - uint64_t ipcbst:1; 505 505 - uint64_t picbst:1; 506 506 - uint64_t xrdmsk:1; 507 507 - uint64_t xrddat:1; 508 508 - #else 509 509 - uint64_t xrddat:1; 510 510 - uint64_t xrdmsk:1; 511 511 - uint64_t picbst:1; 512 512 - uint64_t ipcbst:1; 513 513 - uint64_t rhdf:4; 514 514 - uint64_t rmdf:4; 515 515 - uint64_t mrb:4; 516 516 - uint64_t reserved_16_63:48; 517 517 - #endif 518 518 - } cn38xx; 519 519 - struct cvmx_l2c_bst2_cn38xx cn38xxp2; 520 520 - struct cvmx_l2c_bst2_cn30xx cn50xx; 521 521 - struct cvmx_l2c_bst2_cn30xx cn52xx; 522 522 - struct cvmx_l2c_bst2_cn30xx cn52xxp1; 523 523 - struct cvmx_l2c_bst2_cn56xx { 524 524 - #ifdef __BIG_ENDIAN_BITFIELD 525 525 - uint64_t reserved_16_63:48; 526 526 - uint64_t mrb:4; 527 527 - uint64_t rmdb:4; 528 528 - uint64_t rhdb:4; 529 529 - uint64_t ipcbst:1; 530 530 - uint64_t picbst:1; 531 531 - uint64_t xrdmsk:1; 532 532 - uint64_t xrddat:1; 533 533 - #else 534 534 - uint64_t xrddat:1; 535 535 - uint64_t xrdmsk:1; 536 536 - uint64_t picbst:1; 537 537 - uint64_t ipcbst:1; 538 538 - uint64_t rhdb:4; 539 539 - uint64_t rmdb:4; 540 540 - uint64_t mrb:4; 541 541 - uint64_t reserved_16_63:48; 542 542 - #endif 543 543 - } cn56xx; 544 544 - struct cvmx_l2c_bst2_cn56xx cn56xxp1; 545 545 - struct cvmx_l2c_bst2_cn56xx cn58xx; 546 546 - struct cvmx_l2c_bst2_cn56xx cn58xxp1; 547 547 - }; 548 548 - 549 549 - union cvmx_l2c_bst_memx { 550 550 - uint64_t u64; 551 551 - struct cvmx_l2c_bst_memx_s { 552 552 - #ifdef __BIG_ENDIAN_BITFIELD 553 553 - uint64_t start_bist:1; 554 554 - uint64_t clear_bist:1; 555 555 - uint64_t reserved_5_61:57; 556 556 - uint64_t rdffl:1; 557 557 - uint64_t vbffl:4; 558 558 - #else 559 559 - uint64_t vbffl:4; 560 560 - uint64_t rdffl:1; 561 561 - uint64_t reserved_5_61:57; 562 562 - uint64_t clear_bist:1; 563 563 - uint64_t start_bist:1; 564 564 - #endif 565 565 - } s; 566 566 - struct cvmx_l2c_bst_memx_s cn61xx; 567 567 - struct cvmx_l2c_bst_memx_s cn63xx; 568 568 - struct cvmx_l2c_bst_memx_s cn63xxp1; 569 569 - struct cvmx_l2c_bst_memx_s cn66xx; 570 570 - struct cvmx_l2c_bst_memx_s cn68xx; 571 571 - struct cvmx_l2c_bst_memx_s cn68xxp1; 572 572 - struct cvmx_l2c_bst_memx_s cnf71xx; 573 573 - }; 574 574 - 575 575 - union cvmx_l2c_bst_tdtx { 576 576 - uint64_t u64; 577 577 - struct cvmx_l2c_bst_tdtx_s { 578 578 - #ifdef __BIG_ENDIAN_BITFIELD 579 579 - uint64_t reserved_32_63:32; 580 580 - uint64_t fbfrspfl:8; 581 581 - uint64_t sbffl:8; 582 582 - uint64_t fbffl:8; 583 583 - uint64_t l2dfl:8; 584 584 - #else 585 585 - uint64_t l2dfl:8; 586 586 - uint64_t fbffl:8; 587 587 - uint64_t sbffl:8; 588 588 - uint64_t fbfrspfl:8; 589 589 - uint64_t reserved_32_63:32; 590 590 - #endif 591 591 - } s; 592 592 - struct cvmx_l2c_bst_tdtx_s cn61xx; 593 593 - struct cvmx_l2c_bst_tdtx_s cn63xx; 594 594 - struct cvmx_l2c_bst_tdtx_cn63xxp1 { 595 595 - #ifdef __BIG_ENDIAN_BITFIELD 596 596 - uint64_t reserved_24_63:40; 597 597 - uint64_t sbffl:8; 598 598 - uint64_t fbffl:8; 599 599 - uint64_t l2dfl:8; 600 600 - #else 601 601 - uint64_t l2dfl:8; 602 602 - uint64_t fbffl:8; 603 603 - uint64_t sbffl:8; 604 604 - uint64_t reserved_24_63:40; 605 605 - #endif 606 606 - } cn63xxp1; 607 607 - struct cvmx_l2c_bst_tdtx_s cn66xx; 608 608 - struct cvmx_l2c_bst_tdtx_s cn68xx; 609 609 - struct cvmx_l2c_bst_tdtx_s cn68xxp1; 610 610 - struct cvmx_l2c_bst_tdtx_s cnf71xx; 611 611 - }; 612 612 - 613 613 - union cvmx_l2c_bst_ttgx { 614 614 - uint64_t u64; 615 615 - struct cvmx_l2c_bst_ttgx_s { 616 616 - #ifdef __BIG_ENDIAN_BITFIELD 617 617 - uint64_t reserved_17_63:47; 618 618 - uint64_t lrufl:1; 619 619 - uint64_t tagfl:16; 620 620 - #else 621 621 - uint64_t tagfl:16; 622 622 - uint64_t lrufl:1; 623 623 - uint64_t reserved_17_63:47; 624 624 - #endif 625 625 - } s; 626 626 - struct cvmx_l2c_bst_ttgx_s cn61xx; 627 627 - struct cvmx_l2c_bst_ttgx_s cn63xx; 628 628 - struct cvmx_l2c_bst_ttgx_s cn63xxp1; 629 629 - struct cvmx_l2c_bst_ttgx_s cn66xx; 630 630 - struct cvmx_l2c_bst_ttgx_s cn68xx; 631 631 - struct cvmx_l2c_bst_ttgx_s cn68xxp1; 632 632 - struct cvmx_l2c_bst_ttgx_s cnf71xx; 633 633 - }; 634 71 635 72 union cvmx_l2c_cfg { 636 73 uint64_t u64; 637 74 struct cvmx_l2c_cfg_s { 638 638 - #ifdef __BIG_ENDIAN_BITFIELD 639 639 - uint64_t reserved_20_63:44; 640 640 - uint64_t bstrun:1; 641 641 - uint64_t lbist:1; 642 642 - uint64_t xor_bank:1; 643 643 - uint64_t dpres1:1; 644 644 - uint64_t dpres0:1; 645 645 - uint64_t dfill_dis:1; 646 646 - uint64_t fpexp:4; 647 647 - uint64_t fpempty:1; 648 648 - uint64_t fpen:1; 649 649 - uint64_t idxalias:1; 650 650 - uint64_t mwf_crd:4; 651 651 - uint64_t rsp_arb_mode:1; 652 652 - uint64_t rfb_arb_mode:1; 653 653 - uint64_t lrf_arb_mode:1; 654 654 - #else 655 655 - uint64_t lrf_arb_mode:1; 656 656 - uint64_t rfb_arb_mode:1; 657 657 - uint64_t rsp_arb_mode:1; 658 658 - uint64_t mwf_crd:4; 659 659 - uint64_t idxalias:1; 660 660 - uint64_t fpen:1; 661 661 - uint64_t fpempty:1; 662 662 - uint64_t fpexp:4; 663 663 - uint64_t dfill_dis:1; 664 664 - uint64_t dpres0:1; 665 665 - uint64_t dpres1:1; 666 666 - uint64_t xor_bank:1; 667 667 - uint64_t lbist:1; 668 668 - uint64_t bstrun:1; 669 669 - uint64_t reserved_20_63:44; 670 670 - #endif 75 75 + __BITFIELD_FIELD(uint64_t reserved_20_63:44, 76 76 + __BITFIELD_FIELD(uint64_t bstrun:1, 77 77 + __BITFIELD_FIELD(uint64_t lbist:1, 78 78 + __BITFIELD_FIELD(uint64_t xor_bank:1, 79 79 + __BITFIELD_FIELD(uint64_t dpres1:1, 80 80 + __BITFIELD_FIELD(uint64_t dpres0:1, 81 81 + __BITFIELD_FIELD(uint64_t dfill_dis:1, 82 82 + __BITFIELD_FIELD(uint64_t fpexp:4, 83 83 + __BITFIELD_FIELD(uint64_t fpempty:1, 84 84 + __BITFIELD_FIELD(uint64_t fpen:1, 85 85 + __BITFIELD_FIELD(uint64_t idxalias:1, 86 86 + __BITFIELD_FIELD(uint64_t mwf_crd:4, 87 87 + __BITFIELD_FIELD(uint64_t rsp_arb_mode:1, 88 88 + __BITFIELD_FIELD(uint64_t rfb_arb_mode:1, 89 89 + __BITFIELD_FIELD(uint64_t lrf_arb_mode:1, 90 90 + ;))))))))))))))) 671 91 } s; 672 672 - struct cvmx_l2c_cfg_cn30xx { 673 673 - #ifdef __BIG_ENDIAN_BITFIELD 674 674 - uint64_t reserved_14_63:50; 675 675 - uint64_t fpexp:4; 676 676 - uint64_t fpempty:1; 677 677 - uint64_t fpen:1; 678 678 - uint64_t idxalias:1; 679 679 - uint64_t mwf_crd:4; 680 680 - uint64_t rsp_arb_mode:1; 681 681 - uint64_t rfb_arb_mode:1; 682 682 - uint64_t lrf_arb_mode:1; 683 683 - #else 684 684 - uint64_t lrf_arb_mode:1; 685 685 - uint64_t rfb_arb_mode:1; 686 686 - uint64_t rsp_arb_mode:1; 687 687 - uint64_t mwf_crd:4; 688 688 - uint64_t idxalias:1; 689 689 - uint64_t fpen:1; 690 690 - uint64_t fpempty:1; 691 691 - uint64_t fpexp:4; 692 692 - uint64_t reserved_14_63:50; 693 693 - #endif 694 694 - } cn30xx; 695 695 - struct cvmx_l2c_cfg_cn30xx cn31xx; 696 696 - struct cvmx_l2c_cfg_cn30xx cn38xx; 697 697 - struct cvmx_l2c_cfg_cn30xx cn38xxp2; 698 698 - struct cvmx_l2c_cfg_cn50xx { 699 699 - #ifdef __BIG_ENDIAN_BITFIELD 700 700 - uint64_t reserved_20_63:44; 701 701 - uint64_t bstrun:1; 702 702 - uint64_t lbist:1; 703 703 - uint64_t reserved_14_17:4; 704 704 - uint64_t fpexp:4; 705 705 - uint64_t fpempty:1; 706 706 - uint64_t fpen:1; 707 707 - uint64_t idxalias:1; 708 708 - uint64_t mwf_crd:4; 709 709 - uint64_t rsp_arb_mode:1; 710 710 - uint64_t rfb_arb_mode:1; 711 711 - uint64_t lrf_arb_mode:1; 712 712 - #else 713 713 - uint64_t lrf_arb_mode:1; 714 714 - uint64_t rfb_arb_mode:1; 715 715 - uint64_t rsp_arb_mode:1; 716 716 - uint64_t mwf_crd:4; 717 717 - uint64_t idxalias:1; 718 718 - uint64_t fpen:1; 719 719 - uint64_t fpempty:1; 720 720 - uint64_t fpexp:4; 721 721 - uint64_t reserved_14_17:4; 722 722 - uint64_t lbist:1; 723 723 - uint64_t bstrun:1; 724 724 - uint64_t reserved_20_63:44; 725 725 - #endif 726 726 - } cn50xx; 727 727 - struct cvmx_l2c_cfg_cn50xx cn52xx; 728 728 - struct cvmx_l2c_cfg_cn50xx cn52xxp1; 729 729 - struct cvmx_l2c_cfg_s cn56xx; 730 730 - struct cvmx_l2c_cfg_s cn56xxp1; 731 731 - struct cvmx_l2c_cfg_cn58xx { 732 732 - #ifdef __BIG_ENDIAN_BITFIELD 733 733 - uint64_t reserved_20_63:44; 734 734 - uint64_t bstrun:1; 735 735 - uint64_t lbist:1; 736 736 - uint64_t reserved_15_17:3; 737 737 - uint64_t dfill_dis:1; 738 738 - uint64_t fpexp:4; 739 739 - uint64_t fpempty:1; 740 740 - uint64_t fpen:1; 741 741 - uint64_t idxalias:1; 742 742 - uint64_t mwf_crd:4; 743 743 - uint64_t rsp_arb_mode:1; 744 744 - uint64_t rfb_arb_mode:1; 745 745 - uint64_t lrf_arb_mode:1; 746 746 - #else 747 747 - uint64_t lrf_arb_mode:1; 748 748 - uint64_t rfb_arb_mode:1; 749 749 - uint64_t rsp_arb_mode:1; 750 750 - uint64_t mwf_crd:4; 751 751 - uint64_t idxalias:1; 752 752 - uint64_t fpen:1; 753 753 - uint64_t fpempty:1; 754 754 - uint64_t fpexp:4; 755 755 - uint64_t dfill_dis:1; 756 756 - uint64_t reserved_15_17:3; 757 757 - uint64_t lbist:1; 758 758 - uint64_t bstrun:1; 759 759 - uint64_t reserved_20_63:44; 760 760 - #endif 761 761 - } cn58xx; 762 762 - struct cvmx_l2c_cfg_cn58xxp1 { 763 763 - #ifdef __BIG_ENDIAN_BITFIELD 764 764 - uint64_t reserved_15_63:49; 765 765 - uint64_t dfill_dis:1; 766 766 - uint64_t fpexp:4; 767 767 - uint64_t fpempty:1; 768 768 - uint64_t fpen:1; 769 769 - uint64_t idxalias:1; 770 770 - uint64_t mwf_crd:4; 771 771 - uint64_t rsp_arb_mode:1; 772 772 - uint64_t rfb_arb_mode:1; 773 773 - uint64_t lrf_arb_mode:1; 774 774 - #else 775 775 - uint64_t lrf_arb_mode:1; 776 776 - uint64_t rfb_arb_mode:1; 777 777 - uint64_t rsp_arb_mode:1; 778 778 - uint64_t mwf_crd:4; 779 779 - uint64_t idxalias:1; 780 780 - uint64_t fpen:1; 781 781 - uint64_t fpempty:1; 782 782 - uint64_t fpexp:4; 783 783 - uint64_t dfill_dis:1; 784 784 - uint64_t reserved_15_63:49; 785 785 - #endif 786 786 - } cn58xxp1; 787 787 - }; 788 788 - 789 789 - union cvmx_l2c_cop0_mapx { 790 790 - uint64_t u64; 791 791 - struct cvmx_l2c_cop0_mapx_s { 792 792 - #ifdef __BIG_ENDIAN_BITFIELD 793 793 - uint64_t data:64; 794 794 - #else 795 795 - uint64_t data:64; 796 796 - #endif 797 797 - } s; 798 798 - struct cvmx_l2c_cop0_mapx_s cn61xx; 799 799 - struct cvmx_l2c_cop0_mapx_s cn63xx; 800 800 - struct cvmx_l2c_cop0_mapx_s cn63xxp1; 801 801 - struct cvmx_l2c_cop0_mapx_s cn66xx; 802 802 - struct cvmx_l2c_cop0_mapx_s cn68xx; 803 803 - struct cvmx_l2c_cop0_mapx_s cn68xxp1; 804 804 - struct cvmx_l2c_cop0_mapx_s cnf71xx; 805 92 }; 806 93 807 94 union cvmx_l2c_ctl { 808 95 uint64_t u64; 809 96 struct cvmx_l2c_ctl_s { 810 810 - #ifdef __BIG_ENDIAN_BITFIELD 811 811 - uint64_t reserved_30_63:34; 812 812 - uint64_t sepcmt:1; 813 813 - uint64_t rdf_fast:1; 814 814 - uint64_t disstgl2i:1; 815 815 - uint64_t l2dfsbe:1; 816 816 - uint64_t l2dfdbe:1; 817 817 - uint64_t discclk:1; 818 818 - uint64_t maxvab:4; 819 819 - uint64_t maxlfb:4; 820 820 - uint64_t rsp_arb_mode:1; 821 821 - uint64_t xmc_arb_mode:1; 822 822 - uint64_t ef_ena:1; 823 823 - uint64_t ef_cnt:7; 824 824 - uint64_t vab_thresh:4; 825 825 - uint64_t disecc:1; 826 826 - uint64_t disidxalias:1; 827 827 - #else 828 828 - uint64_t disidxalias:1; 829 829 - uint64_t disecc:1; 830 830 - uint64_t vab_thresh:4; 831 831 - uint64_t ef_cnt:7; 832 832 - uint64_t ef_ena:1; 833 833 - uint64_t xmc_arb_mode:1; 834 834 - uint64_t rsp_arb_mode:1; 835 835 - uint64_t maxlfb:4; 836 836 - uint64_t maxvab:4; 837 837 - uint64_t discclk:1; 838 838 - uint64_t l2dfdbe:1; 839 839 - uint64_t l2dfsbe:1; 840 840 - uint64_t disstgl2i:1; 841 841 - uint64_t rdf_fast:1; 842 842 - uint64_t sepcmt:1; 843 843 - uint64_t reserved_30_63:34; 844 844 - #endif 97 97 + __BITFIELD_FIELD(uint64_t reserved_30_63:34, 98 98 + __BITFIELD_FIELD(uint64_t sepcmt:1, 99 99 + __BITFIELD_FIELD(uint64_t rdf_fast:1, 100 100 + __BITFIELD_FIELD(uint64_t disstgl2i:1, 101 101 + __BITFIELD_FIELD(uint64_t l2dfsbe:1, 102 102 + __BITFIELD_FIELD(uint64_t l2dfdbe:1, 103 103 + __BITFIELD_FIELD(uint64_t discclk:1, 104 104 + __BITFIELD_FIELD(uint64_t maxvab:4, 105 105 + __BITFIELD_FIELD(uint64_t maxlfb:4, 106 106 + __BITFIELD_FIELD(uint64_t rsp_arb_mode:1, 107 107 + __BITFIELD_FIELD(uint64_t xmc_arb_mode:1, 108 108 + __BITFIELD_FIELD(uint64_t ef_ena:1, 109 109 + __BITFIELD_FIELD(uint64_t ef_cnt:7, 110 110 + __BITFIELD_FIELD(uint64_t vab_thresh:4, 111 111 + __BITFIELD_FIELD(uint64_t disecc:1, 112 112 + __BITFIELD_FIELD(uint64_t disidxalias:1, 113 113 + ;)))))))))))))))) 845 114 } s; 846 846 - struct cvmx_l2c_ctl_cn61xx { 847 847 - #ifdef __BIG_ENDIAN_BITFIELD 848 848 - uint64_t reserved_29_63:35; 849 849 - uint64_t rdf_fast:1; 850 850 - uint64_t disstgl2i:1; 851 851 - uint64_t l2dfsbe:1; 852 852 - uint64_t l2dfdbe:1; 853 853 - uint64_t discclk:1; 854 854 - uint64_t maxvab:4; 855 855 - uint64_t maxlfb:4; 856 856 - uint64_t rsp_arb_mode:1; 857 857 - uint64_t xmc_arb_mode:1; 858 858 - uint64_t ef_ena:1; 859 859 - uint64_t ef_cnt:7; 860 860 - uint64_t vab_thresh:4; 861 861 - uint64_t disecc:1; 862 862 - uint64_t disidxalias:1; 863 863 - #else 864 864 - uint64_t disidxalias:1; 865 865 - uint64_t disecc:1; 866 866 - uint64_t vab_thresh:4; 867 867 - uint64_t ef_cnt:7; 868 868 - uint64_t ef_ena:1; 869 869 - uint64_t xmc_arb_mode:1; 870 870 - uint64_t rsp_arb_mode:1; 871 871 - uint64_t maxlfb:4; 872 872 - uint64_t maxvab:4; 873 873 - uint64_t discclk:1; 874 874 - uint64_t l2dfdbe:1; 875 875 - uint64_t l2dfsbe:1; 876 876 - uint64_t disstgl2i:1; 877 877 - uint64_t rdf_fast:1; 878 878 - uint64_t reserved_29_63:35; 879 879 - #endif 880 880 - } cn61xx; 881 881 - struct cvmx_l2c_ctl_cn63xx { 882 882 - #ifdef __BIG_ENDIAN_BITFIELD 883 883 - uint64_t reserved_28_63:36; 884 884 - uint64_t disstgl2i:1; 885 885 - uint64_t l2dfsbe:1; 886 886 - uint64_t l2dfdbe:1; 887 887 - uint64_t discclk:1; 888 888 - uint64_t maxvab:4; 889 889 - uint64_t maxlfb:4; 890 890 - uint64_t rsp_arb_mode:1; 891 891 - uint64_t xmc_arb_mode:1; 892 892 - uint64_t ef_ena:1; 893 893 - uint64_t ef_cnt:7; 894 894 - uint64_t vab_thresh:4; 895 895 - uint64_t disecc:1; 896 896 - uint64_t disidxalias:1; 897 897 - #else 898 898 - uint64_t disidxalias:1; 899 899 - uint64_t disecc:1; 900 900 - uint64_t vab_thresh:4; 901 901 - uint64_t ef_cnt:7; 902 902 - uint64_t ef_ena:1; 903 903 - uint64_t xmc_arb_mode:1; 904 904 - uint64_t rsp_arb_mode:1; 905 905 - uint64_t maxlfb:4; 906 906 - uint64_t maxvab:4; 907 907 - uint64_t discclk:1; 908 908 - uint64_t l2dfdbe:1; 909 909 - uint64_t l2dfsbe:1; 910 910 - uint64_t disstgl2i:1; 911 911 - uint64_t reserved_28_63:36; 912 912 - #endif 913 913 - } cn63xx; 914 914 - struct cvmx_l2c_ctl_cn63xxp1 { 915 915 - #ifdef __BIG_ENDIAN_BITFIELD 916 916 - uint64_t reserved_25_63:39; 917 917 - uint64_t discclk:1; 918 918 - uint64_t maxvab:4; 919 919 - uint64_t maxlfb:4; 920 920 - uint64_t rsp_arb_mode:1; 921 921 - uint64_t xmc_arb_mode:1; 922 922 - uint64_t ef_ena:1; 923 923 - uint64_t ef_cnt:7; 924 924 - uint64_t vab_thresh:4; 925 925 - uint64_t disecc:1; 926 926 - uint64_t disidxalias:1; 927 927 - #else 928 928 - uint64_t disidxalias:1; 929 929 - uint64_t disecc:1; 930 930 - uint64_t vab_thresh:4; 931 931 - uint64_t ef_cnt:7; 932 932 - uint64_t ef_ena:1; 933 933 - uint64_t xmc_arb_mode:1; 934 934 - uint64_t rsp_arb_mode:1; 935 935 - uint64_t maxlfb:4; 936 936 - uint64_t maxvab:4; 937 937 - uint64_t discclk:1; 938 938 - uint64_t reserved_25_63:39; 939 939 - #endif 940 940 - } cn63xxp1; 941 941 - struct cvmx_l2c_ctl_cn61xx cn66xx; 942 942 - struct cvmx_l2c_ctl_s cn68xx; 943 943 - struct cvmx_l2c_ctl_cn63xx cn68xxp1; 944 944 - struct cvmx_l2c_ctl_cn61xx cnf71xx; 945 115 }; 946 116 947 117 union cvmx_l2c_dbg { 948 118 uint64_t u64; 949 119 struct cvmx_l2c_dbg_s { 950 950 - #ifdef __BIG_ENDIAN_BITFIELD 951 951 - uint64_t reserved_15_63:49; 952 952 - uint64_t lfb_enum:4; 953 953 - uint64_t lfb_dmp:1; 954 954 - uint64_t ppnum:4; 955 955 - uint64_t set:3; 956 956 - uint64_t finv:1; 957 957 - uint64_t l2d:1; 958 958 - uint64_t l2t:1; 959 959 - #else 960 960 - uint64_t l2t:1; 961 961 - uint64_t l2d:1; 962 962 - uint64_t finv:1; 963 963 - uint64_t set:3; 964 964 - uint64_t ppnum:4; 965 965 - uint64_t lfb_dmp:1; 966 966 - uint64_t lfb_enum:4; 967 967 - uint64_t reserved_15_63:49; 968 968 - #endif 120 120 + __BITFIELD_FIELD(uint64_t reserved_15_63:49, 121 121 + __BITFIELD_FIELD(uint64_t lfb_enum:4, 122 122 + __BITFIELD_FIELD(uint64_t lfb_dmp:1, 123 123 + __BITFIELD_FIELD(uint64_t ppnum:4, 124 124 + __BITFIELD_FIELD(uint64_t set:3, 125 125 + __BITFIELD_FIELD(uint64_t finv:1, 126 126 + __BITFIELD_FIELD(uint64_t l2d:1, 127 127 + __BITFIELD_FIELD(uint64_t l2t:1, 128 128 + ;)))))))) 969 129 } s; 970 970 - struct cvmx_l2c_dbg_cn30xx { 971 971 - #ifdef __BIG_ENDIAN_BITFIELD 972 972 - uint64_t reserved_13_63:51; 973 973 - uint64_t lfb_enum:2; 974 974 - uint64_t lfb_dmp:1; 975 975 - uint64_t reserved_7_9:3; 976 976 - uint64_t ppnum:1; 977 977 - uint64_t reserved_5_5:1; 978 978 - uint64_t set:2; 979 979 - uint64_t finv:1; 980 980 - uint64_t l2d:1; 981 981 - uint64_t l2t:1; 982 982 - #else 983 983 - uint64_t l2t:1; 984 984 - uint64_t l2d:1; 985 985 - uint64_t finv:1; 986 986 - uint64_t set:2; 987 987 - uint64_t reserved_5_5:1; 988 988 - uint64_t ppnum:1; 989 989 - uint64_t reserved_7_9:3; 990 990 - uint64_t lfb_dmp:1; 991 991 - uint64_t lfb_enum:2; 992 992 - uint64_t reserved_13_63:51; 993 993 - #endif 994 994 - } cn30xx; 995 995 - struct cvmx_l2c_dbg_cn31xx { 996 996 - #ifdef __BIG_ENDIAN_BITFIELD 997 997 - uint64_t reserved_14_63:50; 998 998 - uint64_t lfb_enum:3; 999 999 - uint64_t lfb_dmp:1; 1000 1000 - uint64_t reserved_7_9:3; 1001 1001 - uint64_t ppnum:1; 1002 1002 - uint64_t reserved_5_5:1; 1003 1003 - uint64_t set:2; 1004 1004 - uint64_t finv:1; 1005 1005 - uint64_t l2d:1; 1006 1006 - uint64_t l2t:1; 1007 1007 - #else 1008 1008 - uint64_t l2t:1; 1009 1009 - uint64_t l2d:1; 1010 1010 - uint64_t finv:1; 1011 1011 - uint64_t set:2; 1012 1012 - uint64_t reserved_5_5:1; 1013 1013 - uint64_t ppnum:1; 1014 1014 - uint64_t reserved_7_9:3; 1015 1015 - uint64_t lfb_dmp:1; 1016 1016 - uint64_t lfb_enum:3; 1017 1017 - uint64_t reserved_14_63:50; 1018 1018 - #endif 1019 1019 - } cn31xx; 1020 1020 - struct cvmx_l2c_dbg_s cn38xx; 1021 1021 - struct cvmx_l2c_dbg_s cn38xxp2; 1022 1022 - struct cvmx_l2c_dbg_cn50xx { 1023 1023 - #ifdef __BIG_ENDIAN_BITFIELD 1024 1024 - uint64_t reserved_14_63:50; 1025 1025 - uint64_t lfb_enum:3; 1026 1026 - uint64_t lfb_dmp:1; 1027 1027 - uint64_t reserved_7_9:3; 1028 1028 - uint64_t ppnum:1; 1029 1029 - uint64_t set:3; 1030 1030 - uint64_t finv:1; 1031 1031 - uint64_t l2d:1; 1032 1032 - uint64_t l2t:1; 1033 1033 - #else 1034 1034 - uint64_t l2t:1; 1035 1035 - uint64_t l2d:1; 1036 1036 - uint64_t finv:1; 1037 1037 - uint64_t set:3; 1038 1038 - uint64_t ppnum:1; 1039 1039 - uint64_t reserved_7_9:3; 1040 1040 - uint64_t lfb_dmp:1; 1041 1041 - uint64_t lfb_enum:3; 1042 1042 - uint64_t reserved_14_63:50; 1043 1043 - #endif 1044 1044 - } cn50xx; 1045 1045 - struct cvmx_l2c_dbg_cn52xx { 1046 1046 - #ifdef __BIG_ENDIAN_BITFIELD 1047 1047 - uint64_t reserved_14_63:50; 1048 1048 - uint64_t lfb_enum:3; 1049 1049 - uint64_t lfb_dmp:1; 1050 1050 - uint64_t reserved_8_9:2; 1051 1051 - uint64_t ppnum:2; 1052 1052 - uint64_t set:3; 1053 1053 - uint64_t finv:1; 1054 1054 - uint64_t l2d:1; 1055 1055 - uint64_t l2t:1; 1056 1056 - #else 1057 1057 - uint64_t l2t:1; 1058 1058 - uint64_t l2d:1; 1059 1059 - uint64_t finv:1; 1060 1060 - uint64_t set:3; 1061 1061 - uint64_t ppnum:2; 1062 1062 - uint64_t reserved_8_9:2; 1063 1063 - uint64_t lfb_dmp:1; 1064 1064 - uint64_t lfb_enum:3; 1065 1065 - uint64_t reserved_14_63:50; 1066 1066 - #endif 1067 1067 - } cn52xx; 1068 1068 - struct cvmx_l2c_dbg_cn52xx cn52xxp1; 1069 1069 - struct cvmx_l2c_dbg_s cn56xx; 1070 1070 - struct cvmx_l2c_dbg_s cn56xxp1; 1071 1071 - struct cvmx_l2c_dbg_s cn58xx; 1072 1072 - struct cvmx_l2c_dbg_s cn58xxp1; 1073 1073 - }; 1074 1074 - 1075 1075 - union cvmx_l2c_dut { 1076 1076 - uint64_t u64; 1077 1077 - struct cvmx_l2c_dut_s { 1078 1078 - #ifdef __BIG_ENDIAN_BITFIELD 1079 1079 - uint64_t reserved_32_63:32; 1080 1080 - uint64_t dtena:1; 1081 1081 - uint64_t reserved_30_30:1; 1082 1082 - uint64_t dt_vld:1; 1083 1083 - uint64_t dt_tag:29; 1084 1084 - #else 1085 1085 - uint64_t dt_tag:29; 1086 1086 - uint64_t dt_vld:1; 1087 1087 - uint64_t reserved_30_30:1; 1088 1088 - uint64_t dtena:1; 1089 1089 - uint64_t reserved_32_63:32; 1090 1090 - #endif 1091 1091 - } s; 1092 1092 - struct cvmx_l2c_dut_s cn30xx; 1093 1093 - struct cvmx_l2c_dut_s cn31xx; 1094 1094 - struct cvmx_l2c_dut_s cn38xx; 1095 1095 - struct cvmx_l2c_dut_s cn38xxp2; 1096 1096 - struct cvmx_l2c_dut_s cn50xx; 1097 1097 - struct cvmx_l2c_dut_s cn52xx; 1098 1098 - struct cvmx_l2c_dut_s cn52xxp1; 1099 1099 - struct cvmx_l2c_dut_s cn56xx; 1100 1100 - struct cvmx_l2c_dut_s cn56xxp1; 1101 1101 - struct cvmx_l2c_dut_s cn58xx; 1102 1102 - struct cvmx_l2c_dut_s cn58xxp1; 1103 1103 - }; 1104 1104 - 1105 1105 - union cvmx_l2c_dut_mapx { 1106 1106 - uint64_t u64; 1107 1107 - struct cvmx_l2c_dut_mapx_s { 1108 1108 - #ifdef __BIG_ENDIAN_BITFIELD 1109 1109 - uint64_t reserved_38_63:26; 1110 1110 - uint64_t tag:28; 1111 1111 - uint64_t reserved_1_9:9; 1112 1112 - uint64_t valid:1; 1113 1113 - #else 1114 1114 - uint64_t valid:1; 1115 1115 - uint64_t reserved_1_9:9; 1116 1116 - uint64_t tag:28; 1117 1117 - uint64_t reserved_38_63:26; 1118 1118 - #endif 1119 1119 - } s; 1120 1120 - struct cvmx_l2c_dut_mapx_s cn61xx; 1121 1121 - struct cvmx_l2c_dut_mapx_s cn63xx; 1122 1122 - struct cvmx_l2c_dut_mapx_s cn63xxp1; 1123 1123 - struct cvmx_l2c_dut_mapx_s cn66xx; 1124 1124 - struct cvmx_l2c_dut_mapx_s cn68xx; 1125 1125 - struct cvmx_l2c_dut_mapx_s cn68xxp1; 1126 1126 - struct cvmx_l2c_dut_mapx_s cnf71xx; 1127 1127 - }; 1128 1128 - 1129 1129 - union cvmx_l2c_err_tdtx { 1130 1130 - uint64_t u64; 1131 1131 - struct cvmx_l2c_err_tdtx_s { 1132 1132 - #ifdef __BIG_ENDIAN_BITFIELD 1133 1133 - uint64_t dbe:1; 1134 1134 - uint64_t sbe:1; 1135 1135 - uint64_t vdbe:1; 1136 1136 - uint64_t vsbe:1; 1137 1137 - uint64_t syn:10; 1138 1138 - uint64_t reserved_22_49:28; 1139 1139 - uint64_t wayidx:18; 1140 1140 - uint64_t reserved_2_3:2; 1141 1141 - uint64_t type:2; 1142 1142 - #else 1143 1143 - uint64_t type:2; 1144 1144 - uint64_t reserved_2_3:2; 1145 1145 - uint64_t wayidx:18; 1146 1146 - uint64_t reserved_22_49:28; 1147 1147 - uint64_t syn:10; 1148 1148 - uint64_t vsbe:1; 1149 1149 - uint64_t vdbe:1; 1150 1150 - uint64_t sbe:1; 1151 1151 - uint64_t dbe:1; 1152 1152 - #endif 1153 1153 - } s; 1154 1154 - struct cvmx_l2c_err_tdtx_cn61xx { 1155 1155 - #ifdef __BIG_ENDIAN_BITFIELD 1156 1156 - uint64_t dbe:1; 1157 1157 - uint64_t sbe:1; 1158 1158 - uint64_t vdbe:1; 1159 1159 - uint64_t vsbe:1; 1160 1160 - uint64_t syn:10; 1161 1161 - uint64_t reserved_20_49:30; 1162 1162 - uint64_t wayidx:16; 1163 1163 - uint64_t reserved_2_3:2; 1164 1164 - uint64_t type:2; 1165 1165 - #else 1166 1166 - uint64_t type:2; 1167 1167 - uint64_t reserved_2_3:2; 1168 1168 - uint64_t wayidx:16; 1169 1169 - uint64_t reserved_20_49:30; 1170 1170 - uint64_t syn:10; 1171 1171 - uint64_t vsbe:1; 1172 1172 - uint64_t vdbe:1; 1173 1173 - uint64_t sbe:1; 1174 1174 - uint64_t dbe:1; 1175 1175 - #endif 1176 1176 - } cn61xx; 1177 1177 - struct cvmx_l2c_err_tdtx_cn63xx { 1178 1178 - #ifdef __BIG_ENDIAN_BITFIELD 1179 1179 - uint64_t dbe:1; 1180 1180 - uint64_t sbe:1; 1181 1181 - uint64_t vdbe:1; 1182 1182 - uint64_t vsbe:1; 1183 1183 - uint64_t syn:10; 1184 1184 - uint64_t reserved_21_49:29; 1185 1185 - uint64_t wayidx:17; 1186 1186 - uint64_t reserved_2_3:2; 1187 1187 - uint64_t type:2; 1188 1188 - #else 1189 1189 - uint64_t type:2; 1190 1190 - uint64_t reserved_2_3:2; 1191 1191 - uint64_t wayidx:17; 1192 1192 - uint64_t reserved_21_49:29; 1193 1193 - uint64_t syn:10; 1194 1194 - uint64_t vsbe:1; 1195 1195 - uint64_t vdbe:1; 1196 1196 - uint64_t sbe:1; 1197 1197 - uint64_t dbe:1; 1198 1198 - #endif 1199 1199 - } cn63xx; 1200 1200 - struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1; 1201 1201 - struct cvmx_l2c_err_tdtx_cn63xx cn66xx; 1202 1202 - struct cvmx_l2c_err_tdtx_s cn68xx; 1203 1203 - struct cvmx_l2c_err_tdtx_s cn68xxp1; 1204 1204 - struct cvmx_l2c_err_tdtx_cn61xx cnf71xx; 1205 1205 - }; 1206 1206 - 1207 1207 - union cvmx_l2c_err_ttgx { 1208 1208 - uint64_t u64; 1209 1209 - struct cvmx_l2c_err_ttgx_s { 1210 1210 - #ifdef __BIG_ENDIAN_BITFIELD 1211 1211 - uint64_t dbe:1; 1212 1212 - uint64_t sbe:1; 1213 1213 - uint64_t noway:1; 1214 1214 - uint64_t reserved_56_60:5; 1215 1215 - uint64_t syn:6; 1216 1216 - uint64_t reserved_22_49:28; 1217 1217 - uint64_t wayidx:15; 1218 1218 - uint64_t reserved_2_6:5; 1219 1219 - uint64_t type:2; 1220 1220 - #else 1221 1221 - uint64_t type:2; 1222 1222 - uint64_t reserved_2_6:5; 1223 1223 - uint64_t wayidx:15; 1224 1224 - uint64_t reserved_22_49:28; 1225 1225 - uint64_t syn:6; 1226 1226 - uint64_t reserved_56_60:5; 1227 1227 - uint64_t noway:1; 1228 1228 - uint64_t sbe:1; 1229 1229 - uint64_t dbe:1; 1230 1230 - #endif 1231 1231 - } s; 1232 1232 - struct cvmx_l2c_err_ttgx_cn61xx { 1233 1233 - #ifdef __BIG_ENDIAN_BITFIELD 1234 1234 - uint64_t dbe:1; 1235 1235 - uint64_t sbe:1; 1236 1236 - uint64_t noway:1; 1237 1237 - uint64_t reserved_56_60:5; 1238 1238 - uint64_t syn:6; 1239 1239 - uint64_t reserved_20_49:30; 1240 1240 - uint64_t wayidx:13; 1241 1241 - uint64_t reserved_2_6:5; 1242 1242 - uint64_t type:2; 1243 1243 - #else 1244 1244 - uint64_t type:2; 1245 1245 - uint64_t reserved_2_6:5; 1246 1246 - uint64_t wayidx:13; 1247 1247 - uint64_t reserved_20_49:30; 1248 1248 - uint64_t syn:6; 1249 1249 - uint64_t reserved_56_60:5; 1250 1250 - uint64_t noway:1; 1251 1251 - uint64_t sbe:1; 1252 1252 - uint64_t dbe:1; 1253 1253 - #endif 1254 1254 - } cn61xx; 1255 1255 - struct cvmx_l2c_err_ttgx_cn63xx { 1256 1256 - #ifdef __BIG_ENDIAN_BITFIELD 1257 1257 - uint64_t dbe:1; 1258 1258 - uint64_t sbe:1; 1259 1259 - uint64_t noway:1; 1260 1260 - uint64_t reserved_56_60:5; 1261 1261 - uint64_t syn:6; 1262 1262 - uint64_t reserved_21_49:29; 1263 1263 - uint64_t wayidx:14; 1264 1264 - uint64_t reserved_2_6:5; 1265 1265 - uint64_t type:2; 1266 1266 - #else 1267 1267 - uint64_t type:2; 1268 1268 - uint64_t reserved_2_6:5; 1269 1269 - uint64_t wayidx:14; 1270 1270 - uint64_t reserved_21_49:29; 1271 1271 - uint64_t syn:6; 1272 1272 - uint64_t reserved_56_60:5; 1273 1273 - uint64_t noway:1; 1274 1274 - uint64_t sbe:1; 1275 1275 - uint64_t dbe:1; 1276 1276 - #endif 1277 1277 - } cn63xx; 1278 1278 - struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1; 1279 1279 - struct cvmx_l2c_err_ttgx_cn63xx cn66xx; 1280 1280 - struct cvmx_l2c_err_ttgx_s cn68xx; 1281 1281 - struct cvmx_l2c_err_ttgx_s cn68xxp1; 1282 1282 - struct cvmx_l2c_err_ttgx_cn61xx cnf71xx; 1283 1283 - }; 1284 1284 - 1285 1285 - union cvmx_l2c_err_vbfx { 1286 1286 - uint64_t u64; 1287 1287 - struct cvmx_l2c_err_vbfx_s { 1288 1288 - #ifdef __BIG_ENDIAN_BITFIELD 1289 1289 - uint64_t reserved_62_63:2; 1290 1290 - uint64_t vdbe:1; 1291 1291 - uint64_t vsbe:1; 1292 1292 - uint64_t vsyn:10; 1293 1293 - uint64_t reserved_2_49:48; 1294 1294 - uint64_t type:2; 1295 1295 - #else 1296 1296 - uint64_t type:2; 1297 1297 - uint64_t reserved_2_49:48; 1298 1298 - uint64_t vsyn:10; 1299 1299 - uint64_t vsbe:1; 1300 1300 - uint64_t vdbe:1; 1301 1301 - uint64_t reserved_62_63:2; 1302 1302 - #endif 1303 1303 - } s; 1304 1304 - struct cvmx_l2c_err_vbfx_s cn61xx; 1305 1305 - struct cvmx_l2c_err_vbfx_s cn63xx; 1306 1306 - struct cvmx_l2c_err_vbfx_s cn63xxp1; 1307 1307 - struct cvmx_l2c_err_vbfx_s cn66xx; 1308 1308 - struct cvmx_l2c_err_vbfx_s cn68xx; 1309 1309 - struct cvmx_l2c_err_vbfx_s cn68xxp1; 1310 1310 - struct cvmx_l2c_err_vbfx_s cnf71xx; 1311 1311 - }; 1312 1312 - 1313 1313 - union cvmx_l2c_err_xmc { 1314 1314 - uint64_t u64; 1315 1315 - struct cvmx_l2c_err_xmc_s { 1316 1316 - #ifdef __BIG_ENDIAN_BITFIELD 1317 1317 - uint64_t cmd:6; 1318 1318 - uint64_t reserved_54_57:4; 1319 1319 - uint64_t sid:6; 1320 1320 - uint64_t reserved_38_47:10; 1321 1321 - uint64_t addr:38; 1322 1322 - #else 1323 1323 - uint64_t addr:38; 1324 1324 - uint64_t reserved_38_47:10; 1325 1325 - uint64_t sid:6; 1326 1326 - uint64_t reserved_54_57:4; 1327 1327 - uint64_t cmd:6; 1328 1328 - #endif 1329 1329 - } s; 1330 1330 - struct cvmx_l2c_err_xmc_cn61xx { 1331 1331 - #ifdef __BIG_ENDIAN_BITFIELD 1332 1332 - uint64_t cmd:6; 1333 1333 - uint64_t reserved_52_57:6; 1334 1334 - uint64_t sid:4; 1335 1335 - uint64_t reserved_38_47:10; 1336 1336 - uint64_t addr:38; 1337 1337 - #else 1338 1338 - uint64_t addr:38; 1339 1339 - uint64_t reserved_38_47:10; 1340 1340 - uint64_t sid:4; 1341 1341 - uint64_t reserved_52_57:6; 1342 1342 - uint64_t cmd:6; 1343 1343 - #endif 1344 1344 - } cn61xx; 1345 1345 - struct cvmx_l2c_err_xmc_cn61xx cn63xx; 1346 1346 - struct cvmx_l2c_err_xmc_cn61xx cn63xxp1; 1347 1347 - struct cvmx_l2c_err_xmc_cn66xx { 1348 1348 - #ifdef __BIG_ENDIAN_BITFIELD 1349 1349 - uint64_t cmd:6; 1350 1350 - uint64_t reserved_53_57:5; 1351 1351 - uint64_t sid:5; 1352 1352 - uint64_t reserved_38_47:10; 1353 1353 - uint64_t addr:38; 1354 1354 - #else 1355 1355 - uint64_t addr:38; 1356 1356 - uint64_t reserved_38_47:10; 1357 1357 - uint64_t sid:5; 1358 1358 - uint64_t reserved_53_57:5; 1359 1359 - uint64_t cmd:6; 1360 1360 - #endif 1361 1361 - } cn66xx; 1362 1362 - struct cvmx_l2c_err_xmc_s cn68xx; 1363 1363 - struct cvmx_l2c_err_xmc_s cn68xxp1; 1364 1364 - struct cvmx_l2c_err_xmc_cn61xx cnf71xx; 1365 1365 - }; 1366 1366 - 1367 1367 - union cvmx_l2c_grpwrr0 { 1368 1368 - uint64_t u64; 1369 1369 - struct cvmx_l2c_grpwrr0_s { 1370 1370 - #ifdef __BIG_ENDIAN_BITFIELD 1371 1371 - uint64_t plc1rmsk:32; 1372 1372 - uint64_t plc0rmsk:32; 1373 1373 - #else 1374 1374 - uint64_t plc0rmsk:32; 1375 1375 - uint64_t plc1rmsk:32; 1376 1376 - #endif 1377 1377 - } s; 1378 1378 - struct cvmx_l2c_grpwrr0_s cn52xx; 1379 1379 - struct cvmx_l2c_grpwrr0_s cn52xxp1; 1380 1380 - struct cvmx_l2c_grpwrr0_s cn56xx; 1381 1381 - struct cvmx_l2c_grpwrr0_s cn56xxp1; 1382 1382 - }; 1383 1383 - 1384 1384 - union cvmx_l2c_grpwrr1 { 1385 1385 - uint64_t u64; 1386 1386 - struct cvmx_l2c_grpwrr1_s { 1387 1387 - #ifdef __BIG_ENDIAN_BITFIELD 1388 1388 - uint64_t ilcrmsk:32; 1389 1389 - uint64_t plc2rmsk:32; 1390 1390 - #else 1391 1391 - uint64_t plc2rmsk:32; 1392 1392 - uint64_t ilcrmsk:32; 1393 1393 - #endif 1394 1394 - } s; 1395 1395 - struct cvmx_l2c_grpwrr1_s cn52xx; 1396 1396 - struct cvmx_l2c_grpwrr1_s cn52xxp1; 1397 1397 - struct cvmx_l2c_grpwrr1_s cn56xx; 1398 1398 - struct cvmx_l2c_grpwrr1_s cn56xxp1; 1399 1399 - }; 1400 1400 - 1401 1401 - union cvmx_l2c_int_en { 1402 1402 - uint64_t u64; 1403 1403 - struct cvmx_l2c_int_en_s { 1404 1404 - #ifdef __BIG_ENDIAN_BITFIELD 1405 1405 - uint64_t reserved_9_63:55; 1406 1406 - uint64_t lck2ena:1; 1407 1407 - uint64_t lckena:1; 1408 1408 - uint64_t l2ddeden:1; 1409 1409 - uint64_t l2dsecen:1; 1410 1410 - uint64_t l2tdeden:1; 1411 1411 - uint64_t l2tsecen:1; 1412 1412 - uint64_t oob3en:1; 1413 1413 - uint64_t oob2en:1; 1414 1414 - uint64_t oob1en:1; 1415 1415 - #else 1416 1416 - uint64_t oob1en:1; 1417 1417 - uint64_t oob2en:1; 1418 1418 - uint64_t oob3en:1; 1419 1419 - uint64_t l2tsecen:1; 1420 1420 - uint64_t l2tdeden:1; 1421 1421 - uint64_t l2dsecen:1; 1422 1422 - uint64_t l2ddeden:1; 1423 1423 - uint64_t lckena:1; 1424 1424 - uint64_t lck2ena:1; 1425 1425 - uint64_t reserved_9_63:55; 1426 1426 - #endif 1427 1427 - } s; 1428 1428 - struct cvmx_l2c_int_en_s cn52xx; 1429 1429 - struct cvmx_l2c_int_en_s cn52xxp1; 1430 1430 - struct cvmx_l2c_int_en_s cn56xx; 1431 1431 - struct cvmx_l2c_int_en_s cn56xxp1; 1432 1432 - }; 1433 1433 - 1434 1434 - union cvmx_l2c_int_ena { 1435 1435 - uint64_t u64; 1436 1436 - struct cvmx_l2c_int_ena_s { 1437 1437 - #ifdef __BIG_ENDIAN_BITFIELD 1438 1438 - uint64_t reserved_8_63:56; 1439 1439 - uint64_t bigrd:1; 1440 1440 - uint64_t bigwr:1; 1441 1441 - uint64_t vrtpe:1; 1442 1442 - uint64_t vrtadrng:1; 1443 1443 - uint64_t vrtidrng:1; 1444 1444 - uint64_t vrtwr:1; 1445 1445 - uint64_t holewr:1; 1446 1446 - uint64_t holerd:1; 1447 1447 - #else 1448 1448 - uint64_t holerd:1; 1449 1449 - uint64_t holewr:1; 1450 1450 - uint64_t vrtwr:1; 1451 1451 - uint64_t vrtidrng:1; 1452 1452 - uint64_t vrtadrng:1; 1453 1453 - uint64_t vrtpe:1; 1454 1454 - uint64_t bigwr:1; 1455 1455 - uint64_t bigrd:1; 1456 1456 - uint64_t reserved_8_63:56; 1457 1457 - #endif 1458 1458 - } s; 1459 1459 - struct cvmx_l2c_int_ena_s cn61xx; 1460 1460 - struct cvmx_l2c_int_ena_s cn63xx; 1461 1461 - struct cvmx_l2c_int_ena_cn63xxp1 { 1462 1462 - #ifdef __BIG_ENDIAN_BITFIELD 1463 1463 - uint64_t reserved_6_63:58; 1464 1464 - uint64_t vrtpe:1; 1465 1465 - uint64_t vrtadrng:1; 1466 1466 - uint64_t vrtidrng:1; 1467 1467 - uint64_t vrtwr:1; 1468 1468 - uint64_t holewr:1; 1469 1469 - uint64_t holerd:1; 1470 1470 - #else 1471 1471 - uint64_t holerd:1; 1472 1472 - uint64_t holewr:1; 1473 1473 - uint64_t vrtwr:1; 1474 1474 - uint64_t vrtidrng:1; 1475 1475 - uint64_t vrtadrng:1; 1476 1476 - uint64_t vrtpe:1; 1477 1477 - uint64_t reserved_6_63:58; 1478 1478 - #endif 1479 1479 - } cn63xxp1; 1480 1480 - struct cvmx_l2c_int_ena_s cn66xx; 1481 1481 - struct cvmx_l2c_int_ena_s cn68xx; 1482 1482 - struct cvmx_l2c_int_ena_s cn68xxp1; 1483 1483 - struct cvmx_l2c_int_ena_s cnf71xx; 1484 1484 - }; 1485 1485 - 1486 1486 - union cvmx_l2c_int_reg { 1487 1487 - uint64_t u64; 1488 1488 - struct cvmx_l2c_int_reg_s { 1489 1489 - #ifdef __BIG_ENDIAN_BITFIELD 1490 1490 - uint64_t reserved_20_63:44; 1491 1491 - uint64_t tad3:1; 1492 1492 - uint64_t tad2:1; 1493 1493 - uint64_t tad1:1; 1494 1494 - uint64_t tad0:1; 1495 1495 - uint64_t reserved_8_15:8; 1496 1496 - uint64_t bigrd:1; 1497 1497 - uint64_t bigwr:1; 1498 1498 - uint64_t vrtpe:1; 1499 1499 - uint64_t vrtadrng:1; 1500 1500 - uint64_t vrtidrng:1; 1501 1501 - uint64_t vrtwr:1; 1502 1502 - uint64_t holewr:1; 1503 1503 - uint64_t holerd:1; 1504 1504 - #else 1505 1505 - uint64_t holerd:1; 1506 1506 - uint64_t holewr:1; 1507 1507 - uint64_t vrtwr:1; 1508 1508 - uint64_t vrtidrng:1; 1509 1509 - uint64_t vrtadrng:1; 1510 1510 - uint64_t vrtpe:1; 1511 1511 - uint64_t bigwr:1; 1512 1512 - uint64_t bigrd:1; 1513 1513 - uint64_t reserved_8_15:8; 1514 1514 - uint64_t tad0:1; 1515 1515 - uint64_t tad1:1; 1516 1516 - uint64_t tad2:1; 1517 1517 - uint64_t tad3:1; 1518 1518 - uint64_t reserved_20_63:44; 1519 1519 - #endif 1520 1520 - } s; 1521 1521 - struct cvmx_l2c_int_reg_cn61xx { 1522 1522 - #ifdef __BIG_ENDIAN_BITFIELD 1523 1523 - uint64_t reserved_17_63:47; 1524 1524 - uint64_t tad0:1; 1525 1525 - uint64_t reserved_8_15:8; 1526 1526 - uint64_t bigrd:1; 1527 1527 - uint64_t bigwr:1; 1528 1528 - uint64_t vrtpe:1; 1529 1529 - uint64_t vrtadrng:1; 1530 1530 - uint64_t vrtidrng:1; 1531 1531 - uint64_t vrtwr:1; 1532 1532 - uint64_t holewr:1; 1533 1533 - uint64_t holerd:1; 1534 1534 - #else 1535 1535 - uint64_t holerd:1; 1536 1536 - uint64_t holewr:1; 1537 1537 - uint64_t vrtwr:1; 1538 1538 - uint64_t vrtidrng:1; 1539 1539 - uint64_t vrtadrng:1; 1540 1540 - uint64_t vrtpe:1; 1541 1541 - uint64_t bigwr:1; 1542 1542 - uint64_t bigrd:1; 1543 1543 - uint64_t reserved_8_15:8; 1544 1544 - uint64_t tad0:1; 1545 1545 - uint64_t reserved_17_63:47; 1546 1546 - #endif 1547 1547 - } cn61xx; 1548 1548 - struct cvmx_l2c_int_reg_cn61xx cn63xx; 1549 1549 - struct cvmx_l2c_int_reg_cn63xxp1 { 1550 1550 - #ifdef __BIG_ENDIAN_BITFIELD 1551 1551 - uint64_t reserved_17_63:47; 1552 1552 - uint64_t tad0:1; 1553 1553 - uint64_t reserved_6_15:10; 1554 1554 - uint64_t vrtpe:1; 1555 1555 - uint64_t vrtadrng:1; 1556 1556 - uint64_t vrtidrng:1; 1557 1557 - uint64_t vrtwr:1; 1558 1558 - uint64_t holewr:1; 1559 1559 - uint64_t holerd:1; 1560 1560 - #else 1561 1561 - uint64_t holerd:1; 1562 1562 - uint64_t holewr:1; 1563 1563 - uint64_t vrtwr:1; 1564 1564 - uint64_t vrtidrng:1; 1565 1565 - uint64_t vrtadrng:1; 1566 1566 - uint64_t vrtpe:1; 1567 1567 - uint64_t reserved_6_15:10; 1568 1568 - uint64_t tad0:1; 1569 1569 - uint64_t reserved_17_63:47; 1570 1570 - #endif 1571 1571 - } cn63xxp1; 1572 1572 - struct cvmx_l2c_int_reg_cn61xx cn66xx; 1573 1573 - struct cvmx_l2c_int_reg_s cn68xx; 1574 1574 - struct cvmx_l2c_int_reg_s cn68xxp1; 1575 1575 - struct cvmx_l2c_int_reg_cn61xx cnf71xx; 1576 1576 - }; 1577 1577 - 1578 1578 - union cvmx_l2c_int_stat { 1579 1579 - uint64_t u64; 1580 1580 - struct cvmx_l2c_int_stat_s { 1581 1581 - #ifdef __BIG_ENDIAN_BITFIELD 1582 1582 - uint64_t reserved_9_63:55; 1583 1583 - uint64_t lck2:1; 1584 1584 - uint64_t lck:1; 1585 1585 - uint64_t l2dded:1; 1586 1586 - uint64_t l2dsec:1; 1587 1587 - uint64_t l2tded:1; 1588 1588 - uint64_t l2tsec:1; 1589 1589 - uint64_t oob3:1; 1590 1590 - uint64_t oob2:1; 1591 1591 - uint64_t oob1:1; 1592 1592 - #else 1593 1593 - uint64_t oob1:1; 1594 1594 - uint64_t oob2:1; 1595 1595 - uint64_t oob3:1; 1596 1596 - uint64_t l2tsec:1; 1597 1597 - uint64_t l2tded:1; 1598 1598 - uint64_t l2dsec:1; 1599 1599 - uint64_t l2dded:1; 1600 1600 - uint64_t lck:1; 1601 1601 - uint64_t lck2:1; 1602 1602 - uint64_t reserved_9_63:55; 1603 1603 - #endif 1604 1604 - } s; 1605 1605 - struct cvmx_l2c_int_stat_s cn52xx; 1606 1606 - struct cvmx_l2c_int_stat_s cn52xxp1; 1607 1607 - struct cvmx_l2c_int_stat_s cn56xx; 1608 1608 - struct cvmx_l2c_int_stat_s cn56xxp1; 1609 1609 - }; 1610 1610 - 1611 1611 - union cvmx_l2c_iocx_pfc { 1612 1612 - uint64_t u64; 1613 1613 - struct cvmx_l2c_iocx_pfc_s { 1614 1614 - #ifdef __BIG_ENDIAN_BITFIELD 1615 1615 - uint64_t count:64; 1616 1616 - #else 1617 1617 - uint64_t count:64; 1618 1618 - #endif 1619 1619 - } s; 1620 1620 - struct cvmx_l2c_iocx_pfc_s cn61xx; 1621 1621 - struct cvmx_l2c_iocx_pfc_s cn63xx; 1622 1622 - struct cvmx_l2c_iocx_pfc_s cn63xxp1; 1623 1623 - struct cvmx_l2c_iocx_pfc_s cn66xx; 1624 1624 - struct cvmx_l2c_iocx_pfc_s cn68xx; 1625 1625 - struct cvmx_l2c_iocx_pfc_s cn68xxp1; 1626 1626 - struct cvmx_l2c_iocx_pfc_s cnf71xx; 1627 1627 - }; 1628 1628 - 1629 1629 - union cvmx_l2c_iorx_pfc { 1630 1630 - uint64_t u64; 1631 1631 - struct cvmx_l2c_iorx_pfc_s { 1632 1632 - #ifdef __BIG_ENDIAN_BITFIELD 1633 1633 - uint64_t count:64; 1634 1634 - #else 1635 1635 - uint64_t count:64; 1636 1636 - #endif 1637 1637 - } s; 1638 1638 - struct cvmx_l2c_iorx_pfc_s cn61xx; 1639 1639 - struct cvmx_l2c_iorx_pfc_s cn63xx; 1640 1640 - struct cvmx_l2c_iorx_pfc_s cn63xxp1; 1641 1641 - struct cvmx_l2c_iorx_pfc_s cn66xx; 1642 1642 - struct cvmx_l2c_iorx_pfc_s cn68xx; 1643 1643 - struct cvmx_l2c_iorx_pfc_s cn68xxp1; 1644 1644 - struct cvmx_l2c_iorx_pfc_s cnf71xx; 1645 1645 - }; 1646 1646 - 1647 1647 - union cvmx_l2c_lckbase { 1648 1648 - uint64_t u64; 1649 1649 - struct cvmx_l2c_lckbase_s { 1650 1650 - #ifdef __BIG_ENDIAN_BITFIELD 1651 1651 - uint64_t reserved_31_63:33; 1652 1652 - uint64_t lck_base:27; 1653 1653 - uint64_t reserved_1_3:3; 1654 1654 - uint64_t lck_ena:1; 1655 1655 - #else 1656 1656 - uint64_t lck_ena:1; 1657 1657 - uint64_t reserved_1_3:3; 1658 1658 - uint64_t lck_base:27; 1659 1659 - uint64_t reserved_31_63:33; 1660 1660 - #endif 1661 1661 - } s; 1662 1662 - struct cvmx_l2c_lckbase_s cn30xx; 1663 1663 - struct cvmx_l2c_lckbase_s cn31xx; 1664 1664 - struct cvmx_l2c_lckbase_s cn38xx; 1665 1665 - struct cvmx_l2c_lckbase_s cn38xxp2; 1666 1666 - struct cvmx_l2c_lckbase_s cn50xx; 1667 1667 - struct cvmx_l2c_lckbase_s cn52xx; 1668 1668 - struct cvmx_l2c_lckbase_s cn52xxp1; 1669 1669 - struct cvmx_l2c_lckbase_s cn56xx; 1670 1670 - struct cvmx_l2c_lckbase_s cn56xxp1; 1671 1671 - struct cvmx_l2c_lckbase_s cn58xx; 1672 1672 - struct cvmx_l2c_lckbase_s cn58xxp1; 1673 1673 - }; 1674 1674 - 1675 1675 - union cvmx_l2c_lckoff { 1676 1676 - uint64_t u64; 1677 1677 - struct cvmx_l2c_lckoff_s { 1678 1678 - #ifdef __BIG_ENDIAN_BITFIELD 1679 1679 - uint64_t reserved_10_63:54; 1680 1680 - uint64_t lck_offset:10; 1681 1681 - #else 1682 1682 - uint64_t lck_offset:10; 1683 1683 - uint64_t reserved_10_63:54; 1684 1684 - #endif 1685 1685 - } s; 1686 1686 - struct cvmx_l2c_lckoff_s cn30xx; 1687 1687 - struct cvmx_l2c_lckoff_s cn31xx; 1688 1688 - struct cvmx_l2c_lckoff_s cn38xx; 1689 1689 - struct cvmx_l2c_lckoff_s cn38xxp2; 1690 1690 - struct cvmx_l2c_lckoff_s cn50xx; 1691 1691 - struct cvmx_l2c_lckoff_s cn52xx; 1692 1692 - struct cvmx_l2c_lckoff_s cn52xxp1; 1693 1693 - struct cvmx_l2c_lckoff_s cn56xx; 1694 1694 - struct cvmx_l2c_lckoff_s cn56xxp1; 1695 1695 - struct cvmx_l2c_lckoff_s cn58xx; 1696 1696 - struct cvmx_l2c_lckoff_s cn58xxp1; 1697 1697 - }; 1698 1698 - 1699 1699 - union cvmx_l2c_lfb0 { 1700 1700 - uint64_t u64; 1701 1701 - struct cvmx_l2c_lfb0_s { 1702 1702 - #ifdef __BIG_ENDIAN_BITFIELD 1703 1703 - uint64_t reserved_32_63:32; 1704 1704 - uint64_t stcpnd:1; 1705 1705 - uint64_t stpnd:1; 1706 1706 - uint64_t stinv:1; 1707 1707 - uint64_t stcfl:1; 1708 1708 - uint64_t vam:1; 1709 1709 - uint64_t inxt:4; 1710 1710 - uint64_t itl:1; 1711 1711 - uint64_t ihd:1; 1712 1712 - uint64_t set:3; 1713 1713 - uint64_t vabnum:4; 1714 1714 - uint64_t sid:9; 1715 1715 - uint64_t cmd:4; 1716 1716 - uint64_t vld:1; 1717 1717 - #else 1718 1718 - uint64_t vld:1; 1719 1719 - uint64_t cmd:4; 1720 1720 - uint64_t sid:9; 1721 1721 - uint64_t vabnum:4; 1722 1722 - uint64_t set:3; 1723 1723 - uint64_t ihd:1; 1724 1724 - uint64_t itl:1; 1725 1725 - uint64_t inxt:4; 1726 1726 - uint64_t vam:1; 1727 1727 - uint64_t stcfl:1; 1728 1728 - uint64_t stinv:1; 1729 1729 - uint64_t stpnd:1; 1730 1730 - uint64_t stcpnd:1; 1731 1731 - uint64_t reserved_32_63:32; 1732 1732 - #endif 1733 1733 - } s; 1734 1734 - struct cvmx_l2c_lfb0_cn30xx { 1735 1735 - #ifdef __BIG_ENDIAN_BITFIELD 1736 1736 - uint64_t reserved_32_63:32; 1737 1737 - uint64_t stcpnd:1; 1738 1738 - uint64_t stpnd:1; 1739 1739 - uint64_t stinv:1; 1740 1740 - uint64_t stcfl:1; 1741 1741 - uint64_t vam:1; 1742 1742 - uint64_t reserved_25_26:2; 1743 1743 - uint64_t inxt:2; 1744 1744 - uint64_t itl:1; 1745 1745 - uint64_t ihd:1; 1746 1746 - uint64_t reserved_20_20:1; 1747 1747 - uint64_t set:2; 1748 1748 - uint64_t reserved_16_17:2; 1749 1749 - uint64_t vabnum:2; 1750 1750 - uint64_t sid:9; 1751 1751 - uint64_t cmd:4; 1752 1752 - uint64_t vld:1; 1753 1753 - #else 1754 1754 - uint64_t vld:1; 1755 1755 - uint64_t cmd:4; 1756 1756 - uint64_t sid:9; 1757 1757 - uint64_t vabnum:2; 1758 1758 - uint64_t reserved_16_17:2; 1759 1759 - uint64_t set:2; 1760 1760 - uint64_t reserved_20_20:1; 1761 1761 - uint64_t ihd:1; 1762 1762 - uint64_t itl:1; 1763 1763 - uint64_t inxt:2; 1764 1764 - uint64_t reserved_25_26:2; 1765 1765 - uint64_t vam:1; 1766 1766 - uint64_t stcfl:1; 1767 1767 - uint64_t stinv:1; 1768 1768 - uint64_t stpnd:1; 1769 1769 - uint64_t stcpnd:1; 1770 1770 - uint64_t reserved_32_63:32; 1771 1771 - #endif 1772 1772 - } cn30xx; 1773 1773 - struct cvmx_l2c_lfb0_cn31xx { 1774 1774 - #ifdef __BIG_ENDIAN_BITFIELD 1775 1775 - uint64_t reserved_32_63:32; 1776 1776 - uint64_t stcpnd:1; 1777 1777 - uint64_t stpnd:1; 1778 1778 - uint64_t stinv:1; 1779 1779 - uint64_t stcfl:1; 1780 1780 - uint64_t vam:1; 1781 1781 - uint64_t reserved_26_26:1; 1782 1782 - uint64_t inxt:3; 1783 1783 - uint64_t itl:1; 1784 1784 - uint64_t ihd:1; 1785 1785 - uint64_t reserved_20_20:1; 1786 1786 - uint64_t set:2; 1787 1787 - uint64_t reserved_17_17:1; 1788 1788 - uint64_t vabnum:3; 1789 1789 - uint64_t sid:9; 1790 1790 - uint64_t cmd:4; 1791 1791 - uint64_t vld:1; 1792 1792 - #else 1793 1793 - uint64_t vld:1; 1794 1794 - uint64_t cmd:4; 1795 1795 - uint64_t sid:9; 1796 1796 - uint64_t vabnum:3; 1797 1797 - uint64_t reserved_17_17:1; 1798 1798 - uint64_t set:2; 1799 1799 - uint64_t reserved_20_20:1; 1800 1800 - uint64_t ihd:1; 1801 1801 - uint64_t itl:1; 1802 1802 - uint64_t inxt:3; 1803 1803 - uint64_t reserved_26_26:1; 1804 1804 - uint64_t vam:1; 1805 1805 - uint64_t stcfl:1; 1806 1806 - uint64_t stinv:1; 1807 1807 - uint64_t stpnd:1; 1808 1808 - uint64_t stcpnd:1; 1809 1809 - uint64_t reserved_32_63:32; 1810 1810 - #endif 1811 1811 - } cn31xx; 1812 1812 - struct cvmx_l2c_lfb0_s cn38xx; 1813 1813 - struct cvmx_l2c_lfb0_s cn38xxp2; 1814 1814 - struct cvmx_l2c_lfb0_cn50xx { 1815 1815 - #ifdef __BIG_ENDIAN_BITFIELD 1816 1816 - uint64_t reserved_32_63:32; 1817 1817 - uint64_t stcpnd:1; 1818 1818 - uint64_t stpnd:1; 1819 1819 - uint64_t stinv:1; 1820 1820 - uint64_t stcfl:1; 1821 1821 - uint64_t vam:1; 1822 1822 - uint64_t reserved_26_26:1; 1823 1823 - uint64_t inxt:3; 1824 1824 - uint64_t itl:1; 1825 1825 - uint64_t ihd:1; 1826 1826 - uint64_t set:3; 1827 1827 - uint64_t reserved_17_17:1; 1828 1828 - uint64_t vabnum:3; 1829 1829 - uint64_t sid:9; 1830 1830 - uint64_t cmd:4; 1831 1831 - uint64_t vld:1; 1832 1832 - #else 1833 1833 - uint64_t vld:1; 1834 1834 - uint64_t cmd:4; 1835 1835 - uint64_t sid:9; 1836 1836 - uint64_t vabnum:3; 1837 1837 - uint64_t reserved_17_17:1; 1838 1838 - uint64_t set:3; 1839 1839 - uint64_t ihd:1; 1840 1840 - uint64_t itl:1; 1841 1841 - uint64_t inxt:3; 1842 1842 - uint64_t reserved_26_26:1; 1843 1843 - uint64_t vam:1; 1844 1844 - uint64_t stcfl:1; 1845 1845 - uint64_t stinv:1; 1846 1846 - uint64_t stpnd:1; 1847 1847 - uint64_t stcpnd:1; 1848 1848 - uint64_t reserved_32_63:32; 1849 1849 - #endif 1850 1850 - } cn50xx; 1851 1851 - struct cvmx_l2c_lfb0_cn50xx cn52xx; 1852 1852 - struct cvmx_l2c_lfb0_cn50xx cn52xxp1; 1853 1853 - struct cvmx_l2c_lfb0_s cn56xx; 1854 1854 - struct cvmx_l2c_lfb0_s cn56xxp1; 1855 1855 - struct cvmx_l2c_lfb0_s cn58xx; 1856 1856 - struct cvmx_l2c_lfb0_s cn58xxp1; 1857 1857 - }; 1858 1858 - 1859 1859 - union cvmx_l2c_lfb1 { 1860 1860 - uint64_t u64; 1861 1861 - struct cvmx_l2c_lfb1_s { 1862 1862 - #ifdef __BIG_ENDIAN_BITFIELD 1863 1863 - uint64_t reserved_19_63:45; 1864 1864 - uint64_t dsgoing:1; 1865 1865 - uint64_t bid:2; 1866 1866 - uint64_t wtrsp:1; 1867 1867 - uint64_t wtdw:1; 1868 1868 - uint64_t wtdq:1; 1869 1869 - uint64_t wtwhp:1; 1870 1870 - uint64_t wtwhf:1; 1871 1871 - uint64_t wtwrm:1; 1872 1872 - uint64_t wtstm:1; 1873 1873 - uint64_t wtrda:1; 1874 1874 - uint64_t wtstdt:1; 1875 1875 - uint64_t wtstrsp:1; 1876 1876 - uint64_t wtstrsc:1; 1877 1877 - uint64_t wtvtm:1; 1878 1878 - uint64_t wtmfl:1; 1879 1879 - uint64_t prbrty:1; 1880 1880 - uint64_t wtprb:1; 1881 1881 - uint64_t vld:1; 1882 1882 - #else 1883 1883 - uint64_t vld:1; 1884 1884 - uint64_t wtprb:1; 1885 1885 - uint64_t prbrty:1; 1886 1886 - uint64_t wtmfl:1; 1887 1887 - uint64_t wtvtm:1; 1888 1888 - uint64_t wtstrsc:1; 1889 1889 - uint64_t wtstrsp:1; 1890 1890 - uint64_t wtstdt:1; 1891 1891 - uint64_t wtrda:1; 1892 1892 - uint64_t wtstm:1; 1893 1893 - uint64_t wtwrm:1; 1894 1894 - uint64_t wtwhf:1; 1895 1895 - uint64_t wtwhp:1; 1896 1896 - uint64_t wtdq:1; 1897 1897 - uint64_t wtdw:1; 1898 1898 - uint64_t wtrsp:1; 1899 1899 - uint64_t bid:2; 1900 1900 - uint64_t dsgoing:1; 1901 1901 - uint64_t reserved_19_63:45; 1902 1902 - #endif 1903 1903 - } s; 1904 1904 - struct cvmx_l2c_lfb1_s cn30xx; 1905 1905 - struct cvmx_l2c_lfb1_s cn31xx; 1906 1906 - struct cvmx_l2c_lfb1_s cn38xx; 1907 1907 - struct cvmx_l2c_lfb1_s cn38xxp2; 1908 1908 - struct cvmx_l2c_lfb1_s cn50xx; 1909 1909 - struct cvmx_l2c_lfb1_s cn52xx; 1910 1910 - struct cvmx_l2c_lfb1_s cn52xxp1; 1911 1911 - struct cvmx_l2c_lfb1_s cn56xx; 1912 1912 - struct cvmx_l2c_lfb1_s cn56xxp1; 1913 1913 - struct cvmx_l2c_lfb1_s cn58xx; 1914 1914 - struct cvmx_l2c_lfb1_s cn58xxp1; 1915 1915 - }; 1916 1916 - 1917 1917 - union cvmx_l2c_lfb2 { 1918 1918 - uint64_t u64; 1919 1919 - struct cvmx_l2c_lfb2_s { 1920 1920 - #ifdef __BIG_ENDIAN_BITFIELD 1921 1921 - uint64_t reserved_0_63:64; 1922 1922 - #else 1923 1923 - uint64_t reserved_0_63:64; 1924 1924 - #endif 1925 1925 - } s; 1926 1926 - struct cvmx_l2c_lfb2_cn30xx { 1927 1927 - #ifdef __BIG_ENDIAN_BITFIELD 1928 1928 - uint64_t reserved_27_63:37; 1929 1929 - uint64_t lfb_tag:19; 1930 1930 - uint64_t lfb_idx:8; 1931 1931 - #else 1932 1932 - uint64_t lfb_idx:8; 1933 1933 - uint64_t lfb_tag:19; 1934 1934 - uint64_t reserved_27_63:37; 1935 1935 - #endif 1936 1936 - } cn30xx; 1937 1937 - struct cvmx_l2c_lfb2_cn31xx { 1938 1938 - #ifdef __BIG_ENDIAN_BITFIELD 1939 1939 - uint64_t reserved_27_63:37; 1940 1940 - uint64_t lfb_tag:17; 1941 1941 - uint64_t lfb_idx:10; 1942 1942 - #else 1943 1943 - uint64_t lfb_idx:10; 1944 1944 - uint64_t lfb_tag:17; 1945 1945 - uint64_t reserved_27_63:37; 1946 1946 - #endif 1947 1947 - } cn31xx; 1948 1948 - struct cvmx_l2c_lfb2_cn31xx cn38xx; 1949 1949 - struct cvmx_l2c_lfb2_cn31xx cn38xxp2; 1950 1950 - struct cvmx_l2c_lfb2_cn50xx { 1951 1951 - #ifdef __BIG_ENDIAN_BITFIELD 1952 1952 - uint64_t reserved_27_63:37; 1953 1953 - uint64_t lfb_tag:20; 1954 1954 - uint64_t lfb_idx:7; 1955 1955 - #else 1956 1956 - uint64_t lfb_idx:7; 1957 1957 - uint64_t lfb_tag:20; 1958 1958 - uint64_t reserved_27_63:37; 1959 1959 - #endif 1960 1960 - } cn50xx; 1961 1961 - struct cvmx_l2c_lfb2_cn52xx { 1962 1962 - #ifdef __BIG_ENDIAN_BITFIELD 1963 1963 - uint64_t reserved_27_63:37; 1964 1964 - uint64_t lfb_tag:18; 1965 1965 - uint64_t lfb_idx:9; 1966 1966 - #else 1967 1967 - uint64_t lfb_idx:9; 1968 1968 - uint64_t lfb_tag:18; 1969 1969 - uint64_t reserved_27_63:37; 1970 1970 - #endif 1971 1971 - } cn52xx; 1972 1972 - struct cvmx_l2c_lfb2_cn52xx cn52xxp1; 1973 1973 - struct cvmx_l2c_lfb2_cn56xx { 1974 1974 - #ifdef __BIG_ENDIAN_BITFIELD 1975 1975 - uint64_t reserved_27_63:37; 1976 1976 - uint64_t lfb_tag:16; 1977 1977 - uint64_t lfb_idx:11; 1978 1978 - #else 1979 1979 - uint64_t lfb_idx:11; 1980 1980 - uint64_t lfb_tag:16; 1981 1981 - uint64_t reserved_27_63:37; 1982 1982 - #endif 1983 1983 - } cn56xx; 1984 1984 - struct cvmx_l2c_lfb2_cn56xx cn56xxp1; 1985 1985 - struct cvmx_l2c_lfb2_cn56xx cn58xx; 1986 1986 - struct cvmx_l2c_lfb2_cn56xx cn58xxp1; 1987 1987 - }; 1988 1988 - 1989 1989 - union cvmx_l2c_lfb3 { 1990 1990 - uint64_t u64; 1991 1991 - struct cvmx_l2c_lfb3_s { 1992 1992 - #ifdef __BIG_ENDIAN_BITFIELD 1993 1993 - uint64_t reserved_5_63:59; 1994 1994 - uint64_t stpartdis:1; 1995 1995 - uint64_t lfb_hwm:4; 1996 1996 - #else 1997 1997 - uint64_t lfb_hwm:4; 1998 1998 - uint64_t stpartdis:1; 1999 1999 - uint64_t reserved_5_63:59; 2000 2000 - #endif 2001 2001 - } s; 2002 2002 - struct cvmx_l2c_lfb3_cn30xx { 2003 2003 - #ifdef __BIG_ENDIAN_BITFIELD 2004 2004 - uint64_t reserved_5_63:59; 2005 2005 - uint64_t stpartdis:1; 2006 2006 - uint64_t reserved_2_3:2; 2007 2007 - uint64_t lfb_hwm:2; 2008 2008 - #else 2009 2009 - uint64_t lfb_hwm:2; 2010 2010 - uint64_t reserved_2_3:2; 2011 2011 - uint64_t stpartdis:1; 2012 2012 - uint64_t reserved_5_63:59; 2013 2013 - #endif 2014 2014 - } cn30xx; 2015 2015 - struct cvmx_l2c_lfb3_cn31xx { 2016 2016 - #ifdef __BIG_ENDIAN_BITFIELD 2017 2017 - uint64_t reserved_5_63:59; 2018 2018 - uint64_t stpartdis:1; 2019 2019 - uint64_t reserved_3_3:1; 2020 2020 - uint64_t lfb_hwm:3; 2021 2021 - #else 2022 2022 - uint64_t lfb_hwm:3; 2023 2023 - uint64_t reserved_3_3:1; 2024 2024 - uint64_t stpartdis:1; 2025 2025 - uint64_t reserved_5_63:59; 2026 2026 - #endif 2027 2027 - } cn31xx; 2028 2028 - struct cvmx_l2c_lfb3_s cn38xx; 2029 2029 - struct cvmx_l2c_lfb3_s cn38xxp2; 2030 2030 - struct cvmx_l2c_lfb3_cn31xx cn50xx; 2031 2031 - struct cvmx_l2c_lfb3_cn31xx cn52xx; 2032 2032 - struct cvmx_l2c_lfb3_cn31xx cn52xxp1; 2033 2033 - struct cvmx_l2c_lfb3_s cn56xx; 2034 2034 - struct cvmx_l2c_lfb3_s cn56xxp1; 2035 2035 - struct cvmx_l2c_lfb3_s cn58xx; 2036 2036 - struct cvmx_l2c_lfb3_s cn58xxp1; 2037 2037 - }; 2038 2038 - 2039 2039 - union cvmx_l2c_oob { 2040 2040 - uint64_t u64; 2041 2041 - struct cvmx_l2c_oob_s { 2042 2042 - #ifdef __BIG_ENDIAN_BITFIELD 2043 2043 - uint64_t reserved_2_63:62; 2044 2044 - uint64_t dwbena:1; 2045 2045 - uint64_t stena:1; 2046 2046 - #else 2047 2047 - uint64_t stena:1; 2048 2048 - uint64_t dwbena:1; 2049 2049 - uint64_t reserved_2_63:62; 2050 2050 - #endif 2051 2051 - } s; 2052 2052 - struct cvmx_l2c_oob_s cn52xx; 2053 2053 - struct cvmx_l2c_oob_s cn52xxp1; 2054 2054 - struct cvmx_l2c_oob_s cn56xx; 2055 2055 - struct cvmx_l2c_oob_s cn56xxp1; 2056 2056 - }; 2057 2057 - 2058 2058 - union cvmx_l2c_oob1 { 2059 2059 - uint64_t u64; 2060 2060 - struct cvmx_l2c_oob1_s { 2061 2061 - #ifdef __BIG_ENDIAN_BITFIELD 2062 2062 - uint64_t fadr:27; 2063 2063 - uint64_t fsrc:1; 2064 2064 - uint64_t reserved_34_35:2; 2065 2065 - uint64_t sadr:14; 2066 2066 - uint64_t reserved_14_19:6; 2067 2067 - uint64_t size:14; 2068 2068 - #else 2069 2069 - uint64_t size:14; 2070 2070 - uint64_t reserved_14_19:6; 2071 2071 - uint64_t sadr:14; 2072 2072 - uint64_t reserved_34_35:2; 2073 2073 - uint64_t fsrc:1; 2074 2074 - uint64_t fadr:27; 2075 2075 - #endif 2076 2076 - } s; 2077 2077 - struct cvmx_l2c_oob1_s cn52xx; 2078 2078 - struct cvmx_l2c_oob1_s cn52xxp1; 2079 2079 - struct cvmx_l2c_oob1_s cn56xx; 2080 2080 - struct cvmx_l2c_oob1_s cn56xxp1; 2081 2081 - }; 2082 2082 - 2083 2083 - union cvmx_l2c_oob2 { 2084 2084 - uint64_t u64; 2085 2085 - struct cvmx_l2c_oob2_s { 2086 2086 - #ifdef __BIG_ENDIAN_BITFIELD 2087 2087 - uint64_t fadr:27; 2088 2088 - uint64_t fsrc:1; 2089 2089 - uint64_t reserved_34_35:2; 2090 2090 - uint64_t sadr:14; 2091 2091 - uint64_t reserved_14_19:6; 2092 2092 - uint64_t size:14; 2093 2093 - #else 2094 2094 - uint64_t size:14; 2095 2095 - uint64_t reserved_14_19:6; 2096 2096 - uint64_t sadr:14; 2097 2097 - uint64_t reserved_34_35:2; 2098 2098 - uint64_t fsrc:1; 2099 2099 - uint64_t fadr:27; 2100 2100 - #endif 2101 2101 - } s; 2102 2102 - struct cvmx_l2c_oob2_s cn52xx; 2103 2103 - struct cvmx_l2c_oob2_s cn52xxp1; 2104 2104 - struct cvmx_l2c_oob2_s cn56xx; 2105 2105 - struct cvmx_l2c_oob2_s cn56xxp1; 2106 2106 - }; 2107 2107 - 2108 2108 - union cvmx_l2c_oob3 { 2109 2109 - uint64_t u64; 2110 2110 - struct cvmx_l2c_oob3_s { 2111 2111 - #ifdef __BIG_ENDIAN_BITFIELD 2112 2112 - uint64_t fadr:27; 2113 2113 - uint64_t fsrc:1; 2114 2114 - uint64_t reserved_34_35:2; 2115 2115 - uint64_t sadr:14; 2116 2116 - uint64_t reserved_14_19:6; 2117 2117 - uint64_t size:14; 2118 2118 - #else 2119 2119 - uint64_t size:14; 2120 2120 - uint64_t reserved_14_19:6; 2121 2121 - uint64_t sadr:14; 2122 2122 - uint64_t reserved_34_35:2; 2123 2123 - uint64_t fsrc:1; 2124 2124 - uint64_t fadr:27; 2125 2125 - #endif 2126 2126 - } s; 2127 2127 - struct cvmx_l2c_oob3_s cn52xx; 2128 2128 - struct cvmx_l2c_oob3_s cn52xxp1; 2129 2129 - struct cvmx_l2c_oob3_s cn56xx; 2130 2130 - struct cvmx_l2c_oob3_s cn56xxp1; 2131 2131 - }; 2132 2132 - 2133 2133 - union cvmx_l2c_pfcx { 2134 2134 - uint64_t u64; 2135 2135 - struct cvmx_l2c_pfcx_s { 2136 2136 - #ifdef __BIG_ENDIAN_BITFIELD 2137 2137 - uint64_t reserved_36_63:28; 2138 2138 - uint64_t pfcnt0:36; 2139 2139 - #else 2140 2140 - uint64_t pfcnt0:36; 2141 2141 - uint64_t reserved_36_63:28; 2142 2142 - #endif 2143 2143 - } s; 2144 2144 - struct cvmx_l2c_pfcx_s cn30xx; 2145 2145 - struct cvmx_l2c_pfcx_s cn31xx; 2146 2146 - struct cvmx_l2c_pfcx_s cn38xx; 2147 2147 - struct cvmx_l2c_pfcx_s cn38xxp2; 2148 2148 - struct cvmx_l2c_pfcx_s cn50xx; 2149 2149 - struct cvmx_l2c_pfcx_s cn52xx; 2150 2150 - struct cvmx_l2c_pfcx_s cn52xxp1; 2151 2151 - struct cvmx_l2c_pfcx_s cn56xx; 2152 2152 - struct cvmx_l2c_pfcx_s cn56xxp1; 2153 2153 - struct cvmx_l2c_pfcx_s cn58xx; 2154 2154 - struct cvmx_l2c_pfcx_s cn58xxp1; 2155 130 }; 2156 131 2157 132 union cvmx_l2c_pfctl { 2158 133 uint64_t u64; 2159 134 struct cvmx_l2c_pfctl_s { 2160 2160 - #ifdef __BIG_ENDIAN_BITFIELD 2161 2161 - uint64_t reserved_36_63:28; 2162 2162 - uint64_t cnt3rdclr:1; 2163 2163 - uint64_t cnt2rdclr:1; 2164 2164 - uint64_t cnt1rdclr:1; 2165 2165 - uint64_t cnt0rdclr:1; 2166 2166 - uint64_t cnt3ena:1; 2167 2167 - uint64_t cnt3clr:1; 2168 2168 - uint64_t cnt3sel:6; 2169 2169 - uint64_t cnt2ena:1; 2170 2170 - uint64_t cnt2clr:1; 2171 2171 - uint64_t cnt2sel:6; 2172 2172 - uint64_t cnt1ena:1; 2173 2173 - uint64_t cnt1clr:1; 2174 2174 - uint64_t cnt1sel:6; 2175 2175 - uint64_t cnt0ena:1; 2176 2176 - uint64_t cnt0clr:1; 2177 2177 - uint64_t cnt0sel:6; 2178 2178 - #else 2179 2179 - uint64_t cnt0sel:6; 2180 2180 - uint64_t cnt0clr:1; 2181 2181 - uint64_t cnt0ena:1; 2182 2182 - uint64_t cnt1sel:6; 2183 2183 - uint64_t cnt1clr:1; 2184 2184 - uint64_t cnt1ena:1; 2185 2185 - uint64_t cnt2sel:6; 2186 2186 - uint64_t cnt2clr:1; 2187 2187 - uint64_t cnt2ena:1; 2188 2188 - uint64_t cnt3sel:6; 2189 2189 - uint64_t cnt3clr:1; 2190 2190 - uint64_t cnt3ena:1; 2191 2191 - uint64_t cnt0rdclr:1; 2192 2192 - uint64_t cnt1rdclr:1; 2193 2193 - uint64_t cnt2rdclr:1; 2194 2194 - uint64_t cnt3rdclr:1; 2195 2195 - uint64_t reserved_36_63:28; 2196 2196 - #endif 135 135 + __BITFIELD_FIELD(uint64_t reserved_36_63:28, 136 136 + __BITFIELD_FIELD(uint64_t cnt3rdclr:1, 137 137 + __BITFIELD_FIELD(uint64_t cnt2rdclr:1, 138 138 + __BITFIELD_FIELD(uint64_t cnt1rdclr:1, 139 139 + __BITFIELD_FIELD(uint64_t cnt0rdclr:1, 140 140 + __BITFIELD_FIELD(uint64_t cnt3ena:1, 141 141 + __BITFIELD_FIELD(uint64_t cnt3clr:1, 142 142 + __BITFIELD_FIELD(uint64_t cnt3sel:6, 143 143 + __BITFIELD_FIELD(uint64_t cnt2ena:1, 144 144 + __BITFIELD_FIELD(uint64_t cnt2clr:1, 145 145 + __BITFIELD_FIELD(uint64_t cnt2sel:6, 146 146 + __BITFIELD_FIELD(uint64_t cnt1ena:1, 147 147 + __BITFIELD_FIELD(uint64_t cnt1clr:1, 148 148 + __BITFIELD_FIELD(uint64_t cnt1sel:6, 149 149 + __BITFIELD_FIELD(uint64_t cnt0ena:1, 150 150 + __BITFIELD_FIELD(uint64_t cnt0clr:1, 151 151 + __BITFIELD_FIELD(uint64_t cnt0sel:6, 152 152 + ;))))))))))))))))) 2197 153 } s; 2198 2198 - struct cvmx_l2c_pfctl_s cn30xx; 2199 2199 - struct cvmx_l2c_pfctl_s cn31xx; 2200 2200 - struct cvmx_l2c_pfctl_s cn38xx; 2201 2201 - struct cvmx_l2c_pfctl_s cn38xxp2; 2202 2202 - struct cvmx_l2c_pfctl_s cn50xx; 2203 2203 - struct cvmx_l2c_pfctl_s cn52xx; 2204 2204 - struct cvmx_l2c_pfctl_s cn52xxp1; 2205 2205 - struct cvmx_l2c_pfctl_s cn56xx; 2206 2206 - struct cvmx_l2c_pfctl_s cn56xxp1; 2207 2207 - struct cvmx_l2c_pfctl_s cn58xx; 2208 2208 - struct cvmx_l2c_pfctl_s cn58xxp1; 2209 2209 - }; 2210 2210 - 2211 2211 - union cvmx_l2c_ppgrp { 2212 2212 - uint64_t u64; 2213 2213 - struct cvmx_l2c_ppgrp_s { 2214 2214 - #ifdef __BIG_ENDIAN_BITFIELD 2215 2215 - uint64_t reserved_24_63:40; 2216 2216 - uint64_t pp11grp:2; 2217 2217 - uint64_t pp10grp:2; 2218 2218 - uint64_t pp9grp:2; 2219 2219 - uint64_t pp8grp:2; 2220 2220 - uint64_t pp7grp:2; 2221 2221 - uint64_t pp6grp:2; 2222 2222 - uint64_t pp5grp:2; 2223 2223 - uint64_t pp4grp:2; 2224 2224 - uint64_t pp3grp:2; 2225 2225 - uint64_t pp2grp:2; 2226 2226 - uint64_t pp1grp:2; 2227 2227 - uint64_t pp0grp:2; 2228 2228 - #else 2229 2229 - uint64_t pp0grp:2; 2230 2230 - uint64_t pp1grp:2; 2231 2231 - uint64_t pp2grp:2; 2232 2232 - uint64_t pp3grp:2; 2233 2233 - uint64_t pp4grp:2; 2234 2234 - uint64_t pp5grp:2; 2235 2235 - uint64_t pp6grp:2; 2236 2236 - uint64_t pp7grp:2; 2237 2237 - uint64_t pp8grp:2; 2238 2238 - uint64_t pp9grp:2; 2239 2239 - uint64_t pp10grp:2; 2240 2240 - uint64_t pp11grp:2; 2241 2241 - uint64_t reserved_24_63:40; 2242 2242 - #endif 2243 2243 - } s; 2244 2244 - struct cvmx_l2c_ppgrp_cn52xx { 2245 2245 - #ifdef __BIG_ENDIAN_BITFIELD 2246 2246 - uint64_t reserved_8_63:56; 2247 2247 - uint64_t pp3grp:2; 2248 2248 - uint64_t pp2grp:2; 2249 2249 - uint64_t pp1grp:2; 2250 2250 - uint64_t pp0grp:2; 2251 2251 - #else 2252 2252 - uint64_t pp0grp:2; 2253 2253 - uint64_t pp1grp:2; 2254 2254 - uint64_t pp2grp:2; 2255 2255 - uint64_t pp3grp:2; 2256 2256 - uint64_t reserved_8_63:56; 2257 2257 - #endif 2258 2258 - } cn52xx; 2259 2259 - struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; 2260 2260 - struct cvmx_l2c_ppgrp_s cn56xx; 2261 2261 - struct cvmx_l2c_ppgrp_s cn56xxp1; 2262 2262 - }; 2263 2263 - 2264 2264 - union cvmx_l2c_qos_iobx { 2265 2265 - uint64_t u64; 2266 2266 - struct cvmx_l2c_qos_iobx_s { 2267 2267 - #ifdef __BIG_ENDIAN_BITFIELD 2268 2268 - uint64_t reserved_7_63:57; 2269 2269 - uint64_t dwblvl:3; 2270 2270 - uint64_t reserved_3_3:1; 2271 2271 - uint64_t lvl:3; 2272 2272 - #else 2273 2273 - uint64_t lvl:3; 2274 2274 - uint64_t reserved_3_3:1; 2275 2275 - uint64_t dwblvl:3; 2276 2276 - uint64_t reserved_7_63:57; 2277 2277 - #endif 2278 2278 - } s; 2279 2279 - struct cvmx_l2c_qos_iobx_cn61xx { 2280 2280 - #ifdef __BIG_ENDIAN_BITFIELD 2281 2281 - uint64_t reserved_6_63:58; 2282 2282 - uint64_t dwblvl:2; 2283 2283 - uint64_t reserved_2_3:2; 2284 2284 - uint64_t lvl:2; 2285 2285 - #else 2286 2286 - uint64_t lvl:2; 2287 2287 - uint64_t reserved_2_3:2; 2288 2288 - uint64_t dwblvl:2; 2289 2289 - uint64_t reserved_6_63:58; 2290 2290 - #endif 2291 2291 - } cn61xx; 2292 2292 - struct cvmx_l2c_qos_iobx_cn61xx cn63xx; 2293 2293 - struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1; 2294 2294 - struct cvmx_l2c_qos_iobx_cn61xx cn66xx; 2295 2295 - struct cvmx_l2c_qos_iobx_s cn68xx; 2296 2296 - struct cvmx_l2c_qos_iobx_s cn68xxp1; 2297 2297 - struct cvmx_l2c_qos_iobx_cn61xx cnf71xx; 2298 2298 - }; 2299 2299 - 2300 2300 - union cvmx_l2c_qos_ppx { 2301 2301 - uint64_t u64; 2302 2302 - struct cvmx_l2c_qos_ppx_s { 2303 2303 - #ifdef __BIG_ENDIAN_BITFIELD 2304 2304 - uint64_t reserved_3_63:61; 2305 2305 - uint64_t lvl:3; 2306 2306 - #else 2307 2307 - uint64_t lvl:3; 2308 2308 - uint64_t reserved_3_63:61; 2309 2309 - #endif 2310 2310 - } s; 2311 2311 - struct cvmx_l2c_qos_ppx_cn61xx { 2312 2312 - #ifdef __BIG_ENDIAN_BITFIELD 2313 2313 - uint64_t reserved_2_63:62; 2314 2314 - uint64_t lvl:2; 2315 2315 - #else 2316 2316 - uint64_t lvl:2; 2317 2317 - uint64_t reserved_2_63:62; 2318 2318 - #endif 2319 2319 - } cn61xx; 2320 2320 - struct cvmx_l2c_qos_ppx_cn61xx cn63xx; 2321 2321 - struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1; 2322 2322 - struct cvmx_l2c_qos_ppx_cn61xx cn66xx; 2323 2323 - struct cvmx_l2c_qos_ppx_s cn68xx; 2324 2324 - struct cvmx_l2c_qos_ppx_s cn68xxp1; 2325 2325 - struct cvmx_l2c_qos_ppx_cn61xx cnf71xx; 2326 2326 - }; 2327 2327 - 2328 2328 - union cvmx_l2c_qos_wgt { 2329 2329 - uint64_t u64; 2330 2330 - struct cvmx_l2c_qos_wgt_s { 2331 2331 - #ifdef __BIG_ENDIAN_BITFIELD 2332 2332 - uint64_t wgt7:8; 2333 2333 - uint64_t wgt6:8; 2334 2334 - uint64_t wgt5:8; 2335 2335 - uint64_t wgt4:8; 2336 2336 - uint64_t wgt3:8; 2337 2337 - uint64_t wgt2:8; 2338 2338 - uint64_t wgt1:8; 2339 2339 - uint64_t wgt0:8; 2340 2340 - #else 2341 2341 - uint64_t wgt0:8; 2342 2342 - uint64_t wgt1:8; 2343 2343 - uint64_t wgt2:8; 2344 2344 - uint64_t wgt3:8; 2345 2345 - uint64_t wgt4:8; 2346 2346 - uint64_t wgt5:8; 2347 2347 - uint64_t wgt6:8; 2348 2348 - uint64_t wgt7:8; 2349 2349 - #endif 2350 2350 - } s; 2351 2351 - struct cvmx_l2c_qos_wgt_cn61xx { 2352 2352 - #ifdef __BIG_ENDIAN_BITFIELD 2353 2353 - uint64_t reserved_32_63:32; 2354 2354 - uint64_t wgt3:8; 2355 2355 - uint64_t wgt2:8; 2356 2356 - uint64_t wgt1:8; 2357 2357 - uint64_t wgt0:8; 2358 2358 - #else 2359 2359 - uint64_t wgt0:8; 2360 2360 - uint64_t wgt1:8; 2361 2361 - uint64_t wgt2:8; 2362 2362 - uint64_t wgt3:8; 2363 2363 - uint64_t reserved_32_63:32; 2364 2364 - #endif 2365 2365 - } cn61xx; 2366 2366 - struct cvmx_l2c_qos_wgt_cn61xx cn63xx; 2367 2367 - struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1; 2368 2368 - struct cvmx_l2c_qos_wgt_cn61xx cn66xx; 2369 2369 - struct cvmx_l2c_qos_wgt_s cn68xx; 2370 2370 - struct cvmx_l2c_qos_wgt_s cn68xxp1; 2371 2371 - struct cvmx_l2c_qos_wgt_cn61xx cnf71xx; 2372 2372 - }; 2373 2373 - 2374 2374 - union cvmx_l2c_rscx_pfc { 2375 2375 - uint64_t u64; 2376 2376 - struct cvmx_l2c_rscx_pfc_s { 2377 2377 - #ifdef __BIG_ENDIAN_BITFIELD 2378 2378 - uint64_t count:64; 2379 2379 - #else 2380 2380 - uint64_t count:64; 2381 2381 - #endif 2382 2382 - } s; 2383 2383 - struct cvmx_l2c_rscx_pfc_s cn61xx; 2384 2384 - struct cvmx_l2c_rscx_pfc_s cn63xx; 2385 2385 - struct cvmx_l2c_rscx_pfc_s cn63xxp1; 2386 2386 - struct cvmx_l2c_rscx_pfc_s cn66xx; 2387 2387 - struct cvmx_l2c_rscx_pfc_s cn68xx; 2388 2388 - struct cvmx_l2c_rscx_pfc_s cn68xxp1; 2389 2389 - struct cvmx_l2c_rscx_pfc_s cnf71xx; 2390 2390 - }; 2391 2391 - 2392 2392 - union cvmx_l2c_rsdx_pfc { 2393 2393 - uint64_t u64; 2394 2394 - struct cvmx_l2c_rsdx_pfc_s { 2395 2395 - #ifdef __BIG_ENDIAN_BITFIELD 2396 2396 - uint64_t count:64; 2397 2397 - #else 2398 2398 - uint64_t count:64; 2399 2399 - #endif 2400 2400 - } s; 2401 2401 - struct cvmx_l2c_rsdx_pfc_s cn61xx; 2402 2402 - struct cvmx_l2c_rsdx_pfc_s cn63xx; 2403 2403 - struct cvmx_l2c_rsdx_pfc_s cn63xxp1; 2404 2404 - struct cvmx_l2c_rsdx_pfc_s cn66xx; 2405 2405 - struct cvmx_l2c_rsdx_pfc_s cn68xx; 2406 2406 - struct cvmx_l2c_rsdx_pfc_s cn68xxp1; 2407 2407 - struct cvmx_l2c_rsdx_pfc_s cnf71xx; 2408 2408 - }; 2409 2409 - 2410 2410 - union cvmx_l2c_spar0 { 2411 2411 - uint64_t u64; 2412 2412 - struct cvmx_l2c_spar0_s { 2413 2413 - #ifdef __BIG_ENDIAN_BITFIELD 2414 2414 - uint64_t reserved_32_63:32; 2415 2415 - uint64_t umsk3:8; 2416 2416 - uint64_t umsk2:8; 2417 2417 - uint64_t umsk1:8; 2418 2418 - uint64_t umsk0:8; 2419 2419 - #else 2420 2420 - uint64_t umsk0:8; 2421 2421 - uint64_t umsk1:8; 2422 2422 - uint64_t umsk2:8; 2423 2423 - uint64_t umsk3:8; 2424 2424 - uint64_t reserved_32_63:32; 2425 2425 - #endif 2426 2426 - } s; 2427 2427 - struct cvmx_l2c_spar0_cn30xx { 2428 2428 - #ifdef __BIG_ENDIAN_BITFIELD 2429 2429 - uint64_t reserved_4_63:60; 2430 2430 - uint64_t umsk0:4; 2431 2431 - #else 2432 2432 - uint64_t umsk0:4; 2433 2433 - uint64_t reserved_4_63:60; 2434 2434 - #endif 2435 2435 - } cn30xx; 2436 2436 - struct cvmx_l2c_spar0_cn31xx { 2437 2437 - #ifdef __BIG_ENDIAN_BITFIELD 2438 2438 - uint64_t reserved_12_63:52; 2439 2439 - uint64_t umsk1:4; 2440 2440 - uint64_t reserved_4_7:4; 2441 2441 - uint64_t umsk0:4; 2442 2442 - #else 2443 2443 - uint64_t umsk0:4; 2444 2444 - uint64_t reserved_4_7:4; 2445 2445 - uint64_t umsk1:4; 2446 2446 - uint64_t reserved_12_63:52; 2447 2447 - #endif 2448 2448 - } cn31xx; 2449 2449 - struct cvmx_l2c_spar0_s cn38xx; 2450 2450 - struct cvmx_l2c_spar0_s cn38xxp2; 2451 2451 - struct cvmx_l2c_spar0_cn50xx { 2452 2452 - #ifdef __BIG_ENDIAN_BITFIELD 2453 2453 - uint64_t reserved_16_63:48; 2454 2454 - uint64_t umsk1:8; 2455 2455 - uint64_t umsk0:8; 2456 2456 - #else 2457 2457 - uint64_t umsk0:8; 2458 2458 - uint64_t umsk1:8; 2459 2459 - uint64_t reserved_16_63:48; 2460 2460 - #endif 2461 2461 - } cn50xx; 2462 2462 - struct cvmx_l2c_spar0_s cn52xx; 2463 2463 - struct cvmx_l2c_spar0_s cn52xxp1; 2464 2464 - struct cvmx_l2c_spar0_s cn56xx; 2465 2465 - struct cvmx_l2c_spar0_s cn56xxp1; 2466 2466 - struct cvmx_l2c_spar0_s cn58xx; 2467 2467 - struct cvmx_l2c_spar0_s cn58xxp1; 2468 2468 - }; 2469 2469 - 2470 2470 - union cvmx_l2c_spar1 { 2471 2471 - uint64_t u64; 2472 2472 - struct cvmx_l2c_spar1_s { 2473 2473 - #ifdef __BIG_ENDIAN_BITFIELD 2474 2474 - uint64_t reserved_32_63:32; 2475 2475 - uint64_t umsk7:8; 2476 2476 - uint64_t umsk6:8; 2477 2477 - uint64_t umsk5:8; 2478 2478 - uint64_t umsk4:8; 2479 2479 - #else 2480 2480 - uint64_t umsk4:8; 2481 2481 - uint64_t umsk5:8; 2482 2482 - uint64_t umsk6:8; 2483 2483 - uint64_t umsk7:8; 2484 2484 - uint64_t reserved_32_63:32; 2485 2485 - #endif 2486 2486 - } s; 2487 2487 - struct cvmx_l2c_spar1_s cn38xx; 2488 2488 - struct cvmx_l2c_spar1_s cn38xxp2; 2489 2489 - struct cvmx_l2c_spar1_s cn56xx; 2490 2490 - struct cvmx_l2c_spar1_s cn56xxp1; 2491 2491 - struct cvmx_l2c_spar1_s cn58xx; 2492 2492 - struct cvmx_l2c_spar1_s cn58xxp1; 2493 2493 - }; 2494 2494 - 2495 2495 - union cvmx_l2c_spar2 { 2496 2496 - uint64_t u64; 2497 2497 - struct cvmx_l2c_spar2_s { 2498 2498 - #ifdef __BIG_ENDIAN_BITFIELD 2499 2499 - uint64_t reserved_32_63:32; 2500 2500 - uint64_t umsk11:8; 2501 2501 - uint64_t umsk10:8; 2502 2502 - uint64_t umsk9:8; 2503 2503 - uint64_t umsk8:8; 2504 2504 - #else 2505 2505 - uint64_t umsk8:8; 2506 2506 - uint64_t umsk9:8; 2507 2507 - uint64_t umsk10:8; 2508 2508 - uint64_t umsk11:8; 2509 2509 - uint64_t reserved_32_63:32; 2510 2510 - #endif 2511 2511 - } s; 2512 2512 - struct cvmx_l2c_spar2_s cn38xx; 2513 2513 - struct cvmx_l2c_spar2_s cn38xxp2; 2514 2514 - struct cvmx_l2c_spar2_s cn56xx; 2515 2515 - struct cvmx_l2c_spar2_s cn56xxp1; 2516 2516 - struct cvmx_l2c_spar2_s cn58xx; 2517 2517 - struct cvmx_l2c_spar2_s cn58xxp1; 2518 2518 - }; 2519 2519 - 2520 2520 - union cvmx_l2c_spar3 { 2521 2521 - uint64_t u64; 2522 2522 - struct cvmx_l2c_spar3_s { 2523 2523 - #ifdef __BIG_ENDIAN_BITFIELD 2524 2524 - uint64_t reserved_32_63:32; 2525 2525 - uint64_t umsk15:8; 2526 2526 - uint64_t umsk14:8; 2527 2527 - uint64_t umsk13:8; 2528 2528 - uint64_t umsk12:8; 2529 2529 - #else 2530 2530 - uint64_t umsk12:8; 2531 2531 - uint64_t umsk13:8; 2532 2532 - uint64_t umsk14:8; 2533 2533 - uint64_t umsk15:8; 2534 2534 - uint64_t reserved_32_63:32; 2535 2535 - #endif 2536 2536 - } s; 2537 2537 - struct cvmx_l2c_spar3_s cn38xx; 2538 2538 - struct cvmx_l2c_spar3_s cn38xxp2; 2539 2539 - struct cvmx_l2c_spar3_s cn58xx; 2540 2540 - struct cvmx_l2c_spar3_s cn58xxp1; 2541 2541 - }; 2542 2542 - 2543 2543 - union cvmx_l2c_spar4 { 2544 2544 - uint64_t u64; 2545 2545 - struct cvmx_l2c_spar4_s { 2546 2546 - #ifdef __BIG_ENDIAN_BITFIELD 2547 2547 - uint64_t reserved_8_63:56; 2548 2548 - uint64_t umskiob:8; 2549 2549 - #else 2550 2550 - uint64_t umskiob:8; 2551 2551 - uint64_t reserved_8_63:56; 2552 2552 - #endif 2553 2553 - } s; 2554 2554 - struct cvmx_l2c_spar4_cn30xx { 2555 2555 - #ifdef __BIG_ENDIAN_BITFIELD 2556 2556 - uint64_t reserved_4_63:60; 2557 2557 - uint64_t umskiob:4; 2558 2558 - #else 2559 2559 - uint64_t umskiob:4; 2560 2560 - uint64_t reserved_4_63:60; 2561 2561 - #endif 2562 2562 - } cn30xx; 2563 2563 - struct cvmx_l2c_spar4_cn30xx cn31xx; 2564 2564 - struct cvmx_l2c_spar4_s cn38xx; 2565 2565 - struct cvmx_l2c_spar4_s cn38xxp2; 2566 2566 - struct cvmx_l2c_spar4_s cn50xx; 2567 2567 - struct cvmx_l2c_spar4_s cn52xx; 2568 2568 - struct cvmx_l2c_spar4_s cn52xxp1; 2569 2569 - struct cvmx_l2c_spar4_s cn56xx; 2570 2570 - struct cvmx_l2c_spar4_s cn56xxp1; 2571 2571 - struct cvmx_l2c_spar4_s cn58xx; 2572 2572 - struct cvmx_l2c_spar4_s cn58xxp1; 2573 2573 - }; 2574 2574 - 2575 2575 - union cvmx_l2c_tadx_ecc0 { 2576 2576 - uint64_t u64; 2577 2577 - struct cvmx_l2c_tadx_ecc0_s { 2578 2578 - #ifdef __BIG_ENDIAN_BITFIELD 2579 2579 - uint64_t reserved_58_63:6; 2580 2580 - uint64_t ow3ecc:10; 2581 2581 - uint64_t reserved_42_47:6; 2582 2582 - uint64_t ow2ecc:10; 2583 2583 - uint64_t reserved_26_31:6; 2584 2584 - uint64_t ow1ecc:10; 2585 2585 - uint64_t reserved_10_15:6; 2586 2586 - uint64_t ow0ecc:10; 2587 2587 - #else 2588 2588 - uint64_t ow0ecc:10; 2589 2589 - uint64_t reserved_10_15:6; 2590 2590 - uint64_t ow1ecc:10; 2591 2591 - uint64_t reserved_26_31:6; 2592 2592 - uint64_t ow2ecc:10; 2593 2593 - uint64_t reserved_42_47:6; 2594 2594 - uint64_t ow3ecc:10; 2595 2595 - uint64_t reserved_58_63:6; 2596 2596 - #endif 2597 2597 - } s; 2598 2598 - struct cvmx_l2c_tadx_ecc0_s cn61xx; 2599 2599 - struct cvmx_l2c_tadx_ecc0_s cn63xx; 2600 2600 - struct cvmx_l2c_tadx_ecc0_s cn63xxp1; 2601 2601 - struct cvmx_l2c_tadx_ecc0_s cn66xx; 2602 2602 - struct cvmx_l2c_tadx_ecc0_s cn68xx; 2603 2603 - struct cvmx_l2c_tadx_ecc0_s cn68xxp1; 2604 2604 - struct cvmx_l2c_tadx_ecc0_s cnf71xx; 2605 2605 - }; 2606 2606 - 2607 2607 - union cvmx_l2c_tadx_ecc1 { 2608 2608 - uint64_t u64; 2609 2609 - struct cvmx_l2c_tadx_ecc1_s { 2610 2610 - #ifdef __BIG_ENDIAN_BITFIELD 2611 2611 - uint64_t reserved_58_63:6; 2612 2612 - uint64_t ow7ecc:10; 2613 2613 - uint64_t reserved_42_47:6; 2614 2614 - uint64_t ow6ecc:10; 2615 2615 - uint64_t reserved_26_31:6; 2616 2616 - uint64_t ow5ecc:10; 2617 2617 - uint64_t reserved_10_15:6; 2618 2618 - uint64_t ow4ecc:10; 2619 2619 - #else 2620 2620 - uint64_t ow4ecc:10; 2621 2621 - uint64_t reserved_10_15:6; 2622 2622 - uint64_t ow5ecc:10; 2623 2623 - uint64_t reserved_26_31:6; 2624 2624 - uint64_t ow6ecc:10; 2625 2625 - uint64_t reserved_42_47:6; 2626 2626 - uint64_t ow7ecc:10; 2627 2627 - uint64_t reserved_58_63:6; 2628 2628 - #endif 2629 2629 - } s; 2630 2630 - struct cvmx_l2c_tadx_ecc1_s cn61xx; 2631 2631 - struct cvmx_l2c_tadx_ecc1_s cn63xx; 2632 2632 - struct cvmx_l2c_tadx_ecc1_s cn63xxp1; 2633 2633 - struct cvmx_l2c_tadx_ecc1_s cn66xx; 2634 2634 - struct cvmx_l2c_tadx_ecc1_s cn68xx; 2635 2635 - struct cvmx_l2c_tadx_ecc1_s cn68xxp1; 2636 2636 - struct cvmx_l2c_tadx_ecc1_s cnf71xx; 2637 2637 - }; 2638 2638 - 2639 2639 - union cvmx_l2c_tadx_ien { 2640 2640 - uint64_t u64; 2641 2641 - struct cvmx_l2c_tadx_ien_s { 2642 2642 - #ifdef __BIG_ENDIAN_BITFIELD 2643 2643 - uint64_t reserved_9_63:55; 2644 2644 - uint64_t wrdislmc:1; 2645 2645 - uint64_t rddislmc:1; 2646 2646 - uint64_t noway:1; 2647 2647 - uint64_t vbfdbe:1; 2648 2648 - uint64_t vbfsbe:1; 2649 2649 - uint64_t tagdbe:1; 2650 2650 - uint64_t tagsbe:1; 2651 2651 - uint64_t l2ddbe:1; 2652 2652 - uint64_t l2dsbe:1; 2653 2653 - #else 2654 2654 - uint64_t l2dsbe:1; 2655 2655 - uint64_t l2ddbe:1; 2656 2656 - uint64_t tagsbe:1; 2657 2657 - uint64_t tagdbe:1; 2658 2658 - uint64_t vbfsbe:1; 2659 2659 - uint64_t vbfdbe:1; 2660 2660 - uint64_t noway:1; 2661 2661 - uint64_t rddislmc:1; 2662 2662 - uint64_t wrdislmc:1; 2663 2663 - uint64_t reserved_9_63:55; 2664 2664 - #endif 2665 2665 - } s; 2666 2666 - struct cvmx_l2c_tadx_ien_s cn61xx; 2667 2667 - struct cvmx_l2c_tadx_ien_s cn63xx; 2668 2668 - struct cvmx_l2c_tadx_ien_cn63xxp1 { 2669 2669 - #ifdef __BIG_ENDIAN_BITFIELD 2670 2670 - uint64_t reserved_7_63:57; 2671 2671 - uint64_t noway:1; 2672 2672 - uint64_t vbfdbe:1; 2673 2673 - uint64_t vbfsbe:1; 2674 2674 - uint64_t tagdbe:1; 2675 2675 - uint64_t tagsbe:1; 2676 2676 - uint64_t l2ddbe:1; 2677 2677 - uint64_t l2dsbe:1; 2678 2678 - #else 2679 2679 - uint64_t l2dsbe:1; 2680 2680 - uint64_t l2ddbe:1; 2681 2681 - uint64_t tagsbe:1; 2682 2682 - uint64_t tagdbe:1; 2683 2683 - uint64_t vbfsbe:1; 2684 2684 - uint64_t vbfdbe:1; 2685 2685 - uint64_t noway:1; 2686 2686 - uint64_t reserved_7_63:57; 2687 2687 - #endif 2688 2688 - } cn63xxp1; 2689 2689 - struct cvmx_l2c_tadx_ien_s cn66xx; 2690 2690 - struct cvmx_l2c_tadx_ien_s cn68xx; 2691 2691 - struct cvmx_l2c_tadx_ien_s cn68xxp1; 2692 2692 - struct cvmx_l2c_tadx_ien_s cnf71xx; 2693 2693 - }; 2694 2694 - 2695 2695 - union cvmx_l2c_tadx_int { 2696 2696 - uint64_t u64; 2697 2697 - struct cvmx_l2c_tadx_int_s { 2698 2698 - #ifdef __BIG_ENDIAN_BITFIELD 2699 2699 - uint64_t reserved_9_63:55; 2700 2700 - uint64_t wrdislmc:1; 2701 2701 - uint64_t rddislmc:1; 2702 2702 - uint64_t noway:1; 2703 2703 - uint64_t vbfdbe:1; 2704 2704 - uint64_t vbfsbe:1; 2705 2705 - uint64_t tagdbe:1; 2706 2706 - uint64_t tagsbe:1; 2707 2707 - uint64_t l2ddbe:1; 2708 2708 - uint64_t l2dsbe:1; 2709 2709 - #else 2710 2710 - uint64_t l2dsbe:1; 2711 2711 - uint64_t l2ddbe:1; 2712 2712 - uint64_t tagsbe:1; 2713 2713 - uint64_t tagdbe:1; 2714 2714 - uint64_t vbfsbe:1; 2715 2715 - uint64_t vbfdbe:1; 2716 2716 - uint64_t noway:1; 2717 2717 - uint64_t rddislmc:1; 2718 2718 - uint64_t wrdislmc:1; 2719 2719 - uint64_t reserved_9_63:55; 2720 2720 - #endif 2721 2721 - } s; 2722 2722 - struct cvmx_l2c_tadx_int_s cn61xx; 2723 2723 - struct cvmx_l2c_tadx_int_s cn63xx; 2724 2724 - struct cvmx_l2c_tadx_int_s cn66xx; 2725 2725 - struct cvmx_l2c_tadx_int_s cn68xx; 2726 2726 - struct cvmx_l2c_tadx_int_s cn68xxp1; 2727 2727 - struct cvmx_l2c_tadx_int_s cnf71xx; 2728 2728 - }; 2729 2729 - 2730 2730 - union cvmx_l2c_tadx_pfc0 { 2731 2731 - uint64_t u64; 2732 2732 - struct cvmx_l2c_tadx_pfc0_s { 2733 2733 - #ifdef __BIG_ENDIAN_BITFIELD 2734 2734 - uint64_t count:64; 2735 2735 - #else 2736 2736 - uint64_t count:64; 2737 2737 - #endif 2738 2738 - } s; 2739 2739 - struct cvmx_l2c_tadx_pfc0_s cn61xx; 2740 2740 - struct cvmx_l2c_tadx_pfc0_s cn63xx; 2741 2741 - struct cvmx_l2c_tadx_pfc0_s cn63xxp1; 2742 2742 - struct cvmx_l2c_tadx_pfc0_s cn66xx; 2743 2743 - struct cvmx_l2c_tadx_pfc0_s cn68xx; 2744 2744 - struct cvmx_l2c_tadx_pfc0_s cn68xxp1; 2745 2745 - struct cvmx_l2c_tadx_pfc0_s cnf71xx; 2746 2746 - }; 2747 2747 - 2748 2748 - union cvmx_l2c_tadx_pfc1 { 2749 2749 - uint64_t u64; 2750 2750 - struct cvmx_l2c_tadx_pfc1_s { 2751 2751 - #ifdef __BIG_ENDIAN_BITFIELD 2752 2752 - uint64_t count:64; 2753 2753 - #else 2754 2754 - uint64_t count:64; 2755 2755 - #endif 2756 2756 - } s; 2757 2757 - struct cvmx_l2c_tadx_pfc1_s cn61xx; 2758 2758 - struct cvmx_l2c_tadx_pfc1_s cn63xx; 2759 2759 - struct cvmx_l2c_tadx_pfc1_s cn63xxp1; 2760 2760 - struct cvmx_l2c_tadx_pfc1_s cn66xx; 2761 2761 - struct cvmx_l2c_tadx_pfc1_s cn68xx; 2762 2762 - struct cvmx_l2c_tadx_pfc1_s cn68xxp1; 2763 2763 - struct cvmx_l2c_tadx_pfc1_s cnf71xx; 2764 2764 - }; 2765 2765 - 2766 2766 - union cvmx_l2c_tadx_pfc2 { 2767 2767 - uint64_t u64; 2768 2768 - struct cvmx_l2c_tadx_pfc2_s { 2769 2769 - #ifdef __BIG_ENDIAN_BITFIELD 2770 2770 - uint64_t count:64; 2771 2771 - #else 2772 2772 - uint64_t count:64; 2773 2773 - #endif 2774 2774 - } s; 2775 2775 - struct cvmx_l2c_tadx_pfc2_s cn61xx; 2776 2776 - struct cvmx_l2c_tadx_pfc2_s cn63xx; 2777 2777 - struct cvmx_l2c_tadx_pfc2_s cn63xxp1; 2778 2778 - struct cvmx_l2c_tadx_pfc2_s cn66xx; 2779 2779 - struct cvmx_l2c_tadx_pfc2_s cn68xx; 2780 2780 - struct cvmx_l2c_tadx_pfc2_s cn68xxp1; 2781 2781 - struct cvmx_l2c_tadx_pfc2_s cnf71xx; 2782 2782 - }; 2783 2783 - 2784 2784 - union cvmx_l2c_tadx_pfc3 { 2785 2785 - uint64_t u64; 2786 2786 - struct cvmx_l2c_tadx_pfc3_s { 2787 2787 - #ifdef __BIG_ENDIAN_BITFIELD 2788 2788 - uint64_t count:64; 2789 2789 - #else 2790 2790 - uint64_t count:64; 2791 2791 - #endif 2792 2792 - } s; 2793 2793 - struct cvmx_l2c_tadx_pfc3_s cn61xx; 2794 2794 - struct cvmx_l2c_tadx_pfc3_s cn63xx; 2795 2795 - struct cvmx_l2c_tadx_pfc3_s cn63xxp1; 2796 2796 - struct cvmx_l2c_tadx_pfc3_s cn66xx; 2797 2797 - struct cvmx_l2c_tadx_pfc3_s cn68xx; 2798 2798 - struct cvmx_l2c_tadx_pfc3_s cn68xxp1; 2799 2799 - struct cvmx_l2c_tadx_pfc3_s cnf71xx; 2800 154 }; 2801 155 2802 156 union cvmx_l2c_tadx_prf { 2803 157 uint64_t u64; 2804 158 struct cvmx_l2c_tadx_prf_s { 2805 2805 - #ifdef __BIG_ENDIAN_BITFIELD 2806 2806 - uint64_t reserved_32_63:32; 2807 2807 - uint64_t cnt3sel:8; 2808 2808 - uint64_t cnt2sel:8; 2809 2809 - uint64_t cnt1sel:8; 2810 2810 - uint64_t cnt0sel:8; 2811 2811 - #else 2812 2812 - uint64_t cnt0sel:8; 2813 2813 - uint64_t cnt1sel:8; 2814 2814 - uint64_t cnt2sel:8; 2815 2815 - uint64_t cnt3sel:8; 2816 2816 - uint64_t reserved_32_63:32; 2817 2817 - #endif 159 159 + __BITFIELD_FIELD(uint64_t reserved_32_63:32, 160 160 + __BITFIELD_FIELD(uint64_t cnt3sel:8, 161 161 + __BITFIELD_FIELD(uint64_t cnt2sel:8, 162 162 + __BITFIELD_FIELD(uint64_t cnt1sel:8, 163 163 + __BITFIELD_FIELD(uint64_t cnt0sel:8, 164 164 + ;))))) 2818 165 } s; 2819 2819 - struct cvmx_l2c_tadx_prf_s cn61xx; 2820 2820 - struct cvmx_l2c_tadx_prf_s cn63xx; 2821 2821 - struct cvmx_l2c_tadx_prf_s cn63xxp1; 2822 2822 - struct cvmx_l2c_tadx_prf_s cn66xx; 2823 2823 - struct cvmx_l2c_tadx_prf_s cn68xx; 2824 2824 - struct cvmx_l2c_tadx_prf_s cn68xxp1; 2825 2825 - struct cvmx_l2c_tadx_prf_s cnf71xx; 2826 166 }; 2827 167 2828 168 union cvmx_l2c_tadx_tag { 2829 169 uint64_t u64; 2830 170 struct cvmx_l2c_tadx_tag_s { 2831 2831 - #ifdef __BIG_ENDIAN_BITFIELD 2832 2832 - uint64_t reserved_46_63:18; 2833 2833 - uint64_t ecc:6; 2834 2834 - uint64_t reserved_36_39:4; 2835 2835 - uint64_t tag:19; 2836 2836 - uint64_t reserved_4_16:13; 2837 2837 - uint64_t use:1; 2838 2838 - uint64_t valid:1; 2839 2839 - uint64_t dirty:1; 2840 2840 - uint64_t lock:1; 2841 2841 - #else 2842 2842 - uint64_t lock:1; 2843 2843 - uint64_t dirty:1; 2844 2844 - uint64_t valid:1; 2845 2845 - uint64_t use:1; 2846 2846 - uint64_t reserved_4_16:13; 2847 2847 - uint64_t tag:19; 2848 2848 - uint64_t reserved_36_39:4; 2849 2849 - uint64_t ecc:6; 2850 2850 - uint64_t reserved_46_63:18; 2851 2851 - #endif 171 171 + __BITFIELD_FIELD(uint64_t reserved_46_63:18, 172 172 + __BITFIELD_FIELD(uint64_t ecc:6, 173 173 + __BITFIELD_FIELD(uint64_t reserved_36_39:4, 174 174 + __BITFIELD_FIELD(uint64_t tag:19, 175 175 + __BITFIELD_FIELD(uint64_t reserved_4_16:13, 176 176 + __BITFIELD_FIELD(uint64_t use:1, 177 177 + __BITFIELD_FIELD(uint64_t valid:1, 178 178 + __BITFIELD_FIELD(uint64_t dirty:1, 179 179 + __BITFIELD_FIELD(uint64_t lock:1, 180 180 + ;))))))))) 2852 181 } s; 2853 2853 - struct cvmx_l2c_tadx_tag_s cn61xx; 2854 2854 - struct cvmx_l2c_tadx_tag_s cn63xx; 2855 2855 - struct cvmx_l2c_tadx_tag_s cn63xxp1; 2856 2856 - struct cvmx_l2c_tadx_tag_s cn66xx; 2857 2857 - struct cvmx_l2c_tadx_tag_s cn68xx; 2858 2858 - struct cvmx_l2c_tadx_tag_s cn68xxp1; 2859 2859 - struct cvmx_l2c_tadx_tag_s cnf71xx; 2860 182 }; 2861 183 2862 2862 - union cvmx_l2c_ver_id { 184 184 + union cvmx_l2c_lckbase { 2863 185 uint64_t u64; 2864 2864 - struct cvmx_l2c_ver_id_s { 2865 2865 - #ifdef __BIG_ENDIAN_BITFIELD 2866 2866 - uint64_t mask:64; 2867 2867 - #else 2868 2868 - uint64_t mask:64; 2869 2869 - #endif 186 186 + struct cvmx_l2c_lckbase_s { 187 187 + __BITFIELD_FIELD(uint64_t reserved_31_63:33, 188 188 + __BITFIELD_FIELD(uint64_t lck_base:27, 189 189 + __BITFIELD_FIELD(uint64_t reserved_1_3:3, 190 190 + __BITFIELD_FIELD(uint64_t lck_ena:1, 191 191 + ;)))) 2870 192 } s; 2871 2871 - struct cvmx_l2c_ver_id_s cn61xx; 2872 2872 - struct cvmx_l2c_ver_id_s cn63xx; 2873 2873 - struct cvmx_l2c_ver_id_s cn63xxp1; 2874 2874 - struct cvmx_l2c_ver_id_s cn66xx; 2875 2875 - struct cvmx_l2c_ver_id_s cn68xx; 2876 2876 - struct cvmx_l2c_ver_id_s cn68xxp1; 2877 2877 - struct cvmx_l2c_ver_id_s cnf71xx; 2878 193 }; 2879 194 2880 2880 - union cvmx_l2c_ver_iob { 195 195 + union cvmx_l2c_lckoff { 2881 196 uint64_t u64; 2882 2882 - struct cvmx_l2c_ver_iob_s { 2883 2883 - #ifdef __BIG_ENDIAN_BITFIELD 2884 2884 - uint64_t reserved_2_63:62; 2885 2885 - uint64_t mask:2; 2886 2886 - #else 2887 2887 - uint64_t mask:2; 2888 2888 - uint64_t reserved_2_63:62; 2889 2889 - #endif 197 197 + struct cvmx_l2c_lckoff_s { 198 198 + __BITFIELD_FIELD(uint64_t reserved_10_63:54, 199 199 + __BITFIELD_FIELD(uint64_t lck_offset:10, 200 200 + ;)) 2890 201 } s; 2891 2891 - struct cvmx_l2c_ver_iob_cn61xx { 2892 2892 - #ifdef __BIG_ENDIAN_BITFIELD 2893 2893 - uint64_t reserved_1_63:63; 2894 2894 - uint64_t mask:1; 2895 2895 - #else 2896 2896 - uint64_t mask:1; 2897 2897 - uint64_t reserved_1_63:63; 2898 2898 - #endif 2899 2899 - } cn61xx; 2900 2900 - struct cvmx_l2c_ver_iob_cn61xx cn63xx; 2901 2901 - struct cvmx_l2c_ver_iob_cn61xx cn63xxp1; 2902 2902 - struct cvmx_l2c_ver_iob_cn61xx cn66xx; 2903 2903 - struct cvmx_l2c_ver_iob_s cn68xx; 2904 2904 - struct cvmx_l2c_ver_iob_s cn68xxp1; 2905 2905 - struct cvmx_l2c_ver_iob_cn61xx cnf71xx; 2906 2906 - }; 2907 2907 - 2908 2908 - union cvmx_l2c_ver_msc { 2909 2909 - uint64_t u64; 2910 2910 - struct cvmx_l2c_ver_msc_s { 2911 2911 - #ifdef __BIG_ENDIAN_BITFIELD 2912 2912 - uint64_t reserved_2_63:62; 2913 2913 - uint64_t invl2:1; 2914 2914 - uint64_t dwb:1; 2915 2915 - #else 2916 2916 - uint64_t dwb:1; 2917 2917 - uint64_t invl2:1; 2918 2918 - uint64_t reserved_2_63:62; 2919 2919 - #endif 2920 2920 - } s; 2921 2921 - struct cvmx_l2c_ver_msc_s cn61xx; 2922 2922 - struct cvmx_l2c_ver_msc_s cn63xx; 2923 2923 - struct cvmx_l2c_ver_msc_s cn66xx; 2924 2924 - struct cvmx_l2c_ver_msc_s cn68xx; 2925 2925 - struct cvmx_l2c_ver_msc_s cn68xxp1; 2926 2926 - struct cvmx_l2c_ver_msc_s cnf71xx; 2927 2927 - }; 2928 2928 - 2929 2929 - union cvmx_l2c_ver_pp { 2930 2930 - uint64_t u64; 2931 2931 - struct cvmx_l2c_ver_pp_s { 2932 2932 - #ifdef __BIG_ENDIAN_BITFIELD 2933 2933 - uint64_t reserved_32_63:32; 2934 2934 - uint64_t mask:32; 2935 2935 - #else 2936 2936 - uint64_t mask:32; 2937 2937 - uint64_t reserved_32_63:32; 2938 2938 - #endif 2939 2939 - } s; 2940 2940 - struct cvmx_l2c_ver_pp_cn61xx { 2941 2941 - #ifdef __BIG_ENDIAN_BITFIELD 2942 2942 - uint64_t reserved_4_63:60; 2943 2943 - uint64_t mask:4; 2944 2944 - #else 2945 2945 - uint64_t mask:4; 2946 2946 - uint64_t reserved_4_63:60; 2947 2947 - #endif 2948 2948 - } cn61xx; 2949 2949 - struct cvmx_l2c_ver_pp_cn63xx { 2950 2950 - #ifdef __BIG_ENDIAN_BITFIELD 2951 2951 - uint64_t reserved_6_63:58; 2952 2952 - uint64_t mask:6; 2953 2953 - #else 2954 2954 - uint64_t mask:6; 2955 2955 - uint64_t reserved_6_63:58; 2956 2956 - #endif 2957 2957 - } cn63xx; 2958 2958 - struct cvmx_l2c_ver_pp_cn63xx cn63xxp1; 2959 2959 - struct cvmx_l2c_ver_pp_cn66xx { 2960 2960 - #ifdef __BIG_ENDIAN_BITFIELD 2961 2961 - uint64_t reserved_10_63:54; 2962 2962 - uint64_t mask:10; 2963 2963 - #else 2964 2964 - uint64_t mask:10; 2965 2965 - uint64_t reserved_10_63:54; 2966 2966 - #endif 2967 2967 - } cn66xx; 2968 2968 - struct cvmx_l2c_ver_pp_s cn68xx; 2969 2969 - struct cvmx_l2c_ver_pp_s cn68xxp1; 2970 2970 - struct cvmx_l2c_ver_pp_cn61xx cnf71xx; 2971 2971 - }; 2972 2972 - 2973 2973 - union cvmx_l2c_virtid_iobx { 2974 2974 - uint64_t u64; 2975 2975 - struct cvmx_l2c_virtid_iobx_s { 2976 2976 - #ifdef __BIG_ENDIAN_BITFIELD 2977 2977 - uint64_t reserved_14_63:50; 2978 2978 - uint64_t dwbid:6; 2979 2979 - uint64_t reserved_6_7:2; 2980 2980 - uint64_t id:6; 2981 2981 - #else 2982 2982 - uint64_t id:6; 2983 2983 - uint64_t reserved_6_7:2; 2984 2984 - uint64_t dwbid:6; 2985 2985 - uint64_t reserved_14_63:50; 2986 2986 - #endif 2987 2987 - } s; 2988 2988 - struct cvmx_l2c_virtid_iobx_s cn61xx; 2989 2989 - struct cvmx_l2c_virtid_iobx_s cn63xx; 2990 2990 - struct cvmx_l2c_virtid_iobx_s cn63xxp1; 2991 2991 - struct cvmx_l2c_virtid_iobx_s cn66xx; 2992 2992 - struct cvmx_l2c_virtid_iobx_s cn68xx; 2993 2993 - struct cvmx_l2c_virtid_iobx_s cn68xxp1; 2994 2994 - struct cvmx_l2c_virtid_iobx_s cnf71xx; 2995 2995 - }; 2996 2996 - 2997 2997 - union cvmx_l2c_virtid_ppx { 2998 2998 - uint64_t u64; 2999 2999 - struct cvmx_l2c_virtid_ppx_s { 3000 3000 - #ifdef __BIG_ENDIAN_BITFIELD 3001 3001 - uint64_t reserved_6_63:58; 3002 3002 - uint64_t id:6; 3003 3003 - #else 3004 3004 - uint64_t id:6; 3005 3005 - uint64_t reserved_6_63:58; 3006 3006 - #endif 3007 3007 - } s; 3008 3008 - struct cvmx_l2c_virtid_ppx_s cn61xx; 3009 3009 - struct cvmx_l2c_virtid_ppx_s cn63xx; 3010 3010 - struct cvmx_l2c_virtid_ppx_s cn63xxp1; 3011 3011 - struct cvmx_l2c_virtid_ppx_s cn66xx; 3012 3012 - struct cvmx_l2c_virtid_ppx_s cn68xx; 3013 3013 - struct cvmx_l2c_virtid_ppx_s cn68xxp1; 3014 3014 - struct cvmx_l2c_virtid_ppx_s cnf71xx; 3015 3015 - }; 3016 3016 - 3017 3017 - union cvmx_l2c_vrt_ctl { 3018 3018 - uint64_t u64; 3019 3019 - struct cvmx_l2c_vrt_ctl_s { 3020 3020 - #ifdef __BIG_ENDIAN_BITFIELD 3021 3021 - uint64_t reserved_9_63:55; 3022 3022 - uint64_t ooberr:1; 3023 3023 - uint64_t reserved_7_7:1; 3024 3024 - uint64_t memsz:3; 3025 3025 - uint64_t numid:3; 3026 3026 - uint64_t enable:1; 3027 3027 - #else 3028 3028 - uint64_t enable:1; 3029 3029 - uint64_t numid:3; 3030 3030 - uint64_t memsz:3; 3031 3031 - uint64_t reserved_7_7:1; 3032 3032 - uint64_t ooberr:1; 3033 3033 - uint64_t reserved_9_63:55; 3034 3034 - #endif 3035 3035 - } s; 3036 3036 - struct cvmx_l2c_vrt_ctl_s cn61xx; 3037 3037 - struct cvmx_l2c_vrt_ctl_s cn63xx; 3038 3038 - struct cvmx_l2c_vrt_ctl_s cn63xxp1; 3039 3039 - struct cvmx_l2c_vrt_ctl_s cn66xx; 3040 3040 - struct cvmx_l2c_vrt_ctl_s cn68xx; 3041 3041 - struct cvmx_l2c_vrt_ctl_s cn68xxp1; 3042 3042 - struct cvmx_l2c_vrt_ctl_s cnf71xx; 3043 3043 - }; 3044 3044 - 3045 3045 - union cvmx_l2c_vrt_memx { 3046 3046 - uint64_t u64; 3047 3047 - struct cvmx_l2c_vrt_memx_s { 3048 3048 - #ifdef __BIG_ENDIAN_BITFIELD 3049 3049 - uint64_t reserved_36_63:28; 3050 3050 - uint64_t parity:4; 3051 3051 - uint64_t data:32; 3052 3052 - #else 3053 3053 - uint64_t data:32; 3054 3054 - uint64_t parity:4; 3055 3055 - uint64_t reserved_36_63:28; 3056 3056 - #endif 3057 3057 - } s; 3058 3058 - struct cvmx_l2c_vrt_memx_s cn61xx; 3059 3059 - struct cvmx_l2c_vrt_memx_s cn63xx; 3060 3060 - struct cvmx_l2c_vrt_memx_s cn63xxp1; 3061 3061 - struct cvmx_l2c_vrt_memx_s cn66xx; 3062 3062 - struct cvmx_l2c_vrt_memx_s cn68xx; 3063 3063 - struct cvmx_l2c_vrt_memx_s cn68xxp1; 3064 3064 - struct cvmx_l2c_vrt_memx_s cnf71xx; 3065 3065 - }; 3066 3066 - 3067 3067 - union cvmx_l2c_wpar_iobx { 3068 3068 - uint64_t u64; 3069 3069 - struct cvmx_l2c_wpar_iobx_s { 3070 3070 - #ifdef __BIG_ENDIAN_BITFIELD 3071 3071 - uint64_t reserved_16_63:48; 3072 3072 - uint64_t mask:16; 3073 3073 - #else 3074 3074 - uint64_t mask:16; 3075 3075 - uint64_t reserved_16_63:48; 3076 3076 - #endif 3077 3077 - } s; 3078 3078 - struct cvmx_l2c_wpar_iobx_s cn61xx; 3079 3079 - struct cvmx_l2c_wpar_iobx_s cn63xx; 3080 3080 - struct cvmx_l2c_wpar_iobx_s cn63xxp1; 3081 3081 - struct cvmx_l2c_wpar_iobx_s cn66xx; 3082 3082 - struct cvmx_l2c_wpar_iobx_s cn68xx; 3083 3083 - struct cvmx_l2c_wpar_iobx_s cn68xxp1; 3084 3084 - struct cvmx_l2c_wpar_iobx_s cnf71xx; 3085 3085 - }; 3086 3086 - 3087 3087 - union cvmx_l2c_wpar_ppx { 3088 3088 - uint64_t u64; 3089 3089 - struct cvmx_l2c_wpar_ppx_s { 3090 3090 - #ifdef __BIG_ENDIAN_BITFIELD 3091 3091 - uint64_t reserved_16_63:48; 3092 3092 - uint64_t mask:16; 3093 3093 - #else 3094 3094 - uint64_t mask:16; 3095 3095 - uint64_t reserved_16_63:48; 3096 3096 - #endif 3097 3097 - } s; 3098 3098 - struct cvmx_l2c_wpar_ppx_s cn61xx; 3099 3099 - struct cvmx_l2c_wpar_ppx_s cn63xx; 3100 3100 - struct cvmx_l2c_wpar_ppx_s cn63xxp1; 3101 3101 - struct cvmx_l2c_wpar_ppx_s cn66xx; 3102 3102 - struct cvmx_l2c_wpar_ppx_s cn68xx; 3103 3103 - struct cvmx_l2c_wpar_ppx_s cn68xxp1; 3104 3104 - struct cvmx_l2c_wpar_ppx_s cnf71xx; 3105 3105 - }; 3106 3106 - 3107 3107 - union cvmx_l2c_xmcx_pfc { 3108 3108 - uint64_t u64; 3109 3109 - struct cvmx_l2c_xmcx_pfc_s { 3110 3110 - #ifdef __BIG_ENDIAN_BITFIELD 3111 3111 - uint64_t count:64; 3112 3112 - #else 3113 3113 - uint64_t count:64; 3114 3114 - #endif 3115 3115 - } s; 3116 3116 - struct cvmx_l2c_xmcx_pfc_s cn61xx; 3117 3117 - struct cvmx_l2c_xmcx_pfc_s cn63xx; 3118 3118 - struct cvmx_l2c_xmcx_pfc_s cn63xxp1; 3119 3119 - struct cvmx_l2c_xmcx_pfc_s cn66xx; 3120 3120 - struct cvmx_l2c_xmcx_pfc_s cn68xx; 3121 3121 - struct cvmx_l2c_xmcx_pfc_s cn68xxp1; 3122 3122 - struct cvmx_l2c_xmcx_pfc_s cnf71xx; 3123 3123 - }; 3124 3124 - 3125 3125 - union cvmx_l2c_xmc_cmd { 3126 3126 - uint64_t u64; 3127 3127 - struct cvmx_l2c_xmc_cmd_s { 3128 3128 - #ifdef __BIG_ENDIAN_BITFIELD 3129 3129 - uint64_t inuse:1; 3130 3130 - uint64_t cmd:6; 3131 3131 - uint64_t reserved_38_56:19; 3132 3132 - uint64_t addr:38; 3133 3133 - #else 3134 3134 - uint64_t addr:38; 3135 3135 - uint64_t reserved_38_56:19; 3136 3136 - uint64_t cmd:6; 3137 3137 - uint64_t inuse:1; 3138 3138 - #endif 3139 3139 - } s; 3140 3140 - struct cvmx_l2c_xmc_cmd_s cn61xx; 3141 3141 - struct cvmx_l2c_xmc_cmd_s cn63xx; 3142 3142 - struct cvmx_l2c_xmc_cmd_s cn63xxp1; 3143 3143 - struct cvmx_l2c_xmc_cmd_s cn66xx; 3144 3144 - struct cvmx_l2c_xmc_cmd_s cn68xx; 3145 3145 - struct cvmx_l2c_xmc_cmd_s cn68xxp1; 3146 3146 - struct cvmx_l2c_xmc_cmd_s cnf71xx; 3147 3147 - }; 3148 3148 - 3149 3149 - union cvmx_l2c_xmdx_pfc { 3150 3150 - uint64_t u64; 3151 3151 - struct cvmx_l2c_xmdx_pfc_s { 3152 3152 - #ifdef __BIG_ENDIAN_BITFIELD 3153 3153 - uint64_t count:64; 3154 3154 - #else 3155 3155 - uint64_t count:64; 3156 3156 - #endif 3157 3157 - } s; 3158 3158 - struct cvmx_l2c_xmdx_pfc_s cn61xx; 3159 3159 - struct cvmx_l2c_xmdx_pfc_s cn63xx; 3160 3160 - struct cvmx_l2c_xmdx_pfc_s cn63xxp1; 3161 3161 - struct cvmx_l2c_xmdx_pfc_s cn66xx; 3162 3162 - struct cvmx_l2c_xmdx_pfc_s cn68xx; 3163 3163 - struct cvmx_l2c_xmdx_pfc_s cn68xxp1; 3164 3164 - struct cvmx_l2c_xmdx_pfc_s cnf71xx; 3165 202 }; 3166 203 3167 204 #endif

+31 -36

arch/mips/include/asm/octeon/cvmx-l2c.h

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2010 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 33 33 #ifndef __CVMX_L2C_H__ 34 34 #define __CVMX_L2C_H__ 35 35 36 36 - #define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ 37 37 - #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ 38 38 - #define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ 36 36 + #include <uapi/asm/bitfield.h> 39 37 38 38 + #define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro */ 39 39 + #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro */ 40 40 + #define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro */ 40 41 41 41 - #define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 42 42 + /* Based on 128 byte cache line size */ 43 43 + #define CVMX_L2C_IDX_ADDR_SHIFT 7 42 44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 43 45 44 46 /* Defines for index aliasing computations */ 45 45 - #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 47 47 + #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + \ 48 48 + cvmx_l2c_get_set_bits()) 46 49 #define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 47 47 - #define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 48 48 - 49 49 - /* Defines for Virtualizations, valid only from Octeon II onwards. */ 50 50 - #define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0) 51 51 - #define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0) 52 52 - 53 53 - union cvmx_l2c_tag { 54 54 - uint64_t u64; 55 55 - struct { 56 56 - #ifdef __BIG_ENDIAN_BITFIELD 57 57 - uint64_t reserved:28; 58 58 - uint64_t V:1; /* Line valid */ 59 59 - uint64_t D:1; /* Line dirty */ 60 60 - uint64_t L:1; /* Line locked */ 61 61 - uint64_t U:1; /* Use, LRU eviction */ 62 62 - uint64_t addr:32; /* Phys mem (not all bits valid) */ 63 63 - #else 64 64 - uint64_t addr:32; /* Phys mem (not all bits valid) */ 65 65 - uint64_t U:1; /* Use, LRU eviction */ 66 66 - uint64_t L:1; /* Line locked */ 67 67 - uint64_t D:1; /* Line dirty */ 68 68 - uint64_t V:1; /* Line valid */ 69 69 - uint64_t reserved:28; 70 70 - #endif 71 71 - } s; 72 72 - }; 50 50 + #define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 73 51 74 52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ 75 53 #define CVMX_L2C_TADS 1 76 54 77 77 - /* L2C Performance Counter events. */ 55 55 + union cvmx_l2c_tag { 56 56 + uint64_t u64; 57 57 + struct { 58 58 + __BITFIELD_FIELD(uint64_t reserved:28, 59 59 + __BITFIELD_FIELD(uint64_t V:1, 60 60 + __BITFIELD_FIELD(uint64_t D:1, 61 61 + __BITFIELD_FIELD(uint64_t L:1, 62 62 + __BITFIELD_FIELD(uint64_t U:1, 63 63 + __BITFIELD_FIELD(uint64_t addr:32, 64 64 + ;)))))) 65 65 + } s; 66 66 + }; 67 67 + 68 68 + /* L2C Performance Counter events. */ 78 69 enum cvmx_l2c_event { 79 70 CVMX_L2C_EVENT_CYCLES = 0, 80 71 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, ··· 166 175 * 167 176 * @note The routine does not clear the counter. 168 177 */ 169 169 - void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read); 178 178 + void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, 179 179 + uint32_t clear_on_read); 170 180 171 181 /** 172 182 * Read the given L2 Cache performance counter. The counter must be configured ··· 299 307 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); 300 308 301 309 /* Wrapper providing a deprecated old function name */ 302 302 - static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated)); 303 303 - static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) 310 310 + static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, 311 311 + uint32_t index) 312 312 + __attribute__((deprecated)); 313 313 + static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, 314 314 + uint32_t index) 304 315 { 305 316 return cvmx_l2c_get_tag(association, index); 306 317 }

-526

arch/mips/include/asm/octeon/cvmx-l2d-defs.h

reviewed

··· 1 1 - /***********************license start*************** 2 2 - * Author: Cavium Networks 3 3 - * 4 4 - * Contact: support@caviumnetworks.com 5 5 - * This file is part of the OCTEON SDK 6 6 - * 7 7 - * Copyright (c) 2003-2012 Cavium Networks 8 8 - * 9 9 - * This file is free software; you can redistribute it and/or modify 10 10 - * it under the terms of the GNU General Public License, Version 2, as 11 11 - * published by the Free Software Foundation. 12 12 - * 13 13 - * This file is distributed in the hope that it will be useful, but 14 14 - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 15 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 16 - * NONINFRINGEMENT. See the GNU General Public License for more 17 17 - * details. 18 18 - * 19 19 - * You should have received a copy of the GNU General Public License 20 20 - * along with this file; if not, write to the Free Software 21 21 - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 22 - * or visit http://www.gnu.org/licenses/. 23 23 - * 24 24 - * This file may also be available under a different license from Cavium. 25 25 - * Contact Cavium Networks for more information 26 26 - ***********************license end**************************************/ 27 27 - 28 28 - #ifndef __CVMX_L2D_DEFS_H__ 29 29 - #define __CVMX_L2D_DEFS_H__ 30 30 - 31 31 - #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull)) 32 32 - #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull)) 33 33 - #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull)) 34 34 - #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull)) 35 35 - #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull)) 36 36 - #define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull)) 37 37 - #define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull)) 38 38 - #define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull)) 39 39 - #define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull)) 40 40 - #define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull)) 41 41 - #define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull)) 42 42 - #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) 43 43 - 44 44 - union cvmx_l2d_bst0 { 45 45 - uint64_t u64; 46 46 - struct cvmx_l2d_bst0_s { 47 47 - #ifdef __BIG_ENDIAN_BITFIELD 48 48 - uint64_t reserved_35_63:29; 49 49 - uint64_t ftl:1; 50 50 - uint64_t q0stat:34; 51 51 - #else 52 52 - uint64_t q0stat:34; 53 53 - uint64_t ftl:1; 54 54 - uint64_t reserved_35_63:29; 55 55 - #endif 56 56 - } s; 57 57 - struct cvmx_l2d_bst0_s cn30xx; 58 58 - struct cvmx_l2d_bst0_s cn31xx; 59 59 - struct cvmx_l2d_bst0_s cn38xx; 60 60 - struct cvmx_l2d_bst0_s cn38xxp2; 61 61 - struct cvmx_l2d_bst0_s cn50xx; 62 62 - struct cvmx_l2d_bst0_s cn52xx; 63 63 - struct cvmx_l2d_bst0_s cn52xxp1; 64 64 - struct cvmx_l2d_bst0_s cn56xx; 65 65 - struct cvmx_l2d_bst0_s cn56xxp1; 66 66 - struct cvmx_l2d_bst0_s cn58xx; 67 67 - struct cvmx_l2d_bst0_s cn58xxp1; 68 68 - }; 69 69 - 70 70 - union cvmx_l2d_bst1 { 71 71 - uint64_t u64; 72 72 - struct cvmx_l2d_bst1_s { 73 73 - #ifdef __BIG_ENDIAN_BITFIELD 74 74 - uint64_t reserved_34_63:30; 75 75 - uint64_t q1stat:34; 76 76 - #else 77 77 - uint64_t q1stat:34; 78 78 - uint64_t reserved_34_63:30; 79 79 - #endif 80 80 - } s; 81 81 - struct cvmx_l2d_bst1_s cn30xx; 82 82 - struct cvmx_l2d_bst1_s cn31xx; 83 83 - struct cvmx_l2d_bst1_s cn38xx; 84 84 - struct cvmx_l2d_bst1_s cn38xxp2; 85 85 - struct cvmx_l2d_bst1_s cn50xx; 86 86 - struct cvmx_l2d_bst1_s cn52xx; 87 87 - struct cvmx_l2d_bst1_s cn52xxp1; 88 88 - struct cvmx_l2d_bst1_s cn56xx; 89 89 - struct cvmx_l2d_bst1_s cn56xxp1; 90 90 - struct cvmx_l2d_bst1_s cn58xx; 91 91 - struct cvmx_l2d_bst1_s cn58xxp1; 92 92 - }; 93 93 - 94 94 - union cvmx_l2d_bst2 { 95 95 - uint64_t u64; 96 96 - struct cvmx_l2d_bst2_s { 97 97 - #ifdef __BIG_ENDIAN_BITFIELD 98 98 - uint64_t reserved_34_63:30; 99 99 - uint64_t q2stat:34; 100 100 - #else 101 101 - uint64_t q2stat:34; 102 102 - uint64_t reserved_34_63:30; 103 103 - #endif 104 104 - } s; 105 105 - struct cvmx_l2d_bst2_s cn30xx; 106 106 - struct cvmx_l2d_bst2_s cn31xx; 107 107 - struct cvmx_l2d_bst2_s cn38xx; 108 108 - struct cvmx_l2d_bst2_s cn38xxp2; 109 109 - struct cvmx_l2d_bst2_s cn50xx; 110 110 - struct cvmx_l2d_bst2_s cn52xx; 111 111 - struct cvmx_l2d_bst2_s cn52xxp1; 112 112 - struct cvmx_l2d_bst2_s cn56xx; 113 113 - struct cvmx_l2d_bst2_s cn56xxp1; 114 114 - struct cvmx_l2d_bst2_s cn58xx; 115 115 - struct cvmx_l2d_bst2_s cn58xxp1; 116 116 - }; 117 117 - 118 118 - union cvmx_l2d_bst3 { 119 119 - uint64_t u64; 120 120 - struct cvmx_l2d_bst3_s { 121 121 - #ifdef __BIG_ENDIAN_BITFIELD 122 122 - uint64_t reserved_34_63:30; 123 123 - uint64_t q3stat:34; 124 124 - #else 125 125 - uint64_t q3stat:34; 126 126 - uint64_t reserved_34_63:30; 127 127 - #endif 128 128 - } s; 129 129 - struct cvmx_l2d_bst3_s cn30xx; 130 130 - struct cvmx_l2d_bst3_s cn31xx; 131 131 - struct cvmx_l2d_bst3_s cn38xx; 132 132 - struct cvmx_l2d_bst3_s cn38xxp2; 133 133 - struct cvmx_l2d_bst3_s cn50xx; 134 134 - struct cvmx_l2d_bst3_s cn52xx; 135 135 - struct cvmx_l2d_bst3_s cn52xxp1; 136 136 - struct cvmx_l2d_bst3_s cn56xx; 137 137 - struct cvmx_l2d_bst3_s cn56xxp1; 138 138 - struct cvmx_l2d_bst3_s cn58xx; 139 139 - struct cvmx_l2d_bst3_s cn58xxp1; 140 140 - }; 141 141 - 142 142 - union cvmx_l2d_err { 143 143 - uint64_t u64; 144 144 - struct cvmx_l2d_err_s { 145 145 - #ifdef __BIG_ENDIAN_BITFIELD 146 146 - uint64_t reserved_6_63:58; 147 147 - uint64_t bmhclsel:1; 148 148 - uint64_t ded_err:1; 149 149 - uint64_t sec_err:1; 150 150 - uint64_t ded_intena:1; 151 151 - uint64_t sec_intena:1; 152 152 - uint64_t ecc_ena:1; 153 153 - #else 154 154 - uint64_t ecc_ena:1; 155 155 - uint64_t sec_intena:1; 156 156 - uint64_t ded_intena:1; 157 157 - uint64_t sec_err:1; 158 158 - uint64_t ded_err:1; 159 159 - uint64_t bmhclsel:1; 160 160 - uint64_t reserved_6_63:58; 161 161 - #endif 162 162 - } s; 163 163 - struct cvmx_l2d_err_s cn30xx; 164 164 - struct cvmx_l2d_err_s cn31xx; 165 165 - struct cvmx_l2d_err_s cn38xx; 166 166 - struct cvmx_l2d_err_s cn38xxp2; 167 167 - struct cvmx_l2d_err_s cn50xx; 168 168 - struct cvmx_l2d_err_s cn52xx; 169 169 - struct cvmx_l2d_err_s cn52xxp1; 170 170 - struct cvmx_l2d_err_s cn56xx; 171 171 - struct cvmx_l2d_err_s cn56xxp1; 172 172 - struct cvmx_l2d_err_s cn58xx; 173 173 - struct cvmx_l2d_err_s cn58xxp1; 174 174 - }; 175 175 - 176 176 - union cvmx_l2d_fadr { 177 177 - uint64_t u64; 178 178 - struct cvmx_l2d_fadr_s { 179 179 - #ifdef __BIG_ENDIAN_BITFIELD 180 180 - uint64_t reserved_19_63:45; 181 181 - uint64_t fadru:1; 182 182 - uint64_t fowmsk:4; 183 183 - uint64_t fset:3; 184 184 - uint64_t fadr:11; 185 185 - #else 186 186 - uint64_t fadr:11; 187 187 - uint64_t fset:3; 188 188 - uint64_t fowmsk:4; 189 189 - uint64_t fadru:1; 190 190 - uint64_t reserved_19_63:45; 191 191 - #endif 192 192 - } s; 193 193 - struct cvmx_l2d_fadr_cn30xx { 194 194 - #ifdef __BIG_ENDIAN_BITFIELD 195 195 - uint64_t reserved_18_63:46; 196 196 - uint64_t fowmsk:4; 197 197 - uint64_t reserved_13_13:1; 198 198 - uint64_t fset:2; 199 199 - uint64_t reserved_9_10:2; 200 200 - uint64_t fadr:9; 201 201 - #else 202 202 - uint64_t fadr:9; 203 203 - uint64_t reserved_9_10:2; 204 204 - uint64_t fset:2; 205 205 - uint64_t reserved_13_13:1; 206 206 - uint64_t fowmsk:4; 207 207 - uint64_t reserved_18_63:46; 208 208 - #endif 209 209 - } cn30xx; 210 210 - struct cvmx_l2d_fadr_cn31xx { 211 211 - #ifdef __BIG_ENDIAN_BITFIELD 212 212 - uint64_t reserved_18_63:46; 213 213 - uint64_t fowmsk:4; 214 214 - uint64_t reserved_13_13:1; 215 215 - uint64_t fset:2; 216 216 - uint64_t reserved_10_10:1; 217 217 - uint64_t fadr:10; 218 218 - #else 219 219 - uint64_t fadr:10; 220 220 - uint64_t reserved_10_10:1; 221 221 - uint64_t fset:2; 222 222 - uint64_t reserved_13_13:1; 223 223 - uint64_t fowmsk:4; 224 224 - uint64_t reserved_18_63:46; 225 225 - #endif 226 226 - } cn31xx; 227 227 - struct cvmx_l2d_fadr_cn38xx { 228 228 - #ifdef __BIG_ENDIAN_BITFIELD 229 229 - uint64_t reserved_18_63:46; 230 230 - uint64_t fowmsk:4; 231 231 - uint64_t fset:3; 232 232 - uint64_t fadr:11; 233 233 - #else 234 234 - uint64_t fadr:11; 235 235 - uint64_t fset:3; 236 236 - uint64_t fowmsk:4; 237 237 - uint64_t reserved_18_63:46; 238 238 - #endif 239 239 - } cn38xx; 240 240 - struct cvmx_l2d_fadr_cn38xx cn38xxp2; 241 241 - struct cvmx_l2d_fadr_cn50xx { 242 242 - #ifdef __BIG_ENDIAN_BITFIELD 243 243 - uint64_t reserved_18_63:46; 244 244 - uint64_t fowmsk:4; 245 245 - uint64_t fset:3; 246 246 - uint64_t reserved_8_10:3; 247 247 - uint64_t fadr:8; 248 248 - #else 249 249 - uint64_t fadr:8; 250 250 - uint64_t reserved_8_10:3; 251 251 - uint64_t fset:3; 252 252 - uint64_t fowmsk:4; 253 253 - uint64_t reserved_18_63:46; 254 254 - #endif 255 255 - } cn50xx; 256 256 - struct cvmx_l2d_fadr_cn52xx { 257 257 - #ifdef __BIG_ENDIAN_BITFIELD 258 258 - uint64_t reserved_18_63:46; 259 259 - uint64_t fowmsk:4; 260 260 - uint64_t fset:3; 261 261 - uint64_t reserved_10_10:1; 262 262 - uint64_t fadr:10; 263 263 - #else 264 264 - uint64_t fadr:10; 265 265 - uint64_t reserved_10_10:1; 266 266 - uint64_t fset:3; 267 267 - uint64_t fowmsk:4; 268 268 - uint64_t reserved_18_63:46; 269 269 - #endif 270 270 - } cn52xx; 271 271 - struct cvmx_l2d_fadr_cn52xx cn52xxp1; 272 272 - struct cvmx_l2d_fadr_s cn56xx; 273 273 - struct cvmx_l2d_fadr_s cn56xxp1; 274 274 - struct cvmx_l2d_fadr_s cn58xx; 275 275 - struct cvmx_l2d_fadr_s cn58xxp1; 276 276 - }; 277 277 - 278 278 - union cvmx_l2d_fsyn0 { 279 279 - uint64_t u64; 280 280 - struct cvmx_l2d_fsyn0_s { 281 281 - #ifdef __BIG_ENDIAN_BITFIELD 282 282 - uint64_t reserved_20_63:44; 283 283 - uint64_t fsyn_ow1:10; 284 284 - uint64_t fsyn_ow0:10; 285 285 - #else 286 286 - uint64_t fsyn_ow0:10; 287 287 - uint64_t fsyn_ow1:10; 288 288 - uint64_t reserved_20_63:44; 289 289 - #endif 290 290 - } s; 291 291 - struct cvmx_l2d_fsyn0_s cn30xx; 292 292 - struct cvmx_l2d_fsyn0_s cn31xx; 293 293 - struct cvmx_l2d_fsyn0_s cn38xx; 294 294 - struct cvmx_l2d_fsyn0_s cn38xxp2; 295 295 - struct cvmx_l2d_fsyn0_s cn50xx; 296 296 - struct cvmx_l2d_fsyn0_s cn52xx; 297 297 - struct cvmx_l2d_fsyn0_s cn52xxp1; 298 298 - struct cvmx_l2d_fsyn0_s cn56xx; 299 299 - struct cvmx_l2d_fsyn0_s cn56xxp1; 300 300 - struct cvmx_l2d_fsyn0_s cn58xx; 301 301 - struct cvmx_l2d_fsyn0_s cn58xxp1; 302 302 - }; 303 303 - 304 304 - union cvmx_l2d_fsyn1 { 305 305 - uint64_t u64; 306 306 - struct cvmx_l2d_fsyn1_s { 307 307 - #ifdef __BIG_ENDIAN_BITFIELD 308 308 - uint64_t reserved_20_63:44; 309 309 - uint64_t fsyn_ow3:10; 310 310 - uint64_t fsyn_ow2:10; 311 311 - #else 312 312 - uint64_t fsyn_ow2:10; 313 313 - uint64_t fsyn_ow3:10; 314 314 - uint64_t reserved_20_63:44; 315 315 - #endif 316 316 - } s; 317 317 - struct cvmx_l2d_fsyn1_s cn30xx; 318 318 - struct cvmx_l2d_fsyn1_s cn31xx; 319 319 - struct cvmx_l2d_fsyn1_s cn38xx; 320 320 - struct cvmx_l2d_fsyn1_s cn38xxp2; 321 321 - struct cvmx_l2d_fsyn1_s cn50xx; 322 322 - struct cvmx_l2d_fsyn1_s cn52xx; 323 323 - struct cvmx_l2d_fsyn1_s cn52xxp1; 324 324 - struct cvmx_l2d_fsyn1_s cn56xx; 325 325 - struct cvmx_l2d_fsyn1_s cn56xxp1; 326 326 - struct cvmx_l2d_fsyn1_s cn58xx; 327 327 - struct cvmx_l2d_fsyn1_s cn58xxp1; 328 328 - }; 329 329 - 330 330 - union cvmx_l2d_fus0 { 331 331 - uint64_t u64; 332 332 - struct cvmx_l2d_fus0_s { 333 333 - #ifdef __BIG_ENDIAN_BITFIELD 334 334 - uint64_t reserved_34_63:30; 335 335 - uint64_t q0fus:34; 336 336 - #else 337 337 - uint64_t q0fus:34; 338 338 - uint64_t reserved_34_63:30; 339 339 - #endif 340 340 - } s; 341 341 - struct cvmx_l2d_fus0_s cn30xx; 342 342 - struct cvmx_l2d_fus0_s cn31xx; 343 343 - struct cvmx_l2d_fus0_s cn38xx; 344 344 - struct cvmx_l2d_fus0_s cn38xxp2; 345 345 - struct cvmx_l2d_fus0_s cn50xx; 346 346 - struct cvmx_l2d_fus0_s cn52xx; 347 347 - struct cvmx_l2d_fus0_s cn52xxp1; 348 348 - struct cvmx_l2d_fus0_s cn56xx; 349 349 - struct cvmx_l2d_fus0_s cn56xxp1; 350 350 - struct cvmx_l2d_fus0_s cn58xx; 351 351 - struct cvmx_l2d_fus0_s cn58xxp1; 352 352 - }; 353 353 - 354 354 - union cvmx_l2d_fus1 { 355 355 - uint64_t u64; 356 356 - struct cvmx_l2d_fus1_s { 357 357 - #ifdef __BIG_ENDIAN_BITFIELD 358 358 - uint64_t reserved_34_63:30; 359 359 - uint64_t q1fus:34; 360 360 - #else 361 361 - uint64_t q1fus:34; 362 362 - uint64_t reserved_34_63:30; 363 363 - #endif 364 364 - } s; 365 365 - struct cvmx_l2d_fus1_s cn30xx; 366 366 - struct cvmx_l2d_fus1_s cn31xx; 367 367 - struct cvmx_l2d_fus1_s cn38xx; 368 368 - struct cvmx_l2d_fus1_s cn38xxp2; 369 369 - struct cvmx_l2d_fus1_s cn50xx; 370 370 - struct cvmx_l2d_fus1_s cn52xx; 371 371 - struct cvmx_l2d_fus1_s cn52xxp1; 372 372 - struct cvmx_l2d_fus1_s cn56xx; 373 373 - struct cvmx_l2d_fus1_s cn56xxp1; 374 374 - struct cvmx_l2d_fus1_s cn58xx; 375 375 - struct cvmx_l2d_fus1_s cn58xxp1; 376 376 - }; 377 377 - 378 378 - union cvmx_l2d_fus2 { 379 379 - uint64_t u64; 380 380 - struct cvmx_l2d_fus2_s { 381 381 - #ifdef __BIG_ENDIAN_BITFIELD 382 382 - uint64_t reserved_34_63:30; 383 383 - uint64_t q2fus:34; 384 384 - #else 385 385 - uint64_t q2fus:34; 386 386 - uint64_t reserved_34_63:30; 387 387 - #endif 388 388 - } s; 389 389 - struct cvmx_l2d_fus2_s cn30xx; 390 390 - struct cvmx_l2d_fus2_s cn31xx; 391 391 - struct cvmx_l2d_fus2_s cn38xx; 392 392 - struct cvmx_l2d_fus2_s cn38xxp2; 393 393 - struct cvmx_l2d_fus2_s cn50xx; 394 394 - struct cvmx_l2d_fus2_s cn52xx; 395 395 - struct cvmx_l2d_fus2_s cn52xxp1; 396 396 - struct cvmx_l2d_fus2_s cn56xx; 397 397 - struct cvmx_l2d_fus2_s cn56xxp1; 398 398 - struct cvmx_l2d_fus2_s cn58xx; 399 399 - struct cvmx_l2d_fus2_s cn58xxp1; 400 400 - }; 401 401 - 402 402 - union cvmx_l2d_fus3 { 403 403 - uint64_t u64; 404 404 - struct cvmx_l2d_fus3_s { 405 405 - #ifdef __BIG_ENDIAN_BITFIELD 406 406 - uint64_t reserved_40_63:24; 407 407 - uint64_t ema_ctl:3; 408 408 - uint64_t reserved_34_36:3; 409 409 - uint64_t q3fus:34; 410 410 - #else 411 411 - uint64_t q3fus:34; 412 412 - uint64_t reserved_34_36:3; 413 413 - uint64_t ema_ctl:3; 414 414 - uint64_t reserved_40_63:24; 415 415 - #endif 416 416 - } s; 417 417 - struct cvmx_l2d_fus3_cn30xx { 418 418 - #ifdef __BIG_ENDIAN_BITFIELD 419 419 - uint64_t reserved_35_63:29; 420 420 - uint64_t crip_64k:1; 421 421 - uint64_t q3fus:34; 422 422 - #else 423 423 - uint64_t q3fus:34; 424 424 - uint64_t crip_64k:1; 425 425 - uint64_t reserved_35_63:29; 426 426 - #endif 427 427 - } cn30xx; 428 428 - struct cvmx_l2d_fus3_cn31xx { 429 429 - #ifdef __BIG_ENDIAN_BITFIELD 430 430 - uint64_t reserved_35_63:29; 431 431 - uint64_t crip_128k:1; 432 432 - uint64_t q3fus:34; 433 433 - #else 434 434 - uint64_t q3fus:34; 435 435 - uint64_t crip_128k:1; 436 436 - uint64_t reserved_35_63:29; 437 437 - #endif 438 438 - } cn31xx; 439 439 - struct cvmx_l2d_fus3_cn38xx { 440 440 - #ifdef __BIG_ENDIAN_BITFIELD 441 441 - uint64_t reserved_36_63:28; 442 442 - uint64_t crip_256k:1; 443 443 - uint64_t crip_512k:1; 444 444 - uint64_t q3fus:34; 445 445 - #else 446 446 - uint64_t q3fus:34; 447 447 - uint64_t crip_512k:1; 448 448 - uint64_t crip_256k:1; 449 449 - uint64_t reserved_36_63:28; 450 450 - #endif 451 451 - } cn38xx; 452 452 - struct cvmx_l2d_fus3_cn38xx cn38xxp2; 453 453 - struct cvmx_l2d_fus3_cn50xx { 454 454 - #ifdef __BIG_ENDIAN_BITFIELD 455 455 - uint64_t reserved_40_63:24; 456 456 - uint64_t ema_ctl:3; 457 457 - uint64_t reserved_36_36:1; 458 458 - uint64_t crip_32k:1; 459 459 - uint64_t crip_64k:1; 460 460 - uint64_t q3fus:34; 461 461 - #else 462 462 - uint64_t q3fus:34; 463 463 - uint64_t crip_64k:1; 464 464 - uint64_t crip_32k:1; 465 465 - uint64_t reserved_36_36:1; 466 466 - uint64_t ema_ctl:3; 467 467 - uint64_t reserved_40_63:24; 468 468 - #endif 469 469 - } cn50xx; 470 470 - struct cvmx_l2d_fus3_cn52xx { 471 471 - #ifdef __BIG_ENDIAN_BITFIELD 472 472 - uint64_t reserved_40_63:24; 473 473 - uint64_t ema_ctl:3; 474 474 - uint64_t reserved_36_36:1; 475 475 - uint64_t crip_128k:1; 476 476 - uint64_t crip_256k:1; 477 477 - uint64_t q3fus:34; 478 478 - #else 479 479 - uint64_t q3fus:34; 480 480 - uint64_t crip_256k:1; 481 481 - uint64_t crip_128k:1; 482 482 - uint64_t reserved_36_36:1; 483 483 - uint64_t ema_ctl:3; 484 484 - uint64_t reserved_40_63:24; 485 485 - #endif 486 486 - } cn52xx; 487 487 - struct cvmx_l2d_fus3_cn52xx cn52xxp1; 488 488 - struct cvmx_l2d_fus3_cn56xx { 489 489 - #ifdef __BIG_ENDIAN_BITFIELD 490 490 - uint64_t reserved_40_63:24; 491 491 - uint64_t ema_ctl:3; 492 492 - uint64_t reserved_36_36:1; 493 493 - uint64_t crip_512k:1; 494 494 - uint64_t crip_1024k:1; 495 495 - uint64_t q3fus:34; 496 496 - #else 497 497 - uint64_t q3fus:34; 498 498 - uint64_t crip_1024k:1; 499 499 - uint64_t crip_512k:1; 500 500 - uint64_t reserved_36_36:1; 501 501 - uint64_t ema_ctl:3; 502 502 - uint64_t reserved_40_63:24; 503 503 - #endif 504 504 - } cn56xx; 505 505 - struct cvmx_l2d_fus3_cn56xx cn56xxp1; 506 506 - struct cvmx_l2d_fus3_cn58xx { 507 507 - #ifdef __BIG_ENDIAN_BITFIELD 508 508 - uint64_t reserved_39_63:25; 509 509 - uint64_t ema_ctl:2; 510 510 - uint64_t reserved_36_36:1; 511 511 - uint64_t crip_512k:1; 512 512 - uint64_t crip_1024k:1; 513 513 - uint64_t q3fus:34; 514 514 - #else 515 515 - uint64_t q3fus:34; 516 516 - uint64_t crip_1024k:1; 517 517 - uint64_t crip_512k:1; 518 518 - uint64_t reserved_36_36:1; 519 519 - uint64_t ema_ctl:2; 520 520 - uint64_t reserved_39_63:25; 521 521 - #endif 522 522 - } cn58xx; 523 523 - struct cvmx_l2d_fus3_cn58xx cn58xxp1; 524 524 - }; 525 525 - 526 526 - #endif

+96 -190

arch/mips/include/asm/octeon/cvmx-l2t-defs.h

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2012 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 28 28 #ifndef __CVMX_L2T_DEFS_H__ 29 29 #define __CVMX_L2T_DEFS_H__ 30 30 31 31 - #define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) 31 31 + #include <uapi/asm/bitfield.h> 32 32 + 33 33 + #define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) 34 34 + 32 35 33 36 union cvmx_l2t_err { 34 37 uint64_t u64; 35 38 struct cvmx_l2t_err_s { 36 36 - #ifdef __BIG_ENDIAN_BITFIELD 37 37 - uint64_t reserved_29_63:35; 38 38 - uint64_t fadru:1; 39 39 - uint64_t lck_intena2:1; 40 40 - uint64_t lckerr2:1; 41 41 - uint64_t lck_intena:1; 42 42 - uint64_t lckerr:1; 43 43 - uint64_t fset:3; 44 44 - uint64_t fadr:10; 45 45 - uint64_t fsyn:6; 46 46 - uint64_t ded_err:1; 47 47 - uint64_t sec_err:1; 48 48 - uint64_t ded_intena:1; 49 49 - uint64_t sec_intena:1; 50 50 - uint64_t ecc_ena:1; 51 51 - #else 52 52 - uint64_t ecc_ena:1; 53 53 - uint64_t sec_intena:1; 54 54 - uint64_t ded_intena:1; 55 55 - uint64_t sec_err:1; 56 56 - uint64_t ded_err:1; 57 57 - uint64_t fsyn:6; 58 58 - uint64_t fadr:10; 59 59 - uint64_t fset:3; 60 60 - uint64_t lckerr:1; 61 61 - uint64_t lck_intena:1; 62 62 - uint64_t lckerr2:1; 63 63 - uint64_t lck_intena2:1; 64 64 - uint64_t fadru:1; 65 65 - uint64_t reserved_29_63:35; 66 66 - #endif 39 39 + __BITFIELD_FIELD(uint64_t reserved_29_63:35, 40 40 + __BITFIELD_FIELD(uint64_t fadru:1, 41 41 + __BITFIELD_FIELD(uint64_t lck_intena2:1, 42 42 + __BITFIELD_FIELD(uint64_t lckerr2:1, 43 43 + __BITFIELD_FIELD(uint64_t lck_intena:1, 44 44 + __BITFIELD_FIELD(uint64_t lckerr:1, 45 45 + __BITFIELD_FIELD(uint64_t fset:3, 46 46 + __BITFIELD_FIELD(uint64_t fadr:10, 47 47 + __BITFIELD_FIELD(uint64_t fsyn:6, 48 48 + __BITFIELD_FIELD(uint64_t ded_err:1, 49 49 + __BITFIELD_FIELD(uint64_t sec_err:1, 50 50 + __BITFIELD_FIELD(uint64_t ded_intena:1, 51 51 + __BITFIELD_FIELD(uint64_t sec_intena:1, 52 52 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 53 53 + ;)))))))))))))) 67 54 } s; 68 55 struct cvmx_l2t_err_cn30xx { 69 69 - #ifdef __BIG_ENDIAN_BITFIELD 70 70 - uint64_t reserved_28_63:36; 71 71 - uint64_t lck_intena2:1; 72 72 - uint64_t lckerr2:1; 73 73 - uint64_t lck_intena:1; 74 74 - uint64_t lckerr:1; 75 75 - uint64_t reserved_23_23:1; 76 76 - uint64_t fset:2; 77 77 - uint64_t reserved_19_20:2; 78 78 - uint64_t fadr:8; 79 79 - uint64_t fsyn:6; 80 80 - uint64_t ded_err:1; 81 81 - uint64_t sec_err:1; 82 82 - uint64_t ded_intena:1; 83 83 - uint64_t sec_intena:1; 84 84 - uint64_t ecc_ena:1; 85 85 - #else 86 86 - uint64_t ecc_ena:1; 87 87 - uint64_t sec_intena:1; 88 88 - uint64_t ded_intena:1; 89 89 - uint64_t sec_err:1; 90 90 - uint64_t ded_err:1; 91 91 - uint64_t fsyn:6; 92 92 - uint64_t fadr:8; 93 93 - uint64_t reserved_19_20:2; 94 94 - uint64_t fset:2; 95 95 - uint64_t reserved_23_23:1; 96 96 - uint64_t lckerr:1; 97 97 - uint64_t lck_intena:1; 98 98 - uint64_t lckerr2:1; 99 99 - uint64_t lck_intena2:1; 100 100 - uint64_t reserved_28_63:36; 101 101 - #endif 56 56 + __BITFIELD_FIELD(uint64_t reserved_28_63:36, 57 57 + __BITFIELD_FIELD(uint64_t lck_intena2:1, 58 58 + __BITFIELD_FIELD(uint64_t lckerr2:1, 59 59 + __BITFIELD_FIELD(uint64_t lck_intena:1, 60 60 + __BITFIELD_FIELD(uint64_t lckerr:1, 61 61 + __BITFIELD_FIELD(uint64_t reserved_23_23:1, 62 62 + __BITFIELD_FIELD(uint64_t fset:2, 63 63 + __BITFIELD_FIELD(uint64_t reserved_19_20:2, 64 64 + __BITFIELD_FIELD(uint64_t fadr:8, 65 65 + __BITFIELD_FIELD(uint64_t fsyn:6, 66 66 + __BITFIELD_FIELD(uint64_t ded_err:1, 67 67 + __BITFIELD_FIELD(uint64_t sec_err:1, 68 68 + __BITFIELD_FIELD(uint64_t ded_intena:1, 69 69 + __BITFIELD_FIELD(uint64_t sec_intena:1, 70 70 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 71 71 + ;))))))))))))))) 102 72 } cn30xx; 103 73 struct cvmx_l2t_err_cn31xx { 104 104 - #ifdef __BIG_ENDIAN_BITFIELD 105 105 - uint64_t reserved_28_63:36; 106 106 - uint64_t lck_intena2:1; 107 107 - uint64_t lckerr2:1; 108 108 - uint64_t lck_intena:1; 109 109 - uint64_t lckerr:1; 110 110 - uint64_t reserved_23_23:1; 111 111 - uint64_t fset:2; 112 112 - uint64_t reserved_20_20:1; 113 113 - uint64_t fadr:9; 114 114 - uint64_t fsyn:6; 115 115 - uint64_t ded_err:1; 116 116 - uint64_t sec_err:1; 117 117 - uint64_t ded_intena:1; 118 118 - uint64_t sec_intena:1; 119 119 - uint64_t ecc_ena:1; 120 120 - #else 121 121 - uint64_t ecc_ena:1; 122 122 - uint64_t sec_intena:1; 123 123 - uint64_t ded_intena:1; 124 124 - uint64_t sec_err:1; 125 125 - uint64_t ded_err:1; 126 126 - uint64_t fsyn:6; 127 127 - uint64_t fadr:9; 128 128 - uint64_t reserved_20_20:1; 129 129 - uint64_t fset:2; 130 130 - uint64_t reserved_23_23:1; 131 131 - uint64_t lckerr:1; 132 132 - uint64_t lck_intena:1; 133 133 - uint64_t lckerr2:1; 134 134 - uint64_t lck_intena2:1; 135 135 - uint64_t reserved_28_63:36; 136 136 - #endif 74 74 + __BITFIELD_FIELD(uint64_t reserved_28_63:36, 75 75 + __BITFIELD_FIELD(uint64_t lck_intena2:1, 76 76 + __BITFIELD_FIELD(uint64_t lckerr2:1, 77 77 + __BITFIELD_FIELD(uint64_t lck_intena:1, 78 78 + __BITFIELD_FIELD(uint64_t lckerr:1, 79 79 + __BITFIELD_FIELD(uint64_t reserved_23_23:1, 80 80 + __BITFIELD_FIELD(uint64_t fset:2, 81 81 + __BITFIELD_FIELD(uint64_t reserved_20_20:1, 82 82 + __BITFIELD_FIELD(uint64_t fadr:9, 83 83 + __BITFIELD_FIELD(uint64_t fsyn:6, 84 84 + __BITFIELD_FIELD(uint64_t ded_err:1, 85 85 + __BITFIELD_FIELD(uint64_t sec_err:1, 86 86 + __BITFIELD_FIELD(uint64_t ded_intena:1, 87 87 + __BITFIELD_FIELD(uint64_t sec_intena:1, 88 88 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 89 89 + ;))))))))))))))) 137 90 } cn31xx; 138 91 struct cvmx_l2t_err_cn38xx { 139 139 - #ifdef __BIG_ENDIAN_BITFIELD 140 140 - uint64_t reserved_28_63:36; 141 141 - uint64_t lck_intena2:1; 142 142 - uint64_t lckerr2:1; 143 143 - uint64_t lck_intena:1; 144 144 - uint64_t lckerr:1; 145 145 - uint64_t fset:3; 146 146 - uint64_t fadr:10; 147 147 - uint64_t fsyn:6; 148 148 - uint64_t ded_err:1; 149 149 - uint64_t sec_err:1; 150 150 - uint64_t ded_intena:1; 151 151 - uint64_t sec_intena:1; 152 152 - uint64_t ecc_ena:1; 153 153 - #else 154 154 - uint64_t ecc_ena:1; 155 155 - uint64_t sec_intena:1; 156 156 - uint64_t ded_intena:1; 157 157 - uint64_t sec_err:1; 158 158 - uint64_t ded_err:1; 159 159 - uint64_t fsyn:6; 160 160 - uint64_t fadr:10; 161 161 - uint64_t fset:3; 162 162 - uint64_t lckerr:1; 163 163 - uint64_t lck_intena:1; 164 164 - uint64_t lckerr2:1; 165 165 - uint64_t lck_intena2:1; 166 166 - uint64_t reserved_28_63:36; 167 167 - #endif 92 92 + __BITFIELD_FIELD(uint64_t reserved_28_63:36, 93 93 + __BITFIELD_FIELD(uint64_t lck_intena2:1, 94 94 + __BITFIELD_FIELD(uint64_t lckerr2:1, 95 95 + __BITFIELD_FIELD(uint64_t lck_intena:1, 96 96 + __BITFIELD_FIELD(uint64_t lckerr:1, 97 97 + __BITFIELD_FIELD(uint64_t fset:3, 98 98 + __BITFIELD_FIELD(uint64_t fadr:10, 99 99 + __BITFIELD_FIELD(uint64_t fsyn:6, 100 100 + __BITFIELD_FIELD(uint64_t ded_err:1, 101 101 + __BITFIELD_FIELD(uint64_t sec_err:1, 102 102 + __BITFIELD_FIELD(uint64_t ded_intena:1, 103 103 + __BITFIELD_FIELD(uint64_t sec_intena:1, 104 104 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 105 105 + ;))))))))))))) 168 106 } cn38xx; 169 107 struct cvmx_l2t_err_cn38xx cn38xxp2; 170 108 struct cvmx_l2t_err_cn50xx { 171 171 - #ifdef __BIG_ENDIAN_BITFIELD 172 172 - uint64_t reserved_28_63:36; 173 173 - uint64_t lck_intena2:1; 174 174 - uint64_t lckerr2:1; 175 175 - uint64_t lck_intena:1; 176 176 - uint64_t lckerr:1; 177 177 - uint64_t fset:3; 178 178 - uint64_t reserved_18_20:3; 179 179 - uint64_t fadr:7; 180 180 - uint64_t fsyn:6; 181 181 - uint64_t ded_err:1; 182 182 - uint64_t sec_err:1; 183 183 - uint64_t ded_intena:1; 184 184 - uint64_t sec_intena:1; 185 185 - uint64_t ecc_ena:1; 186 186 - #else 187 187 - uint64_t ecc_ena:1; 188 188 - uint64_t sec_intena:1; 189 189 - uint64_t ded_intena:1; 190 190 - uint64_t sec_err:1; 191 191 - uint64_t ded_err:1; 192 192 - uint64_t fsyn:6; 193 193 - uint64_t fadr:7; 194 194 - uint64_t reserved_18_20:3; 195 195 - uint64_t fset:3; 196 196 - uint64_t lckerr:1; 197 197 - uint64_t lck_intena:1; 198 198 - uint64_t lckerr2:1; 199 199 - uint64_t lck_intena2:1; 200 200 - uint64_t reserved_28_63:36; 201 201 - #endif 109 109 + __BITFIELD_FIELD(uint64_t reserved_28_63:36, 110 110 + __BITFIELD_FIELD(uint64_t lck_intena2:1, 111 111 + __BITFIELD_FIELD(uint64_t lckerr2:1, 112 112 + __BITFIELD_FIELD(uint64_t lck_intena:1, 113 113 + __BITFIELD_FIELD(uint64_t lckerr:1, 114 114 + __BITFIELD_FIELD(uint64_t fset:3, 115 115 + __BITFIELD_FIELD(uint64_t reserved_18_20:3, 116 116 + __BITFIELD_FIELD(uint64_t fadr:7, 117 117 + __BITFIELD_FIELD(uint64_t fsyn:6, 118 118 + __BITFIELD_FIELD(uint64_t ded_err:1, 119 119 + __BITFIELD_FIELD(uint64_t sec_err:1, 120 120 + __BITFIELD_FIELD(uint64_t ded_intena:1, 121 121 + __BITFIELD_FIELD(uint64_t sec_intena:1, 122 122 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 123 123 + ;)))))))))))))) 202 124 } cn50xx; 203 125 struct cvmx_l2t_err_cn52xx { 204 204 - #ifdef __BIG_ENDIAN_BITFIELD 205 205 - uint64_t reserved_28_63:36; 206 206 - uint64_t lck_intena2:1; 207 207 - uint64_t lckerr2:1; 208 208 - uint64_t lck_intena:1; 209 209 - uint64_t lckerr:1; 210 210 - uint64_t fset:3; 211 211 - uint64_t reserved_20_20:1; 212 212 - uint64_t fadr:9; 213 213 - uint64_t fsyn:6; 214 214 - uint64_t ded_err:1; 215 215 - uint64_t sec_err:1; 216 216 - uint64_t ded_intena:1; 217 217 - uint64_t sec_intena:1; 218 218 - uint64_t ecc_ena:1; 219 219 - #else 220 220 - uint64_t ecc_ena:1; 221 221 - uint64_t sec_intena:1; 222 222 - uint64_t ded_intena:1; 223 223 - uint64_t sec_err:1; 224 224 - uint64_t ded_err:1; 225 225 - uint64_t fsyn:6; 226 226 - uint64_t fadr:9; 227 227 - uint64_t reserved_20_20:1; 228 228 - uint64_t fset:3; 229 229 - uint64_t lckerr:1; 230 230 - uint64_t lck_intena:1; 231 231 - uint64_t lckerr2:1; 232 232 - uint64_t lck_intena2:1; 233 233 - uint64_t reserved_28_63:36; 234 234 - #endif 126 126 + __BITFIELD_FIELD(uint64_t reserved_28_63:36, 127 127 + __BITFIELD_FIELD(uint64_t lck_intena2:1, 128 128 + __BITFIELD_FIELD(uint64_t lckerr2:1, 129 129 + __BITFIELD_FIELD(uint64_t lck_intena:1, 130 130 + __BITFIELD_FIELD(uint64_t lckerr:1, 131 131 + __BITFIELD_FIELD(uint64_t fset:3, 132 132 + __BITFIELD_FIELD(uint64_t reserved_20_20:1, 133 133 + __BITFIELD_FIELD(uint64_t fadr:9, 134 134 + __BITFIELD_FIELD(uint64_t fsyn:6, 135 135 + __BITFIELD_FIELD(uint64_t ded_err:1, 136 136 + __BITFIELD_FIELD(uint64_t sec_err:1, 137 137 + __BITFIELD_FIELD(uint64_t ded_intena:1, 138 138 + __BITFIELD_FIELD(uint64_t sec_intena:1, 139 139 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 140 140 + ;)))))))))))))) 235 141 } cn52xx; 236 142 struct cvmx_l2t_err_cn52xx cn52xxp1; 237 143 struct cvmx_l2t_err_s cn56xx;

+209 -3016

arch/mips/include/asm/octeon/cvmx-pciercx-defs.h

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2012 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 28 28 #ifndef __CVMX_PCIERCX_DEFS_H__ 29 29 #define __CVMX_PCIERCX_DEFS_H__ 30 30 31 31 - #define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) 31 31 + #include <uapi/asm/bitfield.h> 32 32 + 32 33 #define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) 33 33 - #define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull) 34 34 - #define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull) 35 35 - #define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull) 36 36 - #define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull) 37 34 #define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) 38 38 - #define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull) 39 35 #define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) 40 36 #define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) 41 37 #define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) 42 38 #define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) 43 43 - #define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull) 44 44 - #define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull) 45 45 - #define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull) 46 46 - #define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull) 47 47 - #define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull) 48 48 - #define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull) 49 49 - #define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull) 50 50 - #define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull) 51 51 - #define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull) 52 52 - #define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull) 53 53 - #define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull) 54 54 - #define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull) 55 39 #define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) 56 40 #define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) 57 41 #define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) 58 58 - #define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull) 59 42 #define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) 60 43 #define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) 61 61 - #define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull) 62 62 - #define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull) 63 63 - #define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull) 64 64 - #define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull) 65 44 #define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) 66 66 - #define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull) 67 67 - #define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull) 68 68 - #define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull) 69 69 - #define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull) 70 45 #define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) 71 71 - #define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull) 72 72 - #define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull) 73 46 #define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) 74 47 #define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) 75 75 - #define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull) 76 76 - #define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull) 77 77 - #define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull) 78 78 - #define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull) 79 48 #define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) 80 80 - #define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull) 81 81 - #define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull) 82 49 #define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) 83 83 - #define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull) 84 84 - #define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull) 85 85 - #define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull) 86 50 #define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) 87 87 - #define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull) 88 88 - #define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull) 89 51 #define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) 90 90 - #define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull) 91 91 - #define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull) 92 92 - #define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull) 93 93 - #define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull) 94 94 - #define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull) 95 95 - #define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull) 96 96 - #define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull) 97 97 - #define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull) 98 98 - #define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull) 99 99 - #define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull) 100 100 - #define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull) 101 101 - #define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull) 102 102 - #define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull) 103 103 - #define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull) 104 104 - #define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull) 105 52 #define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) 106 106 - #define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull) 107 107 - #define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull) 108 108 - 109 109 - union cvmx_pciercx_cfg000 { 110 110 - uint32_t u32; 111 111 - struct cvmx_pciercx_cfg000_s { 112 112 - #ifdef __BIG_ENDIAN_BITFIELD 113 113 - uint32_t devid:16; 114 114 - uint32_t vendid:16; 115 115 - #else 116 116 - uint32_t vendid:16; 117 117 - uint32_t devid:16; 118 118 - #endif 119 119 - } s; 120 120 - struct cvmx_pciercx_cfg000_s cn52xx; 121 121 - struct cvmx_pciercx_cfg000_s cn52xxp1; 122 122 - struct cvmx_pciercx_cfg000_s cn56xx; 123 123 - struct cvmx_pciercx_cfg000_s cn56xxp1; 124 124 - struct cvmx_pciercx_cfg000_s cn61xx; 125 125 - struct cvmx_pciercx_cfg000_s cn63xx; 126 126 - struct cvmx_pciercx_cfg000_s cn63xxp1; 127 127 - struct cvmx_pciercx_cfg000_s cn66xx; 128 128 - struct cvmx_pciercx_cfg000_s cn68xx; 129 129 - struct cvmx_pciercx_cfg000_s cn68xxp1; 130 130 - struct cvmx_pciercx_cfg000_s cnf71xx; 131 131 - }; 132 53 133 54 union cvmx_pciercx_cfg001 { 134 55 uint32_t u32; 135 56 struct cvmx_pciercx_cfg001_s { 136 136 - #ifdef __BIG_ENDIAN_BITFIELD 137 137 - uint32_t dpe:1; 138 138 - uint32_t sse:1; 139 139 - uint32_t rma:1; 140 140 - uint32_t rta:1; 141 141 - uint32_t sta:1; 142 142 - uint32_t devt:2; 143 143 - uint32_t mdpe:1; 144 144 - uint32_t fbb:1; 145 145 - uint32_t reserved_22_22:1; 146 146 - uint32_t m66:1; 147 147 - uint32_t cl:1; 148 148 - uint32_t i_stat:1; 149 149 - uint32_t reserved_11_18:8; 150 150 - uint32_t i_dis:1; 151 151 - uint32_t fbbe:1; 152 152 - uint32_t see:1; 153 153 - uint32_t ids_wcc:1; 154 154 - uint32_t per:1; 155 155 - uint32_t vps:1; 156 156 - uint32_t mwice:1; 157 157 - uint32_t scse:1; 158 158 - uint32_t me:1; 159 159 - uint32_t msae:1; 160 160 - uint32_t isae:1; 161 161 - #else 162 162 - uint32_t isae:1; 163 163 - uint32_t msae:1; 164 164 - uint32_t me:1; 165 165 - uint32_t scse:1; 166 166 - uint32_t mwice:1; 167 167 - uint32_t vps:1; 168 168 - uint32_t per:1; 169 169 - uint32_t ids_wcc:1; 170 170 - uint32_t see:1; 171 171 - uint32_t fbbe:1; 172 172 - uint32_t i_dis:1; 173 173 - uint32_t reserved_11_18:8; 174 174 - uint32_t i_stat:1; 175 175 - uint32_t cl:1; 176 176 - uint32_t m66:1; 177 177 - uint32_t reserved_22_22:1; 178 178 - uint32_t fbb:1; 179 179 - uint32_t mdpe:1; 180 180 - uint32_t devt:2; 181 181 - uint32_t sta:1; 182 182 - uint32_t rta:1; 183 183 - uint32_t rma:1; 184 184 - uint32_t sse:1; 185 185 - uint32_t dpe:1; 186 186 - #endif 57 57 + __BITFIELD_FIELD(uint32_t dpe:1, 58 58 + __BITFIELD_FIELD(uint32_t sse:1, 59 59 + __BITFIELD_FIELD(uint32_t rma:1, 60 60 + __BITFIELD_FIELD(uint32_t rta:1, 61 61 + __BITFIELD_FIELD(uint32_t sta:1, 62 62 + __BITFIELD_FIELD(uint32_t devt:2, 63 63 + __BITFIELD_FIELD(uint32_t mdpe:1, 64 64 + __BITFIELD_FIELD(uint32_t fbb:1, 65 65 + __BITFIELD_FIELD(uint32_t reserved_22_22:1, 66 66 + __BITFIELD_FIELD(uint32_t m66:1, 67 67 + __BITFIELD_FIELD(uint32_t cl:1, 68 68 + __BITFIELD_FIELD(uint32_t i_stat:1, 69 69 + __BITFIELD_FIELD(uint32_t reserved_11_18:8, 70 70 + __BITFIELD_FIELD(uint32_t i_dis:1, 71 71 + __BITFIELD_FIELD(uint32_t fbbe:1, 72 72 + __BITFIELD_FIELD(uint32_t see:1, 73 73 + __BITFIELD_FIELD(uint32_t ids_wcc:1, 74 74 + __BITFIELD_FIELD(uint32_t per:1, 75 75 + __BITFIELD_FIELD(uint32_t vps:1, 76 76 + __BITFIELD_FIELD(uint32_t mwice:1, 77 77 + __BITFIELD_FIELD(uint32_t scse:1, 78 78 + __BITFIELD_FIELD(uint32_t me:1, 79 79 + __BITFIELD_FIELD(uint32_t msae:1, 80 80 + __BITFIELD_FIELD(uint32_t isae:1, 81 81 + ;)))))))))))))))))))))))) 187 82 } s; 188 188 - struct cvmx_pciercx_cfg001_s cn52xx; 189 189 - struct cvmx_pciercx_cfg001_s cn52xxp1; 190 190 - struct cvmx_pciercx_cfg001_s cn56xx; 191 191 - struct cvmx_pciercx_cfg001_s cn56xxp1; 192 192 - struct cvmx_pciercx_cfg001_s cn61xx; 193 193 - struct cvmx_pciercx_cfg001_s cn63xx; 194 194 - struct cvmx_pciercx_cfg001_s cn63xxp1; 195 195 - struct cvmx_pciercx_cfg001_s cn66xx; 196 196 - struct cvmx_pciercx_cfg001_s cn68xx; 197 197 - struct cvmx_pciercx_cfg001_s cn68xxp1; 198 198 - struct cvmx_pciercx_cfg001_s cnf71xx; 199 199 - }; 200 200 - 201 201 - union cvmx_pciercx_cfg002 { 202 202 - uint32_t u32; 203 203 - struct cvmx_pciercx_cfg002_s { 204 204 - #ifdef __BIG_ENDIAN_BITFIELD 205 205 - uint32_t bcc:8; 206 206 - uint32_t sc:8; 207 207 - uint32_t pi:8; 208 208 - uint32_t rid:8; 209 209 - #else 210 210 - uint32_t rid:8; 211 211 - uint32_t pi:8; 212 212 - uint32_t sc:8; 213 213 - uint32_t bcc:8; 214 214 - #endif 215 215 - } s; 216 216 - struct cvmx_pciercx_cfg002_s cn52xx; 217 217 - struct cvmx_pciercx_cfg002_s cn52xxp1; 218 218 - struct cvmx_pciercx_cfg002_s cn56xx; 219 219 - struct cvmx_pciercx_cfg002_s cn56xxp1; 220 220 - struct cvmx_pciercx_cfg002_s cn61xx; 221 221 - struct cvmx_pciercx_cfg002_s cn63xx; 222 222 - struct cvmx_pciercx_cfg002_s cn63xxp1; 223 223 - struct cvmx_pciercx_cfg002_s cn66xx; 224 224 - struct cvmx_pciercx_cfg002_s cn68xx; 225 225 - struct cvmx_pciercx_cfg002_s cn68xxp1; 226 226 - struct cvmx_pciercx_cfg002_s cnf71xx; 227 227 - }; 228 228 - 229 229 - union cvmx_pciercx_cfg003 { 230 230 - uint32_t u32; 231 231 - struct cvmx_pciercx_cfg003_s { 232 232 - #ifdef __BIG_ENDIAN_BITFIELD 233 233 - uint32_t bist:8; 234 234 - uint32_t mfd:1; 235 235 - uint32_t chf:7; 236 236 - uint32_t lt:8; 237 237 - uint32_t cls:8; 238 238 - #else 239 239 - uint32_t cls:8; 240 240 - uint32_t lt:8; 241 241 - uint32_t chf:7; 242 242 - uint32_t mfd:1; 243 243 - uint32_t bist:8; 244 244 - #endif 245 245 - } s; 246 246 - struct cvmx_pciercx_cfg003_s cn52xx; 247 247 - struct cvmx_pciercx_cfg003_s cn52xxp1; 248 248 - struct cvmx_pciercx_cfg003_s cn56xx; 249 249 - struct cvmx_pciercx_cfg003_s cn56xxp1; 250 250 - struct cvmx_pciercx_cfg003_s cn61xx; 251 251 - struct cvmx_pciercx_cfg003_s cn63xx; 252 252 - struct cvmx_pciercx_cfg003_s cn63xxp1; 253 253 - struct cvmx_pciercx_cfg003_s cn66xx; 254 254 - struct cvmx_pciercx_cfg003_s cn68xx; 255 255 - struct cvmx_pciercx_cfg003_s cn68xxp1; 256 256 - struct cvmx_pciercx_cfg003_s cnf71xx; 257 257 - }; 258 258 - 259 259 - union cvmx_pciercx_cfg004 { 260 260 - uint32_t u32; 261 261 - struct cvmx_pciercx_cfg004_s { 262 262 - #ifdef __BIG_ENDIAN_BITFIELD 263 263 - uint32_t reserved_0_31:32; 264 264 - #else 265 265 - uint32_t reserved_0_31:32; 266 266 - #endif 267 267 - } s; 268 268 - struct cvmx_pciercx_cfg004_s cn52xx; 269 269 - struct cvmx_pciercx_cfg004_s cn52xxp1; 270 270 - struct cvmx_pciercx_cfg004_s cn56xx; 271 271 - struct cvmx_pciercx_cfg004_s cn56xxp1; 272 272 - struct cvmx_pciercx_cfg004_s cn61xx; 273 273 - struct cvmx_pciercx_cfg004_s cn63xx; 274 274 - struct cvmx_pciercx_cfg004_s cn63xxp1; 275 275 - struct cvmx_pciercx_cfg004_s cn66xx; 276 276 - struct cvmx_pciercx_cfg004_s cn68xx; 277 277 - struct cvmx_pciercx_cfg004_s cn68xxp1; 278 278 - struct cvmx_pciercx_cfg004_s cnf71xx; 279 279 - }; 280 280 - 281 281 - union cvmx_pciercx_cfg005 { 282 282 - uint32_t u32; 283 283 - struct cvmx_pciercx_cfg005_s { 284 284 - #ifdef __BIG_ENDIAN_BITFIELD 285 285 - uint32_t reserved_0_31:32; 286 286 - #else 287 287 - uint32_t reserved_0_31:32; 288 288 - #endif 289 289 - } s; 290 290 - struct cvmx_pciercx_cfg005_s cn52xx; 291 291 - struct cvmx_pciercx_cfg005_s cn52xxp1; 292 292 - struct cvmx_pciercx_cfg005_s cn56xx; 293 293 - struct cvmx_pciercx_cfg005_s cn56xxp1; 294 294 - struct cvmx_pciercx_cfg005_s cn61xx; 295 295 - struct cvmx_pciercx_cfg005_s cn63xx; 296 296 - struct cvmx_pciercx_cfg005_s cn63xxp1; 297 297 - struct cvmx_pciercx_cfg005_s cn66xx; 298 298 - struct cvmx_pciercx_cfg005_s cn68xx; 299 299 - struct cvmx_pciercx_cfg005_s cn68xxp1; 300 300 - struct cvmx_pciercx_cfg005_s cnf71xx; 301 83 }; 302 84 303 85 union cvmx_pciercx_cfg006 { 304 86 uint32_t u32; 305 87 struct cvmx_pciercx_cfg006_s { 306 306 - #ifdef __BIG_ENDIAN_BITFIELD 307 307 - uint32_t slt:8; 308 308 - uint32_t subbnum:8; 309 309 - uint32_t sbnum:8; 310 310 - uint32_t pbnum:8; 311 311 - #else 312 312 - uint32_t pbnum:8; 313 313 - uint32_t sbnum:8; 314 314 - uint32_t subbnum:8; 315 315 - uint32_t slt:8; 316 316 - #endif 88 88 + __BITFIELD_FIELD(uint32_t slt:8, 89 89 + __BITFIELD_FIELD(uint32_t subbnum:8, 90 90 + __BITFIELD_FIELD(uint32_t sbnum:8, 91 91 + __BITFIELD_FIELD(uint32_t pbnum:8, 92 92 + ;)))) 317 93 } s; 318 318 - struct cvmx_pciercx_cfg006_s cn52xx; 319 319 - struct cvmx_pciercx_cfg006_s cn52xxp1; 320 320 - struct cvmx_pciercx_cfg006_s cn56xx; 321 321 - struct cvmx_pciercx_cfg006_s cn56xxp1; 322 322 - struct cvmx_pciercx_cfg006_s cn61xx; 323 323 - struct cvmx_pciercx_cfg006_s cn63xx; 324 324 - struct cvmx_pciercx_cfg006_s cn63xxp1; 325 325 - struct cvmx_pciercx_cfg006_s cn66xx; 326 326 - struct cvmx_pciercx_cfg006_s cn68xx; 327 327 - struct cvmx_pciercx_cfg006_s cn68xxp1; 328 328 - struct cvmx_pciercx_cfg006_s cnf71xx; 329 329 - }; 330 330 - 331 331 - union cvmx_pciercx_cfg007 { 332 332 - uint32_t u32; 333 333 - struct cvmx_pciercx_cfg007_s { 334 334 - #ifdef __BIG_ENDIAN_BITFIELD 335 335 - uint32_t dpe:1; 336 336 - uint32_t sse:1; 337 337 - uint32_t rma:1; 338 338 - uint32_t rta:1; 339 339 - uint32_t sta:1; 340 340 - uint32_t devt:2; 341 341 - uint32_t mdpe:1; 342 342 - uint32_t fbb:1; 343 343 - uint32_t reserved_22_22:1; 344 344 - uint32_t m66:1; 345 345 - uint32_t reserved_16_20:5; 346 346 - uint32_t lio_limi:4; 347 347 - uint32_t reserved_9_11:3; 348 348 - uint32_t io32b:1; 349 349 - uint32_t lio_base:4; 350 350 - uint32_t reserved_1_3:3; 351 351 - uint32_t io32a:1; 352 352 - #else 353 353 - uint32_t io32a:1; 354 354 - uint32_t reserved_1_3:3; 355 355 - uint32_t lio_base:4; 356 356 - uint32_t io32b:1; 357 357 - uint32_t reserved_9_11:3; 358 358 - uint32_t lio_limi:4; 359 359 - uint32_t reserved_16_20:5; 360 360 - uint32_t m66:1; 361 361 - uint32_t reserved_22_22:1; 362 362 - uint32_t fbb:1; 363 363 - uint32_t mdpe:1; 364 364 - uint32_t devt:2; 365 365 - uint32_t sta:1; 366 366 - uint32_t rta:1; 367 367 - uint32_t rma:1; 368 368 - uint32_t sse:1; 369 369 - uint32_t dpe:1; 370 370 - #endif 371 371 - } s; 372 372 - struct cvmx_pciercx_cfg007_s cn52xx; 373 373 - struct cvmx_pciercx_cfg007_s cn52xxp1; 374 374 - struct cvmx_pciercx_cfg007_s cn56xx; 375 375 - struct cvmx_pciercx_cfg007_s cn56xxp1; 376 376 - struct cvmx_pciercx_cfg007_s cn61xx; 377 377 - struct cvmx_pciercx_cfg007_s cn63xx; 378 378 - struct cvmx_pciercx_cfg007_s cn63xxp1; 379 379 - struct cvmx_pciercx_cfg007_s cn66xx; 380 380 - struct cvmx_pciercx_cfg007_s cn68xx; 381 381 - struct cvmx_pciercx_cfg007_s cn68xxp1; 382 382 - struct cvmx_pciercx_cfg007_s cnf71xx; 383 94 }; 384 95 385 96 union cvmx_pciercx_cfg008 { 386 97 uint32_t u32; 387 98 struct cvmx_pciercx_cfg008_s { 388 388 - #ifdef __BIG_ENDIAN_BITFIELD 389 389 - uint32_t ml_addr:12; 390 390 - uint32_t reserved_16_19:4; 391 391 - uint32_t mb_addr:12; 392 392 - uint32_t reserved_0_3:4; 393 393 - #else 394 394 - uint32_t reserved_0_3:4; 395 395 - uint32_t mb_addr:12; 396 396 - uint32_t reserved_16_19:4; 397 397 - uint32_t ml_addr:12; 398 398 - #endif 99 99 + __BITFIELD_FIELD(uint32_t ml_addr:12, 100 100 + __BITFIELD_FIELD(uint32_t reserved_16_19:4, 101 101 + __BITFIELD_FIELD(uint32_t mb_addr:12, 102 102 + __BITFIELD_FIELD(uint32_t reserved_0_3:4, 103 103 + ;)))) 399 104 } s; 400 400 - struct cvmx_pciercx_cfg008_s cn52xx; 401 401 - struct cvmx_pciercx_cfg008_s cn52xxp1; 402 402 - struct cvmx_pciercx_cfg008_s cn56xx; 403 403 - struct cvmx_pciercx_cfg008_s cn56xxp1; 404 404 - struct cvmx_pciercx_cfg008_s cn61xx; 405 405 - struct cvmx_pciercx_cfg008_s cn63xx; 406 406 - struct cvmx_pciercx_cfg008_s cn63xxp1; 407 407 - struct cvmx_pciercx_cfg008_s cn66xx; 408 408 - struct cvmx_pciercx_cfg008_s cn68xx; 409 409 - struct cvmx_pciercx_cfg008_s cn68xxp1; 410 410 - struct cvmx_pciercx_cfg008_s cnf71xx; 411 105 }; 412 106 413 107 union cvmx_pciercx_cfg009 { 414 108 uint32_t u32; 415 109 struct cvmx_pciercx_cfg009_s { 416 416 - #ifdef __BIG_ENDIAN_BITFIELD 417 417 - uint32_t lmem_limit:12; 418 418 - uint32_t reserved_17_19:3; 419 419 - uint32_t mem64b:1; 420 420 - uint32_t lmem_base:12; 421 421 - uint32_t reserved_1_3:3; 422 422 - uint32_t mem64a:1; 423 423 - #else 424 424 - uint32_t mem64a:1; 425 425 - uint32_t reserved_1_3:3; 426 426 - uint32_t lmem_base:12; 427 427 - uint32_t mem64b:1; 428 428 - uint32_t reserved_17_19:3; 429 429 - uint32_t lmem_limit:12; 430 430 - #endif 110 110 + __BITFIELD_FIELD(uint32_t lmem_limit:12, 111 111 + __BITFIELD_FIELD(uint32_t reserved_17_19:3, 112 112 + __BITFIELD_FIELD(uint32_t mem64b:1, 113 113 + __BITFIELD_FIELD(uint32_t lmem_base:12, 114 114 + __BITFIELD_FIELD(uint32_t reserved_1_3:3, 115 115 + __BITFIELD_FIELD(uint32_t mem64a:1, 116 116 + ;)))))) 431 117 } s; 432 432 - struct cvmx_pciercx_cfg009_s cn52xx; 433 433 - struct cvmx_pciercx_cfg009_s cn52xxp1; 434 434 - struct cvmx_pciercx_cfg009_s cn56xx; 435 435 - struct cvmx_pciercx_cfg009_s cn56xxp1; 436 436 - struct cvmx_pciercx_cfg009_s cn61xx; 437 437 - struct cvmx_pciercx_cfg009_s cn63xx; 438 438 - struct cvmx_pciercx_cfg009_s cn63xxp1; 439 439 - struct cvmx_pciercx_cfg009_s cn66xx; 440 440 - struct cvmx_pciercx_cfg009_s cn68xx; 441 441 - struct cvmx_pciercx_cfg009_s cn68xxp1; 442 442 - struct cvmx_pciercx_cfg009_s cnf71xx; 443 118 }; 444 119 445 120 union cvmx_pciercx_cfg010 { 446 121 uint32_t u32; 447 122 struct cvmx_pciercx_cfg010_s { 448 448 - #ifdef __BIG_ENDIAN_BITFIELD 449 449 - uint32_t umem_base:32; 450 450 - #else 451 451 - uint32_t umem_base:32; 452 452 - #endif 123 123 + uint32_t umem_base; 453 124 } s; 454 454 - struct cvmx_pciercx_cfg010_s cn52xx; 455 455 - struct cvmx_pciercx_cfg010_s cn52xxp1; 456 456 - struct cvmx_pciercx_cfg010_s cn56xx; 457 457 - struct cvmx_pciercx_cfg010_s cn56xxp1; 458 458 - struct cvmx_pciercx_cfg010_s cn61xx; 459 459 - struct cvmx_pciercx_cfg010_s cn63xx; 460 460 - struct cvmx_pciercx_cfg010_s cn63xxp1; 461 461 - struct cvmx_pciercx_cfg010_s cn66xx; 462 462 - struct cvmx_pciercx_cfg010_s cn68xx; 463 463 - struct cvmx_pciercx_cfg010_s cn68xxp1; 464 464 - struct cvmx_pciercx_cfg010_s cnf71xx; 465 125 }; 466 126 467 127 union cvmx_pciercx_cfg011 { 468 128 uint32_t u32; 469 129 struct cvmx_pciercx_cfg011_s { 470 470 - #ifdef __BIG_ENDIAN_BITFIELD 471 471 - uint32_t umem_limit:32; 472 472 - #else 473 473 - uint32_t umem_limit:32; 474 474 - #endif 130 130 + uint32_t umem_limit; 475 131 } s; 476 476 - struct cvmx_pciercx_cfg011_s cn52xx; 477 477 - struct cvmx_pciercx_cfg011_s cn52xxp1; 478 478 - struct cvmx_pciercx_cfg011_s cn56xx; 479 479 - struct cvmx_pciercx_cfg011_s cn56xxp1; 480 480 - struct cvmx_pciercx_cfg011_s cn61xx; 481 481 - struct cvmx_pciercx_cfg011_s cn63xx; 482 482 - struct cvmx_pciercx_cfg011_s cn63xxp1; 483 483 - struct cvmx_pciercx_cfg011_s cn66xx; 484 484 - struct cvmx_pciercx_cfg011_s cn68xx; 485 485 - struct cvmx_pciercx_cfg011_s cn68xxp1; 486 486 - struct cvmx_pciercx_cfg011_s cnf71xx; 487 487 - }; 488 488 - 489 489 - union cvmx_pciercx_cfg012 { 490 490 - uint32_t u32; 491 491 - struct cvmx_pciercx_cfg012_s { 492 492 - #ifdef __BIG_ENDIAN_BITFIELD 493 493 - uint32_t uio_limit:16; 494 494 - uint32_t uio_base:16; 495 495 - #else 496 496 - uint32_t uio_base:16; 497 497 - uint32_t uio_limit:16; 498 498 - #endif 499 499 - } s; 500 500 - struct cvmx_pciercx_cfg012_s cn52xx; 501 501 - struct cvmx_pciercx_cfg012_s cn52xxp1; 502 502 - struct cvmx_pciercx_cfg012_s cn56xx; 503 503 - struct cvmx_pciercx_cfg012_s cn56xxp1; 504 504 - struct cvmx_pciercx_cfg012_s cn61xx; 505 505 - struct cvmx_pciercx_cfg012_s cn63xx; 506 506 - struct cvmx_pciercx_cfg012_s cn63xxp1; 507 507 - struct cvmx_pciercx_cfg012_s cn66xx; 508 508 - struct cvmx_pciercx_cfg012_s cn68xx; 509 509 - struct cvmx_pciercx_cfg012_s cn68xxp1; 510 510 - struct cvmx_pciercx_cfg012_s cnf71xx; 511 511 - }; 512 512 - 513 513 - union cvmx_pciercx_cfg013 { 514 514 - uint32_t u32; 515 515 - struct cvmx_pciercx_cfg013_s { 516 516 - #ifdef __BIG_ENDIAN_BITFIELD 517 517 - uint32_t reserved_8_31:24; 518 518 - uint32_t cp:8; 519 519 - #else 520 520 - uint32_t cp:8; 521 521 - uint32_t reserved_8_31:24; 522 522 - #endif 523 523 - } s; 524 524 - struct cvmx_pciercx_cfg013_s cn52xx; 525 525 - struct cvmx_pciercx_cfg013_s cn52xxp1; 526 526 - struct cvmx_pciercx_cfg013_s cn56xx; 527 527 - struct cvmx_pciercx_cfg013_s cn56xxp1; 528 528 - struct cvmx_pciercx_cfg013_s cn61xx; 529 529 - struct cvmx_pciercx_cfg013_s cn63xx; 530 530 - struct cvmx_pciercx_cfg013_s cn63xxp1; 531 531 - struct cvmx_pciercx_cfg013_s cn66xx; 532 532 - struct cvmx_pciercx_cfg013_s cn68xx; 533 533 - struct cvmx_pciercx_cfg013_s cn68xxp1; 534 534 - struct cvmx_pciercx_cfg013_s cnf71xx; 535 535 - }; 536 536 - 537 537 - union cvmx_pciercx_cfg014 { 538 538 - uint32_t u32; 539 539 - struct cvmx_pciercx_cfg014_s { 540 540 - #ifdef __BIG_ENDIAN_BITFIELD 541 541 - uint32_t reserved_0_31:32; 542 542 - #else 543 543 - uint32_t reserved_0_31:32; 544 544 - #endif 545 545 - } s; 546 546 - struct cvmx_pciercx_cfg014_s cn52xx; 547 547 - struct cvmx_pciercx_cfg014_s cn52xxp1; 548 548 - struct cvmx_pciercx_cfg014_s cn56xx; 549 549 - struct cvmx_pciercx_cfg014_s cn56xxp1; 550 550 - struct cvmx_pciercx_cfg014_s cn61xx; 551 551 - struct cvmx_pciercx_cfg014_s cn63xx; 552 552 - struct cvmx_pciercx_cfg014_s cn63xxp1; 553 553 - struct cvmx_pciercx_cfg014_s cn66xx; 554 554 - struct cvmx_pciercx_cfg014_s cn68xx; 555 555 - struct cvmx_pciercx_cfg014_s cn68xxp1; 556 556 - struct cvmx_pciercx_cfg014_s cnf71xx; 557 557 - }; 558 558 - 559 559 - union cvmx_pciercx_cfg015 { 560 560 - uint32_t u32; 561 561 - struct cvmx_pciercx_cfg015_s { 562 562 - #ifdef __BIG_ENDIAN_BITFIELD 563 563 - uint32_t reserved_28_31:4; 564 564 - uint32_t dtsees:1; 565 565 - uint32_t dts:1; 566 566 - uint32_t sdt:1; 567 567 - uint32_t pdt:1; 568 568 - uint32_t fbbe:1; 569 569 - uint32_t sbrst:1; 570 570 - uint32_t mam:1; 571 571 - uint32_t vga16d:1; 572 572 - uint32_t vgae:1; 573 573 - uint32_t isae:1; 574 574 - uint32_t see:1; 575 575 - uint32_t pere:1; 576 576 - uint32_t inta:8; 577 577 - uint32_t il:8; 578 578 - #else 579 579 - uint32_t il:8; 580 580 - uint32_t inta:8; 581 581 - uint32_t pere:1; 582 582 - uint32_t see:1; 583 583 - uint32_t isae:1; 584 584 - uint32_t vgae:1; 585 585 - uint32_t vga16d:1; 586 586 - uint32_t mam:1; 587 587 - uint32_t sbrst:1; 588 588 - uint32_t fbbe:1; 589 589 - uint32_t pdt:1; 590 590 - uint32_t sdt:1; 591 591 - uint32_t dts:1; 592 592 - uint32_t dtsees:1; 593 593 - uint32_t reserved_28_31:4; 594 594 - #endif 595 595 - } s; 596 596 - struct cvmx_pciercx_cfg015_s cn52xx; 597 597 - struct cvmx_pciercx_cfg015_s cn52xxp1; 598 598 - struct cvmx_pciercx_cfg015_s cn56xx; 599 599 - struct cvmx_pciercx_cfg015_s cn56xxp1; 600 600 - struct cvmx_pciercx_cfg015_s cn61xx; 601 601 - struct cvmx_pciercx_cfg015_s cn63xx; 602 602 - struct cvmx_pciercx_cfg015_s cn63xxp1; 603 603 - struct cvmx_pciercx_cfg015_s cn66xx; 604 604 - struct cvmx_pciercx_cfg015_s cn68xx; 605 605 - struct cvmx_pciercx_cfg015_s cn68xxp1; 606 606 - struct cvmx_pciercx_cfg015_s cnf71xx; 607 607 - }; 608 608 - 609 609 - union cvmx_pciercx_cfg016 { 610 610 - uint32_t u32; 611 611 - struct cvmx_pciercx_cfg016_s { 612 612 - #ifdef __BIG_ENDIAN_BITFIELD 613 613 - uint32_t pmes:5; 614 614 - uint32_t d2s:1; 615 615 - uint32_t d1s:1; 616 616 - uint32_t auxc:3; 617 617 - uint32_t dsi:1; 618 618 - uint32_t reserved_20_20:1; 619 619 - uint32_t pme_clock:1; 620 620 - uint32_t pmsv:3; 621 621 - uint32_t ncp:8; 622 622 - uint32_t pmcid:8; 623 623 - #else 624 624 - uint32_t pmcid:8; 625 625 - uint32_t ncp:8; 626 626 - uint32_t pmsv:3; 627 627 - uint32_t pme_clock:1; 628 628 - uint32_t reserved_20_20:1; 629 629 - uint32_t dsi:1; 630 630 - uint32_t auxc:3; 631 631 - uint32_t d1s:1; 632 632 - uint32_t d2s:1; 633 633 - uint32_t pmes:5; 634 634 - #endif 635 635 - } s; 636 636 - struct cvmx_pciercx_cfg016_s cn52xx; 637 637 - struct cvmx_pciercx_cfg016_s cn52xxp1; 638 638 - struct cvmx_pciercx_cfg016_s cn56xx; 639 639 - struct cvmx_pciercx_cfg016_s cn56xxp1; 640 640 - struct cvmx_pciercx_cfg016_s cn61xx; 641 641 - struct cvmx_pciercx_cfg016_s cn63xx; 642 642 - struct cvmx_pciercx_cfg016_s cn63xxp1; 643 643 - struct cvmx_pciercx_cfg016_s cn66xx; 644 644 - struct cvmx_pciercx_cfg016_s cn68xx; 645 645 - struct cvmx_pciercx_cfg016_s cn68xxp1; 646 646 - struct cvmx_pciercx_cfg016_s cnf71xx; 647 647 - }; 648 648 - 649 649 - union cvmx_pciercx_cfg017 { 650 650 - uint32_t u32; 651 651 - struct cvmx_pciercx_cfg017_s { 652 652 - #ifdef __BIG_ENDIAN_BITFIELD 653 653 - uint32_t pmdia:8; 654 654 - uint32_t bpccee:1; 655 655 - uint32_t bd3h:1; 656 656 - uint32_t reserved_16_21:6; 657 657 - uint32_t pmess:1; 658 658 - uint32_t pmedsia:2; 659 659 - uint32_t pmds:4; 660 660 - uint32_t pmeens:1; 661 661 - uint32_t reserved_4_7:4; 662 662 - uint32_t nsr:1; 663 663 - uint32_t reserved_2_2:1; 664 664 - uint32_t ps:2; 665 665 - #else 666 666 - uint32_t ps:2; 667 667 - uint32_t reserved_2_2:1; 668 668 - uint32_t nsr:1; 669 669 - uint32_t reserved_4_7:4; 670 670 - uint32_t pmeens:1; 671 671 - uint32_t pmds:4; 672 672 - uint32_t pmedsia:2; 673 673 - uint32_t pmess:1; 674 674 - uint32_t reserved_16_21:6; 675 675 - uint32_t bd3h:1; 676 676 - uint32_t bpccee:1; 677 677 - uint32_t pmdia:8; 678 678 - #endif 679 679 - } s; 680 680 - struct cvmx_pciercx_cfg017_s cn52xx; 681 681 - struct cvmx_pciercx_cfg017_s cn52xxp1; 682 682 - struct cvmx_pciercx_cfg017_s cn56xx; 683 683 - struct cvmx_pciercx_cfg017_s cn56xxp1; 684 684 - struct cvmx_pciercx_cfg017_s cn61xx; 685 685 - struct cvmx_pciercx_cfg017_s cn63xx; 686 686 - struct cvmx_pciercx_cfg017_s cn63xxp1; 687 687 - struct cvmx_pciercx_cfg017_s cn66xx; 688 688 - struct cvmx_pciercx_cfg017_s cn68xx; 689 689 - struct cvmx_pciercx_cfg017_s cn68xxp1; 690 690 - struct cvmx_pciercx_cfg017_s cnf71xx; 691 691 - }; 692 692 - 693 693 - union cvmx_pciercx_cfg020 { 694 694 - uint32_t u32; 695 695 - struct cvmx_pciercx_cfg020_s { 696 696 - #ifdef __BIG_ENDIAN_BITFIELD 697 697 - uint32_t reserved_25_31:7; 698 698 - uint32_t pvm:1; 699 699 - uint32_t m64:1; 700 700 - uint32_t mme:3; 701 701 - uint32_t mmc:3; 702 702 - uint32_t msien:1; 703 703 - uint32_t ncp:8; 704 704 - uint32_t msicid:8; 705 705 - #else 706 706 - uint32_t msicid:8; 707 707 - uint32_t ncp:8; 708 708 - uint32_t msien:1; 709 709 - uint32_t mmc:3; 710 710 - uint32_t mme:3; 711 711 - uint32_t m64:1; 712 712 - uint32_t pvm:1; 713 713 - uint32_t reserved_25_31:7; 714 714 - #endif 715 715 - } s; 716 716 - struct cvmx_pciercx_cfg020_cn52xx { 717 717 - #ifdef __BIG_ENDIAN_BITFIELD 718 718 - uint32_t reserved_24_31:8; 719 719 - uint32_t m64:1; 720 720 - uint32_t mme:3; 721 721 - uint32_t mmc:3; 722 722 - uint32_t msien:1; 723 723 - uint32_t ncp:8; 724 724 - uint32_t msicid:8; 725 725 - #else 726 726 - uint32_t msicid:8; 727 727 - uint32_t ncp:8; 728 728 - uint32_t msien:1; 729 729 - uint32_t mmc:3; 730 730 - uint32_t mme:3; 731 731 - uint32_t m64:1; 732 732 - uint32_t reserved_24_31:8; 733 733 - #endif 734 734 - } cn52xx; 735 735 - struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; 736 736 - struct cvmx_pciercx_cfg020_cn52xx cn56xx; 737 737 - struct cvmx_pciercx_cfg020_cn52xx cn56xxp1; 738 738 - struct cvmx_pciercx_cfg020_s cn61xx; 739 739 - struct cvmx_pciercx_cfg020_cn52xx cn63xx; 740 740 - struct cvmx_pciercx_cfg020_cn52xx cn63xxp1; 741 741 - struct cvmx_pciercx_cfg020_cn52xx cn66xx; 742 742 - struct cvmx_pciercx_cfg020_cn52xx cn68xx; 743 743 - struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; 744 744 - struct cvmx_pciercx_cfg020_s cnf71xx; 745 745 - }; 746 746 - 747 747 - union cvmx_pciercx_cfg021 { 748 748 - uint32_t u32; 749 749 - struct cvmx_pciercx_cfg021_s { 750 750 - #ifdef __BIG_ENDIAN_BITFIELD 751 751 - uint32_t lmsi:30; 752 752 - uint32_t reserved_0_1:2; 753 753 - #else 754 754 - uint32_t reserved_0_1:2; 755 755 - uint32_t lmsi:30; 756 756 - #endif 757 757 - } s; 758 758 - struct cvmx_pciercx_cfg021_s cn52xx; 759 759 - struct cvmx_pciercx_cfg021_s cn52xxp1; 760 760 - struct cvmx_pciercx_cfg021_s cn56xx; 761 761 - struct cvmx_pciercx_cfg021_s cn56xxp1; 762 762 - struct cvmx_pciercx_cfg021_s cn61xx; 763 763 - struct cvmx_pciercx_cfg021_s cn63xx; 764 764 - struct cvmx_pciercx_cfg021_s cn63xxp1; 765 765 - struct cvmx_pciercx_cfg021_s cn66xx; 766 766 - struct cvmx_pciercx_cfg021_s cn68xx; 767 767 - struct cvmx_pciercx_cfg021_s cn68xxp1; 768 768 - struct cvmx_pciercx_cfg021_s cnf71xx; 769 769 - }; 770 770 - 771 771 - union cvmx_pciercx_cfg022 { 772 772 - uint32_t u32; 773 773 - struct cvmx_pciercx_cfg022_s { 774 774 - #ifdef __BIG_ENDIAN_BITFIELD 775 775 - uint32_t umsi:32; 776 776 - #else 777 777 - uint32_t umsi:32; 778 778 - #endif 779 779 - } s; 780 780 - struct cvmx_pciercx_cfg022_s cn52xx; 781 781 - struct cvmx_pciercx_cfg022_s cn52xxp1; 782 782 - struct cvmx_pciercx_cfg022_s cn56xx; 783 783 - struct cvmx_pciercx_cfg022_s cn56xxp1; 784 784 - struct cvmx_pciercx_cfg022_s cn61xx; 785 785 - struct cvmx_pciercx_cfg022_s cn63xx; 786 786 - struct cvmx_pciercx_cfg022_s cn63xxp1; 787 787 - struct cvmx_pciercx_cfg022_s cn66xx; 788 788 - struct cvmx_pciercx_cfg022_s cn68xx; 789 789 - struct cvmx_pciercx_cfg022_s cn68xxp1; 790 790 - struct cvmx_pciercx_cfg022_s cnf71xx; 791 791 - }; 792 792 - 793 793 - union cvmx_pciercx_cfg023 { 794 794 - uint32_t u32; 795 795 - struct cvmx_pciercx_cfg023_s { 796 796 - #ifdef __BIG_ENDIAN_BITFIELD 797 797 - uint32_t reserved_16_31:16; 798 798 - uint32_t msimd:16; 799 799 - #else 800 800 - uint32_t msimd:16; 801 801 - uint32_t reserved_16_31:16; 802 802 - #endif 803 803 - } s; 804 804 - struct cvmx_pciercx_cfg023_s cn52xx; 805 805 - struct cvmx_pciercx_cfg023_s cn52xxp1; 806 806 - struct cvmx_pciercx_cfg023_s cn56xx; 807 807 - struct cvmx_pciercx_cfg023_s cn56xxp1; 808 808 - struct cvmx_pciercx_cfg023_s cn61xx; 809 809 - struct cvmx_pciercx_cfg023_s cn63xx; 810 810 - struct cvmx_pciercx_cfg023_s cn63xxp1; 811 811 - struct cvmx_pciercx_cfg023_s cn66xx; 812 812 - struct cvmx_pciercx_cfg023_s cn68xx; 813 813 - struct cvmx_pciercx_cfg023_s cn68xxp1; 814 814 - struct cvmx_pciercx_cfg023_s cnf71xx; 815 815 - }; 816 816 - 817 817 - union cvmx_pciercx_cfg028 { 818 818 - uint32_t u32; 819 819 - struct cvmx_pciercx_cfg028_s { 820 820 - #ifdef __BIG_ENDIAN_BITFIELD 821 821 - uint32_t reserved_30_31:2; 822 822 - uint32_t imn:5; 823 823 - uint32_t si:1; 824 824 - uint32_t dpt:4; 825 825 - uint32_t pciecv:4; 826 826 - uint32_t ncp:8; 827 827 - uint32_t pcieid:8; 828 828 - #else 829 829 - uint32_t pcieid:8; 830 830 - uint32_t ncp:8; 831 831 - uint32_t pciecv:4; 832 832 - uint32_t dpt:4; 833 833 - uint32_t si:1; 834 834 - uint32_t imn:5; 835 835 - uint32_t reserved_30_31:2; 836 836 - #endif 837 837 - } s; 838 838 - struct cvmx_pciercx_cfg028_s cn52xx; 839 839 - struct cvmx_pciercx_cfg028_s cn52xxp1; 840 840 - struct cvmx_pciercx_cfg028_s cn56xx; 841 841 - struct cvmx_pciercx_cfg028_s cn56xxp1; 842 842 - struct cvmx_pciercx_cfg028_s cn61xx; 843 843 - struct cvmx_pciercx_cfg028_s cn63xx; 844 844 - struct cvmx_pciercx_cfg028_s cn63xxp1; 845 845 - struct cvmx_pciercx_cfg028_s cn66xx; 846 846 - struct cvmx_pciercx_cfg028_s cn68xx; 847 847 - struct cvmx_pciercx_cfg028_s cn68xxp1; 848 848 - struct cvmx_pciercx_cfg028_s cnf71xx; 849 849 - }; 850 850 - 851 851 - union cvmx_pciercx_cfg029 { 852 852 - uint32_t u32; 853 853 - struct cvmx_pciercx_cfg029_s { 854 854 - #ifdef __BIG_ENDIAN_BITFIELD 855 855 - uint32_t reserved_28_31:4; 856 856 - uint32_t cspls:2; 857 857 - uint32_t csplv:8; 858 858 - uint32_t reserved_16_17:2; 859 859 - uint32_t rber:1; 860 860 - uint32_t reserved_12_14:3; 861 861 - uint32_t el1al:3; 862 862 - uint32_t el0al:3; 863 863 - uint32_t etfs:1; 864 864 - uint32_t pfs:2; 865 865 - uint32_t mpss:3; 866 866 - #else 867 867 - uint32_t mpss:3; 868 868 - uint32_t pfs:2; 869 869 - uint32_t etfs:1; 870 870 - uint32_t el0al:3; 871 871 - uint32_t el1al:3; 872 872 - uint32_t reserved_12_14:3; 873 873 - uint32_t rber:1; 874 874 - uint32_t reserved_16_17:2; 875 875 - uint32_t csplv:8; 876 876 - uint32_t cspls:2; 877 877 - uint32_t reserved_28_31:4; 878 878 - #endif 879 879 - } s; 880 880 - struct cvmx_pciercx_cfg029_s cn52xx; 881 881 - struct cvmx_pciercx_cfg029_s cn52xxp1; 882 882 - struct cvmx_pciercx_cfg029_s cn56xx; 883 883 - struct cvmx_pciercx_cfg029_s cn56xxp1; 884 884 - struct cvmx_pciercx_cfg029_s cn61xx; 885 885 - struct cvmx_pciercx_cfg029_s cn63xx; 886 886 - struct cvmx_pciercx_cfg029_s cn63xxp1; 887 887 - struct cvmx_pciercx_cfg029_s cn66xx; 888 888 - struct cvmx_pciercx_cfg029_s cn68xx; 889 889 - struct cvmx_pciercx_cfg029_s cn68xxp1; 890 890 - struct cvmx_pciercx_cfg029_s cnf71xx; 891 132 }; 892 133 893 134 union cvmx_pciercx_cfg030 { 894 135 uint32_t u32; 895 136 struct cvmx_pciercx_cfg030_s { 896 896 - #ifdef __BIG_ENDIAN_BITFIELD 897 897 - uint32_t reserved_22_31:10; 898 898 - uint32_t tp:1; 899 899 - uint32_t ap_d:1; 900 900 - uint32_t ur_d:1; 901 901 - uint32_t fe_d:1; 902 902 - uint32_t nfe_d:1; 903 903 - uint32_t ce_d:1; 904 904 - uint32_t reserved_15_15:1; 905 905 - uint32_t mrrs:3; 906 906 - uint32_t ns_en:1; 907 907 - uint32_t ap_en:1; 908 908 - uint32_t pf_en:1; 909 909 - uint32_t etf_en:1; 910 910 - uint32_t mps:3; 911 911 - uint32_t ro_en:1; 912 912 - uint32_t ur_en:1; 913 913 - uint32_t fe_en:1; 914 914 - uint32_t nfe_en:1; 915 915 - uint32_t ce_en:1; 916 916 - #else 917 917 - uint32_t ce_en:1; 918 918 - uint32_t nfe_en:1; 919 919 - uint32_t fe_en:1; 920 920 - uint32_t ur_en:1; 921 921 - uint32_t ro_en:1; 922 922 - uint32_t mps:3; 923 923 - uint32_t etf_en:1; 924 924 - uint32_t pf_en:1; 925 925 - uint32_t ap_en:1; 926 926 - uint32_t ns_en:1; 927 927 - uint32_t mrrs:3; 928 928 - uint32_t reserved_15_15:1; 929 929 - uint32_t ce_d:1; 930 930 - uint32_t nfe_d:1; 931 931 - uint32_t fe_d:1; 932 932 - uint32_t ur_d:1; 933 933 - uint32_t ap_d:1; 934 934 - uint32_t tp:1; 935 935 - uint32_t reserved_22_31:10; 936 936 - #endif 137 137 + __BITFIELD_FIELD(uint32_t reserved_22_31:10, 138 138 + __BITFIELD_FIELD(uint32_t tp:1, 139 139 + __BITFIELD_FIELD(uint32_t ap_d:1, 140 140 + __BITFIELD_FIELD(uint32_t ur_d:1, 141 141 + __BITFIELD_FIELD(uint32_t fe_d:1, 142 142 + __BITFIELD_FIELD(uint32_t nfe_d:1, 143 143 + __BITFIELD_FIELD(uint32_t ce_d:1, 144 144 + __BITFIELD_FIELD(uint32_t reserved_15_15:1, 145 145 + __BITFIELD_FIELD(uint32_t mrrs:3, 146 146 + __BITFIELD_FIELD(uint32_t ns_en:1, 147 147 + __BITFIELD_FIELD(uint32_t ap_en:1, 148 148 + __BITFIELD_FIELD(uint32_t pf_en:1, 149 149 + __BITFIELD_FIELD(uint32_t etf_en:1, 150 150 + __BITFIELD_FIELD(uint32_t mps:3, 151 151 + __BITFIELD_FIELD(uint32_t ro_en:1, 152 152 + __BITFIELD_FIELD(uint32_t ur_en:1, 153 153 + __BITFIELD_FIELD(uint32_t fe_en:1, 154 154 + __BITFIELD_FIELD(uint32_t nfe_en:1, 155 155 + __BITFIELD_FIELD(uint32_t ce_en:1, 156 156 + ;))))))))))))))))))) 937 157 } s; 938 938 - struct cvmx_pciercx_cfg030_s cn52xx; 939 939 - struct cvmx_pciercx_cfg030_s cn52xxp1; 940 940 - struct cvmx_pciercx_cfg030_s cn56xx; 941 941 - struct cvmx_pciercx_cfg030_s cn56xxp1; 942 942 - struct cvmx_pciercx_cfg030_s cn61xx; 943 943 - struct cvmx_pciercx_cfg030_s cn63xx; 944 944 - struct cvmx_pciercx_cfg030_s cn63xxp1; 945 945 - struct cvmx_pciercx_cfg030_s cn66xx; 946 946 - struct cvmx_pciercx_cfg030_s cn68xx; 947 947 - struct cvmx_pciercx_cfg030_s cn68xxp1; 948 948 - struct cvmx_pciercx_cfg030_s cnf71xx; 949 158 }; 950 159 951 160 union cvmx_pciercx_cfg031 { 952 161 uint32_t u32; 953 162 struct cvmx_pciercx_cfg031_s { 954 954 - #ifdef __BIG_ENDIAN_BITFIELD 955 955 - uint32_t pnum:8; 956 956 - uint32_t reserved_23_23:1; 957 957 - uint32_t aspm:1; 958 958 - uint32_t lbnc:1; 959 959 - uint32_t dllarc:1; 960 960 - uint32_t sderc:1; 961 961 - uint32_t cpm:1; 962 962 - uint32_t l1el:3; 963 963 - uint32_t l0el:3; 964 964 - uint32_t aslpms:2; 965 965 - uint32_t mlw:6; 966 966 - uint32_t mls:4; 967 967 - #else 968 968 - uint32_t mls:4; 969 969 - uint32_t mlw:6; 970 970 - uint32_t aslpms:2; 971 971 - uint32_t l0el:3; 972 972 - uint32_t l1el:3; 973 973 - uint32_t cpm:1; 974 974 - uint32_t sderc:1; 975 975 - uint32_t dllarc:1; 976 976 - uint32_t lbnc:1; 977 977 - uint32_t aspm:1; 978 978 - uint32_t reserved_23_23:1; 979 979 - uint32_t pnum:8; 980 980 - #endif 163 163 + __BITFIELD_FIELD(uint32_t pnum:8, 164 164 + __BITFIELD_FIELD(uint32_t reserved_23_23:1, 165 165 + __BITFIELD_FIELD(uint32_t aspm:1, 166 166 + __BITFIELD_FIELD(uint32_t lbnc:1, 167 167 + __BITFIELD_FIELD(uint32_t dllarc:1, 168 168 + __BITFIELD_FIELD(uint32_t sderc:1, 169 169 + __BITFIELD_FIELD(uint32_t cpm:1, 170 170 + __BITFIELD_FIELD(uint32_t l1el:3, 171 171 + __BITFIELD_FIELD(uint32_t l0el:3, 172 172 + __BITFIELD_FIELD(uint32_t aslpms:2, 173 173 + __BITFIELD_FIELD(uint32_t mlw:6, 174 174 + __BITFIELD_FIELD(uint32_t mls:4, 175 175 + ;)))))))))))) 981 176 } s; 982 982 - struct cvmx_pciercx_cfg031_cn52xx { 983 983 - #ifdef __BIG_ENDIAN_BITFIELD 984 984 - uint32_t pnum:8; 985 985 - uint32_t reserved_22_23:2; 986 986 - uint32_t lbnc:1; 987 987 - uint32_t dllarc:1; 988 988 - uint32_t sderc:1; 989 989 - uint32_t cpm:1; 990 990 - uint32_t l1el:3; 991 991 - uint32_t l0el:3; 992 992 - uint32_t aslpms:2; 993 993 - uint32_t mlw:6; 994 994 - uint32_t mls:4; 995 995 - #else 996 996 - uint32_t mls:4; 997 997 - uint32_t mlw:6; 998 998 - uint32_t aslpms:2; 999 999 - uint32_t l0el:3; 1000 1000 - uint32_t l1el:3; 1001 1001 - uint32_t cpm:1; 1002 1002 - uint32_t sderc:1; 1003 1003 - uint32_t dllarc:1; 1004 1004 - uint32_t lbnc:1; 1005 1005 - uint32_t reserved_22_23:2; 1006 1006 - uint32_t pnum:8; 1007 1007 - #endif 1008 1008 - } cn52xx; 1009 1009 - struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; 1010 1010 - struct cvmx_pciercx_cfg031_cn52xx cn56xx; 1011 1011 - struct cvmx_pciercx_cfg031_cn52xx cn56xxp1; 1012 1012 - struct cvmx_pciercx_cfg031_s cn61xx; 1013 1013 - struct cvmx_pciercx_cfg031_cn52xx cn63xx; 1014 1014 - struct cvmx_pciercx_cfg031_cn52xx cn63xxp1; 1015 1015 - struct cvmx_pciercx_cfg031_s cn66xx; 1016 1016 - struct cvmx_pciercx_cfg031_s cn68xx; 1017 1017 - struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; 1018 1018 - struct cvmx_pciercx_cfg031_s cnf71xx; 1019 177 }; 1020 178 1021 179 union cvmx_pciercx_cfg032 { 1022 180 uint32_t u32; 1023 181 struct cvmx_pciercx_cfg032_s { 1024 1024 - #ifdef __BIG_ENDIAN_BITFIELD 1025 1025 - uint32_t lab:1; 1026 1026 - uint32_t lbm:1; 1027 1027 - uint32_t dlla:1; 1028 1028 - uint32_t scc:1; 1029 1029 - uint32_t lt:1; 1030 1030 - uint32_t reserved_26_26:1; 1031 1031 - uint32_t nlw:6; 1032 1032 - uint32_t ls:4; 1033 1033 - uint32_t reserved_12_15:4; 1034 1034 - uint32_t lab_int_enb:1; 1035 1035 - uint32_t lbm_int_enb:1; 1036 1036 - uint32_t hawd:1; 1037 1037 - uint32_t ecpm:1; 1038 1038 - uint32_t es:1; 1039 1039 - uint32_t ccc:1; 1040 1040 - uint32_t rl:1; 1041 1041 - uint32_t ld:1; 1042 1042 - uint32_t rcb:1; 1043 1043 - uint32_t reserved_2_2:1; 1044 1044 - uint32_t aslpc:2; 1045 1045 - #else 1046 1046 - uint32_t aslpc:2; 1047 1047 - uint32_t reserved_2_2:1; 1048 1048 - uint32_t rcb:1; 1049 1049 - uint32_t ld:1; 1050 1050 - uint32_t rl:1; 1051 1051 - uint32_t ccc:1; 1052 1052 - uint32_t es:1; 1053 1053 - uint32_t ecpm:1; 1054 1054 - uint32_t hawd:1; 1055 1055 - uint32_t lbm_int_enb:1; 1056 1056 - uint32_t lab_int_enb:1; 1057 1057 - uint32_t reserved_12_15:4; 1058 1058 - uint32_t ls:4; 1059 1059 - uint32_t nlw:6; 1060 1060 - uint32_t reserved_26_26:1; 1061 1061 - uint32_t lt:1; 1062 1062 - uint32_t scc:1; 1063 1063 - uint32_t dlla:1; 1064 1064 - uint32_t lbm:1; 1065 1065 - uint32_t lab:1; 1066 1066 - #endif 182 182 + __BITFIELD_FIELD(uint32_t lab:1, 183 183 + __BITFIELD_FIELD(uint32_t lbm:1, 184 184 + __BITFIELD_FIELD(uint32_t dlla:1, 185 185 + __BITFIELD_FIELD(uint32_t scc:1, 186 186 + __BITFIELD_FIELD(uint32_t lt:1, 187 187 + __BITFIELD_FIELD(uint32_t reserved_26_26:1, 188 188 + __BITFIELD_FIELD(uint32_t nlw:6, 189 189 + __BITFIELD_FIELD(uint32_t ls:4, 190 190 + __BITFIELD_FIELD(uint32_t reserved_12_15:4, 191 191 + __BITFIELD_FIELD(uint32_t lab_int_enb:1, 192 192 + __BITFIELD_FIELD(uint32_t lbm_int_enb:1, 193 193 + __BITFIELD_FIELD(uint32_t hawd:1, 194 194 + __BITFIELD_FIELD(uint32_t ecpm:1, 195 195 + __BITFIELD_FIELD(uint32_t es:1, 196 196 + __BITFIELD_FIELD(uint32_t ccc:1, 197 197 + __BITFIELD_FIELD(uint32_t rl:1, 198 198 + __BITFIELD_FIELD(uint32_t ld:1, 199 199 + __BITFIELD_FIELD(uint32_t rcb:1, 200 200 + __BITFIELD_FIELD(uint32_t reserved_2_2:1, 201 201 + __BITFIELD_FIELD(uint32_t aslpc:2, 202 202 + ;)))))))))))))))))))) 1067 203 } s; 1068 1068 - struct cvmx_pciercx_cfg032_s cn52xx; 1069 1069 - struct cvmx_pciercx_cfg032_s cn52xxp1; 1070 1070 - struct cvmx_pciercx_cfg032_s cn56xx; 1071 1071 - struct cvmx_pciercx_cfg032_s cn56xxp1; 1072 1072 - struct cvmx_pciercx_cfg032_s cn61xx; 1073 1073 - struct cvmx_pciercx_cfg032_s cn63xx; 1074 1074 - struct cvmx_pciercx_cfg032_s cn63xxp1; 1075 1075 - struct cvmx_pciercx_cfg032_s cn66xx; 1076 1076 - struct cvmx_pciercx_cfg032_s cn68xx; 1077 1077 - struct cvmx_pciercx_cfg032_s cn68xxp1; 1078 1078 - struct cvmx_pciercx_cfg032_s cnf71xx; 1079 1079 - }; 1080 1080 - 1081 1081 - union cvmx_pciercx_cfg033 { 1082 1082 - uint32_t u32; 1083 1083 - struct cvmx_pciercx_cfg033_s { 1084 1084 - #ifdef __BIG_ENDIAN_BITFIELD 1085 1085 - uint32_t ps_num:13; 1086 1086 - uint32_t nccs:1; 1087 1087 - uint32_t emip:1; 1088 1088 - uint32_t sp_ls:2; 1089 1089 - uint32_t sp_lv:8; 1090 1090 - uint32_t hp_c:1; 1091 1091 - uint32_t hp_s:1; 1092 1092 - uint32_t pip:1; 1093 1093 - uint32_t aip:1; 1094 1094 - uint32_t mrlsp:1; 1095 1095 - uint32_t pcp:1; 1096 1096 - uint32_t abp:1; 1097 1097 - #else 1098 1098 - uint32_t abp:1; 1099 1099 - uint32_t pcp:1; 1100 1100 - uint32_t mrlsp:1; 1101 1101 - uint32_t aip:1; 1102 1102 - uint32_t pip:1; 1103 1103 - uint32_t hp_s:1; 1104 1104 - uint32_t hp_c:1; 1105 1105 - uint32_t sp_lv:8; 1106 1106 - uint32_t sp_ls:2; 1107 1107 - uint32_t emip:1; 1108 1108 - uint32_t nccs:1; 1109 1109 - uint32_t ps_num:13; 1110 1110 - #endif 1111 1111 - } s; 1112 1112 - struct cvmx_pciercx_cfg033_s cn52xx; 1113 1113 - struct cvmx_pciercx_cfg033_s cn52xxp1; 1114 1114 - struct cvmx_pciercx_cfg033_s cn56xx; 1115 1115 - struct cvmx_pciercx_cfg033_s cn56xxp1; 1116 1116 - struct cvmx_pciercx_cfg033_s cn61xx; 1117 1117 - struct cvmx_pciercx_cfg033_s cn63xx; 1118 1118 - struct cvmx_pciercx_cfg033_s cn63xxp1; 1119 1119 - struct cvmx_pciercx_cfg033_s cn66xx; 1120 1120 - struct cvmx_pciercx_cfg033_s cn68xx; 1121 1121 - struct cvmx_pciercx_cfg033_s cn68xxp1; 1122 1122 - struct cvmx_pciercx_cfg033_s cnf71xx; 1123 204 }; 1124 205 1125 206 union cvmx_pciercx_cfg034 { 1126 207 uint32_t u32; 1127 208 struct cvmx_pciercx_cfg034_s { 1128 1128 - #ifdef __BIG_ENDIAN_BITFIELD 1129 1129 - uint32_t reserved_25_31:7; 1130 1130 - uint32_t dlls_c:1; 1131 1131 - uint32_t emis:1; 1132 1132 - uint32_t pds:1; 1133 1133 - uint32_t mrlss:1; 1134 1134 - uint32_t ccint_d:1; 1135 1135 - uint32_t pd_c:1; 1136 1136 - uint32_t mrls_c:1; 1137 1137 - uint32_t pf_d:1; 1138 1138 - uint32_t abp_d:1; 1139 1139 - uint32_t reserved_13_15:3; 1140 1140 - uint32_t dlls_en:1; 1141 1141 - uint32_t emic:1; 1142 1142 - uint32_t pcc:1; 1143 1143 - uint32_t pic:2; 1144 1144 - uint32_t aic:2; 1145 1145 - uint32_t hpint_en:1; 1146 1146 - uint32_t ccint_en:1; 1147 1147 - uint32_t pd_en:1; 1148 1148 - uint32_t mrls_en:1; 1149 1149 - uint32_t pf_en:1; 1150 1150 - uint32_t abp_en:1; 1151 1151 - #else 1152 1152 - uint32_t abp_en:1; 1153 1153 - uint32_t pf_en:1; 1154 1154 - uint32_t mrls_en:1; 1155 1155 - uint32_t pd_en:1; 1156 1156 - uint32_t ccint_en:1; 1157 1157 - uint32_t hpint_en:1; 1158 1158 - uint32_t aic:2; 1159 1159 - uint32_t pic:2; 1160 1160 - uint32_t pcc:1; 1161 1161 - uint32_t emic:1; 1162 1162 - uint32_t dlls_en:1; 1163 1163 - uint32_t reserved_13_15:3; 1164 1164 - uint32_t abp_d:1; 1165 1165 - uint32_t pf_d:1; 1166 1166 - uint32_t mrls_c:1; 1167 1167 - uint32_t pd_c:1; 1168 1168 - uint32_t ccint_d:1; 1169 1169 - uint32_t mrlss:1; 1170 1170 - uint32_t pds:1; 1171 1171 - uint32_t emis:1; 1172 1172 - uint32_t dlls_c:1; 1173 1173 - uint32_t reserved_25_31:7; 1174 1174 - #endif 209 209 + __BITFIELD_FIELD(uint32_t reserved_25_31:7, 210 210 + __BITFIELD_FIELD(uint32_t dlls_c:1, 211 211 + __BITFIELD_FIELD(uint32_t emis:1, 212 212 + __BITFIELD_FIELD(uint32_t pds:1, 213 213 + __BITFIELD_FIELD(uint32_t mrlss:1, 214 214 + __BITFIELD_FIELD(uint32_t ccint_d:1, 215 215 + __BITFIELD_FIELD(uint32_t pd_c:1, 216 216 + __BITFIELD_FIELD(uint32_t mrls_c:1, 217 217 + __BITFIELD_FIELD(uint32_t pf_d:1, 218 218 + __BITFIELD_FIELD(uint32_t abp_d:1, 219 219 + __BITFIELD_FIELD(uint32_t reserved_13_15:3, 220 220 + __BITFIELD_FIELD(uint32_t dlls_en:1, 221 221 + __BITFIELD_FIELD(uint32_t emic:1, 222 222 + __BITFIELD_FIELD(uint32_t pcc:1, 223 223 + __BITFIELD_FIELD(uint32_t pic:1, 224 224 + __BITFIELD_FIELD(uint32_t aic:1, 225 225 + __BITFIELD_FIELD(uint32_t hpint_en:1, 226 226 + __BITFIELD_FIELD(uint32_t ccint_en:1, 227 227 + __BITFIELD_FIELD(uint32_t pd_en:1, 228 228 + __BITFIELD_FIELD(uint32_t mrls_en:1, 229 229 + __BITFIELD_FIELD(uint32_t pf_en:1, 230 230 + __BITFIELD_FIELD(uint32_t abp_en:1, 231 231 + ;)))))))))))))))))))))) 1175 232 } s; 1176 1176 - struct cvmx_pciercx_cfg034_s cn52xx; 1177 1177 - struct cvmx_pciercx_cfg034_s cn52xxp1; 1178 1178 - struct cvmx_pciercx_cfg034_s cn56xx; 1179 1179 - struct cvmx_pciercx_cfg034_s cn56xxp1; 1180 1180 - struct cvmx_pciercx_cfg034_s cn61xx; 1181 1181 - struct cvmx_pciercx_cfg034_s cn63xx; 1182 1182 - struct cvmx_pciercx_cfg034_s cn63xxp1; 1183 1183 - struct cvmx_pciercx_cfg034_s cn66xx; 1184 1184 - struct cvmx_pciercx_cfg034_s cn68xx; 1185 1185 - struct cvmx_pciercx_cfg034_s cn68xxp1; 1186 1186 - struct cvmx_pciercx_cfg034_s cnf71xx; 1187 233 }; 1188 234 1189 235 union cvmx_pciercx_cfg035 { 1190 236 uint32_t u32; 1191 237 struct cvmx_pciercx_cfg035_s { 1192 1192 - #ifdef __BIG_ENDIAN_BITFIELD 1193 1193 - uint32_t reserved_17_31:15; 1194 1194 - uint32_t crssv:1; 1195 1195 - uint32_t reserved_5_15:11; 1196 1196 - uint32_t crssve:1; 1197 1197 - uint32_t pmeie:1; 1198 1198 - uint32_t sefee:1; 1199 1199 - uint32_t senfee:1; 1200 1200 - uint32_t secee:1; 1201 1201 - #else 1202 1202 - uint32_t secee:1; 1203 1203 - uint32_t senfee:1; 1204 1204 - uint32_t sefee:1; 1205 1205 - uint32_t pmeie:1; 1206 1206 - uint32_t crssve:1; 1207 1207 - uint32_t reserved_5_15:11; 1208 1208 - uint32_t crssv:1; 1209 1209 - uint32_t reserved_17_31:15; 1210 1210 - #endif 238 238 + __BITFIELD_FIELD(uint32_t reserved_17_31:15, 239 239 + __BITFIELD_FIELD(uint32_t crssv:1, 240 240 + __BITFIELD_FIELD(uint32_t reserved_5_15:11, 241 241 + __BITFIELD_FIELD(uint32_t crssve:1, 242 242 + __BITFIELD_FIELD(uint32_t pmeie:1, 243 243 + __BITFIELD_FIELD(uint32_t sefee:1, 244 244 + __BITFIELD_FIELD(uint32_t senfee:1, 245 245 + __BITFIELD_FIELD(uint32_t secee:1, 246 246 + ;)))))))) 1211 247 } s; 1212 1212 - struct cvmx_pciercx_cfg035_s cn52xx; 1213 1213 - struct cvmx_pciercx_cfg035_s cn52xxp1; 1214 1214 - struct cvmx_pciercx_cfg035_s cn56xx; 1215 1215 - struct cvmx_pciercx_cfg035_s cn56xxp1; 1216 1216 - struct cvmx_pciercx_cfg035_s cn61xx; 1217 1217 - struct cvmx_pciercx_cfg035_s cn63xx; 1218 1218 - struct cvmx_pciercx_cfg035_s cn63xxp1; 1219 1219 - struct cvmx_pciercx_cfg035_s cn66xx; 1220 1220 - struct cvmx_pciercx_cfg035_s cn68xx; 1221 1221 - struct cvmx_pciercx_cfg035_s cn68xxp1; 1222 1222 - struct cvmx_pciercx_cfg035_s cnf71xx; 1223 1223 - }; 1224 1224 - 1225 1225 - union cvmx_pciercx_cfg036 { 1226 1226 - uint32_t u32; 1227 1227 - struct cvmx_pciercx_cfg036_s { 1228 1228 - #ifdef __BIG_ENDIAN_BITFIELD 1229 1229 - uint32_t reserved_18_31:14; 1230 1230 - uint32_t pme_pend:1; 1231 1231 - uint32_t pme_stat:1; 1232 1232 - uint32_t pme_rid:16; 1233 1233 - #else 1234 1234 - uint32_t pme_rid:16; 1235 1235 - uint32_t pme_stat:1; 1236 1236 - uint32_t pme_pend:1; 1237 1237 - uint32_t reserved_18_31:14; 1238 1238 - #endif 1239 1239 - } s; 1240 1240 - struct cvmx_pciercx_cfg036_s cn52xx; 1241 1241 - struct cvmx_pciercx_cfg036_s cn52xxp1; 1242 1242 - struct cvmx_pciercx_cfg036_s cn56xx; 1243 1243 - struct cvmx_pciercx_cfg036_s cn56xxp1; 1244 1244 - struct cvmx_pciercx_cfg036_s cn61xx; 1245 1245 - struct cvmx_pciercx_cfg036_s cn63xx; 1246 1246 - struct cvmx_pciercx_cfg036_s cn63xxp1; 1247 1247 - struct cvmx_pciercx_cfg036_s cn66xx; 1248 1248 - struct cvmx_pciercx_cfg036_s cn68xx; 1249 1249 - struct cvmx_pciercx_cfg036_s cn68xxp1; 1250 1250 - struct cvmx_pciercx_cfg036_s cnf71xx; 1251 1251 - }; 1252 1252 - 1253 1253 - union cvmx_pciercx_cfg037 { 1254 1254 - uint32_t u32; 1255 1255 - struct cvmx_pciercx_cfg037_s { 1256 1256 - #ifdef __BIG_ENDIAN_BITFIELD 1257 1257 - uint32_t reserved_20_31:12; 1258 1258 - uint32_t obffs:2; 1259 1259 - uint32_t reserved_12_17:6; 1260 1260 - uint32_t ltrs:1; 1261 1261 - uint32_t noroprpr:1; 1262 1262 - uint32_t atom128s:1; 1263 1263 - uint32_t atom64s:1; 1264 1264 - uint32_t atom32s:1; 1265 1265 - uint32_t atom_ops:1; 1266 1266 - uint32_t reserved_5_5:1; 1267 1267 - uint32_t ctds:1; 1268 1268 - uint32_t ctrs:4; 1269 1269 - #else 1270 1270 - uint32_t ctrs:4; 1271 1271 - uint32_t ctds:1; 1272 1272 - uint32_t reserved_5_5:1; 1273 1273 - uint32_t atom_ops:1; 1274 1274 - uint32_t atom32s:1; 1275 1275 - uint32_t atom64s:1; 1276 1276 - uint32_t atom128s:1; 1277 1277 - uint32_t noroprpr:1; 1278 1278 - uint32_t ltrs:1; 1279 1279 - uint32_t reserved_12_17:6; 1280 1280 - uint32_t obffs:2; 1281 1281 - uint32_t reserved_20_31:12; 1282 1282 - #endif 1283 1283 - } s; 1284 1284 - struct cvmx_pciercx_cfg037_cn52xx { 1285 1285 - #ifdef __BIG_ENDIAN_BITFIELD 1286 1286 - uint32_t reserved_5_31:27; 1287 1287 - uint32_t ctds:1; 1288 1288 - uint32_t ctrs:4; 1289 1289 - #else 1290 1290 - uint32_t ctrs:4; 1291 1291 - uint32_t ctds:1; 1292 1292 - uint32_t reserved_5_31:27; 1293 1293 - #endif 1294 1294 - } cn52xx; 1295 1295 - struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; 1296 1296 - struct cvmx_pciercx_cfg037_cn52xx cn56xx; 1297 1297 - struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; 1298 1298 - struct cvmx_pciercx_cfg037_cn61xx { 1299 1299 - #ifdef __BIG_ENDIAN_BITFIELD 1300 1300 - uint32_t reserved_14_31:18; 1301 1301 - uint32_t tph:2; 1302 1302 - uint32_t reserved_11_11:1; 1303 1303 - uint32_t noroprpr:1; 1304 1304 - uint32_t atom128s:1; 1305 1305 - uint32_t atom64s:1; 1306 1306 - uint32_t atom32s:1; 1307 1307 - uint32_t atom_ops:1; 1308 1308 - uint32_t ari_fw:1; 1309 1309 - uint32_t ctds:1; 1310 1310 - uint32_t ctrs:4; 1311 1311 - #else 1312 1312 - uint32_t ctrs:4; 1313 1313 - uint32_t ctds:1; 1314 1314 - uint32_t ari_fw:1; 1315 1315 - uint32_t atom_ops:1; 1316 1316 - uint32_t atom32s:1; 1317 1317 - uint32_t atom64s:1; 1318 1318 - uint32_t atom128s:1; 1319 1319 - uint32_t noroprpr:1; 1320 1320 - uint32_t reserved_11_11:1; 1321 1321 - uint32_t tph:2; 1322 1322 - uint32_t reserved_14_31:18; 1323 1323 - #endif 1324 1324 - } cn61xx; 1325 1325 - struct cvmx_pciercx_cfg037_cn52xx cn63xx; 1326 1326 - struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; 1327 1327 - struct cvmx_pciercx_cfg037_cn66xx { 1328 1328 - #ifdef __BIG_ENDIAN_BITFIELD 1329 1329 - uint32_t reserved_14_31:18; 1330 1330 - uint32_t tph:2; 1331 1331 - uint32_t reserved_11_11:1; 1332 1332 - uint32_t noroprpr:1; 1333 1333 - uint32_t atom128s:1; 1334 1334 - uint32_t atom64s:1; 1335 1335 - uint32_t atom32s:1; 1336 1336 - uint32_t atom_ops:1; 1337 1337 - uint32_t ari:1; 1338 1338 - uint32_t ctds:1; 1339 1339 - uint32_t ctrs:4; 1340 1340 - #else 1341 1341 - uint32_t ctrs:4; 1342 1342 - uint32_t ctds:1; 1343 1343 - uint32_t ari:1; 1344 1344 - uint32_t atom_ops:1; 1345 1345 - uint32_t atom32s:1; 1346 1346 - uint32_t atom64s:1; 1347 1347 - uint32_t atom128s:1; 1348 1348 - uint32_t noroprpr:1; 1349 1349 - uint32_t reserved_11_11:1; 1350 1350 - uint32_t tph:2; 1351 1351 - uint32_t reserved_14_31:18; 1352 1352 - #endif 1353 1353 - } cn66xx; 1354 1354 - struct cvmx_pciercx_cfg037_cn66xx cn68xx; 1355 1355 - struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; 1356 1356 - struct cvmx_pciercx_cfg037_cnf71xx { 1357 1357 - #ifdef __BIG_ENDIAN_BITFIELD 1358 1358 - uint32_t reserved_20_31:12; 1359 1359 - uint32_t obffs:2; 1360 1360 - uint32_t reserved_14_17:4; 1361 1361 - uint32_t tphs:2; 1362 1362 - uint32_t ltrs:1; 1363 1363 - uint32_t noroprpr:1; 1364 1364 - uint32_t atom128s:1; 1365 1365 - uint32_t atom64s:1; 1366 1366 - uint32_t atom32s:1; 1367 1367 - uint32_t atom_ops:1; 1368 1368 - uint32_t ari_fw:1; 1369 1369 - uint32_t ctds:1; 1370 1370 - uint32_t ctrs:4; 1371 1371 - #else 1372 1372 - uint32_t ctrs:4; 1373 1373 - uint32_t ctds:1; 1374 1374 - uint32_t ari_fw:1; 1375 1375 - uint32_t atom_ops:1; 1376 1376 - uint32_t atom32s:1; 1377 1377 - uint32_t atom64s:1; 1378 1378 - uint32_t atom128s:1; 1379 1379 - uint32_t noroprpr:1; 1380 1380 - uint32_t ltrs:1; 1381 1381 - uint32_t tphs:2; 1382 1382 - uint32_t reserved_14_17:4; 1383 1383 - uint32_t obffs:2; 1384 1384 - uint32_t reserved_20_31:12; 1385 1385 - #endif 1386 1386 - } cnf71xx; 1387 1387 - }; 1388 1388 - 1389 1389 - union cvmx_pciercx_cfg038 { 1390 1390 - uint32_t u32; 1391 1391 - struct cvmx_pciercx_cfg038_s { 1392 1392 - #ifdef __BIG_ENDIAN_BITFIELD 1393 1393 - uint32_t reserved_15_31:17; 1394 1394 - uint32_t obffe:2; 1395 1395 - uint32_t reserved_11_12:2; 1396 1396 - uint32_t ltre:1; 1397 1397 - uint32_t id0_cp:1; 1398 1398 - uint32_t id0_rq:1; 1399 1399 - uint32_t atom_op_eb:1; 1400 1400 - uint32_t atom_op:1; 1401 1401 - uint32_t ari:1; 1402 1402 - uint32_t ctd:1; 1403 1403 - uint32_t ctv:4; 1404 1404 - #else 1405 1405 - uint32_t ctv:4; 1406 1406 - uint32_t ctd:1; 1407 1407 - uint32_t ari:1; 1408 1408 - uint32_t atom_op:1; 1409 1409 - uint32_t atom_op_eb:1; 1410 1410 - uint32_t id0_rq:1; 1411 1411 - uint32_t id0_cp:1; 1412 1412 - uint32_t ltre:1; 1413 1413 - uint32_t reserved_11_12:2; 1414 1414 - uint32_t obffe:2; 1415 1415 - uint32_t reserved_15_31:17; 1416 1416 - #endif 1417 1417 - } s; 1418 1418 - struct cvmx_pciercx_cfg038_cn52xx { 1419 1419 - #ifdef __BIG_ENDIAN_BITFIELD 1420 1420 - uint32_t reserved_5_31:27; 1421 1421 - uint32_t ctd:1; 1422 1422 - uint32_t ctv:4; 1423 1423 - #else 1424 1424 - uint32_t ctv:4; 1425 1425 - uint32_t ctd:1; 1426 1426 - uint32_t reserved_5_31:27; 1427 1427 - #endif 1428 1428 - } cn52xx; 1429 1429 - struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; 1430 1430 - struct cvmx_pciercx_cfg038_cn52xx cn56xx; 1431 1431 - struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; 1432 1432 - struct cvmx_pciercx_cfg038_cn61xx { 1433 1433 - #ifdef __BIG_ENDIAN_BITFIELD 1434 1434 - uint32_t reserved_10_31:22; 1435 1435 - uint32_t id0_cp:1; 1436 1436 - uint32_t id0_rq:1; 1437 1437 - uint32_t atom_op_eb:1; 1438 1438 - uint32_t atom_op:1; 1439 1439 - uint32_t ari:1; 1440 1440 - uint32_t ctd:1; 1441 1441 - uint32_t ctv:4; 1442 1442 - #else 1443 1443 - uint32_t ctv:4; 1444 1444 - uint32_t ctd:1; 1445 1445 - uint32_t ari:1; 1446 1446 - uint32_t atom_op:1; 1447 1447 - uint32_t atom_op_eb:1; 1448 1448 - uint32_t id0_rq:1; 1449 1449 - uint32_t id0_cp:1; 1450 1450 - uint32_t reserved_10_31:22; 1451 1451 - #endif 1452 1452 - } cn61xx; 1453 1453 - struct cvmx_pciercx_cfg038_cn52xx cn63xx; 1454 1454 - struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; 1455 1455 - struct cvmx_pciercx_cfg038_cn61xx cn66xx; 1456 1456 - struct cvmx_pciercx_cfg038_cn61xx cn68xx; 1457 1457 - struct cvmx_pciercx_cfg038_cn61xx cn68xxp1; 1458 1458 - struct cvmx_pciercx_cfg038_s cnf71xx; 1459 1459 - }; 1460 1460 - 1461 1461 - union cvmx_pciercx_cfg039 { 1462 1462 - uint32_t u32; 1463 1463 - struct cvmx_pciercx_cfg039_s { 1464 1464 - #ifdef __BIG_ENDIAN_BITFIELD 1465 1465 - uint32_t reserved_9_31:23; 1466 1466 - uint32_t cls:1; 1467 1467 - uint32_t slsv:7; 1468 1468 - uint32_t reserved_0_0:1; 1469 1469 - #else 1470 1470 - uint32_t reserved_0_0:1; 1471 1471 - uint32_t slsv:7; 1472 1472 - uint32_t cls:1; 1473 1473 - uint32_t reserved_9_31:23; 1474 1474 - #endif 1475 1475 - } s; 1476 1476 - struct cvmx_pciercx_cfg039_cn52xx { 1477 1477 - #ifdef __BIG_ENDIAN_BITFIELD 1478 1478 - uint32_t reserved_0_31:32; 1479 1479 - #else 1480 1480 - uint32_t reserved_0_31:32; 1481 1481 - #endif 1482 1482 - } cn52xx; 1483 1483 - struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; 1484 1484 - struct cvmx_pciercx_cfg039_cn52xx cn56xx; 1485 1485 - struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; 1486 1486 - struct cvmx_pciercx_cfg039_s cn61xx; 1487 1487 - struct cvmx_pciercx_cfg039_s cn63xx; 1488 1488 - struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; 1489 1489 - struct cvmx_pciercx_cfg039_s cn66xx; 1490 1490 - struct cvmx_pciercx_cfg039_s cn68xx; 1491 1491 - struct cvmx_pciercx_cfg039_s cn68xxp1; 1492 1492 - struct cvmx_pciercx_cfg039_s cnf71xx; 1493 248 }; 1494 249 1495 250 union cvmx_pciercx_cfg040 { 1496 251 uint32_t u32; 1497 252 struct cvmx_pciercx_cfg040_s { 1498 1498 - #ifdef __BIG_ENDIAN_BITFIELD 1499 1499 - uint32_t reserved_17_31:15; 1500 1500 - uint32_t cdl:1; 1501 1501 - uint32_t reserved_13_15:3; 1502 1502 - uint32_t cde:1; 1503 1503 - uint32_t csos:1; 1504 1504 - uint32_t emc:1; 1505 1505 - uint32_t tm:3; 1506 1506 - uint32_t sde:1; 1507 1507 - uint32_t hasd:1; 1508 1508 - uint32_t ec:1; 1509 1509 - uint32_t tls:4; 1510 1510 - #else 1511 1511 - uint32_t tls:4; 1512 1512 - uint32_t ec:1; 1513 1513 - uint32_t hasd:1; 1514 1514 - uint32_t sde:1; 1515 1515 - uint32_t tm:3; 1516 1516 - uint32_t emc:1; 1517 1517 - uint32_t csos:1; 1518 1518 - uint32_t cde:1; 1519 1519 - uint32_t reserved_13_15:3; 1520 1520 - uint32_t cdl:1; 1521 1521 - uint32_t reserved_17_31:15; 1522 1522 - #endif 253 253 + __BITFIELD_FIELD(uint32_t reserved_22_31:10, 254 254 + __BITFIELD_FIELD(uint32_t ler:1, 255 255 + __BITFIELD_FIELD(uint32_t ep3s:1, 256 256 + __BITFIELD_FIELD(uint32_t ep2s:1, 257 257 + __BITFIELD_FIELD(uint32_t ep1s:1, 258 258 + __BITFIELD_FIELD(uint32_t eqc:1, 259 259 + __BITFIELD_FIELD(uint32_t cdl:1, 260 260 + __BITFIELD_FIELD(uint32_t cde:4, 261 261 + __BITFIELD_FIELD(uint32_t csos:1, 262 262 + __BITFIELD_FIELD(uint32_t emc:1, 263 263 + __BITFIELD_FIELD(uint32_t tm:3, 264 264 + __BITFIELD_FIELD(uint32_t sde:1, 265 265 + __BITFIELD_FIELD(uint32_t hasd:1, 266 266 + __BITFIELD_FIELD(uint32_t ec:1, 267 267 + __BITFIELD_FIELD(uint32_t tls:4, 268 268 + ;))))))))))))))) 1523 269 } s; 1524 1524 - struct cvmx_pciercx_cfg040_cn52xx { 1525 1525 - #ifdef __BIG_ENDIAN_BITFIELD 1526 1526 - uint32_t reserved_0_31:32; 1527 1527 - #else 1528 1528 - uint32_t reserved_0_31:32; 1529 1529 - #endif 1530 1530 - } cn52xx; 1531 1531 - struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 1532 1532 - struct cvmx_pciercx_cfg040_cn52xx cn56xx; 1533 1533 - struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 1534 1534 - struct cvmx_pciercx_cfg040_s cn61xx; 1535 1535 - struct cvmx_pciercx_cfg040_s cn63xx; 1536 1536 - struct cvmx_pciercx_cfg040_s cn63xxp1; 1537 1537 - struct cvmx_pciercx_cfg040_s cn66xx; 1538 1538 - struct cvmx_pciercx_cfg040_s cn68xx; 1539 1539 - struct cvmx_pciercx_cfg040_s cn68xxp1; 1540 1540 - struct cvmx_pciercx_cfg040_s cnf71xx; 1541 1541 - }; 1542 1542 - 1543 1543 - union cvmx_pciercx_cfg041 { 1544 1544 - uint32_t u32; 1545 1545 - struct cvmx_pciercx_cfg041_s { 1546 1546 - #ifdef __BIG_ENDIAN_BITFIELD 1547 1547 - uint32_t reserved_0_31:32; 1548 1548 - #else 1549 1549 - uint32_t reserved_0_31:32; 1550 1550 - #endif 1551 1551 - } s; 1552 1552 - struct cvmx_pciercx_cfg041_s cn52xx; 1553 1553 - struct cvmx_pciercx_cfg041_s cn52xxp1; 1554 1554 - struct cvmx_pciercx_cfg041_s cn56xx; 1555 1555 - struct cvmx_pciercx_cfg041_s cn56xxp1; 1556 1556 - struct cvmx_pciercx_cfg041_s cn61xx; 1557 1557 - struct cvmx_pciercx_cfg041_s cn63xx; 1558 1558 - struct cvmx_pciercx_cfg041_s cn63xxp1; 1559 1559 - struct cvmx_pciercx_cfg041_s cn66xx; 1560 1560 - struct cvmx_pciercx_cfg041_s cn68xx; 1561 1561 - struct cvmx_pciercx_cfg041_s cn68xxp1; 1562 1562 - struct cvmx_pciercx_cfg041_s cnf71xx; 1563 1563 - }; 1564 1564 - 1565 1565 - union cvmx_pciercx_cfg042 { 1566 1566 - uint32_t u32; 1567 1567 - struct cvmx_pciercx_cfg042_s { 1568 1568 - #ifdef __BIG_ENDIAN_BITFIELD 1569 1569 - uint32_t reserved_0_31:32; 1570 1570 - #else 1571 1571 - uint32_t reserved_0_31:32; 1572 1572 - #endif 1573 1573 - } s; 1574 1574 - struct cvmx_pciercx_cfg042_s cn52xx; 1575 1575 - struct cvmx_pciercx_cfg042_s cn52xxp1; 1576 1576 - struct cvmx_pciercx_cfg042_s cn56xx; 1577 1577 - struct cvmx_pciercx_cfg042_s cn56xxp1; 1578 1578 - struct cvmx_pciercx_cfg042_s cn61xx; 1579 1579 - struct cvmx_pciercx_cfg042_s cn63xx; 1580 1580 - struct cvmx_pciercx_cfg042_s cn63xxp1; 1581 1581 - struct cvmx_pciercx_cfg042_s cn66xx; 1582 1582 - struct cvmx_pciercx_cfg042_s cn68xx; 1583 1583 - struct cvmx_pciercx_cfg042_s cn68xxp1; 1584 1584 - struct cvmx_pciercx_cfg042_s cnf71xx; 1585 1585 - }; 1586 1586 - 1587 1587 - union cvmx_pciercx_cfg064 { 1588 1588 - uint32_t u32; 1589 1589 - struct cvmx_pciercx_cfg064_s { 1590 1590 - #ifdef __BIG_ENDIAN_BITFIELD 1591 1591 - uint32_t nco:12; 1592 1592 - uint32_t cv:4; 1593 1593 - uint32_t pcieec:16; 1594 1594 - #else 1595 1595 - uint32_t pcieec:16; 1596 1596 - uint32_t cv:4; 1597 1597 - uint32_t nco:12; 1598 1598 - #endif 1599 1599 - } s; 1600 1600 - struct cvmx_pciercx_cfg064_s cn52xx; 1601 1601 - struct cvmx_pciercx_cfg064_s cn52xxp1; 1602 1602 - struct cvmx_pciercx_cfg064_s cn56xx; 1603 1603 - struct cvmx_pciercx_cfg064_s cn56xxp1; 1604 1604 - struct cvmx_pciercx_cfg064_s cn61xx; 1605 1605 - struct cvmx_pciercx_cfg064_s cn63xx; 1606 1606 - struct cvmx_pciercx_cfg064_s cn63xxp1; 1607 1607 - struct cvmx_pciercx_cfg064_s cn66xx; 1608 1608 - struct cvmx_pciercx_cfg064_s cn68xx; 1609 1609 - struct cvmx_pciercx_cfg064_s cn68xxp1; 1610 1610 - struct cvmx_pciercx_cfg064_s cnf71xx; 1611 1611 - }; 1612 1612 - 1613 1613 - union cvmx_pciercx_cfg065 { 1614 1614 - uint32_t u32; 1615 1615 - struct cvmx_pciercx_cfg065_s { 1616 1616 - #ifdef __BIG_ENDIAN_BITFIELD 1617 1617 - uint32_t reserved_25_31:7; 1618 1618 - uint32_t uatombs:1; 1619 1619 - uint32_t reserved_23_23:1; 1620 1620 - uint32_t ucies:1; 1621 1621 - uint32_t reserved_21_21:1; 1622 1622 - uint32_t ures:1; 1623 1623 - uint32_t ecrces:1; 1624 1624 - uint32_t mtlps:1; 1625 1625 - uint32_t ros:1; 1626 1626 - uint32_t ucs:1; 1627 1627 - uint32_t cas:1; 1628 1628 - uint32_t cts:1; 1629 1629 - uint32_t fcpes:1; 1630 1630 - uint32_t ptlps:1; 1631 1631 - uint32_t reserved_6_11:6; 1632 1632 - uint32_t sdes:1; 1633 1633 - uint32_t dlpes:1; 1634 1634 - uint32_t reserved_0_3:4; 1635 1635 - #else 1636 1636 - uint32_t reserved_0_3:4; 1637 1637 - uint32_t dlpes:1; 1638 1638 - uint32_t sdes:1; 1639 1639 - uint32_t reserved_6_11:6; 1640 1640 - uint32_t ptlps:1; 1641 1641 - uint32_t fcpes:1; 1642 1642 - uint32_t cts:1; 1643 1643 - uint32_t cas:1; 1644 1644 - uint32_t ucs:1; 1645 1645 - uint32_t ros:1; 1646 1646 - uint32_t mtlps:1; 1647 1647 - uint32_t ecrces:1; 1648 1648 - uint32_t ures:1; 1649 1649 - uint32_t reserved_21_21:1; 1650 1650 - uint32_t ucies:1; 1651 1651 - uint32_t reserved_23_23:1; 1652 1652 - uint32_t uatombs:1; 1653 1653 - uint32_t reserved_25_31:7; 1654 1654 - #endif 1655 1655 - } s; 1656 1656 - struct cvmx_pciercx_cfg065_cn52xx { 1657 1657 - #ifdef __BIG_ENDIAN_BITFIELD 1658 1658 - uint32_t reserved_21_31:11; 1659 1659 - uint32_t ures:1; 1660 1660 - uint32_t ecrces:1; 1661 1661 - uint32_t mtlps:1; 1662 1662 - uint32_t ros:1; 1663 1663 - uint32_t ucs:1; 1664 1664 - uint32_t cas:1; 1665 1665 - uint32_t cts:1; 1666 1666 - uint32_t fcpes:1; 1667 1667 - uint32_t ptlps:1; 1668 1668 - uint32_t reserved_6_11:6; 1669 1669 - uint32_t sdes:1; 1670 1670 - uint32_t dlpes:1; 1671 1671 - uint32_t reserved_0_3:4; 1672 1672 - #else 1673 1673 - uint32_t reserved_0_3:4; 1674 1674 - uint32_t dlpes:1; 1675 1675 - uint32_t sdes:1; 1676 1676 - uint32_t reserved_6_11:6; 1677 1677 - uint32_t ptlps:1; 1678 1678 - uint32_t fcpes:1; 1679 1679 - uint32_t cts:1; 1680 1680 - uint32_t cas:1; 1681 1681 - uint32_t ucs:1; 1682 1682 - uint32_t ros:1; 1683 1683 - uint32_t mtlps:1; 1684 1684 - uint32_t ecrces:1; 1685 1685 - uint32_t ures:1; 1686 1686 - uint32_t reserved_21_31:11; 1687 1687 - #endif 1688 1688 - } cn52xx; 1689 1689 - struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; 1690 1690 - struct cvmx_pciercx_cfg065_cn52xx cn56xx; 1691 1691 - struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; 1692 1692 - struct cvmx_pciercx_cfg065_cn61xx { 1693 1693 - #ifdef __BIG_ENDIAN_BITFIELD 1694 1694 - uint32_t reserved_25_31:7; 1695 1695 - uint32_t uatombs:1; 1696 1696 - uint32_t reserved_21_23:3; 1697 1697 - uint32_t ures:1; 1698 1698 - uint32_t ecrces:1; 1699 1699 - uint32_t mtlps:1; 1700 1700 - uint32_t ros:1; 1701 1701 - uint32_t ucs:1; 1702 1702 - uint32_t cas:1; 1703 1703 - uint32_t cts:1; 1704 1704 - uint32_t fcpes:1; 1705 1705 - uint32_t ptlps:1; 1706 1706 - uint32_t reserved_6_11:6; 1707 1707 - uint32_t sdes:1; 1708 1708 - uint32_t dlpes:1; 1709 1709 - uint32_t reserved_0_3:4; 1710 1710 - #else 1711 1711 - uint32_t reserved_0_3:4; 1712 1712 - uint32_t dlpes:1; 1713 1713 - uint32_t sdes:1; 1714 1714 - uint32_t reserved_6_11:6; 1715 1715 - uint32_t ptlps:1; 1716 1716 - uint32_t fcpes:1; 1717 1717 - uint32_t cts:1; 1718 1718 - uint32_t cas:1; 1719 1719 - uint32_t ucs:1; 1720 1720 - uint32_t ros:1; 1721 1721 - uint32_t mtlps:1; 1722 1722 - uint32_t ecrces:1; 1723 1723 - uint32_t ures:1; 1724 1724 - uint32_t reserved_21_23:3; 1725 1725 - uint32_t uatombs:1; 1726 1726 - uint32_t reserved_25_31:7; 1727 1727 - #endif 1728 1728 - } cn61xx; 1729 1729 - struct cvmx_pciercx_cfg065_cn52xx cn63xx; 1730 1730 - struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; 1731 1731 - struct cvmx_pciercx_cfg065_cn61xx cn66xx; 1732 1732 - struct cvmx_pciercx_cfg065_cn61xx cn68xx; 1733 1733 - struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; 1734 1734 - struct cvmx_pciercx_cfg065_s cnf71xx; 1735 1735 - }; 1736 1736 - 1737 1737 - union cvmx_pciercx_cfg066 { 1738 1738 - uint32_t u32; 1739 1739 - struct cvmx_pciercx_cfg066_s { 1740 1740 - #ifdef __BIG_ENDIAN_BITFIELD 1741 1741 - uint32_t reserved_25_31:7; 1742 1742 - uint32_t uatombm:1; 1743 1743 - uint32_t reserved_23_23:1; 1744 1744 - uint32_t uciem:1; 1745 1745 - uint32_t reserved_21_21:1; 1746 1746 - uint32_t urem:1; 1747 1747 - uint32_t ecrcem:1; 1748 1748 - uint32_t mtlpm:1; 1749 1749 - uint32_t rom:1; 1750 1750 - uint32_t ucm:1; 1751 1751 - uint32_t cam:1; 1752 1752 - uint32_t ctm:1; 1753 1753 - uint32_t fcpem:1; 1754 1754 - uint32_t ptlpm:1; 1755 1755 - uint32_t reserved_6_11:6; 1756 1756 - uint32_t sdem:1; 1757 1757 - uint32_t dlpem:1; 1758 1758 - uint32_t reserved_0_3:4; 1759 1759 - #else 1760 1760 - uint32_t reserved_0_3:4; 1761 1761 - uint32_t dlpem:1; 1762 1762 - uint32_t sdem:1; 1763 1763 - uint32_t reserved_6_11:6; 1764 1764 - uint32_t ptlpm:1; 1765 1765 - uint32_t fcpem:1; 1766 1766 - uint32_t ctm:1; 1767 1767 - uint32_t cam:1; 1768 1768 - uint32_t ucm:1; 1769 1769 - uint32_t rom:1; 1770 1770 - uint32_t mtlpm:1; 1771 1771 - uint32_t ecrcem:1; 1772 1772 - uint32_t urem:1; 1773 1773 - uint32_t reserved_21_21:1; 1774 1774 - uint32_t uciem:1; 1775 1775 - uint32_t reserved_23_23:1; 1776 1776 - uint32_t uatombm:1; 1777 1777 - uint32_t reserved_25_31:7; 1778 1778 - #endif 1779 1779 - } s; 1780 1780 - struct cvmx_pciercx_cfg066_cn52xx { 1781 1781 - #ifdef __BIG_ENDIAN_BITFIELD 1782 1782 - uint32_t reserved_21_31:11; 1783 1783 - uint32_t urem:1; 1784 1784 - uint32_t ecrcem:1; 1785 1785 - uint32_t mtlpm:1; 1786 1786 - uint32_t rom:1; 1787 1787 - uint32_t ucm:1; 1788 1788 - uint32_t cam:1; 1789 1789 - uint32_t ctm:1; 1790 1790 - uint32_t fcpem:1; 1791 1791 - uint32_t ptlpm:1; 1792 1792 - uint32_t reserved_6_11:6; 1793 1793 - uint32_t sdem:1; 1794 1794 - uint32_t dlpem:1; 1795 1795 - uint32_t reserved_0_3:4; 1796 1796 - #else 1797 1797 - uint32_t reserved_0_3:4; 1798 1798 - uint32_t dlpem:1; 1799 1799 - uint32_t sdem:1; 1800 1800 - uint32_t reserved_6_11:6; 1801 1801 - uint32_t ptlpm:1; 1802 1802 - uint32_t fcpem:1; 1803 1803 - uint32_t ctm:1; 1804 1804 - uint32_t cam:1; 1805 1805 - uint32_t ucm:1; 1806 1806 - uint32_t rom:1; 1807 1807 - uint32_t mtlpm:1; 1808 1808 - uint32_t ecrcem:1; 1809 1809 - uint32_t urem:1; 1810 1810 - uint32_t reserved_21_31:11; 1811 1811 - #endif 1812 1812 - } cn52xx; 1813 1813 - struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; 1814 1814 - struct cvmx_pciercx_cfg066_cn52xx cn56xx; 1815 1815 - struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; 1816 1816 - struct cvmx_pciercx_cfg066_cn61xx { 1817 1817 - #ifdef __BIG_ENDIAN_BITFIELD 1818 1818 - uint32_t reserved_25_31:7; 1819 1819 - uint32_t uatombm:1; 1820 1820 - uint32_t reserved_21_23:3; 1821 1821 - uint32_t urem:1; 1822 1822 - uint32_t ecrcem:1; 1823 1823 - uint32_t mtlpm:1; 1824 1824 - uint32_t rom:1; 1825 1825 - uint32_t ucm:1; 1826 1826 - uint32_t cam:1; 1827 1827 - uint32_t ctm:1; 1828 1828 - uint32_t fcpem:1; 1829 1829 - uint32_t ptlpm:1; 1830 1830 - uint32_t reserved_6_11:6; 1831 1831 - uint32_t sdem:1; 1832 1832 - uint32_t dlpem:1; 1833 1833 - uint32_t reserved_0_3:4; 1834 1834 - #else 1835 1835 - uint32_t reserved_0_3:4; 1836 1836 - uint32_t dlpem:1; 1837 1837 - uint32_t sdem:1; 1838 1838 - uint32_t reserved_6_11:6; 1839 1839 - uint32_t ptlpm:1; 1840 1840 - uint32_t fcpem:1; 1841 1841 - uint32_t ctm:1; 1842 1842 - uint32_t cam:1; 1843 1843 - uint32_t ucm:1; 1844 1844 - uint32_t rom:1; 1845 1845 - uint32_t mtlpm:1; 1846 1846 - uint32_t ecrcem:1; 1847 1847 - uint32_t urem:1; 1848 1848 - uint32_t reserved_21_23:3; 1849 1849 - uint32_t uatombm:1; 1850 1850 - uint32_t reserved_25_31:7; 1851 1851 - #endif 1852 1852 - } cn61xx; 1853 1853 - struct cvmx_pciercx_cfg066_cn52xx cn63xx; 1854 1854 - struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; 1855 1855 - struct cvmx_pciercx_cfg066_cn61xx cn66xx; 1856 1856 - struct cvmx_pciercx_cfg066_cn61xx cn68xx; 1857 1857 - struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; 1858 1858 - struct cvmx_pciercx_cfg066_s cnf71xx; 1859 1859 - }; 1860 1860 - 1861 1861 - union cvmx_pciercx_cfg067 { 1862 1862 - uint32_t u32; 1863 1863 - struct cvmx_pciercx_cfg067_s { 1864 1864 - #ifdef __BIG_ENDIAN_BITFIELD 1865 1865 - uint32_t reserved_25_31:7; 1866 1866 - uint32_t uatombs:1; 1867 1867 - uint32_t reserved_23_23:1; 1868 1868 - uint32_t ucies:1; 1869 1869 - uint32_t reserved_21_21:1; 1870 1870 - uint32_t ures:1; 1871 1871 - uint32_t ecrces:1; 1872 1872 - uint32_t mtlps:1; 1873 1873 - uint32_t ros:1; 1874 1874 - uint32_t ucs:1; 1875 1875 - uint32_t cas:1; 1876 1876 - uint32_t cts:1; 1877 1877 - uint32_t fcpes:1; 1878 1878 - uint32_t ptlps:1; 1879 1879 - uint32_t reserved_6_11:6; 1880 1880 - uint32_t sdes:1; 1881 1881 - uint32_t dlpes:1; 1882 1882 - uint32_t reserved_0_3:4; 1883 1883 - #else 1884 1884 - uint32_t reserved_0_3:4; 1885 1885 - uint32_t dlpes:1; 1886 1886 - uint32_t sdes:1; 1887 1887 - uint32_t reserved_6_11:6; 1888 1888 - uint32_t ptlps:1; 1889 1889 - uint32_t fcpes:1; 1890 1890 - uint32_t cts:1; 1891 1891 - uint32_t cas:1; 1892 1892 - uint32_t ucs:1; 1893 1893 - uint32_t ros:1; 1894 1894 - uint32_t mtlps:1; 1895 1895 - uint32_t ecrces:1; 1896 1896 - uint32_t ures:1; 1897 1897 - uint32_t reserved_21_21:1; 1898 1898 - uint32_t ucies:1; 1899 1899 - uint32_t reserved_23_23:1; 1900 1900 - uint32_t uatombs:1; 1901 1901 - uint32_t reserved_25_31:7; 1902 1902 - #endif 1903 1903 - } s; 1904 1904 - struct cvmx_pciercx_cfg067_cn52xx { 1905 1905 - #ifdef __BIG_ENDIAN_BITFIELD 1906 1906 - uint32_t reserved_21_31:11; 1907 1907 - uint32_t ures:1; 1908 1908 - uint32_t ecrces:1; 1909 1909 - uint32_t mtlps:1; 1910 1910 - uint32_t ros:1; 1911 1911 - uint32_t ucs:1; 1912 1912 - uint32_t cas:1; 1913 1913 - uint32_t cts:1; 1914 1914 - uint32_t fcpes:1; 1915 1915 - uint32_t ptlps:1; 1916 1916 - uint32_t reserved_6_11:6; 1917 1917 - uint32_t sdes:1; 1918 1918 - uint32_t dlpes:1; 1919 1919 - uint32_t reserved_0_3:4; 1920 1920 - #else 1921 1921 - uint32_t reserved_0_3:4; 1922 1922 - uint32_t dlpes:1; 1923 1923 - uint32_t sdes:1; 1924 1924 - uint32_t reserved_6_11:6; 1925 1925 - uint32_t ptlps:1; 1926 1926 - uint32_t fcpes:1; 1927 1927 - uint32_t cts:1; 1928 1928 - uint32_t cas:1; 1929 1929 - uint32_t ucs:1; 1930 1930 - uint32_t ros:1; 1931 1931 - uint32_t mtlps:1; 1932 1932 - uint32_t ecrces:1; 1933 1933 - uint32_t ures:1; 1934 1934 - uint32_t reserved_21_31:11; 1935 1935 - #endif 1936 1936 - } cn52xx; 1937 1937 - struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; 1938 1938 - struct cvmx_pciercx_cfg067_cn52xx cn56xx; 1939 1939 - struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; 1940 1940 - struct cvmx_pciercx_cfg067_cn61xx { 1941 1941 - #ifdef __BIG_ENDIAN_BITFIELD 1942 1942 - uint32_t reserved_25_31:7; 1943 1943 - uint32_t uatombs:1; 1944 1944 - uint32_t reserved_21_23:3; 1945 1945 - uint32_t ures:1; 1946 1946 - uint32_t ecrces:1; 1947 1947 - uint32_t mtlps:1; 1948 1948 - uint32_t ros:1; 1949 1949 - uint32_t ucs:1; 1950 1950 - uint32_t cas:1; 1951 1951 - uint32_t cts:1; 1952 1952 - uint32_t fcpes:1; 1953 1953 - uint32_t ptlps:1; 1954 1954 - uint32_t reserved_6_11:6; 1955 1955 - uint32_t sdes:1; 1956 1956 - uint32_t dlpes:1; 1957 1957 - uint32_t reserved_0_3:4; 1958 1958 - #else 1959 1959 - uint32_t reserved_0_3:4; 1960 1960 - uint32_t dlpes:1; 1961 1961 - uint32_t sdes:1; 1962 1962 - uint32_t reserved_6_11:6; 1963 1963 - uint32_t ptlps:1; 1964 1964 - uint32_t fcpes:1; 1965 1965 - uint32_t cts:1; 1966 1966 - uint32_t cas:1; 1967 1967 - uint32_t ucs:1; 1968 1968 - uint32_t ros:1; 1969 1969 - uint32_t mtlps:1; 1970 1970 - uint32_t ecrces:1; 1971 1971 - uint32_t ures:1; 1972 1972 - uint32_t reserved_21_23:3; 1973 1973 - uint32_t uatombs:1; 1974 1974 - uint32_t reserved_25_31:7; 1975 1975 - #endif 1976 1976 - } cn61xx; 1977 1977 - struct cvmx_pciercx_cfg067_cn52xx cn63xx; 1978 1978 - struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; 1979 1979 - struct cvmx_pciercx_cfg067_cn61xx cn66xx; 1980 1980 - struct cvmx_pciercx_cfg067_cn61xx cn68xx; 1981 1981 - struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; 1982 1982 - struct cvmx_pciercx_cfg067_s cnf71xx; 1983 1983 - }; 1984 1984 - 1985 1985 - union cvmx_pciercx_cfg068 { 1986 1986 - uint32_t u32; 1987 1987 - struct cvmx_pciercx_cfg068_s { 1988 1988 - #ifdef __BIG_ENDIAN_BITFIELD 1989 1989 - uint32_t reserved_15_31:17; 1990 1990 - uint32_t cies:1; 1991 1991 - uint32_t anfes:1; 1992 1992 - uint32_t rtts:1; 1993 1993 - uint32_t reserved_9_11:3; 1994 1994 - uint32_t rnrs:1; 1995 1995 - uint32_t bdllps:1; 1996 1996 - uint32_t btlps:1; 1997 1997 - uint32_t reserved_1_5:5; 1998 1998 - uint32_t res:1; 1999 1999 - #else 2000 2000 - uint32_t res:1; 2001 2001 - uint32_t reserved_1_5:5; 2002 2002 - uint32_t btlps:1; 2003 2003 - uint32_t bdllps:1; 2004 2004 - uint32_t rnrs:1; 2005 2005 - uint32_t reserved_9_11:3; 2006 2006 - uint32_t rtts:1; 2007 2007 - uint32_t anfes:1; 2008 2008 - uint32_t cies:1; 2009 2009 - uint32_t reserved_15_31:17; 2010 2010 - #endif 2011 2011 - } s; 2012 2012 - struct cvmx_pciercx_cfg068_cn52xx { 2013 2013 - #ifdef __BIG_ENDIAN_BITFIELD 2014 2014 - uint32_t reserved_14_31:18; 2015 2015 - uint32_t anfes:1; 2016 2016 - uint32_t rtts:1; 2017 2017 - uint32_t reserved_9_11:3; 2018 2018 - uint32_t rnrs:1; 2019 2019 - uint32_t bdllps:1; 2020 2020 - uint32_t btlps:1; 2021 2021 - uint32_t reserved_1_5:5; 2022 2022 - uint32_t res:1; 2023 2023 - #else 2024 2024 - uint32_t res:1; 2025 2025 - uint32_t reserved_1_5:5; 2026 2026 - uint32_t btlps:1; 2027 2027 - uint32_t bdllps:1; 2028 2028 - uint32_t rnrs:1; 2029 2029 - uint32_t reserved_9_11:3; 2030 2030 - uint32_t rtts:1; 2031 2031 - uint32_t anfes:1; 2032 2032 - uint32_t reserved_14_31:18; 2033 2033 - #endif 2034 2034 - } cn52xx; 2035 2035 - struct cvmx_pciercx_cfg068_cn52xx cn52xxp1; 2036 2036 - struct cvmx_pciercx_cfg068_cn52xx cn56xx; 2037 2037 - struct cvmx_pciercx_cfg068_cn52xx cn56xxp1; 2038 2038 - struct cvmx_pciercx_cfg068_cn52xx cn61xx; 2039 2039 - struct cvmx_pciercx_cfg068_cn52xx cn63xx; 2040 2040 - struct cvmx_pciercx_cfg068_cn52xx cn63xxp1; 2041 2041 - struct cvmx_pciercx_cfg068_cn52xx cn66xx; 2042 2042 - struct cvmx_pciercx_cfg068_cn52xx cn68xx; 2043 2043 - struct cvmx_pciercx_cfg068_cn52xx cn68xxp1; 2044 2044 - struct cvmx_pciercx_cfg068_s cnf71xx; 2045 2045 - }; 2046 2046 - 2047 2047 - union cvmx_pciercx_cfg069 { 2048 2048 - uint32_t u32; 2049 2049 - struct cvmx_pciercx_cfg069_s { 2050 2050 - #ifdef __BIG_ENDIAN_BITFIELD 2051 2051 - uint32_t reserved_15_31:17; 2052 2052 - uint32_t ciem:1; 2053 2053 - uint32_t anfem:1; 2054 2054 - uint32_t rttm:1; 2055 2055 - uint32_t reserved_9_11:3; 2056 2056 - uint32_t rnrm:1; 2057 2057 - uint32_t bdllpm:1; 2058 2058 - uint32_t btlpm:1; 2059 2059 - uint32_t reserved_1_5:5; 2060 2060 - uint32_t rem:1; 2061 2061 - #else 2062 2062 - uint32_t rem:1; 2063 2063 - uint32_t reserved_1_5:5; 2064 2064 - uint32_t btlpm:1; 2065 2065 - uint32_t bdllpm:1; 2066 2066 - uint32_t rnrm:1; 2067 2067 - uint32_t reserved_9_11:3; 2068 2068 - uint32_t rttm:1; 2069 2069 - uint32_t anfem:1; 2070 2070 - uint32_t ciem:1; 2071 2071 - uint32_t reserved_15_31:17; 2072 2072 - #endif 2073 2073 - } s; 2074 2074 - struct cvmx_pciercx_cfg069_cn52xx { 2075 2075 - #ifdef __BIG_ENDIAN_BITFIELD 2076 2076 - uint32_t reserved_14_31:18; 2077 2077 - uint32_t anfem:1; 2078 2078 - uint32_t rttm:1; 2079 2079 - uint32_t reserved_9_11:3; 2080 2080 - uint32_t rnrm:1; 2081 2081 - uint32_t bdllpm:1; 2082 2082 - uint32_t btlpm:1; 2083 2083 - uint32_t reserved_1_5:5; 2084 2084 - uint32_t rem:1; 2085 2085 - #else 2086 2086 - uint32_t rem:1; 2087 2087 - uint32_t reserved_1_5:5; 2088 2088 - uint32_t btlpm:1; 2089 2089 - uint32_t bdllpm:1; 2090 2090 - uint32_t rnrm:1; 2091 2091 - uint32_t reserved_9_11:3; 2092 2092 - uint32_t rttm:1; 2093 2093 - uint32_t anfem:1; 2094 2094 - uint32_t reserved_14_31:18; 2095 2095 - #endif 2096 2096 - } cn52xx; 2097 2097 - struct cvmx_pciercx_cfg069_cn52xx cn52xxp1; 2098 2098 - struct cvmx_pciercx_cfg069_cn52xx cn56xx; 2099 2099 - struct cvmx_pciercx_cfg069_cn52xx cn56xxp1; 2100 2100 - struct cvmx_pciercx_cfg069_cn52xx cn61xx; 2101 2101 - struct cvmx_pciercx_cfg069_cn52xx cn63xx; 2102 2102 - struct cvmx_pciercx_cfg069_cn52xx cn63xxp1; 2103 2103 - struct cvmx_pciercx_cfg069_cn52xx cn66xx; 2104 2104 - struct cvmx_pciercx_cfg069_cn52xx cn68xx; 2105 2105 - struct cvmx_pciercx_cfg069_cn52xx cn68xxp1; 2106 2106 - struct cvmx_pciercx_cfg069_s cnf71xx; 2107 270 }; 2108 271 2109 272 union cvmx_pciercx_cfg070 { 2110 273 uint32_t u32; 2111 274 struct cvmx_pciercx_cfg070_s { 2112 2112 - #ifdef __BIG_ENDIAN_BITFIELD 2113 2113 - uint32_t reserved_9_31:23; 2114 2114 - uint32_t ce:1; 2115 2115 - uint32_t cc:1; 2116 2116 - uint32_t ge:1; 2117 2117 - uint32_t gc:1; 2118 2118 - uint32_t fep:5; 2119 2119 - #else 2120 2120 - uint32_t fep:5; 2121 2121 - uint32_t gc:1; 2122 2122 - uint32_t ge:1; 2123 2123 - uint32_t cc:1; 2124 2124 - uint32_t ce:1; 2125 2125 - uint32_t reserved_9_31:23; 2126 2126 - #endif 275 275 + __BITFIELD_FIELD(uint32_t reserved_12_31:20, 276 276 + __BITFIELD_FIELD(uint32_t tplp:1, 277 277 + __BITFIELD_FIELD(uint32_t reserved_9_10:2, 278 278 + __BITFIELD_FIELD(uint32_t ce:1, 279 279 + __BITFIELD_FIELD(uint32_t cc:1, 280 280 + __BITFIELD_FIELD(uint32_t ge:1, 281 281 + __BITFIELD_FIELD(uint32_t gc:1, 282 282 + __BITFIELD_FIELD(uint32_t fep:5, 283 283 + ;)))))))) 2127 284 } s; 2128 2128 - struct cvmx_pciercx_cfg070_s cn52xx; 2129 2129 - struct cvmx_pciercx_cfg070_s cn52xxp1; 2130 2130 - struct cvmx_pciercx_cfg070_s cn56xx; 2131 2131 - struct cvmx_pciercx_cfg070_s cn56xxp1; 2132 2132 - struct cvmx_pciercx_cfg070_s cn61xx; 2133 2133 - struct cvmx_pciercx_cfg070_s cn63xx; 2134 2134 - struct cvmx_pciercx_cfg070_s cn63xxp1; 2135 2135 - struct cvmx_pciercx_cfg070_s cn66xx; 2136 2136 - struct cvmx_pciercx_cfg070_s cn68xx; 2137 2137 - struct cvmx_pciercx_cfg070_s cn68xxp1; 2138 2138 - struct cvmx_pciercx_cfg070_s cnf71xx; 2139 2139 - }; 2140 2140 - 2141 2141 - union cvmx_pciercx_cfg071 { 2142 2142 - uint32_t u32; 2143 2143 - struct cvmx_pciercx_cfg071_s { 2144 2144 - #ifdef __BIG_ENDIAN_BITFIELD 2145 2145 - uint32_t dword1:32; 2146 2146 - #else 2147 2147 - uint32_t dword1:32; 2148 2148 - #endif 2149 2149 - } s; 2150 2150 - struct cvmx_pciercx_cfg071_s cn52xx; 2151 2151 - struct cvmx_pciercx_cfg071_s cn52xxp1; 2152 2152 - struct cvmx_pciercx_cfg071_s cn56xx; 2153 2153 - struct cvmx_pciercx_cfg071_s cn56xxp1; 2154 2154 - struct cvmx_pciercx_cfg071_s cn61xx; 2155 2155 - struct cvmx_pciercx_cfg071_s cn63xx; 2156 2156 - struct cvmx_pciercx_cfg071_s cn63xxp1; 2157 2157 - struct cvmx_pciercx_cfg071_s cn66xx; 2158 2158 - struct cvmx_pciercx_cfg071_s cn68xx; 2159 2159 - struct cvmx_pciercx_cfg071_s cn68xxp1; 2160 2160 - struct cvmx_pciercx_cfg071_s cnf71xx; 2161 2161 - }; 2162 2162 - 2163 2163 - union cvmx_pciercx_cfg072 { 2164 2164 - uint32_t u32; 2165 2165 - struct cvmx_pciercx_cfg072_s { 2166 2166 - #ifdef __BIG_ENDIAN_BITFIELD 2167 2167 - uint32_t dword2:32; 2168 2168 - #else 2169 2169 - uint32_t dword2:32; 2170 2170 - #endif 2171 2171 - } s; 2172 2172 - struct cvmx_pciercx_cfg072_s cn52xx; 2173 2173 - struct cvmx_pciercx_cfg072_s cn52xxp1; 2174 2174 - struct cvmx_pciercx_cfg072_s cn56xx; 2175 2175 - struct cvmx_pciercx_cfg072_s cn56xxp1; 2176 2176 - struct cvmx_pciercx_cfg072_s cn61xx; 2177 2177 - struct cvmx_pciercx_cfg072_s cn63xx; 2178 2178 - struct cvmx_pciercx_cfg072_s cn63xxp1; 2179 2179 - struct cvmx_pciercx_cfg072_s cn66xx; 2180 2180 - struct cvmx_pciercx_cfg072_s cn68xx; 2181 2181 - struct cvmx_pciercx_cfg072_s cn68xxp1; 2182 2182 - struct cvmx_pciercx_cfg072_s cnf71xx; 2183 2183 - }; 2184 2184 - 2185 2185 - union cvmx_pciercx_cfg073 { 2186 2186 - uint32_t u32; 2187 2187 - struct cvmx_pciercx_cfg073_s { 2188 2188 - #ifdef __BIG_ENDIAN_BITFIELD 2189 2189 - uint32_t dword3:32; 2190 2190 - #else 2191 2191 - uint32_t dword3:32; 2192 2192 - #endif 2193 2193 - } s; 2194 2194 - struct cvmx_pciercx_cfg073_s cn52xx; 2195 2195 - struct cvmx_pciercx_cfg073_s cn52xxp1; 2196 2196 - struct cvmx_pciercx_cfg073_s cn56xx; 2197 2197 - struct cvmx_pciercx_cfg073_s cn56xxp1; 2198 2198 - struct cvmx_pciercx_cfg073_s cn61xx; 2199 2199 - struct cvmx_pciercx_cfg073_s cn63xx; 2200 2200 - struct cvmx_pciercx_cfg073_s cn63xxp1; 2201 2201 - struct cvmx_pciercx_cfg073_s cn66xx; 2202 2202 - struct cvmx_pciercx_cfg073_s cn68xx; 2203 2203 - struct cvmx_pciercx_cfg073_s cn68xxp1; 2204 2204 - struct cvmx_pciercx_cfg073_s cnf71xx; 2205 2205 - }; 2206 2206 - 2207 2207 - union cvmx_pciercx_cfg074 { 2208 2208 - uint32_t u32; 2209 2209 - struct cvmx_pciercx_cfg074_s { 2210 2210 - #ifdef __BIG_ENDIAN_BITFIELD 2211 2211 - uint32_t dword4:32; 2212 2212 - #else 2213 2213 - uint32_t dword4:32; 2214 2214 - #endif 2215 2215 - } s; 2216 2216 - struct cvmx_pciercx_cfg074_s cn52xx; 2217 2217 - struct cvmx_pciercx_cfg074_s cn52xxp1; 2218 2218 - struct cvmx_pciercx_cfg074_s cn56xx; 2219 2219 - struct cvmx_pciercx_cfg074_s cn56xxp1; 2220 2220 - struct cvmx_pciercx_cfg074_s cn61xx; 2221 2221 - struct cvmx_pciercx_cfg074_s cn63xx; 2222 2222 - struct cvmx_pciercx_cfg074_s cn63xxp1; 2223 2223 - struct cvmx_pciercx_cfg074_s cn66xx; 2224 2224 - struct cvmx_pciercx_cfg074_s cn68xx; 2225 2225 - struct cvmx_pciercx_cfg074_s cn68xxp1; 2226 2226 - struct cvmx_pciercx_cfg074_s cnf71xx; 2227 285 }; 2228 286 2229 287 union cvmx_pciercx_cfg075 { 2230 288 uint32_t u32; 2231 289 struct cvmx_pciercx_cfg075_s { 2232 2232 - #ifdef __BIG_ENDIAN_BITFIELD 2233 2233 - uint32_t reserved_3_31:29; 2234 2234 - uint32_t fere:1; 2235 2235 - uint32_t nfere:1; 2236 2236 - uint32_t cere:1; 2237 2237 - #else 2238 2238 - uint32_t cere:1; 2239 2239 - uint32_t nfere:1; 2240 2240 - uint32_t fere:1; 2241 2241 - uint32_t reserved_3_31:29; 2242 2242 - #endif 290 290 + __BITFIELD_FIELD(uint32_t reserved_3_31:29, 291 291 + __BITFIELD_FIELD(uint32_t fere:1, 292 292 + __BITFIELD_FIELD(uint32_t nfere:1, 293 293 + __BITFIELD_FIELD(uint32_t cere:1, 294 294 + ;)))) 2243 295 } s; 2244 2244 - struct cvmx_pciercx_cfg075_s cn52xx; 2245 2245 - struct cvmx_pciercx_cfg075_s cn52xxp1; 2246 2246 - struct cvmx_pciercx_cfg075_s cn56xx; 2247 2247 - struct cvmx_pciercx_cfg075_s cn56xxp1; 2248 2248 - struct cvmx_pciercx_cfg075_s cn61xx; 2249 2249 - struct cvmx_pciercx_cfg075_s cn63xx; 2250 2250 - struct cvmx_pciercx_cfg075_s cn63xxp1; 2251 2251 - struct cvmx_pciercx_cfg075_s cn66xx; 2252 2252 - struct cvmx_pciercx_cfg075_s cn68xx; 2253 2253 - struct cvmx_pciercx_cfg075_s cn68xxp1; 2254 2254 - struct cvmx_pciercx_cfg075_s cnf71xx; 2255 2255 - }; 2256 2256 - 2257 2257 - union cvmx_pciercx_cfg076 { 2258 2258 - uint32_t u32; 2259 2259 - struct cvmx_pciercx_cfg076_s { 2260 2260 - #ifdef __BIG_ENDIAN_BITFIELD 2261 2261 - uint32_t aeimn:5; 2262 2262 - uint32_t reserved_7_26:20; 2263 2263 - uint32_t femr:1; 2264 2264 - uint32_t nfemr:1; 2265 2265 - uint32_t fuf:1; 2266 2266 - uint32_t multi_efnfr:1; 2267 2267 - uint32_t efnfr:1; 2268 2268 - uint32_t multi_ecr:1; 2269 2269 - uint32_t ecr:1; 2270 2270 - #else 2271 2271 - uint32_t ecr:1; 2272 2272 - uint32_t multi_ecr:1; 2273 2273 - uint32_t efnfr:1; 2274 2274 - uint32_t multi_efnfr:1; 2275 2275 - uint32_t fuf:1; 2276 2276 - uint32_t nfemr:1; 2277 2277 - uint32_t femr:1; 2278 2278 - uint32_t reserved_7_26:20; 2279 2279 - uint32_t aeimn:5; 2280 2280 - #endif 2281 2281 - } s; 2282 2282 - struct cvmx_pciercx_cfg076_s cn52xx; 2283 2283 - struct cvmx_pciercx_cfg076_s cn52xxp1; 2284 2284 - struct cvmx_pciercx_cfg076_s cn56xx; 2285 2285 - struct cvmx_pciercx_cfg076_s cn56xxp1; 2286 2286 - struct cvmx_pciercx_cfg076_s cn61xx; 2287 2287 - struct cvmx_pciercx_cfg076_s cn63xx; 2288 2288 - struct cvmx_pciercx_cfg076_s cn63xxp1; 2289 2289 - struct cvmx_pciercx_cfg076_s cn66xx; 2290 2290 - struct cvmx_pciercx_cfg076_s cn68xx; 2291 2291 - struct cvmx_pciercx_cfg076_s cn68xxp1; 2292 2292 - struct cvmx_pciercx_cfg076_s cnf71xx; 2293 2293 - }; 2294 2294 - 2295 2295 - union cvmx_pciercx_cfg077 { 2296 2296 - uint32_t u32; 2297 2297 - struct cvmx_pciercx_cfg077_s { 2298 2298 - #ifdef __BIG_ENDIAN_BITFIELD 2299 2299 - uint32_t efnfsi:16; 2300 2300 - uint32_t ecsi:16; 2301 2301 - #else 2302 2302 - uint32_t ecsi:16; 2303 2303 - uint32_t efnfsi:16; 2304 2304 - #endif 2305 2305 - } s; 2306 2306 - struct cvmx_pciercx_cfg077_s cn52xx; 2307 2307 - struct cvmx_pciercx_cfg077_s cn52xxp1; 2308 2308 - struct cvmx_pciercx_cfg077_s cn56xx; 2309 2309 - struct cvmx_pciercx_cfg077_s cn56xxp1; 2310 2310 - struct cvmx_pciercx_cfg077_s cn61xx; 2311 2311 - struct cvmx_pciercx_cfg077_s cn63xx; 2312 2312 - struct cvmx_pciercx_cfg077_s cn63xxp1; 2313 2313 - struct cvmx_pciercx_cfg077_s cn66xx; 2314 2314 - struct cvmx_pciercx_cfg077_s cn68xx; 2315 2315 - struct cvmx_pciercx_cfg077_s cn68xxp1; 2316 2316 - struct cvmx_pciercx_cfg077_s cnf71xx; 2317 296 }; 2318 297 2319 298 union cvmx_pciercx_cfg448 { 2320 299 uint32_t u32; 2321 300 struct cvmx_pciercx_cfg448_s { 2322 2322 - #ifdef __BIG_ENDIAN_BITFIELD 2323 2323 - uint32_t rtl:16; 2324 2324 - uint32_t rtltl:16; 2325 2325 - #else 2326 2326 - uint32_t rtltl:16; 2327 2327 - uint32_t rtl:16; 2328 2328 - #endif 301 301 + __BITFIELD_FIELD(uint32_t rtl:16, 302 302 + __BITFIELD_FIELD(uint32_t rtltl:16, 303 303 + ;)) 2329 304 } s; 2330 2330 - struct cvmx_pciercx_cfg448_s cn52xx; 2331 2331 - struct cvmx_pciercx_cfg448_s cn52xxp1; 2332 2332 - struct cvmx_pciercx_cfg448_s cn56xx; 2333 2333 - struct cvmx_pciercx_cfg448_s cn56xxp1; 2334 2334 - struct cvmx_pciercx_cfg448_s cn61xx; 2335 2335 - struct cvmx_pciercx_cfg448_s cn63xx; 2336 2336 - struct cvmx_pciercx_cfg448_s cn63xxp1; 2337 2337 - struct cvmx_pciercx_cfg448_s cn66xx; 2338 2338 - struct cvmx_pciercx_cfg448_s cn68xx; 2339 2339 - struct cvmx_pciercx_cfg448_s cn68xxp1; 2340 2340 - struct cvmx_pciercx_cfg448_s cnf71xx; 2341 2341 - }; 2342 2342 - 2343 2343 - union cvmx_pciercx_cfg449 { 2344 2344 - uint32_t u32; 2345 2345 - struct cvmx_pciercx_cfg449_s { 2346 2346 - #ifdef __BIG_ENDIAN_BITFIELD 2347 2347 - uint32_t omr:32; 2348 2348 - #else 2349 2349 - uint32_t omr:32; 2350 2350 - #endif 2351 2351 - } s; 2352 2352 - struct cvmx_pciercx_cfg449_s cn52xx; 2353 2353 - struct cvmx_pciercx_cfg449_s cn52xxp1; 2354 2354 - struct cvmx_pciercx_cfg449_s cn56xx; 2355 2355 - struct cvmx_pciercx_cfg449_s cn56xxp1; 2356 2356 - struct cvmx_pciercx_cfg449_s cn61xx; 2357 2357 - struct cvmx_pciercx_cfg449_s cn63xx; 2358 2358 - struct cvmx_pciercx_cfg449_s cn63xxp1; 2359 2359 - struct cvmx_pciercx_cfg449_s cn66xx; 2360 2360 - struct cvmx_pciercx_cfg449_s cn68xx; 2361 2361 - struct cvmx_pciercx_cfg449_s cn68xxp1; 2362 2362 - struct cvmx_pciercx_cfg449_s cnf71xx; 2363 2363 - }; 2364 2364 - 2365 2365 - union cvmx_pciercx_cfg450 { 2366 2366 - uint32_t u32; 2367 2367 - struct cvmx_pciercx_cfg450_s { 2368 2368 - #ifdef __BIG_ENDIAN_BITFIELD 2369 2369 - uint32_t lpec:8; 2370 2370 - uint32_t reserved_22_23:2; 2371 2371 - uint32_t link_state:6; 2372 2372 - uint32_t force_link:1; 2373 2373 - uint32_t reserved_8_14:7; 2374 2374 - uint32_t link_num:8; 2375 2375 - #else 2376 2376 - uint32_t link_num:8; 2377 2377 - uint32_t reserved_8_14:7; 2378 2378 - uint32_t force_link:1; 2379 2379 - uint32_t link_state:6; 2380 2380 - uint32_t reserved_22_23:2; 2381 2381 - uint32_t lpec:8; 2382 2382 - #endif 2383 2383 - } s; 2384 2384 - struct cvmx_pciercx_cfg450_s cn52xx; 2385 2385 - struct cvmx_pciercx_cfg450_s cn52xxp1; 2386 2386 - struct cvmx_pciercx_cfg450_s cn56xx; 2387 2387 - struct cvmx_pciercx_cfg450_s cn56xxp1; 2388 2388 - struct cvmx_pciercx_cfg450_s cn61xx; 2389 2389 - struct cvmx_pciercx_cfg450_s cn63xx; 2390 2390 - struct cvmx_pciercx_cfg450_s cn63xxp1; 2391 2391 - struct cvmx_pciercx_cfg450_s cn66xx; 2392 2392 - struct cvmx_pciercx_cfg450_s cn68xx; 2393 2393 - struct cvmx_pciercx_cfg450_s cn68xxp1; 2394 2394 - struct cvmx_pciercx_cfg450_s cnf71xx; 2395 2395 - }; 2396 2396 - 2397 2397 - union cvmx_pciercx_cfg451 { 2398 2398 - uint32_t u32; 2399 2399 - struct cvmx_pciercx_cfg451_s { 2400 2400 - #ifdef __BIG_ENDIAN_BITFIELD 2401 2401 - uint32_t reserved_31_31:1; 2402 2402 - uint32_t easpml1:1; 2403 2403 - uint32_t l1el:3; 2404 2404 - uint32_t l0el:3; 2405 2405 - uint32_t n_fts_cc:8; 2406 2406 - uint32_t n_fts:8; 2407 2407 - uint32_t ack_freq:8; 2408 2408 - #else 2409 2409 - uint32_t ack_freq:8; 2410 2410 - uint32_t n_fts:8; 2411 2411 - uint32_t n_fts_cc:8; 2412 2412 - uint32_t l0el:3; 2413 2413 - uint32_t l1el:3; 2414 2414 - uint32_t easpml1:1; 2415 2415 - uint32_t reserved_31_31:1; 2416 2416 - #endif 2417 2417 - } s; 2418 2418 - struct cvmx_pciercx_cfg451_cn52xx { 2419 2419 - #ifdef __BIG_ENDIAN_BITFIELD 2420 2420 - uint32_t reserved_30_31:2; 2421 2421 - uint32_t l1el:3; 2422 2422 - uint32_t l0el:3; 2423 2423 - uint32_t n_fts_cc:8; 2424 2424 - uint32_t n_fts:8; 2425 2425 - uint32_t ack_freq:8; 2426 2426 - #else 2427 2427 - uint32_t ack_freq:8; 2428 2428 - uint32_t n_fts:8; 2429 2429 - uint32_t n_fts_cc:8; 2430 2430 - uint32_t l0el:3; 2431 2431 - uint32_t l1el:3; 2432 2432 - uint32_t reserved_30_31:2; 2433 2433 - #endif 2434 2434 - } cn52xx; 2435 2435 - struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; 2436 2436 - struct cvmx_pciercx_cfg451_cn52xx cn56xx; 2437 2437 - struct cvmx_pciercx_cfg451_cn52xx cn56xxp1; 2438 2438 - struct cvmx_pciercx_cfg451_s cn61xx; 2439 2439 - struct cvmx_pciercx_cfg451_cn52xx cn63xx; 2440 2440 - struct cvmx_pciercx_cfg451_cn52xx cn63xxp1; 2441 2441 - struct cvmx_pciercx_cfg451_s cn66xx; 2442 2442 - struct cvmx_pciercx_cfg451_s cn68xx; 2443 2443 - struct cvmx_pciercx_cfg451_s cn68xxp1; 2444 2444 - struct cvmx_pciercx_cfg451_s cnf71xx; 2445 305 }; 2446 306 2447 307 union cvmx_pciercx_cfg452 { 2448 308 uint32_t u32; 2449 309 struct cvmx_pciercx_cfg452_s { 2450 2450 - #ifdef __BIG_ENDIAN_BITFIELD 2451 2451 - uint32_t reserved_26_31:6; 2452 2452 - uint32_t eccrc:1; 2453 2453 - uint32_t reserved_22_24:3; 2454 2454 - uint32_t lme:6; 2455 2455 - uint32_t reserved_8_15:8; 2456 2456 - uint32_t flm:1; 2457 2457 - uint32_t reserved_6_6:1; 2458 2458 - uint32_t dllle:1; 2459 2459 - uint32_t reserved_4_4:1; 2460 2460 - uint32_t ra:1; 2461 2461 - uint32_t le:1; 2462 2462 - uint32_t sd:1; 2463 2463 - uint32_t omr:1; 2464 2464 - #else 2465 2465 - uint32_t omr:1; 2466 2466 - uint32_t sd:1; 2467 2467 - uint32_t le:1; 2468 2468 - uint32_t ra:1; 2469 2469 - uint32_t reserved_4_4:1; 2470 2470 - uint32_t dllle:1; 2471 2471 - uint32_t reserved_6_6:1; 2472 2472 - uint32_t flm:1; 2473 2473 - uint32_t reserved_8_15:8; 2474 2474 - uint32_t lme:6; 2475 2475 - uint32_t reserved_22_24:3; 2476 2476 - uint32_t eccrc:1; 2477 2477 - uint32_t reserved_26_31:6; 2478 2478 - #endif 310 310 + __BITFIELD_FIELD(uint32_t reserved_26_31:6, 311 311 + __BITFIELD_FIELD(uint32_t eccrc:1, 312 312 + __BITFIELD_FIELD(uint32_t reserved_22_24:3, 313 313 + __BITFIELD_FIELD(uint32_t lme:6, 314 314 + __BITFIELD_FIELD(uint32_t reserved_12_15:4, 315 315 + __BITFIELD_FIELD(uint32_t link_rate:4, 316 316 + __BITFIELD_FIELD(uint32_t flm:1, 317 317 + __BITFIELD_FIELD(uint32_t reserved_6_6:1, 318 318 + __BITFIELD_FIELD(uint32_t dllle:1, 319 319 + __BITFIELD_FIELD(uint32_t reserved_4_4:1, 320 320 + __BITFIELD_FIELD(uint32_t ra:1, 321 321 + __BITFIELD_FIELD(uint32_t le:1, 322 322 + __BITFIELD_FIELD(uint32_t sd:1, 323 323 + __BITFIELD_FIELD(uint32_t omr:1, 324 324 + ;)))))))))))))) 2479 325 } s; 2480 2480 - struct cvmx_pciercx_cfg452_s cn52xx; 2481 2481 - struct cvmx_pciercx_cfg452_s cn52xxp1; 2482 2482 - struct cvmx_pciercx_cfg452_s cn56xx; 2483 2483 - struct cvmx_pciercx_cfg452_s cn56xxp1; 2484 2484 - struct cvmx_pciercx_cfg452_cn61xx { 2485 2485 - #ifdef __BIG_ENDIAN_BITFIELD 2486 2486 - uint32_t reserved_22_31:10; 2487 2487 - uint32_t lme:6; 2488 2488 - uint32_t reserved_8_15:8; 2489 2489 - uint32_t flm:1; 2490 2490 - uint32_t reserved_6_6:1; 2491 2491 - uint32_t dllle:1; 2492 2492 - uint32_t reserved_4_4:1; 2493 2493 - uint32_t ra:1; 2494 2494 - uint32_t le:1; 2495 2495 - uint32_t sd:1; 2496 2496 - uint32_t omr:1; 2497 2497 - #else 2498 2498 - uint32_t omr:1; 2499 2499 - uint32_t sd:1; 2500 2500 - uint32_t le:1; 2501 2501 - uint32_t ra:1; 2502 2502 - uint32_t reserved_4_4:1; 2503 2503 - uint32_t dllle:1; 2504 2504 - uint32_t reserved_6_6:1; 2505 2505 - uint32_t flm:1; 2506 2506 - uint32_t reserved_8_15:8; 2507 2507 - uint32_t lme:6; 2508 2508 - uint32_t reserved_22_31:10; 2509 2509 - #endif 2510 2510 - } cn61xx; 2511 2511 - struct cvmx_pciercx_cfg452_s cn63xx; 2512 2512 - struct cvmx_pciercx_cfg452_s cn63xxp1; 2513 2513 - struct cvmx_pciercx_cfg452_cn61xx cn66xx; 2514 2514 - struct cvmx_pciercx_cfg452_cn61xx cn68xx; 2515 2515 - struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; 2516 2516 - struct cvmx_pciercx_cfg452_cn61xx cnf71xx; 2517 2517 - }; 2518 2518 - 2519 2519 - union cvmx_pciercx_cfg453 { 2520 2520 - uint32_t u32; 2521 2521 - struct cvmx_pciercx_cfg453_s { 2522 2522 - #ifdef __BIG_ENDIAN_BITFIELD 2523 2523 - uint32_t dlld:1; 2524 2524 - uint32_t reserved_26_30:5; 2525 2525 - uint32_t ack_nak:1; 2526 2526 - uint32_t fcd:1; 2527 2527 - uint32_t ilst:24; 2528 2528 - #else 2529 2529 - uint32_t ilst:24; 2530 2530 - uint32_t fcd:1; 2531 2531 - uint32_t ack_nak:1; 2532 2532 - uint32_t reserved_26_30:5; 2533 2533 - uint32_t dlld:1; 2534 2534 - #endif 2535 2535 - } s; 2536 2536 - struct cvmx_pciercx_cfg453_s cn52xx; 2537 2537 - struct cvmx_pciercx_cfg453_s cn52xxp1; 2538 2538 - struct cvmx_pciercx_cfg453_s cn56xx; 2539 2539 - struct cvmx_pciercx_cfg453_s cn56xxp1; 2540 2540 - struct cvmx_pciercx_cfg453_s cn61xx; 2541 2541 - struct cvmx_pciercx_cfg453_s cn63xx; 2542 2542 - struct cvmx_pciercx_cfg453_s cn63xxp1; 2543 2543 - struct cvmx_pciercx_cfg453_s cn66xx; 2544 2544 - struct cvmx_pciercx_cfg453_s cn68xx; 2545 2545 - struct cvmx_pciercx_cfg453_s cn68xxp1; 2546 2546 - struct cvmx_pciercx_cfg453_s cnf71xx; 2547 2547 - }; 2548 2548 - 2549 2549 - union cvmx_pciercx_cfg454 { 2550 2550 - uint32_t u32; 2551 2551 - struct cvmx_pciercx_cfg454_s { 2552 2552 - #ifdef __BIG_ENDIAN_BITFIELD 2553 2553 - uint32_t cx_nfunc:3; 2554 2554 - uint32_t tmfcwt:5; 2555 2555 - uint32_t tmanlt:5; 2556 2556 - uint32_t tmrt:5; 2557 2557 - uint32_t reserved_11_13:3; 2558 2558 - uint32_t nskps:3; 2559 2559 - uint32_t reserved_0_7:8; 2560 2560 - #else 2561 2561 - uint32_t reserved_0_7:8; 2562 2562 - uint32_t nskps:3; 2563 2563 - uint32_t reserved_11_13:3; 2564 2564 - uint32_t tmrt:5; 2565 2565 - uint32_t tmanlt:5; 2566 2566 - uint32_t tmfcwt:5; 2567 2567 - uint32_t cx_nfunc:3; 2568 2568 - #endif 2569 2569 - } s; 2570 2570 - struct cvmx_pciercx_cfg454_cn52xx { 2571 2571 - #ifdef __BIG_ENDIAN_BITFIELD 2572 2572 - uint32_t reserved_29_31:3; 2573 2573 - uint32_t tmfcwt:5; 2574 2574 - uint32_t tmanlt:5; 2575 2575 - uint32_t tmrt:5; 2576 2576 - uint32_t reserved_11_13:3; 2577 2577 - uint32_t nskps:3; 2578 2578 - uint32_t reserved_4_7:4; 2579 2579 - uint32_t ntss:4; 2580 2580 - #else 2581 2581 - uint32_t ntss:4; 2582 2582 - uint32_t reserved_4_7:4; 2583 2583 - uint32_t nskps:3; 2584 2584 - uint32_t reserved_11_13:3; 2585 2585 - uint32_t tmrt:5; 2586 2586 - uint32_t tmanlt:5; 2587 2587 - uint32_t tmfcwt:5; 2588 2588 - uint32_t reserved_29_31:3; 2589 2589 - #endif 2590 2590 - } cn52xx; 2591 2591 - struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; 2592 2592 - struct cvmx_pciercx_cfg454_cn52xx cn56xx; 2593 2593 - struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; 2594 2594 - struct cvmx_pciercx_cfg454_cn61xx { 2595 2595 - #ifdef __BIG_ENDIAN_BITFIELD 2596 2596 - uint32_t cx_nfunc:3; 2597 2597 - uint32_t tmfcwt:5; 2598 2598 - uint32_t tmanlt:5; 2599 2599 - uint32_t tmrt:5; 2600 2600 - uint32_t reserved_8_13:6; 2601 2601 - uint32_t mfuncn:8; 2602 2602 - #else 2603 2603 - uint32_t mfuncn:8; 2604 2604 - uint32_t reserved_8_13:6; 2605 2605 - uint32_t tmrt:5; 2606 2606 - uint32_t tmanlt:5; 2607 2607 - uint32_t tmfcwt:5; 2608 2608 - uint32_t cx_nfunc:3; 2609 2609 - #endif 2610 2610 - } cn61xx; 2611 2611 - struct cvmx_pciercx_cfg454_cn52xx cn63xx; 2612 2612 - struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; 2613 2613 - struct cvmx_pciercx_cfg454_cn61xx cn66xx; 2614 2614 - struct cvmx_pciercx_cfg454_cn61xx cn68xx; 2615 2615 - struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; 2616 2616 - struct cvmx_pciercx_cfg454_cn61xx cnf71xx; 2617 326 }; 2618 327 2619 328 union cvmx_pciercx_cfg455 { 2620 329 uint32_t u32; 2621 330 struct cvmx_pciercx_cfg455_s { 2622 2622 - #ifdef __BIG_ENDIAN_BITFIELD 2623 2623 - uint32_t m_cfg0_filt:1; 2624 2624 - uint32_t m_io_filt:1; 2625 2625 - uint32_t msg_ctrl:1; 2626 2626 - uint32_t m_cpl_ecrc_filt:1; 2627 2627 - uint32_t m_ecrc_filt:1; 2628 2628 - uint32_t m_cpl_len_err:1; 2629 2629 - uint32_t m_cpl_attr_err:1; 2630 2630 - uint32_t m_cpl_tc_err:1; 2631 2631 - uint32_t m_cpl_fun_err:1; 2632 2632 - uint32_t m_cpl_rid_err:1; 2633 2633 - uint32_t m_cpl_tag_err:1; 2634 2634 - uint32_t m_lk_filt:1; 2635 2635 - uint32_t m_cfg1_filt:1; 2636 2636 - uint32_t m_bar_match:1; 2637 2637 - uint32_t m_pois_filt:1; 2638 2638 - uint32_t m_fun:1; 2639 2639 - uint32_t dfcwt:1; 2640 2640 - uint32_t reserved_11_14:4; 2641 2641 - uint32_t skpiv:11; 2642 2642 - #else 2643 2643 - uint32_t skpiv:11; 2644 2644 - uint32_t reserved_11_14:4; 2645 2645 - uint32_t dfcwt:1; 2646 2646 - uint32_t m_fun:1; 2647 2647 - uint32_t m_pois_filt:1; 2648 2648 - uint32_t m_bar_match:1; 2649 2649 - uint32_t m_cfg1_filt:1; 2650 2650 - uint32_t m_lk_filt:1; 2651 2651 - uint32_t m_cpl_tag_err:1; 2652 2652 - uint32_t m_cpl_rid_err:1; 2653 2653 - uint32_t m_cpl_fun_err:1; 2654 2654 - uint32_t m_cpl_tc_err:1; 2655 2655 - uint32_t m_cpl_attr_err:1; 2656 2656 - uint32_t m_cpl_len_err:1; 2657 2657 - uint32_t m_ecrc_filt:1; 2658 2658 - uint32_t m_cpl_ecrc_filt:1; 2659 2659 - uint32_t msg_ctrl:1; 2660 2660 - uint32_t m_io_filt:1; 2661 2661 - uint32_t m_cfg0_filt:1; 2662 2662 - #endif 331 331 + __BITFIELD_FIELD(uint32_t m_cfg0_filt:1, 332 332 + __BITFIELD_FIELD(uint32_t m_io_filt:1, 333 333 + __BITFIELD_FIELD(uint32_t msg_ctrl:1, 334 334 + __BITFIELD_FIELD(uint32_t m_cpl_ecrc_filt:1, 335 335 + __BITFIELD_FIELD(uint32_t m_ecrc_filt:1, 336 336 + __BITFIELD_FIELD(uint32_t m_cpl_len_err:1, 337 337 + __BITFIELD_FIELD(uint32_t m_cpl_attr_err:1, 338 338 + __BITFIELD_FIELD(uint32_t m_cpl_tc_err:1, 339 339 + __BITFIELD_FIELD(uint32_t m_cpl_fun_err:1, 340 340 + __BITFIELD_FIELD(uint32_t m_cpl_rid_err:1, 341 341 + __BITFIELD_FIELD(uint32_t m_cpl_tag_err:1, 342 342 + __BITFIELD_FIELD(uint32_t m_lk_filt:1, 343 343 + __BITFIELD_FIELD(uint32_t m_cfg1_filt:1, 344 344 + __BITFIELD_FIELD(uint32_t m_bar_match:1, 345 345 + __BITFIELD_FIELD(uint32_t m_pois_filt:1, 346 346 + __BITFIELD_FIELD(uint32_t m_fun:1, 347 347 + __BITFIELD_FIELD(uint32_t dfcwt:1, 348 348 + __BITFIELD_FIELD(uint32_t reserved_11_14:4, 349 349 + __BITFIELD_FIELD(uint32_t skpiv:11, 350 350 + ;))))))))))))))))))) 2663 351 } s; 2664 2664 - struct cvmx_pciercx_cfg455_s cn52xx; 2665 2665 - struct cvmx_pciercx_cfg455_s cn52xxp1; 2666 2666 - struct cvmx_pciercx_cfg455_s cn56xx; 2667 2667 - struct cvmx_pciercx_cfg455_s cn56xxp1; 2668 2668 - struct cvmx_pciercx_cfg455_s cn61xx; 2669 2669 - struct cvmx_pciercx_cfg455_s cn63xx; 2670 2670 - struct cvmx_pciercx_cfg455_s cn63xxp1; 2671 2671 - struct cvmx_pciercx_cfg455_s cn66xx; 2672 2672 - struct cvmx_pciercx_cfg455_s cn68xx; 2673 2673 - struct cvmx_pciercx_cfg455_s cn68xxp1; 2674 2674 - struct cvmx_pciercx_cfg455_s cnf71xx; 2675 2675 - }; 2676 2676 - 2677 2677 - union cvmx_pciercx_cfg456 { 2678 2678 - uint32_t u32; 2679 2679 - struct cvmx_pciercx_cfg456_s { 2680 2680 - #ifdef __BIG_ENDIAN_BITFIELD 2681 2681 - uint32_t reserved_4_31:28; 2682 2682 - uint32_t m_handle_flush:1; 2683 2683 - uint32_t m_dabort_4ucpl:1; 2684 2684 - uint32_t m_vend1_drp:1; 2685 2685 - uint32_t m_vend0_drp:1; 2686 2686 - #else 2687 2687 - uint32_t m_vend0_drp:1; 2688 2688 - uint32_t m_vend1_drp:1; 2689 2689 - uint32_t m_dabort_4ucpl:1; 2690 2690 - uint32_t m_handle_flush:1; 2691 2691 - uint32_t reserved_4_31:28; 2692 2692 - #endif 2693 2693 - } s; 2694 2694 - struct cvmx_pciercx_cfg456_cn52xx { 2695 2695 - #ifdef __BIG_ENDIAN_BITFIELD 2696 2696 - uint32_t reserved_2_31:30; 2697 2697 - uint32_t m_vend1_drp:1; 2698 2698 - uint32_t m_vend0_drp:1; 2699 2699 - #else 2700 2700 - uint32_t m_vend0_drp:1; 2701 2701 - uint32_t m_vend1_drp:1; 2702 2702 - uint32_t reserved_2_31:30; 2703 2703 - #endif 2704 2704 - } cn52xx; 2705 2705 - struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; 2706 2706 - struct cvmx_pciercx_cfg456_cn52xx cn56xx; 2707 2707 - struct cvmx_pciercx_cfg456_cn52xx cn56xxp1; 2708 2708 - struct cvmx_pciercx_cfg456_s cn61xx; 2709 2709 - struct cvmx_pciercx_cfg456_cn52xx cn63xx; 2710 2710 - struct cvmx_pciercx_cfg456_cn52xx cn63xxp1; 2711 2711 - struct cvmx_pciercx_cfg456_s cn66xx; 2712 2712 - struct cvmx_pciercx_cfg456_s cn68xx; 2713 2713 - struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; 2714 2714 - struct cvmx_pciercx_cfg456_s cnf71xx; 2715 2715 - }; 2716 2716 - 2717 2717 - union cvmx_pciercx_cfg458 { 2718 2718 - uint32_t u32; 2719 2719 - struct cvmx_pciercx_cfg458_s { 2720 2720 - #ifdef __BIG_ENDIAN_BITFIELD 2721 2721 - uint32_t dbg_info_l32:32; 2722 2722 - #else 2723 2723 - uint32_t dbg_info_l32:32; 2724 2724 - #endif 2725 2725 - } s; 2726 2726 - struct cvmx_pciercx_cfg458_s cn52xx; 2727 2727 - struct cvmx_pciercx_cfg458_s cn52xxp1; 2728 2728 - struct cvmx_pciercx_cfg458_s cn56xx; 2729 2729 - struct cvmx_pciercx_cfg458_s cn56xxp1; 2730 2730 - struct cvmx_pciercx_cfg458_s cn61xx; 2731 2731 - struct cvmx_pciercx_cfg458_s cn63xx; 2732 2732 - struct cvmx_pciercx_cfg458_s cn63xxp1; 2733 2733 - struct cvmx_pciercx_cfg458_s cn66xx; 2734 2734 - struct cvmx_pciercx_cfg458_s cn68xx; 2735 2735 - struct cvmx_pciercx_cfg458_s cn68xxp1; 2736 2736 - struct cvmx_pciercx_cfg458_s cnf71xx; 2737 2737 - }; 2738 2738 - 2739 2739 - union cvmx_pciercx_cfg459 { 2740 2740 - uint32_t u32; 2741 2741 - struct cvmx_pciercx_cfg459_s { 2742 2742 - #ifdef __BIG_ENDIAN_BITFIELD 2743 2743 - uint32_t dbg_info_u32:32; 2744 2744 - #else 2745 2745 - uint32_t dbg_info_u32:32; 2746 2746 - #endif 2747 2747 - } s; 2748 2748 - struct cvmx_pciercx_cfg459_s cn52xx; 2749 2749 - struct cvmx_pciercx_cfg459_s cn52xxp1; 2750 2750 - struct cvmx_pciercx_cfg459_s cn56xx; 2751 2751 - struct cvmx_pciercx_cfg459_s cn56xxp1; 2752 2752 - struct cvmx_pciercx_cfg459_s cn61xx; 2753 2753 - struct cvmx_pciercx_cfg459_s cn63xx; 2754 2754 - struct cvmx_pciercx_cfg459_s cn63xxp1; 2755 2755 - struct cvmx_pciercx_cfg459_s cn66xx; 2756 2756 - struct cvmx_pciercx_cfg459_s cn68xx; 2757 2757 - struct cvmx_pciercx_cfg459_s cn68xxp1; 2758 2758 - struct cvmx_pciercx_cfg459_s cnf71xx; 2759 2759 - }; 2760 2760 - 2761 2761 - union cvmx_pciercx_cfg460 { 2762 2762 - uint32_t u32; 2763 2763 - struct cvmx_pciercx_cfg460_s { 2764 2764 - #ifdef __BIG_ENDIAN_BITFIELD 2765 2765 - uint32_t reserved_20_31:12; 2766 2766 - uint32_t tphfcc:8; 2767 2767 - uint32_t tpdfcc:12; 2768 2768 - #else 2769 2769 - uint32_t tpdfcc:12; 2770 2770 - uint32_t tphfcc:8; 2771 2771 - uint32_t reserved_20_31:12; 2772 2772 - #endif 2773 2773 - } s; 2774 2774 - struct cvmx_pciercx_cfg460_s cn52xx; 2775 2775 - struct cvmx_pciercx_cfg460_s cn52xxp1; 2776 2776 - struct cvmx_pciercx_cfg460_s cn56xx; 2777 2777 - struct cvmx_pciercx_cfg460_s cn56xxp1; 2778 2778 - struct cvmx_pciercx_cfg460_s cn61xx; 2779 2779 - struct cvmx_pciercx_cfg460_s cn63xx; 2780 2780 - struct cvmx_pciercx_cfg460_s cn63xxp1; 2781 2781 - struct cvmx_pciercx_cfg460_s cn66xx; 2782 2782 - struct cvmx_pciercx_cfg460_s cn68xx; 2783 2783 - struct cvmx_pciercx_cfg460_s cn68xxp1; 2784 2784 - struct cvmx_pciercx_cfg460_s cnf71xx; 2785 2785 - }; 2786 2786 - 2787 2787 - union cvmx_pciercx_cfg461 { 2788 2788 - uint32_t u32; 2789 2789 - struct cvmx_pciercx_cfg461_s { 2790 2790 - #ifdef __BIG_ENDIAN_BITFIELD 2791 2791 - uint32_t reserved_20_31:12; 2792 2792 - uint32_t tchfcc:8; 2793 2793 - uint32_t tcdfcc:12; 2794 2794 - #else 2795 2795 - uint32_t tcdfcc:12; 2796 2796 - uint32_t tchfcc:8; 2797 2797 - uint32_t reserved_20_31:12; 2798 2798 - #endif 2799 2799 - } s; 2800 2800 - struct cvmx_pciercx_cfg461_s cn52xx; 2801 2801 - struct cvmx_pciercx_cfg461_s cn52xxp1; 2802 2802 - struct cvmx_pciercx_cfg461_s cn56xx; 2803 2803 - struct cvmx_pciercx_cfg461_s cn56xxp1; 2804 2804 - struct cvmx_pciercx_cfg461_s cn61xx; 2805 2805 - struct cvmx_pciercx_cfg461_s cn63xx; 2806 2806 - struct cvmx_pciercx_cfg461_s cn63xxp1; 2807 2807 - struct cvmx_pciercx_cfg461_s cn66xx; 2808 2808 - struct cvmx_pciercx_cfg461_s cn68xx; 2809 2809 - struct cvmx_pciercx_cfg461_s cn68xxp1; 2810 2810 - struct cvmx_pciercx_cfg461_s cnf71xx; 2811 2811 - }; 2812 2812 - 2813 2813 - union cvmx_pciercx_cfg462 { 2814 2814 - uint32_t u32; 2815 2815 - struct cvmx_pciercx_cfg462_s { 2816 2816 - #ifdef __BIG_ENDIAN_BITFIELD 2817 2817 - uint32_t reserved_20_31:12; 2818 2818 - uint32_t tchfcc:8; 2819 2819 - uint32_t tcdfcc:12; 2820 2820 - #else 2821 2821 - uint32_t tcdfcc:12; 2822 2822 - uint32_t tchfcc:8; 2823 2823 - uint32_t reserved_20_31:12; 2824 2824 - #endif 2825 2825 - } s; 2826 2826 - struct cvmx_pciercx_cfg462_s cn52xx; 2827 2827 - struct cvmx_pciercx_cfg462_s cn52xxp1; 2828 2828 - struct cvmx_pciercx_cfg462_s cn56xx; 2829 2829 - struct cvmx_pciercx_cfg462_s cn56xxp1; 2830 2830 - struct cvmx_pciercx_cfg462_s cn61xx; 2831 2831 - struct cvmx_pciercx_cfg462_s cn63xx; 2832 2832 - struct cvmx_pciercx_cfg462_s cn63xxp1; 2833 2833 - struct cvmx_pciercx_cfg462_s cn66xx; 2834 2834 - struct cvmx_pciercx_cfg462_s cn68xx; 2835 2835 - struct cvmx_pciercx_cfg462_s cn68xxp1; 2836 2836 - struct cvmx_pciercx_cfg462_s cnf71xx; 2837 2837 - }; 2838 2838 - 2839 2839 - union cvmx_pciercx_cfg463 { 2840 2840 - uint32_t u32; 2841 2841 - struct cvmx_pciercx_cfg463_s { 2842 2842 - #ifdef __BIG_ENDIAN_BITFIELD 2843 2843 - uint32_t reserved_3_31:29; 2844 2844 - uint32_t rqne:1; 2845 2845 - uint32_t trbne:1; 2846 2846 - uint32_t rtlpfccnr:1; 2847 2847 - #else 2848 2848 - uint32_t rtlpfccnr:1; 2849 2849 - uint32_t trbne:1; 2850 2850 - uint32_t rqne:1; 2851 2851 - uint32_t reserved_3_31:29; 2852 2852 - #endif 2853 2853 - } s; 2854 2854 - struct cvmx_pciercx_cfg463_s cn52xx; 2855 2855 - struct cvmx_pciercx_cfg463_s cn52xxp1; 2856 2856 - struct cvmx_pciercx_cfg463_s cn56xx; 2857 2857 - struct cvmx_pciercx_cfg463_s cn56xxp1; 2858 2858 - struct cvmx_pciercx_cfg463_s cn61xx; 2859 2859 - struct cvmx_pciercx_cfg463_s cn63xx; 2860 2860 - struct cvmx_pciercx_cfg463_s cn63xxp1; 2861 2861 - struct cvmx_pciercx_cfg463_s cn66xx; 2862 2862 - struct cvmx_pciercx_cfg463_s cn68xx; 2863 2863 - struct cvmx_pciercx_cfg463_s cn68xxp1; 2864 2864 - struct cvmx_pciercx_cfg463_s cnf71xx; 2865 2865 - }; 2866 2866 - 2867 2867 - union cvmx_pciercx_cfg464 { 2868 2868 - uint32_t u32; 2869 2869 - struct cvmx_pciercx_cfg464_s { 2870 2870 - #ifdef __BIG_ENDIAN_BITFIELD 2871 2871 - uint32_t wrr_vc3:8; 2872 2872 - uint32_t wrr_vc2:8; 2873 2873 - uint32_t wrr_vc1:8; 2874 2874 - uint32_t wrr_vc0:8; 2875 2875 - #else 2876 2876 - uint32_t wrr_vc0:8; 2877 2877 - uint32_t wrr_vc1:8; 2878 2878 - uint32_t wrr_vc2:8; 2879 2879 - uint32_t wrr_vc3:8; 2880 2880 - #endif 2881 2881 - } s; 2882 2882 - struct cvmx_pciercx_cfg464_s cn52xx; 2883 2883 - struct cvmx_pciercx_cfg464_s cn52xxp1; 2884 2884 - struct cvmx_pciercx_cfg464_s cn56xx; 2885 2885 - struct cvmx_pciercx_cfg464_s cn56xxp1; 2886 2886 - struct cvmx_pciercx_cfg464_s cn61xx; 2887 2887 - struct cvmx_pciercx_cfg464_s cn63xx; 2888 2888 - struct cvmx_pciercx_cfg464_s cn63xxp1; 2889 2889 - struct cvmx_pciercx_cfg464_s cn66xx; 2890 2890 - struct cvmx_pciercx_cfg464_s cn68xx; 2891 2891 - struct cvmx_pciercx_cfg464_s cn68xxp1; 2892 2892 - struct cvmx_pciercx_cfg464_s cnf71xx; 2893 2893 - }; 2894 2894 - 2895 2895 - union cvmx_pciercx_cfg465 { 2896 2896 - uint32_t u32; 2897 2897 - struct cvmx_pciercx_cfg465_s { 2898 2898 - #ifdef __BIG_ENDIAN_BITFIELD 2899 2899 - uint32_t wrr_vc7:8; 2900 2900 - uint32_t wrr_vc6:8; 2901 2901 - uint32_t wrr_vc5:8; 2902 2902 - uint32_t wrr_vc4:8; 2903 2903 - #else 2904 2904 - uint32_t wrr_vc4:8; 2905 2905 - uint32_t wrr_vc5:8; 2906 2906 - uint32_t wrr_vc6:8; 2907 2907 - uint32_t wrr_vc7:8; 2908 2908 - #endif 2909 2909 - } s; 2910 2910 - struct cvmx_pciercx_cfg465_s cn52xx; 2911 2911 - struct cvmx_pciercx_cfg465_s cn52xxp1; 2912 2912 - struct cvmx_pciercx_cfg465_s cn56xx; 2913 2913 - struct cvmx_pciercx_cfg465_s cn56xxp1; 2914 2914 - struct cvmx_pciercx_cfg465_s cn61xx; 2915 2915 - struct cvmx_pciercx_cfg465_s cn63xx; 2916 2916 - struct cvmx_pciercx_cfg465_s cn63xxp1; 2917 2917 - struct cvmx_pciercx_cfg465_s cn66xx; 2918 2918 - struct cvmx_pciercx_cfg465_s cn68xx; 2919 2919 - struct cvmx_pciercx_cfg465_s cn68xxp1; 2920 2920 - struct cvmx_pciercx_cfg465_s cnf71xx; 2921 2921 - }; 2922 2922 - 2923 2923 - union cvmx_pciercx_cfg466 { 2924 2924 - uint32_t u32; 2925 2925 - struct cvmx_pciercx_cfg466_s { 2926 2926 - #ifdef __BIG_ENDIAN_BITFIELD 2927 2927 - uint32_t rx_queue_order:1; 2928 2928 - uint32_t type_ordering:1; 2929 2929 - uint32_t reserved_24_29:6; 2930 2930 - uint32_t queue_mode:3; 2931 2931 - uint32_t reserved_20_20:1; 2932 2932 - uint32_t header_credits:8; 2933 2933 - uint32_t data_credits:12; 2934 2934 - #else 2935 2935 - uint32_t data_credits:12; 2936 2936 - uint32_t header_credits:8; 2937 2937 - uint32_t reserved_20_20:1; 2938 2938 - uint32_t queue_mode:3; 2939 2939 - uint32_t reserved_24_29:6; 2940 2940 - uint32_t type_ordering:1; 2941 2941 - uint32_t rx_queue_order:1; 2942 2942 - #endif 2943 2943 - } s; 2944 2944 - struct cvmx_pciercx_cfg466_s cn52xx; 2945 2945 - struct cvmx_pciercx_cfg466_s cn52xxp1; 2946 2946 - struct cvmx_pciercx_cfg466_s cn56xx; 2947 2947 - struct cvmx_pciercx_cfg466_s cn56xxp1; 2948 2948 - struct cvmx_pciercx_cfg466_s cn61xx; 2949 2949 - struct cvmx_pciercx_cfg466_s cn63xx; 2950 2950 - struct cvmx_pciercx_cfg466_s cn63xxp1; 2951 2951 - struct cvmx_pciercx_cfg466_s cn66xx; 2952 2952 - struct cvmx_pciercx_cfg466_s cn68xx; 2953 2953 - struct cvmx_pciercx_cfg466_s cn68xxp1; 2954 2954 - struct cvmx_pciercx_cfg466_s cnf71xx; 2955 2955 - }; 2956 2956 - 2957 2957 - union cvmx_pciercx_cfg467 { 2958 2958 - uint32_t u32; 2959 2959 - struct cvmx_pciercx_cfg467_s { 2960 2960 - #ifdef __BIG_ENDIAN_BITFIELD 2961 2961 - uint32_t reserved_24_31:8; 2962 2962 - uint32_t queue_mode:3; 2963 2963 - uint32_t reserved_20_20:1; 2964 2964 - uint32_t header_credits:8; 2965 2965 - uint32_t data_credits:12; 2966 2966 - #else 2967 2967 - uint32_t data_credits:12; 2968 2968 - uint32_t header_credits:8; 2969 2969 - uint32_t reserved_20_20:1; 2970 2970 - uint32_t queue_mode:3; 2971 2971 - uint32_t reserved_24_31:8; 2972 2972 - #endif 2973 2973 - } s; 2974 2974 - struct cvmx_pciercx_cfg467_s cn52xx; 2975 2975 - struct cvmx_pciercx_cfg467_s cn52xxp1; 2976 2976 - struct cvmx_pciercx_cfg467_s cn56xx; 2977 2977 - struct cvmx_pciercx_cfg467_s cn56xxp1; 2978 2978 - struct cvmx_pciercx_cfg467_s cn61xx; 2979 2979 - struct cvmx_pciercx_cfg467_s cn63xx; 2980 2980 - struct cvmx_pciercx_cfg467_s cn63xxp1; 2981 2981 - struct cvmx_pciercx_cfg467_s cn66xx; 2982 2982 - struct cvmx_pciercx_cfg467_s cn68xx; 2983 2983 - struct cvmx_pciercx_cfg467_s cn68xxp1; 2984 2984 - struct cvmx_pciercx_cfg467_s cnf71xx; 2985 2985 - }; 2986 2986 - 2987 2987 - union cvmx_pciercx_cfg468 { 2988 2988 - uint32_t u32; 2989 2989 - struct cvmx_pciercx_cfg468_s { 2990 2990 - #ifdef __BIG_ENDIAN_BITFIELD 2991 2991 - uint32_t reserved_24_31:8; 2992 2992 - uint32_t queue_mode:3; 2993 2993 - uint32_t reserved_20_20:1; 2994 2994 - uint32_t header_credits:8; 2995 2995 - uint32_t data_credits:12; 2996 2996 - #else 2997 2997 - uint32_t data_credits:12; 2998 2998 - uint32_t header_credits:8; 2999 2999 - uint32_t reserved_20_20:1; 3000 3000 - uint32_t queue_mode:3; 3001 3001 - uint32_t reserved_24_31:8; 3002 3002 - #endif 3003 3003 - } s; 3004 3004 - struct cvmx_pciercx_cfg468_s cn52xx; 3005 3005 - struct cvmx_pciercx_cfg468_s cn52xxp1; 3006 3006 - struct cvmx_pciercx_cfg468_s cn56xx; 3007 3007 - struct cvmx_pciercx_cfg468_s cn56xxp1; 3008 3008 - struct cvmx_pciercx_cfg468_s cn61xx; 3009 3009 - struct cvmx_pciercx_cfg468_s cn63xx; 3010 3010 - struct cvmx_pciercx_cfg468_s cn63xxp1; 3011 3011 - struct cvmx_pciercx_cfg468_s cn66xx; 3012 3012 - struct cvmx_pciercx_cfg468_s cn68xx; 3013 3013 - struct cvmx_pciercx_cfg468_s cn68xxp1; 3014 3014 - struct cvmx_pciercx_cfg468_s cnf71xx; 3015 3015 - }; 3016 3016 - 3017 3017 - union cvmx_pciercx_cfg490 { 3018 3018 - uint32_t u32; 3019 3019 - struct cvmx_pciercx_cfg490_s { 3020 3020 - #ifdef __BIG_ENDIAN_BITFIELD 3021 3021 - uint32_t reserved_26_31:6; 3022 3022 - uint32_t header_depth:10; 3023 3023 - uint32_t reserved_14_15:2; 3024 3024 - uint32_t data_depth:14; 3025 3025 - #else 3026 3026 - uint32_t data_depth:14; 3027 3027 - uint32_t reserved_14_15:2; 3028 3028 - uint32_t header_depth:10; 3029 3029 - uint32_t reserved_26_31:6; 3030 3030 - #endif 3031 3031 - } s; 3032 3032 - struct cvmx_pciercx_cfg490_s cn52xx; 3033 3033 - struct cvmx_pciercx_cfg490_s cn52xxp1; 3034 3034 - struct cvmx_pciercx_cfg490_s cn56xx; 3035 3035 - struct cvmx_pciercx_cfg490_s cn56xxp1; 3036 3036 - struct cvmx_pciercx_cfg490_s cn61xx; 3037 3037 - struct cvmx_pciercx_cfg490_s cn63xx; 3038 3038 - struct cvmx_pciercx_cfg490_s cn63xxp1; 3039 3039 - struct cvmx_pciercx_cfg490_s cn66xx; 3040 3040 - struct cvmx_pciercx_cfg490_s cn68xx; 3041 3041 - struct cvmx_pciercx_cfg490_s cn68xxp1; 3042 3042 - struct cvmx_pciercx_cfg490_s cnf71xx; 3043 3043 - }; 3044 3044 - 3045 3045 - union cvmx_pciercx_cfg491 { 3046 3046 - uint32_t u32; 3047 3047 - struct cvmx_pciercx_cfg491_s { 3048 3048 - #ifdef __BIG_ENDIAN_BITFIELD 3049 3049 - uint32_t reserved_26_31:6; 3050 3050 - uint32_t header_depth:10; 3051 3051 - uint32_t reserved_14_15:2; 3052 3052 - uint32_t data_depth:14; 3053 3053 - #else 3054 3054 - uint32_t data_depth:14; 3055 3055 - uint32_t reserved_14_15:2; 3056 3056 - uint32_t header_depth:10; 3057 3057 - uint32_t reserved_26_31:6; 3058 3058 - #endif 3059 3059 - } s; 3060 3060 - struct cvmx_pciercx_cfg491_s cn52xx; 3061 3061 - struct cvmx_pciercx_cfg491_s cn52xxp1; 3062 3062 - struct cvmx_pciercx_cfg491_s cn56xx; 3063 3063 - struct cvmx_pciercx_cfg491_s cn56xxp1; 3064 3064 - struct cvmx_pciercx_cfg491_s cn61xx; 3065 3065 - struct cvmx_pciercx_cfg491_s cn63xx; 3066 3066 - struct cvmx_pciercx_cfg491_s cn63xxp1; 3067 3067 - struct cvmx_pciercx_cfg491_s cn66xx; 3068 3068 - struct cvmx_pciercx_cfg491_s cn68xx; 3069 3069 - struct cvmx_pciercx_cfg491_s cn68xxp1; 3070 3070 - struct cvmx_pciercx_cfg491_s cnf71xx; 3071 3071 - }; 3072 3072 - 3073 3073 - union cvmx_pciercx_cfg492 { 3074 3074 - uint32_t u32; 3075 3075 - struct cvmx_pciercx_cfg492_s { 3076 3076 - #ifdef __BIG_ENDIAN_BITFIELD 3077 3077 - uint32_t reserved_26_31:6; 3078 3078 - uint32_t header_depth:10; 3079 3079 - uint32_t reserved_14_15:2; 3080 3080 - uint32_t data_depth:14; 3081 3081 - #else 3082 3082 - uint32_t data_depth:14; 3083 3083 - uint32_t reserved_14_15:2; 3084 3084 - uint32_t header_depth:10; 3085 3085 - uint32_t reserved_26_31:6; 3086 3086 - #endif 3087 3087 - } s; 3088 3088 - struct cvmx_pciercx_cfg492_s cn52xx; 3089 3089 - struct cvmx_pciercx_cfg492_s cn52xxp1; 3090 3090 - struct cvmx_pciercx_cfg492_s cn56xx; 3091 3091 - struct cvmx_pciercx_cfg492_s cn56xxp1; 3092 3092 - struct cvmx_pciercx_cfg492_s cn61xx; 3093 3093 - struct cvmx_pciercx_cfg492_s cn63xx; 3094 3094 - struct cvmx_pciercx_cfg492_s cn63xxp1; 3095 3095 - struct cvmx_pciercx_cfg492_s cn66xx; 3096 3096 - struct cvmx_pciercx_cfg492_s cn68xx; 3097 3097 - struct cvmx_pciercx_cfg492_s cn68xxp1; 3098 3098 - struct cvmx_pciercx_cfg492_s cnf71xx; 3099 352 }; 3100 353 3101 354 union cvmx_pciercx_cfg515 { 3102 355 uint32_t u32; 3103 356 struct cvmx_pciercx_cfg515_s { 3104 3104 - #ifdef __BIG_ENDIAN_BITFIELD 3105 3105 - uint32_t reserved_21_31:11; 3106 3106 - uint32_t s_d_e:1; 3107 3107 - uint32_t ctcrb:1; 3108 3108 - uint32_t cpyts:1; 3109 3109 - uint32_t dsc:1; 3110 3110 - uint32_t le:9; 3111 3111 - uint32_t n_fts:8; 3112 3112 - #else 3113 3113 - uint32_t n_fts:8; 3114 3114 - uint32_t le:9; 3115 3115 - uint32_t dsc:1; 3116 3116 - uint32_t cpyts:1; 3117 3117 - uint32_t ctcrb:1; 3118 3118 - uint32_t s_d_e:1; 3119 3119 - uint32_t reserved_21_31:11; 3120 3120 - #endif 357 357 + __BITFIELD_FIELD(uint32_t reserved_21_31:11, 358 358 + __BITFIELD_FIELD(uint32_t s_d_e:1, 359 359 + __BITFIELD_FIELD(uint32_t ctcrb:1, 360 360 + __BITFIELD_FIELD(uint32_t cpyts:1, 361 361 + __BITFIELD_FIELD(uint32_t dsc:1, 362 362 + __BITFIELD_FIELD(uint32_t le:9, 363 363 + __BITFIELD_FIELD(uint32_t n_fts:8, 364 364 + ;))))))) 3121 365 } s; 3122 3122 - struct cvmx_pciercx_cfg515_s cn61xx; 3123 3123 - struct cvmx_pciercx_cfg515_s cn63xx; 3124 3124 - struct cvmx_pciercx_cfg515_s cn63xxp1; 3125 3125 - struct cvmx_pciercx_cfg515_s cn66xx; 3126 3126 - struct cvmx_pciercx_cfg515_s cn68xx; 3127 3127 - struct cvmx_pciercx_cfg515_s cn68xxp1; 3128 3128 - struct cvmx_pciercx_cfg515_s cnf71xx; 3129 3129 - }; 3130 3130 - 3131 3131 - union cvmx_pciercx_cfg516 { 3132 3132 - uint32_t u32; 3133 3133 - struct cvmx_pciercx_cfg516_s { 3134 3134 - #ifdef __BIG_ENDIAN_BITFIELD 3135 3135 - uint32_t phy_stat:32; 3136 3136 - #else 3137 3137 - uint32_t phy_stat:32; 3138 3138 - #endif 3139 3139 - } s; 3140 3140 - struct cvmx_pciercx_cfg516_s cn52xx; 3141 3141 - struct cvmx_pciercx_cfg516_s cn52xxp1; 3142 3142 - struct cvmx_pciercx_cfg516_s cn56xx; 3143 3143 - struct cvmx_pciercx_cfg516_s cn56xxp1; 3144 3144 - struct cvmx_pciercx_cfg516_s cn61xx; 3145 3145 - struct cvmx_pciercx_cfg516_s cn63xx; 3146 3146 - struct cvmx_pciercx_cfg516_s cn63xxp1; 3147 3147 - struct cvmx_pciercx_cfg516_s cn66xx; 3148 3148 - struct cvmx_pciercx_cfg516_s cn68xx; 3149 3149 - struct cvmx_pciercx_cfg516_s cn68xxp1; 3150 3150 - struct cvmx_pciercx_cfg516_s cnf71xx; 3151 3151 - }; 3152 3152 - 3153 3153 - union cvmx_pciercx_cfg517 { 3154 3154 - uint32_t u32; 3155 3155 - struct cvmx_pciercx_cfg517_s { 3156 3156 - #ifdef __BIG_ENDIAN_BITFIELD 3157 3157 - uint32_t phy_ctrl:32; 3158 3158 - #else 3159 3159 - uint32_t phy_ctrl:32; 3160 3160 - #endif 3161 3161 - } s; 3162 3162 - struct cvmx_pciercx_cfg517_s cn52xx; 3163 3163 - struct cvmx_pciercx_cfg517_s cn52xxp1; 3164 3164 - struct cvmx_pciercx_cfg517_s cn56xx; 3165 3165 - struct cvmx_pciercx_cfg517_s cn56xxp1; 3166 3166 - struct cvmx_pciercx_cfg517_s cn61xx; 3167 3167 - struct cvmx_pciercx_cfg517_s cn63xx; 3168 3168 - struct cvmx_pciercx_cfg517_s cn63xxp1; 3169 3169 - struct cvmx_pciercx_cfg517_s cn66xx; 3170 3170 - struct cvmx_pciercx_cfg517_s cn68xx; 3171 3171 - struct cvmx_pciercx_cfg517_s cn68xxp1; 3172 3172 - struct cvmx_pciercx_cfg517_s cnf71xx; 3173 366 }; 3174 367 3175 368 #endif

+74 -3467

arch/mips/include/asm/octeon/cvmx-sli-defs.h

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2012 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 28 28 #ifndef __CVMX_SLI_DEFS_H__ 29 29 #define __CVMX_SLI_DEFS_H__ 30 30 31 31 - #define CVMX_SLI_BIST_STATUS (0x0000000000000580ull) 32 32 - #define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16) 33 33 - #define CVMX_SLI_CTL_STATUS (0x0000000000000570ull) 34 34 - #define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull) 35 35 - #define CVMX_SLI_DBG_DATA (0x0000000000000310ull) 36 36 - #define CVMX_SLI_DBG_SELECT (0x0000000000000300ull) 37 37 - #define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16) 38 38 - #define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16) 39 39 - #define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16) 40 40 - #define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull) 41 41 - #define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16) 42 42 - #define CVMX_SLI_INT_SUM (0x0000000000000330ull) 43 43 - #define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull) 44 44 - #define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull) 45 45 - #define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull) 46 46 - #define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull) 47 47 - #define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull) 48 48 - #define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull) 49 49 - #define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull) 50 50 - #define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull) 51 51 - #define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12) 52 52 - #define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull) 53 53 - #define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull) 54 54 - #define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull) 55 55 - #define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull) 56 56 - #define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull) 57 57 - #define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull) 58 58 - #define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull) 59 59 - #define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull) 60 60 - #define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull) 61 61 - #define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 62 62 - #define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull) 63 63 - #define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull) 64 64 - #define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull) 65 65 - #define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull) 66 66 - #define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull) 67 67 - #define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull) 68 68 - #define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull) 69 69 - #define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull) 70 70 - #define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull) 71 71 - #define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 72 72 - #define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 73 73 - #define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 74 74 - #define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 75 75 - #define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 76 76 - #define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 77 77 - #define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 78 78 - #define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 79 79 - #define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 80 80 - #define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16) 81 81 - #define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 82 82 - #define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 83 83 - #define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 84 84 - #define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull) 85 85 - #define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull) 86 86 - #define CVMX_SLI_PKT_CTL (0x0000000000001220ull) 87 87 - #define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 88 88 - #define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 89 89 - #define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 90 90 - #define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull) 91 91 - #define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull) 92 92 - #define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull) 93 93 - #define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull) 94 94 - #define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull) 95 95 - #define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull) 96 96 - #define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull) 97 97 - #define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 98 98 - #define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull) 99 99 - #define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull) 100 100 - #define CVMX_SLI_PKT_IPTR (0x0000000000001070ull) 101 101 - #define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull) 102 102 - #define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull) 103 103 - #define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull) 104 104 - #define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull) 105 105 - #define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull) 106 106 - #define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull) 107 107 - #define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull) 108 108 - #define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull) 109 109 - #define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull) 110 110 - #define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull) 111 111 - #define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull) 112 112 - #define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16) 113 113 - #define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16) 114 114 - #define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull) 115 115 - #define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull) 116 116 - #define CVMX_SLI_STATE1 (0x0000000000000620ull) 117 117 - #define CVMX_SLI_STATE2 (0x0000000000000630ull) 118 118 - #define CVMX_SLI_STATE3 (0x0000000000000640ull) 119 119 - #define CVMX_SLI_TX_PIPE (0x0000000000001230ull) 120 120 - #define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull) 121 121 - #define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull) 122 122 - #define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull) 123 123 - #define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull) 124 124 - #define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull) 125 125 - #define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull) 31 31 + #include <uapi/asm/bitfield.h> 126 32 127 127 - union cvmx_sli_bist_status { 128 128 - uint64_t u64; 129 129 - struct cvmx_sli_bist_status_s { 130 130 - #ifdef __BIG_ENDIAN_BITFIELD 131 131 - uint64_t reserved_32_63:32; 132 132 - uint64_t ncb_req:1; 133 133 - uint64_t n2p0_c:1; 134 134 - uint64_t n2p0_o:1; 135 135 - uint64_t n2p1_c:1; 136 136 - uint64_t n2p1_o:1; 137 137 - uint64_t cpl_p0:1; 138 138 - uint64_t cpl_p1:1; 139 139 - uint64_t reserved_19_24:6; 140 140 - uint64_t p2n0_c0:1; 141 141 - uint64_t p2n0_c1:1; 142 142 - uint64_t p2n0_n:1; 143 143 - uint64_t p2n0_p0:1; 144 144 - uint64_t p2n0_p1:1; 145 145 - uint64_t p2n1_c0:1; 146 146 - uint64_t p2n1_c1:1; 147 147 - uint64_t p2n1_n:1; 148 148 - uint64_t p2n1_p0:1; 149 149 - uint64_t p2n1_p1:1; 150 150 - uint64_t reserved_6_8:3; 151 151 - uint64_t dsi1_1:1; 152 152 - uint64_t dsi1_0:1; 153 153 - uint64_t dsi0_1:1; 154 154 - uint64_t dsi0_0:1; 155 155 - uint64_t msi:1; 156 156 - uint64_t ncb_cmd:1; 157 157 - #else 158 158 - uint64_t ncb_cmd:1; 159 159 - uint64_t msi:1; 160 160 - uint64_t dsi0_0:1; 161 161 - uint64_t dsi0_1:1; 162 162 - uint64_t dsi1_0:1; 163 163 - uint64_t dsi1_1:1; 164 164 - uint64_t reserved_6_8:3; 165 165 - uint64_t p2n1_p1:1; 166 166 - uint64_t p2n1_p0:1; 167 167 - uint64_t p2n1_n:1; 168 168 - uint64_t p2n1_c1:1; 169 169 - uint64_t p2n1_c0:1; 170 170 - uint64_t p2n0_p1:1; 171 171 - uint64_t p2n0_p0:1; 172 172 - uint64_t p2n0_n:1; 173 173 - uint64_t p2n0_c1:1; 174 174 - uint64_t p2n0_c0:1; 175 175 - uint64_t reserved_19_24:6; 176 176 - uint64_t cpl_p1:1; 177 177 - uint64_t cpl_p0:1; 178 178 - uint64_t n2p1_o:1; 179 179 - uint64_t n2p1_c:1; 180 180 - uint64_t n2p0_o:1; 181 181 - uint64_t n2p0_c:1; 182 182 - uint64_t ncb_req:1; 183 183 - uint64_t reserved_32_63:32; 184 184 - #endif 185 185 - } s; 186 186 - struct cvmx_sli_bist_status_cn61xx { 187 187 - #ifdef __BIG_ENDIAN_BITFIELD 188 188 - uint64_t reserved_31_63:33; 189 189 - uint64_t n2p0_c:1; 190 190 - uint64_t n2p0_o:1; 191 191 - uint64_t reserved_27_28:2; 192 192 - uint64_t cpl_p0:1; 193 193 - uint64_t cpl_p1:1; 194 194 - uint64_t reserved_19_24:6; 195 195 - uint64_t p2n0_c0:1; 196 196 - uint64_t p2n0_c1:1; 197 197 - uint64_t p2n0_n:1; 198 198 - uint64_t p2n0_p0:1; 199 199 - uint64_t p2n0_p1:1; 200 200 - uint64_t p2n1_c0:1; 201 201 - uint64_t p2n1_c1:1; 202 202 - uint64_t p2n1_n:1; 203 203 - uint64_t p2n1_p0:1; 204 204 - uint64_t p2n1_p1:1; 205 205 - uint64_t reserved_6_8:3; 206 206 - uint64_t dsi1_1:1; 207 207 - uint64_t dsi1_0:1; 208 208 - uint64_t dsi0_1:1; 209 209 - uint64_t dsi0_0:1; 210 210 - uint64_t msi:1; 211 211 - uint64_t ncb_cmd:1; 212 212 - #else 213 213 - uint64_t ncb_cmd:1; 214 214 - uint64_t msi:1; 215 215 - uint64_t dsi0_0:1; 216 216 - uint64_t dsi0_1:1; 217 217 - uint64_t dsi1_0:1; 218 218 - uint64_t dsi1_1:1; 219 219 - uint64_t reserved_6_8:3; 220 220 - uint64_t p2n1_p1:1; 221 221 - uint64_t p2n1_p0:1; 222 222 - uint64_t p2n1_n:1; 223 223 - uint64_t p2n1_c1:1; 224 224 - uint64_t p2n1_c0:1; 225 225 - uint64_t p2n0_p1:1; 226 226 - uint64_t p2n0_p0:1; 227 227 - uint64_t p2n0_n:1; 228 228 - uint64_t p2n0_c1:1; 229 229 - uint64_t p2n0_c0:1; 230 230 - uint64_t reserved_19_24:6; 231 231 - uint64_t cpl_p1:1; 232 232 - uint64_t cpl_p0:1; 233 233 - uint64_t reserved_27_28:2; 234 234 - uint64_t n2p0_o:1; 235 235 - uint64_t n2p0_c:1; 236 236 - uint64_t reserved_31_63:33; 237 237 - #endif 238 238 - } cn61xx; 239 239 - struct cvmx_sli_bist_status_cn63xx { 240 240 - #ifdef __BIG_ENDIAN_BITFIELD 241 241 - uint64_t reserved_31_63:33; 242 242 - uint64_t n2p0_c:1; 243 243 - uint64_t n2p0_o:1; 244 244 - uint64_t n2p1_c:1; 245 245 - uint64_t n2p1_o:1; 246 246 - uint64_t cpl_p0:1; 247 247 - uint64_t cpl_p1:1; 248 248 - uint64_t reserved_19_24:6; 249 249 - uint64_t p2n0_c0:1; 250 250 - uint64_t p2n0_c1:1; 251 251 - uint64_t p2n0_n:1; 252 252 - uint64_t p2n0_p0:1; 253 253 - uint64_t p2n0_p1:1; 254 254 - uint64_t p2n1_c0:1; 255 255 - uint64_t p2n1_c1:1; 256 256 - uint64_t p2n1_n:1; 257 257 - uint64_t p2n1_p0:1; 258 258 - uint64_t p2n1_p1:1; 259 259 - uint64_t reserved_6_8:3; 260 260 - uint64_t dsi1_1:1; 261 261 - uint64_t dsi1_0:1; 262 262 - uint64_t dsi0_1:1; 263 263 - uint64_t dsi0_0:1; 264 264 - uint64_t msi:1; 265 265 - uint64_t ncb_cmd:1; 266 266 - #else 267 267 - uint64_t ncb_cmd:1; 268 268 - uint64_t msi:1; 269 269 - uint64_t dsi0_0:1; 270 270 - uint64_t dsi0_1:1; 271 271 - uint64_t dsi1_0:1; 272 272 - uint64_t dsi1_1:1; 273 273 - uint64_t reserved_6_8:3; 274 274 - uint64_t p2n1_p1:1; 275 275 - uint64_t p2n1_p0:1; 276 276 - uint64_t p2n1_n:1; 277 277 - uint64_t p2n1_c1:1; 278 278 - uint64_t p2n1_c0:1; 279 279 - uint64_t p2n0_p1:1; 280 280 - uint64_t p2n0_p0:1; 281 281 - uint64_t p2n0_n:1; 282 282 - uint64_t p2n0_c1:1; 283 283 - uint64_t p2n0_c0:1; 284 284 - uint64_t reserved_19_24:6; 285 285 - uint64_t cpl_p1:1; 286 286 - uint64_t cpl_p0:1; 287 287 - uint64_t n2p1_o:1; 288 288 - uint64_t n2p1_c:1; 289 289 - uint64_t n2p0_o:1; 290 290 - uint64_t n2p0_c:1; 291 291 - uint64_t reserved_31_63:33; 292 292 - #endif 293 293 - } cn63xx; 294 294 - struct cvmx_sli_bist_status_cn63xx cn63xxp1; 295 295 - struct cvmx_sli_bist_status_cn61xx cn66xx; 296 296 - struct cvmx_sli_bist_status_s cn68xx; 297 297 - struct cvmx_sli_bist_status_s cn68xxp1; 298 298 - struct cvmx_sli_bist_status_cn61xx cnf71xx; 299 299 - }; 33 33 + #define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC() 34 34 + static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void) 35 35 + { 36 36 + switch (cvmx_get_octeon_family()) { 37 37 + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 38 38 + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 39 39 + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 40 40 + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 41 41 + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 42 42 + case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 43 43 + return 0x0000000000003CB0ull; 44 44 + case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 45 45 + case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 46 46 + case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 47 47 + if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 48 48 + return 0x0000000000003CB0ull; 49 49 + default: 50 50 + return 0x0000000000023CB0ull; 51 51 + } 52 52 + } 53 53 + 300 54 301 55 union cvmx_sli_ctl_portx { 302 56 uint64_t u64; 303 57 struct cvmx_sli_ctl_portx_s { 304 304 - #ifdef __BIG_ENDIAN_BITFIELD 305 305 - uint64_t reserved_22_63:42; 306 306 - uint64_t intd:1; 307 307 - uint64_t intc:1; 308 308 - uint64_t intb:1; 309 309 - uint64_t inta:1; 310 310 - uint64_t dis_port:1; 311 311 - uint64_t waitl_com:1; 312 312 - uint64_t intd_map:2; 313 313 - uint64_t intc_map:2; 314 314 - uint64_t intb_map:2; 315 315 - uint64_t inta_map:2; 316 316 - uint64_t ctlp_ro:1; 317 317 - uint64_t reserved_6_6:1; 318 318 - uint64_t ptlp_ro:1; 319 319 - uint64_t reserved_1_4:4; 320 320 - uint64_t wait_com:1; 321 321 - #else 322 322 - uint64_t wait_com:1; 323 323 - uint64_t reserved_1_4:4; 324 324 - uint64_t ptlp_ro:1; 325 325 - uint64_t reserved_6_6:1; 326 326 - uint64_t ctlp_ro:1; 327 327 - uint64_t inta_map:2; 328 328 - uint64_t intb_map:2; 329 329 - uint64_t intc_map:2; 330 330 - uint64_t intd_map:2; 331 331 - uint64_t waitl_com:1; 332 332 - uint64_t dis_port:1; 333 333 - uint64_t inta:1; 334 334 - uint64_t intb:1; 335 335 - uint64_t intc:1; 336 336 - uint64_t intd:1; 337 337 - uint64_t reserved_22_63:42; 338 338 - #endif 58 58 + __BITFIELD_FIELD(uint64_t reserved_22_63:42, 59 59 + __BITFIELD_FIELD(uint64_t intd:1, 60 60 + __BITFIELD_FIELD(uint64_t intc:1, 61 61 + __BITFIELD_FIELD(uint64_t intb:1, 62 62 + __BITFIELD_FIELD(uint64_t inta:1, 63 63 + __BITFIELD_FIELD(uint64_t dis_port:1, 64 64 + __BITFIELD_FIELD(uint64_t waitl_com:1, 65 65 + __BITFIELD_FIELD(uint64_t intd_map:2, 66 66 + __BITFIELD_FIELD(uint64_t intc_map:2, 67 67 + __BITFIELD_FIELD(uint64_t intb_map:2, 68 68 + __BITFIELD_FIELD(uint64_t inta_map:2, 69 69 + __BITFIELD_FIELD(uint64_t ctlp_ro:1, 70 70 + __BITFIELD_FIELD(uint64_t reserved_6_6:1, 71 71 + __BITFIELD_FIELD(uint64_t ptlp_ro:1, 72 72 + __BITFIELD_FIELD(uint64_t reserved_1_4:4, 73 73 + __BITFIELD_FIELD(uint64_t wait_com:1, 74 74 + ;)))))))))))))))) 339 75 } s; 340 340 - struct cvmx_sli_ctl_portx_s cn61xx; 341 341 - struct cvmx_sli_ctl_portx_s cn63xx; 342 342 - struct cvmx_sli_ctl_portx_s cn63xxp1; 343 343 - struct cvmx_sli_ctl_portx_s cn66xx; 344 344 - struct cvmx_sli_ctl_portx_s cn68xx; 345 345 - struct cvmx_sli_ctl_portx_s cn68xxp1; 346 346 - struct cvmx_sli_ctl_portx_s cnf71xx; 347 347 - }; 348 348 - 349 349 - union cvmx_sli_ctl_status { 350 350 - uint64_t u64; 351 351 - struct cvmx_sli_ctl_status_s { 352 352 - #ifdef __BIG_ENDIAN_BITFIELD 353 353 - uint64_t reserved_20_63:44; 354 354 - uint64_t p1_ntags:6; 355 355 - uint64_t p0_ntags:6; 356 356 - uint64_t chip_rev:8; 357 357 - #else 358 358 - uint64_t chip_rev:8; 359 359 - uint64_t p0_ntags:6; 360 360 - uint64_t p1_ntags:6; 361 361 - uint64_t reserved_20_63:44; 362 362 - #endif 363 363 - } s; 364 364 - struct cvmx_sli_ctl_status_cn61xx { 365 365 - #ifdef __BIG_ENDIAN_BITFIELD 366 366 - uint64_t reserved_14_63:50; 367 367 - uint64_t p0_ntags:6; 368 368 - uint64_t chip_rev:8; 369 369 - #else 370 370 - uint64_t chip_rev:8; 371 371 - uint64_t p0_ntags:6; 372 372 - uint64_t reserved_14_63:50; 373 373 - #endif 374 374 - } cn61xx; 375 375 - struct cvmx_sli_ctl_status_s cn63xx; 376 376 - struct cvmx_sli_ctl_status_s cn63xxp1; 377 377 - struct cvmx_sli_ctl_status_cn61xx cn66xx; 378 378 - struct cvmx_sli_ctl_status_s cn68xx; 379 379 - struct cvmx_sli_ctl_status_s cn68xxp1; 380 380 - struct cvmx_sli_ctl_status_cn61xx cnf71xx; 381 381 - }; 382 382 - 383 383 - union cvmx_sli_data_out_cnt { 384 384 - uint64_t u64; 385 385 - struct cvmx_sli_data_out_cnt_s { 386 386 - #ifdef __BIG_ENDIAN_BITFIELD 387 387 - uint64_t reserved_44_63:20; 388 388 - uint64_t p1_ucnt:16; 389 389 - uint64_t p1_fcnt:6; 390 390 - uint64_t p0_ucnt:16; 391 391 - uint64_t p0_fcnt:6; 392 392 - #else 393 393 - uint64_t p0_fcnt:6; 394 394 - uint64_t p0_ucnt:16; 395 395 - uint64_t p1_fcnt:6; 396 396 - uint64_t p1_ucnt:16; 397 397 - uint64_t reserved_44_63:20; 398 398 - #endif 399 399 - } s; 400 400 - struct cvmx_sli_data_out_cnt_s cn61xx; 401 401 - struct cvmx_sli_data_out_cnt_s cn63xx; 402 402 - struct cvmx_sli_data_out_cnt_s cn63xxp1; 403 403 - struct cvmx_sli_data_out_cnt_s cn66xx; 404 404 - struct cvmx_sli_data_out_cnt_s cn68xx; 405 405 - struct cvmx_sli_data_out_cnt_s cn68xxp1; 406 406 - struct cvmx_sli_data_out_cnt_s cnf71xx; 407 407 - }; 408 408 - 409 409 - union cvmx_sli_dbg_data { 410 410 - uint64_t u64; 411 411 - struct cvmx_sli_dbg_data_s { 412 412 - #ifdef __BIG_ENDIAN_BITFIELD 413 413 - uint64_t reserved_18_63:46; 414 414 - uint64_t dsel_ext:1; 415 415 - uint64_t data:17; 416 416 - #else 417 417 - uint64_t data:17; 418 418 - uint64_t dsel_ext:1; 419 419 - uint64_t reserved_18_63:46; 420 420 - #endif 421 421 - } s; 422 422 - struct cvmx_sli_dbg_data_s cn61xx; 423 423 - struct cvmx_sli_dbg_data_s cn63xx; 424 424 - struct cvmx_sli_dbg_data_s cn63xxp1; 425 425 - struct cvmx_sli_dbg_data_s cn66xx; 426 426 - struct cvmx_sli_dbg_data_s cn68xx; 427 427 - struct cvmx_sli_dbg_data_s cn68xxp1; 428 428 - struct cvmx_sli_dbg_data_s cnf71xx; 429 429 - }; 430 430 - 431 431 - union cvmx_sli_dbg_select { 432 432 - uint64_t u64; 433 433 - struct cvmx_sli_dbg_select_s { 434 434 - #ifdef __BIG_ENDIAN_BITFIELD 435 435 - uint64_t reserved_33_63:31; 436 436 - uint64_t adbg_sel:1; 437 437 - uint64_t dbg_sel:32; 438 438 - #else 439 439 - uint64_t dbg_sel:32; 440 440 - uint64_t adbg_sel:1; 441 441 - uint64_t reserved_33_63:31; 442 442 - #endif 443 443 - } s; 444 444 - struct cvmx_sli_dbg_select_s cn61xx; 445 445 - struct cvmx_sli_dbg_select_s cn63xx; 446 446 - struct cvmx_sli_dbg_select_s cn63xxp1; 447 447 - struct cvmx_sli_dbg_select_s cn66xx; 448 448 - struct cvmx_sli_dbg_select_s cn68xx; 449 449 - struct cvmx_sli_dbg_select_s cn68xxp1; 450 450 - struct cvmx_sli_dbg_select_s cnf71xx; 451 451 - }; 452 452 - 453 453 - union cvmx_sli_dmax_cnt { 454 454 - uint64_t u64; 455 455 - struct cvmx_sli_dmax_cnt_s { 456 456 - #ifdef __BIG_ENDIAN_BITFIELD 457 457 - uint64_t reserved_32_63:32; 458 458 - uint64_t cnt:32; 459 459 - #else 460 460 - uint64_t cnt:32; 461 461 - uint64_t reserved_32_63:32; 462 462 - #endif 463 463 - } s; 464 464 - struct cvmx_sli_dmax_cnt_s cn61xx; 465 465 - struct cvmx_sli_dmax_cnt_s cn63xx; 466 466 - struct cvmx_sli_dmax_cnt_s cn63xxp1; 467 467 - struct cvmx_sli_dmax_cnt_s cn66xx; 468 468 - struct cvmx_sli_dmax_cnt_s cn68xx; 469 469 - struct cvmx_sli_dmax_cnt_s cn68xxp1; 470 470 - struct cvmx_sli_dmax_cnt_s cnf71xx; 471 471 - }; 472 472 - 473 473 - union cvmx_sli_dmax_int_level { 474 474 - uint64_t u64; 475 475 - struct cvmx_sli_dmax_int_level_s { 476 476 - #ifdef __BIG_ENDIAN_BITFIELD 477 477 - uint64_t time:32; 478 478 - uint64_t cnt:32; 479 479 - #else 480 480 - uint64_t cnt:32; 481 481 - uint64_t time:32; 482 482 - #endif 483 483 - } s; 484 484 - struct cvmx_sli_dmax_int_level_s cn61xx; 485 485 - struct cvmx_sli_dmax_int_level_s cn63xx; 486 486 - struct cvmx_sli_dmax_int_level_s cn63xxp1; 487 487 - struct cvmx_sli_dmax_int_level_s cn66xx; 488 488 - struct cvmx_sli_dmax_int_level_s cn68xx; 489 489 - struct cvmx_sli_dmax_int_level_s cn68xxp1; 490 490 - struct cvmx_sli_dmax_int_level_s cnf71xx; 491 491 - }; 492 492 - 493 493 - union cvmx_sli_dmax_tim { 494 494 - uint64_t u64; 495 495 - struct cvmx_sli_dmax_tim_s { 496 496 - #ifdef __BIG_ENDIAN_BITFIELD 497 497 - uint64_t reserved_32_63:32; 498 498 - uint64_t tim:32; 499 499 - #else 500 500 - uint64_t tim:32; 501 501 - uint64_t reserved_32_63:32; 502 502 - #endif 503 503 - } s; 504 504 - struct cvmx_sli_dmax_tim_s cn61xx; 505 505 - struct cvmx_sli_dmax_tim_s cn63xx; 506 506 - struct cvmx_sli_dmax_tim_s cn63xxp1; 507 507 - struct cvmx_sli_dmax_tim_s cn66xx; 508 508 - struct cvmx_sli_dmax_tim_s cn68xx; 509 509 - struct cvmx_sli_dmax_tim_s cn68xxp1; 510 510 - struct cvmx_sli_dmax_tim_s cnf71xx; 511 511 - }; 512 512 - 513 513 - union cvmx_sli_int_enb_ciu { 514 514 - uint64_t u64; 515 515 - struct cvmx_sli_int_enb_ciu_s { 516 516 - #ifdef __BIG_ENDIAN_BITFIELD 517 517 - uint64_t reserved_62_63:2; 518 518 - uint64_t pipe_err:1; 519 519 - uint64_t ill_pad:1; 520 520 - uint64_t sprt3_err:1; 521 521 - uint64_t sprt2_err:1; 522 522 - uint64_t sprt1_err:1; 523 523 - uint64_t sprt0_err:1; 524 524 - uint64_t pins_err:1; 525 525 - uint64_t pop_err:1; 526 526 - uint64_t pdi_err:1; 527 527 - uint64_t pgl_err:1; 528 528 - uint64_t pin_bp:1; 529 529 - uint64_t pout_err:1; 530 530 - uint64_t psldbof:1; 531 531 - uint64_t pidbof:1; 532 532 - uint64_t reserved_38_47:10; 533 533 - uint64_t dtime:2; 534 534 - uint64_t dcnt:2; 535 535 - uint64_t dmafi:2; 536 536 - uint64_t reserved_28_31:4; 537 537 - uint64_t m3_un_wi:1; 538 538 - uint64_t m3_un_b0:1; 539 539 - uint64_t m3_up_wi:1; 540 540 - uint64_t m3_up_b0:1; 541 541 - uint64_t m2_un_wi:1; 542 542 - uint64_t m2_un_b0:1; 543 543 - uint64_t m2_up_wi:1; 544 544 - uint64_t m2_up_b0:1; 545 545 - uint64_t reserved_18_19:2; 546 546 - uint64_t mio_int1:1; 547 547 - uint64_t mio_int0:1; 548 548 - uint64_t m1_un_wi:1; 549 549 - uint64_t m1_un_b0:1; 550 550 - uint64_t m1_up_wi:1; 551 551 - uint64_t m1_up_b0:1; 552 552 - uint64_t m0_un_wi:1; 553 553 - uint64_t m0_un_b0:1; 554 554 - uint64_t m0_up_wi:1; 555 555 - uint64_t m0_up_b0:1; 556 556 - uint64_t reserved_6_7:2; 557 557 - uint64_t ptime:1; 558 558 - uint64_t pcnt:1; 559 559 - uint64_t iob2big:1; 560 560 - uint64_t bar0_to:1; 561 561 - uint64_t reserved_1_1:1; 562 562 - uint64_t rml_to:1; 563 563 - #else 564 564 - uint64_t rml_to:1; 565 565 - uint64_t reserved_1_1:1; 566 566 - uint64_t bar0_to:1; 567 567 - uint64_t iob2big:1; 568 568 - uint64_t pcnt:1; 569 569 - uint64_t ptime:1; 570 570 - uint64_t reserved_6_7:2; 571 571 - uint64_t m0_up_b0:1; 572 572 - uint64_t m0_up_wi:1; 573 573 - uint64_t m0_un_b0:1; 574 574 - uint64_t m0_un_wi:1; 575 575 - uint64_t m1_up_b0:1; 576 576 - uint64_t m1_up_wi:1; 577 577 - uint64_t m1_un_b0:1; 578 578 - uint64_t m1_un_wi:1; 579 579 - uint64_t mio_int0:1; 580 580 - uint64_t mio_int1:1; 581 581 - uint64_t reserved_18_19:2; 582 582 - uint64_t m2_up_b0:1; 583 583 - uint64_t m2_up_wi:1; 584 584 - uint64_t m2_un_b0:1; 585 585 - uint64_t m2_un_wi:1; 586 586 - uint64_t m3_up_b0:1; 587 587 - uint64_t m3_up_wi:1; 588 588 - uint64_t m3_un_b0:1; 589 589 - uint64_t m3_un_wi:1; 590 590 - uint64_t reserved_28_31:4; 591 591 - uint64_t dmafi:2; 592 592 - uint64_t dcnt:2; 593 593 - uint64_t dtime:2; 594 594 - uint64_t reserved_38_47:10; 595 595 - uint64_t pidbof:1; 596 596 - uint64_t psldbof:1; 597 597 - uint64_t pout_err:1; 598 598 - uint64_t pin_bp:1; 599 599 - uint64_t pgl_err:1; 600 600 - uint64_t pdi_err:1; 601 601 - uint64_t pop_err:1; 602 602 - uint64_t pins_err:1; 603 603 - uint64_t sprt0_err:1; 604 604 - uint64_t sprt1_err:1; 605 605 - uint64_t sprt2_err:1; 606 606 - uint64_t sprt3_err:1; 607 607 - uint64_t ill_pad:1; 608 608 - uint64_t pipe_err:1; 609 609 - uint64_t reserved_62_63:2; 610 610 - #endif 611 611 - } s; 612 612 - struct cvmx_sli_int_enb_ciu_cn61xx { 613 613 - #ifdef __BIG_ENDIAN_BITFIELD 614 614 - uint64_t reserved_61_63:3; 615 615 - uint64_t ill_pad:1; 616 616 - uint64_t sprt3_err:1; 617 617 - uint64_t sprt2_err:1; 618 618 - uint64_t sprt1_err:1; 619 619 - uint64_t sprt0_err:1; 620 620 - uint64_t pins_err:1; 621 621 - uint64_t pop_err:1; 622 622 - uint64_t pdi_err:1; 623 623 - uint64_t pgl_err:1; 624 624 - uint64_t pin_bp:1; 625 625 - uint64_t pout_err:1; 626 626 - uint64_t psldbof:1; 627 627 - uint64_t pidbof:1; 628 628 - uint64_t reserved_38_47:10; 629 629 - uint64_t dtime:2; 630 630 - uint64_t dcnt:2; 631 631 - uint64_t dmafi:2; 632 632 - uint64_t reserved_28_31:4; 633 633 - uint64_t m3_un_wi:1; 634 634 - uint64_t m3_un_b0:1; 635 635 - uint64_t m3_up_wi:1; 636 636 - uint64_t m3_up_b0:1; 637 637 - uint64_t m2_un_wi:1; 638 638 - uint64_t m2_un_b0:1; 639 639 - uint64_t m2_up_wi:1; 640 640 - uint64_t m2_up_b0:1; 641 641 - uint64_t reserved_18_19:2; 642 642 - uint64_t mio_int1:1; 643 643 - uint64_t mio_int0:1; 644 644 - uint64_t m1_un_wi:1; 645 645 - uint64_t m1_un_b0:1; 646 646 - uint64_t m1_up_wi:1; 647 647 - uint64_t m1_up_b0:1; 648 648 - uint64_t m0_un_wi:1; 649 649 - uint64_t m0_un_b0:1; 650 650 - uint64_t m0_up_wi:1; 651 651 - uint64_t m0_up_b0:1; 652 652 - uint64_t reserved_6_7:2; 653 653 - uint64_t ptime:1; 654 654 - uint64_t pcnt:1; 655 655 - uint64_t iob2big:1; 656 656 - uint64_t bar0_to:1; 657 657 - uint64_t reserved_1_1:1; 658 658 - uint64_t rml_to:1; 659 659 - #else 660 660 - uint64_t rml_to:1; 661 661 - uint64_t reserved_1_1:1; 662 662 - uint64_t bar0_to:1; 663 663 - uint64_t iob2big:1; 664 664 - uint64_t pcnt:1; 665 665 - uint64_t ptime:1; 666 666 - uint64_t reserved_6_7:2; 667 667 - uint64_t m0_up_b0:1; 668 668 - uint64_t m0_up_wi:1; 669 669 - uint64_t m0_un_b0:1; 670 670 - uint64_t m0_un_wi:1; 671 671 - uint64_t m1_up_b0:1; 672 672 - uint64_t m1_up_wi:1; 673 673 - uint64_t m1_un_b0:1; 674 674 - uint64_t m1_un_wi:1; 675 675 - uint64_t mio_int0:1; 676 676 - uint64_t mio_int1:1; 677 677 - uint64_t reserved_18_19:2; 678 678 - uint64_t m2_up_b0:1; 679 679 - uint64_t m2_up_wi:1; 680 680 - uint64_t m2_un_b0:1; 681 681 - uint64_t m2_un_wi:1; 682 682 - uint64_t m3_up_b0:1; 683 683 - uint64_t m3_up_wi:1; 684 684 - uint64_t m3_un_b0:1; 685 685 - uint64_t m3_un_wi:1; 686 686 - uint64_t reserved_28_31:4; 687 687 - uint64_t dmafi:2; 688 688 - uint64_t dcnt:2; 689 689 - uint64_t dtime:2; 690 690 - uint64_t reserved_38_47:10; 691 691 - uint64_t pidbof:1; 692 692 - uint64_t psldbof:1; 693 693 - uint64_t pout_err:1; 694 694 - uint64_t pin_bp:1; 695 695 - uint64_t pgl_err:1; 696 696 - uint64_t pdi_err:1; 697 697 - uint64_t pop_err:1; 698 698 - uint64_t pins_err:1; 699 699 - uint64_t sprt0_err:1; 700 700 - uint64_t sprt1_err:1; 701 701 - uint64_t sprt2_err:1; 702 702 - uint64_t sprt3_err:1; 703 703 - uint64_t ill_pad:1; 704 704 - uint64_t reserved_61_63:3; 705 705 - #endif 706 706 - } cn61xx; 707 707 - struct cvmx_sli_int_enb_ciu_cn63xx { 708 708 - #ifdef __BIG_ENDIAN_BITFIELD 709 709 - uint64_t reserved_61_63:3; 710 710 - uint64_t ill_pad:1; 711 711 - uint64_t reserved_58_59:2; 712 712 - uint64_t sprt1_err:1; 713 713 - uint64_t sprt0_err:1; 714 714 - uint64_t pins_err:1; 715 715 - uint64_t pop_err:1; 716 716 - uint64_t pdi_err:1; 717 717 - uint64_t pgl_err:1; 718 718 - uint64_t pin_bp:1; 719 719 - uint64_t pout_err:1; 720 720 - uint64_t psldbof:1; 721 721 - uint64_t pidbof:1; 722 722 - uint64_t reserved_38_47:10; 723 723 - uint64_t dtime:2; 724 724 - uint64_t dcnt:2; 725 725 - uint64_t dmafi:2; 726 726 - uint64_t reserved_18_31:14; 727 727 - uint64_t mio_int1:1; 728 728 - uint64_t mio_int0:1; 729 729 - uint64_t m1_un_wi:1; 730 730 - uint64_t m1_un_b0:1; 731 731 - uint64_t m1_up_wi:1; 732 732 - uint64_t m1_up_b0:1; 733 733 - uint64_t m0_un_wi:1; 734 734 - uint64_t m0_un_b0:1; 735 735 - uint64_t m0_up_wi:1; 736 736 - uint64_t m0_up_b0:1; 737 737 - uint64_t reserved_6_7:2; 738 738 - uint64_t ptime:1; 739 739 - uint64_t pcnt:1; 740 740 - uint64_t iob2big:1; 741 741 - uint64_t bar0_to:1; 742 742 - uint64_t reserved_1_1:1; 743 743 - uint64_t rml_to:1; 744 744 - #else 745 745 - uint64_t rml_to:1; 746 746 - uint64_t reserved_1_1:1; 747 747 - uint64_t bar0_to:1; 748 748 - uint64_t iob2big:1; 749 749 - uint64_t pcnt:1; 750 750 - uint64_t ptime:1; 751 751 - uint64_t reserved_6_7:2; 752 752 - uint64_t m0_up_b0:1; 753 753 - uint64_t m0_up_wi:1; 754 754 - uint64_t m0_un_b0:1; 755 755 - uint64_t m0_un_wi:1; 756 756 - uint64_t m1_up_b0:1; 757 757 - uint64_t m1_up_wi:1; 758 758 - uint64_t m1_un_b0:1; 759 759 - uint64_t m1_un_wi:1; 760 760 - uint64_t mio_int0:1; 761 761 - uint64_t mio_int1:1; 762 762 - uint64_t reserved_18_31:14; 763 763 - uint64_t dmafi:2; 764 764 - uint64_t dcnt:2; 765 765 - uint64_t dtime:2; 766 766 - uint64_t reserved_38_47:10; 767 767 - uint64_t pidbof:1; 768 768 - uint64_t psldbof:1; 769 769 - uint64_t pout_err:1; 770 770 - uint64_t pin_bp:1; 771 771 - uint64_t pgl_err:1; 772 772 - uint64_t pdi_err:1; 773 773 - uint64_t pop_err:1; 774 774 - uint64_t pins_err:1; 775 775 - uint64_t sprt0_err:1; 776 776 - uint64_t sprt1_err:1; 777 777 - uint64_t reserved_58_59:2; 778 778 - uint64_t ill_pad:1; 779 779 - uint64_t reserved_61_63:3; 780 780 - #endif 781 781 - } cn63xx; 782 782 - struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1; 783 783 - struct cvmx_sli_int_enb_ciu_cn61xx cn66xx; 784 784 - struct cvmx_sli_int_enb_ciu_cn68xx { 785 785 - #ifdef __BIG_ENDIAN_BITFIELD 786 786 - uint64_t reserved_62_63:2; 787 787 - uint64_t pipe_err:1; 788 788 - uint64_t ill_pad:1; 789 789 - uint64_t reserved_58_59:2; 790 790 - uint64_t sprt1_err:1; 791 791 - uint64_t sprt0_err:1; 792 792 - uint64_t pins_err:1; 793 793 - uint64_t pop_err:1; 794 794 - uint64_t pdi_err:1; 795 795 - uint64_t pgl_err:1; 796 796 - uint64_t reserved_51_51:1; 797 797 - uint64_t pout_err:1; 798 798 - uint64_t psldbof:1; 799 799 - uint64_t pidbof:1; 800 800 - uint64_t reserved_38_47:10; 801 801 - uint64_t dtime:2; 802 802 - uint64_t dcnt:2; 803 803 - uint64_t dmafi:2; 804 804 - uint64_t reserved_18_31:14; 805 805 - uint64_t mio_int1:1; 806 806 - uint64_t mio_int0:1; 807 807 - uint64_t m1_un_wi:1; 808 808 - uint64_t m1_un_b0:1; 809 809 - uint64_t m1_up_wi:1; 810 810 - uint64_t m1_up_b0:1; 811 811 - uint64_t m0_un_wi:1; 812 812 - uint64_t m0_un_b0:1; 813 813 - uint64_t m0_up_wi:1; 814 814 - uint64_t m0_up_b0:1; 815 815 - uint64_t reserved_6_7:2; 816 816 - uint64_t ptime:1; 817 817 - uint64_t pcnt:1; 818 818 - uint64_t iob2big:1; 819 819 - uint64_t bar0_to:1; 820 820 - uint64_t reserved_1_1:1; 821 821 - uint64_t rml_to:1; 822 822 - #else 823 823 - uint64_t rml_to:1; 824 824 - uint64_t reserved_1_1:1; 825 825 - uint64_t bar0_to:1; 826 826 - uint64_t iob2big:1; 827 827 - uint64_t pcnt:1; 828 828 - uint64_t ptime:1; 829 829 - uint64_t reserved_6_7:2; 830 830 - uint64_t m0_up_b0:1; 831 831 - uint64_t m0_up_wi:1; 832 832 - uint64_t m0_un_b0:1; 833 833 - uint64_t m0_un_wi:1; 834 834 - uint64_t m1_up_b0:1; 835 835 - uint64_t m1_up_wi:1; 836 836 - uint64_t m1_un_b0:1; 837 837 - uint64_t m1_un_wi:1; 838 838 - uint64_t mio_int0:1; 839 839 - uint64_t mio_int1:1; 840 840 - uint64_t reserved_18_31:14; 841 841 - uint64_t dmafi:2; 842 842 - uint64_t dcnt:2; 843 843 - uint64_t dtime:2; 844 844 - uint64_t reserved_38_47:10; 845 845 - uint64_t pidbof:1; 846 846 - uint64_t psldbof:1; 847 847 - uint64_t pout_err:1; 848 848 - uint64_t reserved_51_51:1; 849 849 - uint64_t pgl_err:1; 850 850 - uint64_t pdi_err:1; 851 851 - uint64_t pop_err:1; 852 852 - uint64_t pins_err:1; 853 853 - uint64_t sprt0_err:1; 854 854 - uint64_t sprt1_err:1; 855 855 - uint64_t reserved_58_59:2; 856 856 - uint64_t ill_pad:1; 857 857 - uint64_t pipe_err:1; 858 858 - uint64_t reserved_62_63:2; 859 859 - #endif 860 860 - } cn68xx; 861 861 - struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1; 862 862 - struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx; 863 863 - }; 864 864 - 865 865 - union cvmx_sli_int_enb_portx { 866 866 - uint64_t u64; 867 867 - struct cvmx_sli_int_enb_portx_s { 868 868 - #ifdef __BIG_ENDIAN_BITFIELD 869 869 - uint64_t reserved_62_63:2; 870 870 - uint64_t pipe_err:1; 871 871 - uint64_t ill_pad:1; 872 872 - uint64_t sprt3_err:1; 873 873 - uint64_t sprt2_err:1; 874 874 - uint64_t sprt1_err:1; 875 875 - uint64_t sprt0_err:1; 876 876 - uint64_t pins_err:1; 877 877 - uint64_t pop_err:1; 878 878 - uint64_t pdi_err:1; 879 879 - uint64_t pgl_err:1; 880 880 - uint64_t pin_bp:1; 881 881 - uint64_t pout_err:1; 882 882 - uint64_t psldbof:1; 883 883 - uint64_t pidbof:1; 884 884 - uint64_t reserved_38_47:10; 885 885 - uint64_t dtime:2; 886 886 - uint64_t dcnt:2; 887 887 - uint64_t dmafi:2; 888 888 - uint64_t reserved_28_31:4; 889 889 - uint64_t m3_un_wi:1; 890 890 - uint64_t m3_un_b0:1; 891 891 - uint64_t m3_up_wi:1; 892 892 - uint64_t m3_up_b0:1; 893 893 - uint64_t m2_un_wi:1; 894 894 - uint64_t m2_un_b0:1; 895 895 - uint64_t m2_up_wi:1; 896 896 - uint64_t m2_up_b0:1; 897 897 - uint64_t mac1_int:1; 898 898 - uint64_t mac0_int:1; 899 899 - uint64_t mio_int1:1; 900 900 - uint64_t mio_int0:1; 901 901 - uint64_t m1_un_wi:1; 902 902 - uint64_t m1_un_b0:1; 903 903 - uint64_t m1_up_wi:1; 904 904 - uint64_t m1_up_b0:1; 905 905 - uint64_t m0_un_wi:1; 906 906 - uint64_t m0_un_b0:1; 907 907 - uint64_t m0_up_wi:1; 908 908 - uint64_t m0_up_b0:1; 909 909 - uint64_t reserved_6_7:2; 910 910 - uint64_t ptime:1; 911 911 - uint64_t pcnt:1; 912 912 - uint64_t iob2big:1; 913 913 - uint64_t bar0_to:1; 914 914 - uint64_t reserved_1_1:1; 915 915 - uint64_t rml_to:1; 916 916 - #else 917 917 - uint64_t rml_to:1; 918 918 - uint64_t reserved_1_1:1; 919 919 - uint64_t bar0_to:1; 920 920 - uint64_t iob2big:1; 921 921 - uint64_t pcnt:1; 922 922 - uint64_t ptime:1; 923 923 - uint64_t reserved_6_7:2; 924 924 - uint64_t m0_up_b0:1; 925 925 - uint64_t m0_up_wi:1; 926 926 - uint64_t m0_un_b0:1; 927 927 - uint64_t m0_un_wi:1; 928 928 - uint64_t m1_up_b0:1; 929 929 - uint64_t m1_up_wi:1; 930 930 - uint64_t m1_un_b0:1; 931 931 - uint64_t m1_un_wi:1; 932 932 - uint64_t mio_int0:1; 933 933 - uint64_t mio_int1:1; 934 934 - uint64_t mac0_int:1; 935 935 - uint64_t mac1_int:1; 936 936 - uint64_t m2_up_b0:1; 937 937 - uint64_t m2_up_wi:1; 938 938 - uint64_t m2_un_b0:1; 939 939 - uint64_t m2_un_wi:1; 940 940 - uint64_t m3_up_b0:1; 941 941 - uint64_t m3_up_wi:1; 942 942 - uint64_t m3_un_b0:1; 943 943 - uint64_t m3_un_wi:1; 944 944 - uint64_t reserved_28_31:4; 945 945 - uint64_t dmafi:2; 946 946 - uint64_t dcnt:2; 947 947 - uint64_t dtime:2; 948 948 - uint64_t reserved_38_47:10; 949 949 - uint64_t pidbof:1; 950 950 - uint64_t psldbof:1; 951 951 - uint64_t pout_err:1; 952 952 - uint64_t pin_bp:1; 953 953 - uint64_t pgl_err:1; 954 954 - uint64_t pdi_err:1; 955 955 - uint64_t pop_err:1; 956 956 - uint64_t pins_err:1; 957 957 - uint64_t sprt0_err:1; 958 958 - uint64_t sprt1_err:1; 959 959 - uint64_t sprt2_err:1; 960 960 - uint64_t sprt3_err:1; 961 961 - uint64_t ill_pad:1; 962 962 - uint64_t pipe_err:1; 963 963 - uint64_t reserved_62_63:2; 964 964 - #endif 965 965 - } s; 966 966 - struct cvmx_sli_int_enb_portx_cn61xx { 967 967 - #ifdef __BIG_ENDIAN_BITFIELD 968 968 - uint64_t reserved_61_63:3; 969 969 - uint64_t ill_pad:1; 970 970 - uint64_t sprt3_err:1; 971 971 - uint64_t sprt2_err:1; 972 972 - uint64_t sprt1_err:1; 973 973 - uint64_t sprt0_err:1; 974 974 - uint64_t pins_err:1; 975 975 - uint64_t pop_err:1; 976 976 - uint64_t pdi_err:1; 977 977 - uint64_t pgl_err:1; 978 978 - uint64_t pin_bp:1; 979 979 - uint64_t pout_err:1; 980 980 - uint64_t psldbof:1; 981 981 - uint64_t pidbof:1; 982 982 - uint64_t reserved_38_47:10; 983 983 - uint64_t dtime:2; 984 984 - uint64_t dcnt:2; 985 985 - uint64_t dmafi:2; 986 986 - uint64_t reserved_28_31:4; 987 987 - uint64_t m3_un_wi:1; 988 988 - uint64_t m3_un_b0:1; 989 989 - uint64_t m3_up_wi:1; 990 990 - uint64_t m3_up_b0:1; 991 991 - uint64_t m2_un_wi:1; 992 992 - uint64_t m2_un_b0:1; 993 993 - uint64_t m2_up_wi:1; 994 994 - uint64_t m2_up_b0:1; 995 995 - uint64_t mac1_int:1; 996 996 - uint64_t mac0_int:1; 997 997 - uint64_t mio_int1:1; 998 998 - uint64_t mio_int0:1; 999 999 - uint64_t m1_un_wi:1; 1000 1000 - uint64_t m1_un_b0:1; 1001 1001 - uint64_t m1_up_wi:1; 1002 1002 - uint64_t m1_up_b0:1; 1003 1003 - uint64_t m0_un_wi:1; 1004 1004 - uint64_t m0_un_b0:1; 1005 1005 - uint64_t m0_up_wi:1; 1006 1006 - uint64_t m0_up_b0:1; 1007 1007 - uint64_t reserved_6_7:2; 1008 1008 - uint64_t ptime:1; 1009 1009 - uint64_t pcnt:1; 1010 1010 - uint64_t iob2big:1; 1011 1011 - uint64_t bar0_to:1; 1012 1012 - uint64_t reserved_1_1:1; 1013 1013 - uint64_t rml_to:1; 1014 1014 - #else 1015 1015 - uint64_t rml_to:1; 1016 1016 - uint64_t reserved_1_1:1; 1017 1017 - uint64_t bar0_to:1; 1018 1018 - uint64_t iob2big:1; 1019 1019 - uint64_t pcnt:1; 1020 1020 - uint64_t ptime:1; 1021 1021 - uint64_t reserved_6_7:2; 1022 1022 - uint64_t m0_up_b0:1; 1023 1023 - uint64_t m0_up_wi:1; 1024 1024 - uint64_t m0_un_b0:1; 1025 1025 - uint64_t m0_un_wi:1; 1026 1026 - uint64_t m1_up_b0:1; 1027 1027 - uint64_t m1_up_wi:1; 1028 1028 - uint64_t m1_un_b0:1; 1029 1029 - uint64_t m1_un_wi:1; 1030 1030 - uint64_t mio_int0:1; 1031 1031 - uint64_t mio_int1:1; 1032 1032 - uint64_t mac0_int:1; 1033 1033 - uint64_t mac1_int:1; 1034 1034 - uint64_t m2_up_b0:1; 1035 1035 - uint64_t m2_up_wi:1; 1036 1036 - uint64_t m2_un_b0:1; 1037 1037 - uint64_t m2_un_wi:1; 1038 1038 - uint64_t m3_up_b0:1; 1039 1039 - uint64_t m3_up_wi:1; 1040 1040 - uint64_t m3_un_b0:1; 1041 1041 - uint64_t m3_un_wi:1; 1042 1042 - uint64_t reserved_28_31:4; 1043 1043 - uint64_t dmafi:2; 1044 1044 - uint64_t dcnt:2; 1045 1045 - uint64_t dtime:2; 1046 1046 - uint64_t reserved_38_47:10; 1047 1047 - uint64_t pidbof:1; 1048 1048 - uint64_t psldbof:1; 1049 1049 - uint64_t pout_err:1; 1050 1050 - uint64_t pin_bp:1; 1051 1051 - uint64_t pgl_err:1; 1052 1052 - uint64_t pdi_err:1; 1053 1053 - uint64_t pop_err:1; 1054 1054 - uint64_t pins_err:1; 1055 1055 - uint64_t sprt0_err:1; 1056 1056 - uint64_t sprt1_err:1; 1057 1057 - uint64_t sprt2_err:1; 1058 1058 - uint64_t sprt3_err:1; 1059 1059 - uint64_t ill_pad:1; 1060 1060 - uint64_t reserved_61_63:3; 1061 1061 - #endif 1062 1062 - } cn61xx; 1063 1063 - struct cvmx_sli_int_enb_portx_cn63xx { 1064 1064 - #ifdef __BIG_ENDIAN_BITFIELD 1065 1065 - uint64_t reserved_61_63:3; 1066 1066 - uint64_t ill_pad:1; 1067 1067 - uint64_t reserved_58_59:2; 1068 1068 - uint64_t sprt1_err:1; 1069 1069 - uint64_t sprt0_err:1; 1070 1070 - uint64_t pins_err:1; 1071 1071 - uint64_t pop_err:1; 1072 1072 - uint64_t pdi_err:1; 1073 1073 - uint64_t pgl_err:1; 1074 1074 - uint64_t pin_bp:1; 1075 1075 - uint64_t pout_err:1; 1076 1076 - uint64_t psldbof:1; 1077 1077 - uint64_t pidbof:1; 1078 1078 - uint64_t reserved_38_47:10; 1079 1079 - uint64_t dtime:2; 1080 1080 - uint64_t dcnt:2; 1081 1081 - uint64_t dmafi:2; 1082 1082 - uint64_t reserved_20_31:12; 1083 1083 - uint64_t mac1_int:1; 1084 1084 - uint64_t mac0_int:1; 1085 1085 - uint64_t mio_int1:1; 1086 1086 - uint64_t mio_int0:1; 1087 1087 - uint64_t m1_un_wi:1; 1088 1088 - uint64_t m1_un_b0:1; 1089 1089 - uint64_t m1_up_wi:1; 1090 1090 - uint64_t m1_up_b0:1; 1091 1091 - uint64_t m0_un_wi:1; 1092 1092 - uint64_t m0_un_b0:1; 1093 1093 - uint64_t m0_up_wi:1; 1094 1094 - uint64_t m0_up_b0:1; 1095 1095 - uint64_t reserved_6_7:2; 1096 1096 - uint64_t ptime:1; 1097 1097 - uint64_t pcnt:1; 1098 1098 - uint64_t iob2big:1; 1099 1099 - uint64_t bar0_to:1; 1100 1100 - uint64_t reserved_1_1:1; 1101 1101 - uint64_t rml_to:1; 1102 1102 - #else 1103 1103 - uint64_t rml_to:1; 1104 1104 - uint64_t reserved_1_1:1; 1105 1105 - uint64_t bar0_to:1; 1106 1106 - uint64_t iob2big:1; 1107 1107 - uint64_t pcnt:1; 1108 1108 - uint64_t ptime:1; 1109 1109 - uint64_t reserved_6_7:2; 1110 1110 - uint64_t m0_up_b0:1; 1111 1111 - uint64_t m0_up_wi:1; 1112 1112 - uint64_t m0_un_b0:1; 1113 1113 - uint64_t m0_un_wi:1; 1114 1114 - uint64_t m1_up_b0:1; 1115 1115 - uint64_t m1_up_wi:1; 1116 1116 - uint64_t m1_un_b0:1; 1117 1117 - uint64_t m1_un_wi:1; 1118 1118 - uint64_t mio_int0:1; 1119 1119 - uint64_t mio_int1:1; 1120 1120 - uint64_t mac0_int:1; 1121 1121 - uint64_t mac1_int:1; 1122 1122 - uint64_t reserved_20_31:12; 1123 1123 - uint64_t dmafi:2; 1124 1124 - uint64_t dcnt:2; 1125 1125 - uint64_t dtime:2; 1126 1126 - uint64_t reserved_38_47:10; 1127 1127 - uint64_t pidbof:1; 1128 1128 - uint64_t psldbof:1; 1129 1129 - uint64_t pout_err:1; 1130 1130 - uint64_t pin_bp:1; 1131 1131 - uint64_t pgl_err:1; 1132 1132 - uint64_t pdi_err:1; 1133 1133 - uint64_t pop_err:1; 1134 1134 - uint64_t pins_err:1; 1135 1135 - uint64_t sprt0_err:1; 1136 1136 - uint64_t sprt1_err:1; 1137 1137 - uint64_t reserved_58_59:2; 1138 1138 - uint64_t ill_pad:1; 1139 1139 - uint64_t reserved_61_63:3; 1140 1140 - #endif 1141 1141 - } cn63xx; 1142 1142 - struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1; 1143 1143 - struct cvmx_sli_int_enb_portx_cn61xx cn66xx; 1144 1144 - struct cvmx_sli_int_enb_portx_cn68xx { 1145 1145 - #ifdef __BIG_ENDIAN_BITFIELD 1146 1146 - uint64_t reserved_62_63:2; 1147 1147 - uint64_t pipe_err:1; 1148 1148 - uint64_t ill_pad:1; 1149 1149 - uint64_t reserved_58_59:2; 1150 1150 - uint64_t sprt1_err:1; 1151 1151 - uint64_t sprt0_err:1; 1152 1152 - uint64_t pins_err:1; 1153 1153 - uint64_t pop_err:1; 1154 1154 - uint64_t pdi_err:1; 1155 1155 - uint64_t pgl_err:1; 1156 1156 - uint64_t reserved_51_51:1; 1157 1157 - uint64_t pout_err:1; 1158 1158 - uint64_t psldbof:1; 1159 1159 - uint64_t pidbof:1; 1160 1160 - uint64_t reserved_38_47:10; 1161 1161 - uint64_t dtime:2; 1162 1162 - uint64_t dcnt:2; 1163 1163 - uint64_t dmafi:2; 1164 1164 - uint64_t reserved_20_31:12; 1165 1165 - uint64_t mac1_int:1; 1166 1166 - uint64_t mac0_int:1; 1167 1167 - uint64_t mio_int1:1; 1168 1168 - uint64_t mio_int0:1; 1169 1169 - uint64_t m1_un_wi:1; 1170 1170 - uint64_t m1_un_b0:1; 1171 1171 - uint64_t m1_up_wi:1; 1172 1172 - uint64_t m1_up_b0:1; 1173 1173 - uint64_t m0_un_wi:1; 1174 1174 - uint64_t m0_un_b0:1; 1175 1175 - uint64_t m0_up_wi:1; 1176 1176 - uint64_t m0_up_b0:1; 1177 1177 - uint64_t reserved_6_7:2; 1178 1178 - uint64_t ptime:1; 1179 1179 - uint64_t pcnt:1; 1180 1180 - uint64_t iob2big:1; 1181 1181 - uint64_t bar0_to:1; 1182 1182 - uint64_t reserved_1_1:1; 1183 1183 - uint64_t rml_to:1; 1184 1184 - #else 1185 1185 - uint64_t rml_to:1; 1186 1186 - uint64_t reserved_1_1:1; 1187 1187 - uint64_t bar0_to:1; 1188 1188 - uint64_t iob2big:1; 1189 1189 - uint64_t pcnt:1; 1190 1190 - uint64_t ptime:1; 1191 1191 - uint64_t reserved_6_7:2; 1192 1192 - uint64_t m0_up_b0:1; 1193 1193 - uint64_t m0_up_wi:1; 1194 1194 - uint64_t m0_un_b0:1; 1195 1195 - uint64_t m0_un_wi:1; 1196 1196 - uint64_t m1_up_b0:1; 1197 1197 - uint64_t m1_up_wi:1; 1198 1198 - uint64_t m1_un_b0:1; 1199 1199 - uint64_t m1_un_wi:1; 1200 1200 - uint64_t mio_int0:1; 1201 1201 - uint64_t mio_int1:1; 1202 1202 - uint64_t mac0_int:1; 1203 1203 - uint64_t mac1_int:1; 1204 1204 - uint64_t reserved_20_31:12; 1205 1205 - uint64_t dmafi:2; 1206 1206 - uint64_t dcnt:2; 1207 1207 - uint64_t dtime:2; 1208 1208 - uint64_t reserved_38_47:10; 1209 1209 - uint64_t pidbof:1; 1210 1210 - uint64_t psldbof:1; 1211 1211 - uint64_t pout_err:1; 1212 1212 - uint64_t reserved_51_51:1; 1213 1213 - uint64_t pgl_err:1; 1214 1214 - uint64_t pdi_err:1; 1215 1215 - uint64_t pop_err:1; 1216 1216 - uint64_t pins_err:1; 1217 1217 - uint64_t sprt0_err:1; 1218 1218 - uint64_t sprt1_err:1; 1219 1219 - uint64_t reserved_58_59:2; 1220 1220 - uint64_t ill_pad:1; 1221 1221 - uint64_t pipe_err:1; 1222 1222 - uint64_t reserved_62_63:2; 1223 1223 - #endif 1224 1224 - } cn68xx; 1225 1225 - struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1; 1226 1226 - struct cvmx_sli_int_enb_portx_cn61xx cnf71xx; 1227 1227 - }; 1228 1228 - 1229 1229 - union cvmx_sli_int_sum { 1230 1230 - uint64_t u64; 1231 1231 - struct cvmx_sli_int_sum_s { 1232 1232 - #ifdef __BIG_ENDIAN_BITFIELD 1233 1233 - uint64_t reserved_62_63:2; 1234 1234 - uint64_t pipe_err:1; 1235 1235 - uint64_t ill_pad:1; 1236 1236 - uint64_t sprt3_err:1; 1237 1237 - uint64_t sprt2_err:1; 1238 1238 - uint64_t sprt1_err:1; 1239 1239 - uint64_t sprt0_err:1; 1240 1240 - uint64_t pins_err:1; 1241 1241 - uint64_t pop_err:1; 1242 1242 - uint64_t pdi_err:1; 1243 1243 - uint64_t pgl_err:1; 1244 1244 - uint64_t pin_bp:1; 1245 1245 - uint64_t pout_err:1; 1246 1246 - uint64_t psldbof:1; 1247 1247 - uint64_t pidbof:1; 1248 1248 - uint64_t reserved_38_47:10; 1249 1249 - uint64_t dtime:2; 1250 1250 - uint64_t dcnt:2; 1251 1251 - uint64_t dmafi:2; 1252 1252 - uint64_t reserved_28_31:4; 1253 1253 - uint64_t m3_un_wi:1; 1254 1254 - uint64_t m3_un_b0:1; 1255 1255 - uint64_t m3_up_wi:1; 1256 1256 - uint64_t m3_up_b0:1; 1257 1257 - uint64_t m2_un_wi:1; 1258 1258 - uint64_t m2_un_b0:1; 1259 1259 - uint64_t m2_up_wi:1; 1260 1260 - uint64_t m2_up_b0:1; 1261 1261 - uint64_t mac1_int:1; 1262 1262 - uint64_t mac0_int:1; 1263 1263 - uint64_t mio_int1:1; 1264 1264 - uint64_t mio_int0:1; 1265 1265 - uint64_t m1_un_wi:1; 1266 1266 - uint64_t m1_un_b0:1; 1267 1267 - uint64_t m1_up_wi:1; 1268 1268 - uint64_t m1_up_b0:1; 1269 1269 - uint64_t m0_un_wi:1; 1270 1270 - uint64_t m0_un_b0:1; 1271 1271 - uint64_t m0_up_wi:1; 1272 1272 - uint64_t m0_up_b0:1; 1273 1273 - uint64_t reserved_6_7:2; 1274 1274 - uint64_t ptime:1; 1275 1275 - uint64_t pcnt:1; 1276 1276 - uint64_t iob2big:1; 1277 1277 - uint64_t bar0_to:1; 1278 1278 - uint64_t reserved_1_1:1; 1279 1279 - uint64_t rml_to:1; 1280 1280 - #else 1281 1281 - uint64_t rml_to:1; 1282 1282 - uint64_t reserved_1_1:1; 1283 1283 - uint64_t bar0_to:1; 1284 1284 - uint64_t iob2big:1; 1285 1285 - uint64_t pcnt:1; 1286 1286 - uint64_t ptime:1; 1287 1287 - uint64_t reserved_6_7:2; 1288 1288 - uint64_t m0_up_b0:1; 1289 1289 - uint64_t m0_up_wi:1; 1290 1290 - uint64_t m0_un_b0:1; 1291 1291 - uint64_t m0_un_wi:1; 1292 1292 - uint64_t m1_up_b0:1; 1293 1293 - uint64_t m1_up_wi:1; 1294 1294 - uint64_t m1_un_b0:1; 1295 1295 - uint64_t m1_un_wi:1; 1296 1296 - uint64_t mio_int0:1; 1297 1297 - uint64_t mio_int1:1; 1298 1298 - uint64_t mac0_int:1; 1299 1299 - uint64_t mac1_int:1; 1300 1300 - uint64_t m2_up_b0:1; 1301 1301 - uint64_t m2_up_wi:1; 1302 1302 - uint64_t m2_un_b0:1; 1303 1303 - uint64_t m2_un_wi:1; 1304 1304 - uint64_t m3_up_b0:1; 1305 1305 - uint64_t m3_up_wi:1; 1306 1306 - uint64_t m3_un_b0:1; 1307 1307 - uint64_t m3_un_wi:1; 1308 1308 - uint64_t reserved_28_31:4; 1309 1309 - uint64_t dmafi:2; 1310 1310 - uint64_t dcnt:2; 1311 1311 - uint64_t dtime:2; 1312 1312 - uint64_t reserved_38_47:10; 1313 1313 - uint64_t pidbof:1; 1314 1314 - uint64_t psldbof:1; 1315 1315 - uint64_t pout_err:1; 1316 1316 - uint64_t pin_bp:1; 1317 1317 - uint64_t pgl_err:1; 1318 1318 - uint64_t pdi_err:1; 1319 1319 - uint64_t pop_err:1; 1320 1320 - uint64_t pins_err:1; 1321 1321 - uint64_t sprt0_err:1; 1322 1322 - uint64_t sprt1_err:1; 1323 1323 - uint64_t sprt2_err:1; 1324 1324 - uint64_t sprt3_err:1; 1325 1325 - uint64_t ill_pad:1; 1326 1326 - uint64_t pipe_err:1; 1327 1327 - uint64_t reserved_62_63:2; 1328 1328 - #endif 1329 1329 - } s; 1330 1330 - struct cvmx_sli_int_sum_cn61xx { 1331 1331 - #ifdef __BIG_ENDIAN_BITFIELD 1332 1332 - uint64_t reserved_61_63:3; 1333 1333 - uint64_t ill_pad:1; 1334 1334 - uint64_t sprt3_err:1; 1335 1335 - uint64_t sprt2_err:1; 1336 1336 - uint64_t sprt1_err:1; 1337 1337 - uint64_t sprt0_err:1; 1338 1338 - uint64_t pins_err:1; 1339 1339 - uint64_t pop_err:1; 1340 1340 - uint64_t pdi_err:1; 1341 1341 - uint64_t pgl_err:1; 1342 1342 - uint64_t pin_bp:1; 1343 1343 - uint64_t pout_err:1; 1344 1344 - uint64_t psldbof:1; 1345 1345 - uint64_t pidbof:1; 1346 1346 - uint64_t reserved_38_47:10; 1347 1347 - uint64_t dtime:2; 1348 1348 - uint64_t dcnt:2; 1349 1349 - uint64_t dmafi:2; 1350 1350 - uint64_t reserved_28_31:4; 1351 1351 - uint64_t m3_un_wi:1; 1352 1352 - uint64_t m3_un_b0:1; 1353 1353 - uint64_t m3_up_wi:1; 1354 1354 - uint64_t m3_up_b0:1; 1355 1355 - uint64_t m2_un_wi:1; 1356 1356 - uint64_t m2_un_b0:1; 1357 1357 - uint64_t m2_up_wi:1; 1358 1358 - uint64_t m2_up_b0:1; 1359 1359 - uint64_t mac1_int:1; 1360 1360 - uint64_t mac0_int:1; 1361 1361 - uint64_t mio_int1:1; 1362 1362 - uint64_t mio_int0:1; 1363 1363 - uint64_t m1_un_wi:1; 1364 1364 - uint64_t m1_un_b0:1; 1365 1365 - uint64_t m1_up_wi:1; 1366 1366 - uint64_t m1_up_b0:1; 1367 1367 - uint64_t m0_un_wi:1; 1368 1368 - uint64_t m0_un_b0:1; 1369 1369 - uint64_t m0_up_wi:1; 1370 1370 - uint64_t m0_up_b0:1; 1371 1371 - uint64_t reserved_6_7:2; 1372 1372 - uint64_t ptime:1; 1373 1373 - uint64_t pcnt:1; 1374 1374 - uint64_t iob2big:1; 1375 1375 - uint64_t bar0_to:1; 1376 1376 - uint64_t reserved_1_1:1; 1377 1377 - uint64_t rml_to:1; 1378 1378 - #else 1379 1379 - uint64_t rml_to:1; 1380 1380 - uint64_t reserved_1_1:1; 1381 1381 - uint64_t bar0_to:1; 1382 1382 - uint64_t iob2big:1; 1383 1383 - uint64_t pcnt:1; 1384 1384 - uint64_t ptime:1; 1385 1385 - uint64_t reserved_6_7:2; 1386 1386 - uint64_t m0_up_b0:1; 1387 1387 - uint64_t m0_up_wi:1; 1388 1388 - uint64_t m0_un_b0:1; 1389 1389 - uint64_t m0_un_wi:1; 1390 1390 - uint64_t m1_up_b0:1; 1391 1391 - uint64_t m1_up_wi:1; 1392 1392 - uint64_t m1_un_b0:1; 1393 1393 - uint64_t m1_un_wi:1; 1394 1394 - uint64_t mio_int0:1; 1395 1395 - uint64_t mio_int1:1; 1396 1396 - uint64_t mac0_int:1; 1397 1397 - uint64_t mac1_int:1; 1398 1398 - uint64_t m2_up_b0:1; 1399 1399 - uint64_t m2_up_wi:1; 1400 1400 - uint64_t m2_un_b0:1; 1401 1401 - uint64_t m2_un_wi:1; 1402 1402 - uint64_t m3_up_b0:1; 1403 1403 - uint64_t m3_up_wi:1; 1404 1404 - uint64_t m3_un_b0:1; 1405 1405 - uint64_t m3_un_wi:1; 1406 1406 - uint64_t reserved_28_31:4; 1407 1407 - uint64_t dmafi:2; 1408 1408 - uint64_t dcnt:2; 1409 1409 - uint64_t dtime:2; 1410 1410 - uint64_t reserved_38_47:10; 1411 1411 - uint64_t pidbof:1; 1412 1412 - uint64_t psldbof:1; 1413 1413 - uint64_t pout_err:1; 1414 1414 - uint64_t pin_bp:1; 1415 1415 - uint64_t pgl_err:1; 1416 1416 - uint64_t pdi_err:1; 1417 1417 - uint64_t pop_err:1; 1418 1418 - uint64_t pins_err:1; 1419 1419 - uint64_t sprt0_err:1; 1420 1420 - uint64_t sprt1_err:1; 1421 1421 - uint64_t sprt2_err:1; 1422 1422 - uint64_t sprt3_err:1; 1423 1423 - uint64_t ill_pad:1; 1424 1424 - uint64_t reserved_61_63:3; 1425 1425 - #endif 1426 1426 - } cn61xx; 1427 1427 - struct cvmx_sli_int_sum_cn63xx { 1428 1428 - #ifdef __BIG_ENDIAN_BITFIELD 1429 1429 - uint64_t reserved_61_63:3; 1430 1430 - uint64_t ill_pad:1; 1431 1431 - uint64_t reserved_58_59:2; 1432 1432 - uint64_t sprt1_err:1; 1433 1433 - uint64_t sprt0_err:1; 1434 1434 - uint64_t pins_err:1; 1435 1435 - uint64_t pop_err:1; 1436 1436 - uint64_t pdi_err:1; 1437 1437 - uint64_t pgl_err:1; 1438 1438 - uint64_t pin_bp:1; 1439 1439 - uint64_t pout_err:1; 1440 1440 - uint64_t psldbof:1; 1441 1441 - uint64_t pidbof:1; 1442 1442 - uint64_t reserved_38_47:10; 1443 1443 - uint64_t dtime:2; 1444 1444 - uint64_t dcnt:2; 1445 1445 - uint64_t dmafi:2; 1446 1446 - uint64_t reserved_20_31:12; 1447 1447 - uint64_t mac1_int:1; 1448 1448 - uint64_t mac0_int:1; 1449 1449 - uint64_t mio_int1:1; 1450 1450 - uint64_t mio_int0:1; 1451 1451 - uint64_t m1_un_wi:1; 1452 1452 - uint64_t m1_un_b0:1; 1453 1453 - uint64_t m1_up_wi:1; 1454 1454 - uint64_t m1_up_b0:1; 1455 1455 - uint64_t m0_un_wi:1; 1456 1456 - uint64_t m0_un_b0:1; 1457 1457 - uint64_t m0_up_wi:1; 1458 1458 - uint64_t m0_up_b0:1; 1459 1459 - uint64_t reserved_6_7:2; 1460 1460 - uint64_t ptime:1; 1461 1461 - uint64_t pcnt:1; 1462 1462 - uint64_t iob2big:1; 1463 1463 - uint64_t bar0_to:1; 1464 1464 - uint64_t reserved_1_1:1; 1465 1465 - uint64_t rml_to:1; 1466 1466 - #else 1467 1467 - uint64_t rml_to:1; 1468 1468 - uint64_t reserved_1_1:1; 1469 1469 - uint64_t bar0_to:1; 1470 1470 - uint64_t iob2big:1; 1471 1471 - uint64_t pcnt:1; 1472 1472 - uint64_t ptime:1; 1473 1473 - uint64_t reserved_6_7:2; 1474 1474 - uint64_t m0_up_b0:1; 1475 1475 - uint64_t m0_up_wi:1; 1476 1476 - uint64_t m0_un_b0:1; 1477 1477 - uint64_t m0_un_wi:1; 1478 1478 - uint64_t m1_up_b0:1; 1479 1479 - uint64_t m1_up_wi:1; 1480 1480 - uint64_t m1_un_b0:1; 1481 1481 - uint64_t m1_un_wi:1; 1482 1482 - uint64_t mio_int0:1; 1483 1483 - uint64_t mio_int1:1; 1484 1484 - uint64_t mac0_int:1; 1485 1485 - uint64_t mac1_int:1; 1486 1486 - uint64_t reserved_20_31:12; 1487 1487 - uint64_t dmafi:2; 1488 1488 - uint64_t dcnt:2; 1489 1489 - uint64_t dtime:2; 1490 1490 - uint64_t reserved_38_47:10; 1491 1491 - uint64_t pidbof:1; 1492 1492 - uint64_t psldbof:1; 1493 1493 - uint64_t pout_err:1; 1494 1494 - uint64_t pin_bp:1; 1495 1495 - uint64_t pgl_err:1; 1496 1496 - uint64_t pdi_err:1; 1497 1497 - uint64_t pop_err:1; 1498 1498 - uint64_t pins_err:1; 1499 1499 - uint64_t sprt0_err:1; 1500 1500 - uint64_t sprt1_err:1; 1501 1501 - uint64_t reserved_58_59:2; 1502 1502 - uint64_t ill_pad:1; 1503 1503 - uint64_t reserved_61_63:3; 1504 1504 - #endif 1505 1505 - } cn63xx; 1506 1506 - struct cvmx_sli_int_sum_cn63xx cn63xxp1; 1507 1507 - struct cvmx_sli_int_sum_cn61xx cn66xx; 1508 1508 - struct cvmx_sli_int_sum_cn68xx { 1509 1509 - #ifdef __BIG_ENDIAN_BITFIELD 1510 1510 - uint64_t reserved_62_63:2; 1511 1511 - uint64_t pipe_err:1; 1512 1512 - uint64_t ill_pad:1; 1513 1513 - uint64_t reserved_58_59:2; 1514 1514 - uint64_t sprt1_err:1; 1515 1515 - uint64_t sprt0_err:1; 1516 1516 - uint64_t pins_err:1; 1517 1517 - uint64_t pop_err:1; 1518 1518 - uint64_t pdi_err:1; 1519 1519 - uint64_t pgl_err:1; 1520 1520 - uint64_t reserved_51_51:1; 1521 1521 - uint64_t pout_err:1; 1522 1522 - uint64_t psldbof:1; 1523 1523 - uint64_t pidbof:1; 1524 1524 - uint64_t reserved_38_47:10; 1525 1525 - uint64_t dtime:2; 1526 1526 - uint64_t dcnt:2; 1527 1527 - uint64_t dmafi:2; 1528 1528 - uint64_t reserved_20_31:12; 1529 1529 - uint64_t mac1_int:1; 1530 1530 - uint64_t mac0_int:1; 1531 1531 - uint64_t mio_int1:1; 1532 1532 - uint64_t mio_int0:1; 1533 1533 - uint64_t m1_un_wi:1; 1534 1534 - uint64_t m1_un_b0:1; 1535 1535 - uint64_t m1_up_wi:1; 1536 1536 - uint64_t m1_up_b0:1; 1537 1537 - uint64_t m0_un_wi:1; 1538 1538 - uint64_t m0_un_b0:1; 1539 1539 - uint64_t m0_up_wi:1; 1540 1540 - uint64_t m0_up_b0:1; 1541 1541 - uint64_t reserved_6_7:2; 1542 1542 - uint64_t ptime:1; 1543 1543 - uint64_t pcnt:1; 1544 1544 - uint64_t iob2big:1; 1545 1545 - uint64_t bar0_to:1; 1546 1546 - uint64_t reserved_1_1:1; 1547 1547 - uint64_t rml_to:1; 1548 1548 - #else 1549 1549 - uint64_t rml_to:1; 1550 1550 - uint64_t reserved_1_1:1; 1551 1551 - uint64_t bar0_to:1; 1552 1552 - uint64_t iob2big:1; 1553 1553 - uint64_t pcnt:1; 1554 1554 - uint64_t ptime:1; 1555 1555 - uint64_t reserved_6_7:2; 1556 1556 - uint64_t m0_up_b0:1; 1557 1557 - uint64_t m0_up_wi:1; 1558 1558 - uint64_t m0_un_b0:1; 1559 1559 - uint64_t m0_un_wi:1; 1560 1560 - uint64_t m1_up_b0:1; 1561 1561 - uint64_t m1_up_wi:1; 1562 1562 - uint64_t m1_un_b0:1; 1563 1563 - uint64_t m1_un_wi:1; 1564 1564 - uint64_t mio_int0:1; 1565 1565 - uint64_t mio_int1:1; 1566 1566 - uint64_t mac0_int:1; 1567 1567 - uint64_t mac1_int:1; 1568 1568 - uint64_t reserved_20_31:12; 1569 1569 - uint64_t dmafi:2; 1570 1570 - uint64_t dcnt:2; 1571 1571 - uint64_t dtime:2; 1572 1572 - uint64_t reserved_38_47:10; 1573 1573 - uint64_t pidbof:1; 1574 1574 - uint64_t psldbof:1; 1575 1575 - uint64_t pout_err:1; 1576 1576 - uint64_t reserved_51_51:1; 1577 1577 - uint64_t pgl_err:1; 1578 1578 - uint64_t pdi_err:1; 1579 1579 - uint64_t pop_err:1; 1580 1580 - uint64_t pins_err:1; 1581 1581 - uint64_t sprt0_err:1; 1582 1582 - uint64_t sprt1_err:1; 1583 1583 - uint64_t reserved_58_59:2; 1584 1584 - uint64_t ill_pad:1; 1585 1585 - uint64_t pipe_err:1; 1586 1586 - uint64_t reserved_62_63:2; 1587 1587 - #endif 1588 1588 - } cn68xx; 1589 1589 - struct cvmx_sli_int_sum_cn68xx cn68xxp1; 1590 1590 - struct cvmx_sli_int_sum_cn61xx cnf71xx; 1591 1591 - }; 1592 1592 - 1593 1593 - union cvmx_sli_last_win_rdata0 { 1594 1594 - uint64_t u64; 1595 1595 - struct cvmx_sli_last_win_rdata0_s { 1596 1596 - #ifdef __BIG_ENDIAN_BITFIELD 1597 1597 - uint64_t data:64; 1598 1598 - #else 1599 1599 - uint64_t data:64; 1600 1600 - #endif 1601 1601 - } s; 1602 1602 - struct cvmx_sli_last_win_rdata0_s cn61xx; 1603 1603 - struct cvmx_sli_last_win_rdata0_s cn63xx; 1604 1604 - struct cvmx_sli_last_win_rdata0_s cn63xxp1; 1605 1605 - struct cvmx_sli_last_win_rdata0_s cn66xx; 1606 1606 - struct cvmx_sli_last_win_rdata0_s cn68xx; 1607 1607 - struct cvmx_sli_last_win_rdata0_s cn68xxp1; 1608 1608 - struct cvmx_sli_last_win_rdata0_s cnf71xx; 1609 1609 - }; 1610 1610 - 1611 1611 - union cvmx_sli_last_win_rdata1 { 1612 1612 - uint64_t u64; 1613 1613 - struct cvmx_sli_last_win_rdata1_s { 1614 1614 - #ifdef __BIG_ENDIAN_BITFIELD 1615 1615 - uint64_t data:64; 1616 1616 - #else 1617 1617 - uint64_t data:64; 1618 1618 - #endif 1619 1619 - } s; 1620 1620 - struct cvmx_sli_last_win_rdata1_s cn61xx; 1621 1621 - struct cvmx_sli_last_win_rdata1_s cn63xx; 1622 1622 - struct cvmx_sli_last_win_rdata1_s cn63xxp1; 1623 1623 - struct cvmx_sli_last_win_rdata1_s cn66xx; 1624 1624 - struct cvmx_sli_last_win_rdata1_s cn68xx; 1625 1625 - struct cvmx_sli_last_win_rdata1_s cn68xxp1; 1626 1626 - struct cvmx_sli_last_win_rdata1_s cnf71xx; 1627 1627 - }; 1628 1628 - 1629 1629 - union cvmx_sli_last_win_rdata2 { 1630 1630 - uint64_t u64; 1631 1631 - struct cvmx_sli_last_win_rdata2_s { 1632 1632 - #ifdef __BIG_ENDIAN_BITFIELD 1633 1633 - uint64_t data:64; 1634 1634 - #else 1635 1635 - uint64_t data:64; 1636 1636 - #endif 1637 1637 - } s; 1638 1638 - struct cvmx_sli_last_win_rdata2_s cn61xx; 1639 1639 - struct cvmx_sli_last_win_rdata2_s cn66xx; 1640 1640 - struct cvmx_sli_last_win_rdata2_s cnf71xx; 1641 1641 - }; 1642 1642 - 1643 1643 - union cvmx_sli_last_win_rdata3 { 1644 1644 - uint64_t u64; 1645 1645 - struct cvmx_sli_last_win_rdata3_s { 1646 1646 - #ifdef __BIG_ENDIAN_BITFIELD 1647 1647 - uint64_t data:64; 1648 1648 - #else 1649 1649 - uint64_t data:64; 1650 1650 - #endif 1651 1651 - } s; 1652 1652 - struct cvmx_sli_last_win_rdata3_s cn61xx; 1653 1653 - struct cvmx_sli_last_win_rdata3_s cn66xx; 1654 1654 - struct cvmx_sli_last_win_rdata3_s cnf71xx; 1655 1655 - }; 1656 1656 - 1657 1657 - union cvmx_sli_mac_credit_cnt { 1658 1658 - uint64_t u64; 1659 1659 - struct cvmx_sli_mac_credit_cnt_s { 1660 1660 - #ifdef __BIG_ENDIAN_BITFIELD 1661 1661 - uint64_t reserved_54_63:10; 1662 1662 - uint64_t p1_c_d:1; 1663 1663 - uint64_t p1_n_d:1; 1664 1664 - uint64_t p1_p_d:1; 1665 1665 - uint64_t p0_c_d:1; 1666 1666 - uint64_t p0_n_d:1; 1667 1667 - uint64_t p0_p_d:1; 1668 1668 - uint64_t p1_ccnt:8; 1669 1669 - uint64_t p1_ncnt:8; 1670 1670 - uint64_t p1_pcnt:8; 1671 1671 - uint64_t p0_ccnt:8; 1672 1672 - uint64_t p0_ncnt:8; 1673 1673 - uint64_t p0_pcnt:8; 1674 1674 - #else 1675 1675 - uint64_t p0_pcnt:8; 1676 1676 - uint64_t p0_ncnt:8; 1677 1677 - uint64_t p0_ccnt:8; 1678 1678 - uint64_t p1_pcnt:8; 1679 1679 - uint64_t p1_ncnt:8; 1680 1680 - uint64_t p1_ccnt:8; 1681 1681 - uint64_t p0_p_d:1; 1682 1682 - uint64_t p0_n_d:1; 1683 1683 - uint64_t p0_c_d:1; 1684 1684 - uint64_t p1_p_d:1; 1685 1685 - uint64_t p1_n_d:1; 1686 1686 - uint64_t p1_c_d:1; 1687 1687 - uint64_t reserved_54_63:10; 1688 1688 - #endif 1689 1689 - } s; 1690 1690 - struct cvmx_sli_mac_credit_cnt_s cn61xx; 1691 1691 - struct cvmx_sli_mac_credit_cnt_s cn63xx; 1692 1692 - struct cvmx_sli_mac_credit_cnt_cn63xxp1 { 1693 1693 - #ifdef __BIG_ENDIAN_BITFIELD 1694 1694 - uint64_t reserved_48_63:16; 1695 1695 - uint64_t p1_ccnt:8; 1696 1696 - uint64_t p1_ncnt:8; 1697 1697 - uint64_t p1_pcnt:8; 1698 1698 - uint64_t p0_ccnt:8; 1699 1699 - uint64_t p0_ncnt:8; 1700 1700 - uint64_t p0_pcnt:8; 1701 1701 - #else 1702 1702 - uint64_t p0_pcnt:8; 1703 1703 - uint64_t p0_ncnt:8; 1704 1704 - uint64_t p0_ccnt:8; 1705 1705 - uint64_t p1_pcnt:8; 1706 1706 - uint64_t p1_ncnt:8; 1707 1707 - uint64_t p1_ccnt:8; 1708 1708 - uint64_t reserved_48_63:16; 1709 1709 - #endif 1710 1710 - } cn63xxp1; 1711 1711 - struct cvmx_sli_mac_credit_cnt_s cn66xx; 1712 1712 - struct cvmx_sli_mac_credit_cnt_s cn68xx; 1713 1713 - struct cvmx_sli_mac_credit_cnt_s cn68xxp1; 1714 1714 - struct cvmx_sli_mac_credit_cnt_s cnf71xx; 1715 1715 - }; 1716 1716 - 1717 1717 - union cvmx_sli_mac_credit_cnt2 { 1718 1718 - uint64_t u64; 1719 1719 - struct cvmx_sli_mac_credit_cnt2_s { 1720 1720 - #ifdef __BIG_ENDIAN_BITFIELD 1721 1721 - uint64_t reserved_54_63:10; 1722 1722 - uint64_t p3_c_d:1; 1723 1723 - uint64_t p3_n_d:1; 1724 1724 - uint64_t p3_p_d:1; 1725 1725 - uint64_t p2_c_d:1; 1726 1726 - uint64_t p2_n_d:1; 1727 1727 - uint64_t p2_p_d:1; 1728 1728 - uint64_t p3_ccnt:8; 1729 1729 - uint64_t p3_ncnt:8; 1730 1730 - uint64_t p3_pcnt:8; 1731 1731 - uint64_t p2_ccnt:8; 1732 1732 - uint64_t p2_ncnt:8; 1733 1733 - uint64_t p2_pcnt:8; 1734 1734 - #else 1735 1735 - uint64_t p2_pcnt:8; 1736 1736 - uint64_t p2_ncnt:8; 1737 1737 - uint64_t p2_ccnt:8; 1738 1738 - uint64_t p3_pcnt:8; 1739 1739 - uint64_t p3_ncnt:8; 1740 1740 - uint64_t p3_ccnt:8; 1741 1741 - uint64_t p2_p_d:1; 1742 1742 - uint64_t p2_n_d:1; 1743 1743 - uint64_t p2_c_d:1; 1744 1744 - uint64_t p3_p_d:1; 1745 1745 - uint64_t p3_n_d:1; 1746 1746 - uint64_t p3_c_d:1; 1747 1747 - uint64_t reserved_54_63:10; 1748 1748 - #endif 1749 1749 - } s; 1750 1750 - struct cvmx_sli_mac_credit_cnt2_s cn61xx; 1751 1751 - struct cvmx_sli_mac_credit_cnt2_s cn66xx; 1752 1752 - struct cvmx_sli_mac_credit_cnt2_s cnf71xx; 1753 1753 - }; 1754 1754 - 1755 1755 - union cvmx_sli_mac_number { 1756 1756 - uint64_t u64; 1757 1757 - struct cvmx_sli_mac_number_s { 1758 1758 - #ifdef __BIG_ENDIAN_BITFIELD 1759 1759 - uint64_t reserved_9_63:55; 1760 1760 - uint64_t a_mode:1; 1761 1761 - uint64_t num:8; 1762 1762 - #else 1763 1763 - uint64_t num:8; 1764 1764 - uint64_t a_mode:1; 1765 1765 - uint64_t reserved_9_63:55; 1766 1766 - #endif 1767 1767 - } s; 1768 1768 - struct cvmx_sli_mac_number_s cn61xx; 1769 1769 - struct cvmx_sli_mac_number_cn63xx { 1770 1770 - #ifdef __BIG_ENDIAN_BITFIELD 1771 1771 - uint64_t reserved_8_63:56; 1772 1772 - uint64_t num:8; 1773 1773 - #else 1774 1774 - uint64_t num:8; 1775 1775 - uint64_t reserved_8_63:56; 1776 1776 - #endif 1777 1777 - } cn63xx; 1778 1778 - struct cvmx_sli_mac_number_s cn66xx; 1779 1779 - struct cvmx_sli_mac_number_cn63xx cn68xx; 1780 1780 - struct cvmx_sli_mac_number_cn63xx cn68xxp1; 1781 1781 - struct cvmx_sli_mac_number_s cnf71xx; 1782 76 }; 1783 77 1784 78 union cvmx_sli_mem_access_ctl { 1785 79 uint64_t u64; 1786 80 struct cvmx_sli_mem_access_ctl_s { 1787 1787 - #ifdef __BIG_ENDIAN_BITFIELD 1788 1788 - uint64_t reserved_14_63:50; 1789 1789 - uint64_t max_word:4; 1790 1790 - uint64_t timer:10; 1791 1791 - #else 1792 1792 - uint64_t timer:10; 1793 1793 - uint64_t max_word:4; 1794 1794 - uint64_t reserved_14_63:50; 1795 1795 - #endif 81 81 + __BITFIELD_FIELD(uint64_t reserved_14_63:50, 82 82 + __BITFIELD_FIELD(uint64_t max_word:4, 83 83 + __BITFIELD_FIELD(uint64_t timer:10, 84 84 + ;))) 1796 85 } s; 1797 1797 - struct cvmx_sli_mem_access_ctl_s cn61xx; 1798 1798 - struct cvmx_sli_mem_access_ctl_s cn63xx; 1799 1799 - struct cvmx_sli_mem_access_ctl_s cn63xxp1; 1800 1800 - struct cvmx_sli_mem_access_ctl_s cn66xx; 1801 1801 - struct cvmx_sli_mem_access_ctl_s cn68xx; 1802 1802 - struct cvmx_sli_mem_access_ctl_s cn68xxp1; 1803 1803 - struct cvmx_sli_mem_access_ctl_s cnf71xx; 1804 1804 - }; 1805 1805 - 1806 1806 - union cvmx_sli_mem_access_subidx { 1807 1807 - uint64_t u64; 1808 1808 - struct cvmx_sli_mem_access_subidx_s { 1809 1809 - #ifdef __BIG_ENDIAN_BITFIELD 1810 1810 - uint64_t reserved_43_63:21; 1811 1811 - uint64_t zero:1; 1812 1812 - uint64_t port:3; 1813 1813 - uint64_t nmerge:1; 1814 1814 - uint64_t esr:2; 1815 1815 - uint64_t esw:2; 1816 1816 - uint64_t wtype:2; 1817 1817 - uint64_t rtype:2; 1818 1818 - uint64_t reserved_0_29:30; 1819 1819 - #else 1820 1820 - uint64_t reserved_0_29:30; 1821 1821 - uint64_t rtype:2; 1822 1822 - uint64_t wtype:2; 1823 1823 - uint64_t esw:2; 1824 1824 - uint64_t esr:2; 1825 1825 - uint64_t nmerge:1; 1826 1826 - uint64_t port:3; 1827 1827 - uint64_t zero:1; 1828 1828 - uint64_t reserved_43_63:21; 1829 1829 - #endif 1830 1830 - } s; 1831 1831 - struct cvmx_sli_mem_access_subidx_cn61xx { 1832 1832 - #ifdef __BIG_ENDIAN_BITFIELD 1833 1833 - uint64_t reserved_43_63:21; 1834 1834 - uint64_t zero:1; 1835 1835 - uint64_t port:3; 1836 1836 - uint64_t nmerge:1; 1837 1837 - uint64_t esr:2; 1838 1838 - uint64_t esw:2; 1839 1839 - uint64_t wtype:2; 1840 1840 - uint64_t rtype:2; 1841 1841 - uint64_t ba:30; 1842 1842 - #else 1843 1843 - uint64_t ba:30; 1844 1844 - uint64_t rtype:2; 1845 1845 - uint64_t wtype:2; 1846 1846 - uint64_t esw:2; 1847 1847 - uint64_t esr:2; 1848 1848 - uint64_t nmerge:1; 1849 1849 - uint64_t port:3; 1850 1850 - uint64_t zero:1; 1851 1851 - uint64_t reserved_43_63:21; 1852 1852 - #endif 1853 1853 - } cn61xx; 1854 1854 - struct cvmx_sli_mem_access_subidx_cn61xx cn63xx; 1855 1855 - struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1; 1856 1856 - struct cvmx_sli_mem_access_subidx_cn61xx cn66xx; 1857 1857 - struct cvmx_sli_mem_access_subidx_cn68xx { 1858 1858 - #ifdef __BIG_ENDIAN_BITFIELD 1859 1859 - uint64_t reserved_43_63:21; 1860 1860 - uint64_t zero:1; 1861 1861 - uint64_t port:3; 1862 1862 - uint64_t nmerge:1; 1863 1863 - uint64_t esr:2; 1864 1864 - uint64_t esw:2; 1865 1865 - uint64_t wtype:2; 1866 1866 - uint64_t rtype:2; 1867 1867 - uint64_t ba:28; 1868 1868 - uint64_t reserved_0_1:2; 1869 1869 - #else 1870 1870 - uint64_t reserved_0_1:2; 1871 1871 - uint64_t ba:28; 1872 1872 - uint64_t rtype:2; 1873 1873 - uint64_t wtype:2; 1874 1874 - uint64_t esw:2; 1875 1875 - uint64_t esr:2; 1876 1876 - uint64_t nmerge:1; 1877 1877 - uint64_t port:3; 1878 1878 - uint64_t zero:1; 1879 1879 - uint64_t reserved_43_63:21; 1880 1880 - #endif 1881 1881 - } cn68xx; 1882 1882 - struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1; 1883 1883 - struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx; 1884 1884 - }; 1885 1885 - 1886 1886 - union cvmx_sli_msi_enb0 { 1887 1887 - uint64_t u64; 1888 1888 - struct cvmx_sli_msi_enb0_s { 1889 1889 - #ifdef __BIG_ENDIAN_BITFIELD 1890 1890 - uint64_t enb:64; 1891 1891 - #else 1892 1892 - uint64_t enb:64; 1893 1893 - #endif 1894 1894 - } s; 1895 1895 - struct cvmx_sli_msi_enb0_s cn61xx; 1896 1896 - struct cvmx_sli_msi_enb0_s cn63xx; 1897 1897 - struct cvmx_sli_msi_enb0_s cn63xxp1; 1898 1898 - struct cvmx_sli_msi_enb0_s cn66xx; 1899 1899 - struct cvmx_sli_msi_enb0_s cn68xx; 1900 1900 - struct cvmx_sli_msi_enb0_s cn68xxp1; 1901 1901 - struct cvmx_sli_msi_enb0_s cnf71xx; 1902 1902 - }; 1903 1903 - 1904 1904 - union cvmx_sli_msi_enb1 { 1905 1905 - uint64_t u64; 1906 1906 - struct cvmx_sli_msi_enb1_s { 1907 1907 - #ifdef __BIG_ENDIAN_BITFIELD 1908 1908 - uint64_t enb:64; 1909 1909 - #else 1910 1910 - uint64_t enb:64; 1911 1911 - #endif 1912 1912 - } s; 1913 1913 - struct cvmx_sli_msi_enb1_s cn61xx; 1914 1914 - struct cvmx_sli_msi_enb1_s cn63xx; 1915 1915 - struct cvmx_sli_msi_enb1_s cn63xxp1; 1916 1916 - struct cvmx_sli_msi_enb1_s cn66xx; 1917 1917 - struct cvmx_sli_msi_enb1_s cn68xx; 1918 1918 - struct cvmx_sli_msi_enb1_s cn68xxp1; 1919 1919 - struct cvmx_sli_msi_enb1_s cnf71xx; 1920 1920 - }; 1921 1921 - 1922 1922 - union cvmx_sli_msi_enb2 { 1923 1923 - uint64_t u64; 1924 1924 - struct cvmx_sli_msi_enb2_s { 1925 1925 - #ifdef __BIG_ENDIAN_BITFIELD 1926 1926 - uint64_t enb:64; 1927 1927 - #else 1928 1928 - uint64_t enb:64; 1929 1929 - #endif 1930 1930 - } s; 1931 1931 - struct cvmx_sli_msi_enb2_s cn61xx; 1932 1932 - struct cvmx_sli_msi_enb2_s cn63xx; 1933 1933 - struct cvmx_sli_msi_enb2_s cn63xxp1; 1934 1934 - struct cvmx_sli_msi_enb2_s cn66xx; 1935 1935 - struct cvmx_sli_msi_enb2_s cn68xx; 1936 1936 - struct cvmx_sli_msi_enb2_s cn68xxp1; 1937 1937 - struct cvmx_sli_msi_enb2_s cnf71xx; 1938 1938 - }; 1939 1939 - 1940 1940 - union cvmx_sli_msi_enb3 { 1941 1941 - uint64_t u64; 1942 1942 - struct cvmx_sli_msi_enb3_s { 1943 1943 - #ifdef __BIG_ENDIAN_BITFIELD 1944 1944 - uint64_t enb:64; 1945 1945 - #else 1946 1946 - uint64_t enb:64; 1947 1947 - #endif 1948 1948 - } s; 1949 1949 - struct cvmx_sli_msi_enb3_s cn61xx; 1950 1950 - struct cvmx_sli_msi_enb3_s cn63xx; 1951 1951 - struct cvmx_sli_msi_enb3_s cn63xxp1; 1952 1952 - struct cvmx_sli_msi_enb3_s cn66xx; 1953 1953 - struct cvmx_sli_msi_enb3_s cn68xx; 1954 1954 - struct cvmx_sli_msi_enb3_s cn68xxp1; 1955 1955 - struct cvmx_sli_msi_enb3_s cnf71xx; 1956 1956 - }; 1957 1957 - 1958 1958 - union cvmx_sli_msi_rcv0 { 1959 1959 - uint64_t u64; 1960 1960 - struct cvmx_sli_msi_rcv0_s { 1961 1961 - #ifdef __BIG_ENDIAN_BITFIELD 1962 1962 - uint64_t intr:64; 1963 1963 - #else 1964 1964 - uint64_t intr:64; 1965 1965 - #endif 1966 1966 - } s; 1967 1967 - struct cvmx_sli_msi_rcv0_s cn61xx; 1968 1968 - struct cvmx_sli_msi_rcv0_s cn63xx; 1969 1969 - struct cvmx_sli_msi_rcv0_s cn63xxp1; 1970 1970 - struct cvmx_sli_msi_rcv0_s cn66xx; 1971 1971 - struct cvmx_sli_msi_rcv0_s cn68xx; 1972 1972 - struct cvmx_sli_msi_rcv0_s cn68xxp1; 1973 1973 - struct cvmx_sli_msi_rcv0_s cnf71xx; 1974 1974 - }; 1975 1975 - 1976 1976 - union cvmx_sli_msi_rcv1 { 1977 1977 - uint64_t u64; 1978 1978 - struct cvmx_sli_msi_rcv1_s { 1979 1979 - #ifdef __BIG_ENDIAN_BITFIELD 1980 1980 - uint64_t intr:64; 1981 1981 - #else 1982 1982 - uint64_t intr:64; 1983 1983 - #endif 1984 1984 - } s; 1985 1985 - struct cvmx_sli_msi_rcv1_s cn61xx; 1986 1986 - struct cvmx_sli_msi_rcv1_s cn63xx; 1987 1987 - struct cvmx_sli_msi_rcv1_s cn63xxp1; 1988 1988 - struct cvmx_sli_msi_rcv1_s cn66xx; 1989 1989 - struct cvmx_sli_msi_rcv1_s cn68xx; 1990 1990 - struct cvmx_sli_msi_rcv1_s cn68xxp1; 1991 1991 - struct cvmx_sli_msi_rcv1_s cnf71xx; 1992 1992 - }; 1993 1993 - 1994 1994 - union cvmx_sli_msi_rcv2 { 1995 1995 - uint64_t u64; 1996 1996 - struct cvmx_sli_msi_rcv2_s { 1997 1997 - #ifdef __BIG_ENDIAN_BITFIELD 1998 1998 - uint64_t intr:64; 1999 1999 - #else 2000 2000 - uint64_t intr:64; 2001 2001 - #endif 2002 2002 - } s; 2003 2003 - struct cvmx_sli_msi_rcv2_s cn61xx; 2004 2004 - struct cvmx_sli_msi_rcv2_s cn63xx; 2005 2005 - struct cvmx_sli_msi_rcv2_s cn63xxp1; 2006 2006 - struct cvmx_sli_msi_rcv2_s cn66xx; 2007 2007 - struct cvmx_sli_msi_rcv2_s cn68xx; 2008 2008 - struct cvmx_sli_msi_rcv2_s cn68xxp1; 2009 2009 - struct cvmx_sli_msi_rcv2_s cnf71xx; 2010 2010 - }; 2011 2011 - 2012 2012 - union cvmx_sli_msi_rcv3 { 2013 2013 - uint64_t u64; 2014 2014 - struct cvmx_sli_msi_rcv3_s { 2015 2015 - #ifdef __BIG_ENDIAN_BITFIELD 2016 2016 - uint64_t intr:64; 2017 2017 - #else 2018 2018 - uint64_t intr:64; 2019 2019 - #endif 2020 2020 - } s; 2021 2021 - struct cvmx_sli_msi_rcv3_s cn61xx; 2022 2022 - struct cvmx_sli_msi_rcv3_s cn63xx; 2023 2023 - struct cvmx_sli_msi_rcv3_s cn63xxp1; 2024 2024 - struct cvmx_sli_msi_rcv3_s cn66xx; 2025 2025 - struct cvmx_sli_msi_rcv3_s cn68xx; 2026 2026 - struct cvmx_sli_msi_rcv3_s cn68xxp1; 2027 2027 - struct cvmx_sli_msi_rcv3_s cnf71xx; 2028 2028 - }; 2029 2029 - 2030 2030 - union cvmx_sli_msi_rd_map { 2031 2031 - uint64_t u64; 2032 2032 - struct cvmx_sli_msi_rd_map_s { 2033 2033 - #ifdef __BIG_ENDIAN_BITFIELD 2034 2034 - uint64_t reserved_16_63:48; 2035 2035 - uint64_t rd_int:8; 2036 2036 - uint64_t msi_int:8; 2037 2037 - #else 2038 2038 - uint64_t msi_int:8; 2039 2039 - uint64_t rd_int:8; 2040 2040 - uint64_t reserved_16_63:48; 2041 2041 - #endif 2042 2042 - } s; 2043 2043 - struct cvmx_sli_msi_rd_map_s cn61xx; 2044 2044 - struct cvmx_sli_msi_rd_map_s cn63xx; 2045 2045 - struct cvmx_sli_msi_rd_map_s cn63xxp1; 2046 2046 - struct cvmx_sli_msi_rd_map_s cn66xx; 2047 2047 - struct cvmx_sli_msi_rd_map_s cn68xx; 2048 2048 - struct cvmx_sli_msi_rd_map_s cn68xxp1; 2049 2049 - struct cvmx_sli_msi_rd_map_s cnf71xx; 2050 2050 - }; 2051 2051 - 2052 2052 - union cvmx_sli_msi_w1c_enb0 { 2053 2053 - uint64_t u64; 2054 2054 - struct cvmx_sli_msi_w1c_enb0_s { 2055 2055 - #ifdef __BIG_ENDIAN_BITFIELD 2056 2056 - uint64_t clr:64; 2057 2057 - #else 2058 2058 - uint64_t clr:64; 2059 2059 - #endif 2060 2060 - } s; 2061 2061 - struct cvmx_sli_msi_w1c_enb0_s cn61xx; 2062 2062 - struct cvmx_sli_msi_w1c_enb0_s cn63xx; 2063 2063 - struct cvmx_sli_msi_w1c_enb0_s cn63xxp1; 2064 2064 - struct cvmx_sli_msi_w1c_enb0_s cn66xx; 2065 2065 - struct cvmx_sli_msi_w1c_enb0_s cn68xx; 2066 2066 - struct cvmx_sli_msi_w1c_enb0_s cn68xxp1; 2067 2067 - struct cvmx_sli_msi_w1c_enb0_s cnf71xx; 2068 2068 - }; 2069 2069 - 2070 2070 - union cvmx_sli_msi_w1c_enb1 { 2071 2071 - uint64_t u64; 2072 2072 - struct cvmx_sli_msi_w1c_enb1_s { 2073 2073 - #ifdef __BIG_ENDIAN_BITFIELD 2074 2074 - uint64_t clr:64; 2075 2075 - #else 2076 2076 - uint64_t clr:64; 2077 2077 - #endif 2078 2078 - } s; 2079 2079 - struct cvmx_sli_msi_w1c_enb1_s cn61xx; 2080 2080 - struct cvmx_sli_msi_w1c_enb1_s cn63xx; 2081 2081 - struct cvmx_sli_msi_w1c_enb1_s cn63xxp1; 2082 2082 - struct cvmx_sli_msi_w1c_enb1_s cn66xx; 2083 2083 - struct cvmx_sli_msi_w1c_enb1_s cn68xx; 2084 2084 - struct cvmx_sli_msi_w1c_enb1_s cn68xxp1; 2085 2085 - struct cvmx_sli_msi_w1c_enb1_s cnf71xx; 2086 2086 - }; 2087 2087 - 2088 2088 - union cvmx_sli_msi_w1c_enb2 { 2089 2089 - uint64_t u64; 2090 2090 - struct cvmx_sli_msi_w1c_enb2_s { 2091 2091 - #ifdef __BIG_ENDIAN_BITFIELD 2092 2092 - uint64_t clr:64; 2093 2093 - #else 2094 2094 - uint64_t clr:64; 2095 2095 - #endif 2096 2096 - } s; 2097 2097 - struct cvmx_sli_msi_w1c_enb2_s cn61xx; 2098 2098 - struct cvmx_sli_msi_w1c_enb2_s cn63xx; 2099 2099 - struct cvmx_sli_msi_w1c_enb2_s cn63xxp1; 2100 2100 - struct cvmx_sli_msi_w1c_enb2_s cn66xx; 2101 2101 - struct cvmx_sli_msi_w1c_enb2_s cn68xx; 2102 2102 - struct cvmx_sli_msi_w1c_enb2_s cn68xxp1; 2103 2103 - struct cvmx_sli_msi_w1c_enb2_s cnf71xx; 2104 2104 - }; 2105 2105 - 2106 2106 - union cvmx_sli_msi_w1c_enb3 { 2107 2107 - uint64_t u64; 2108 2108 - struct cvmx_sli_msi_w1c_enb3_s { 2109 2109 - #ifdef __BIG_ENDIAN_BITFIELD 2110 2110 - uint64_t clr:64; 2111 2111 - #else 2112 2112 - uint64_t clr:64; 2113 2113 - #endif 2114 2114 - } s; 2115 2115 - struct cvmx_sli_msi_w1c_enb3_s cn61xx; 2116 2116 - struct cvmx_sli_msi_w1c_enb3_s cn63xx; 2117 2117 - struct cvmx_sli_msi_w1c_enb3_s cn63xxp1; 2118 2118 - struct cvmx_sli_msi_w1c_enb3_s cn66xx; 2119 2119 - struct cvmx_sli_msi_w1c_enb3_s cn68xx; 2120 2120 - struct cvmx_sli_msi_w1c_enb3_s cn68xxp1; 2121 2121 - struct cvmx_sli_msi_w1c_enb3_s cnf71xx; 2122 2122 - }; 2123 2123 - 2124 2124 - union cvmx_sli_msi_w1s_enb0 { 2125 2125 - uint64_t u64; 2126 2126 - struct cvmx_sli_msi_w1s_enb0_s { 2127 2127 - #ifdef __BIG_ENDIAN_BITFIELD 2128 2128 - uint64_t set:64; 2129 2129 - #else 2130 2130 - uint64_t set:64; 2131 2131 - #endif 2132 2132 - } s; 2133 2133 - struct cvmx_sli_msi_w1s_enb0_s cn61xx; 2134 2134 - struct cvmx_sli_msi_w1s_enb0_s cn63xx; 2135 2135 - struct cvmx_sli_msi_w1s_enb0_s cn63xxp1; 2136 2136 - struct cvmx_sli_msi_w1s_enb0_s cn66xx; 2137 2137 - struct cvmx_sli_msi_w1s_enb0_s cn68xx; 2138 2138 - struct cvmx_sli_msi_w1s_enb0_s cn68xxp1; 2139 2139 - struct cvmx_sli_msi_w1s_enb0_s cnf71xx; 2140 2140 - }; 2141 2141 - 2142 2142 - union cvmx_sli_msi_w1s_enb1 { 2143 2143 - uint64_t u64; 2144 2144 - struct cvmx_sli_msi_w1s_enb1_s { 2145 2145 - #ifdef __BIG_ENDIAN_BITFIELD 2146 2146 - uint64_t set:64; 2147 2147 - #else 2148 2148 - uint64_t set:64; 2149 2149 - #endif 2150 2150 - } s; 2151 2151 - struct cvmx_sli_msi_w1s_enb1_s cn61xx; 2152 2152 - struct cvmx_sli_msi_w1s_enb1_s cn63xx; 2153 2153 - struct cvmx_sli_msi_w1s_enb1_s cn63xxp1; 2154 2154 - struct cvmx_sli_msi_w1s_enb1_s cn66xx; 2155 2155 - struct cvmx_sli_msi_w1s_enb1_s cn68xx; 2156 2156 - struct cvmx_sli_msi_w1s_enb1_s cn68xxp1; 2157 2157 - struct cvmx_sli_msi_w1s_enb1_s cnf71xx; 2158 2158 - }; 2159 2159 - 2160 2160 - union cvmx_sli_msi_w1s_enb2 { 2161 2161 - uint64_t u64; 2162 2162 - struct cvmx_sli_msi_w1s_enb2_s { 2163 2163 - #ifdef __BIG_ENDIAN_BITFIELD 2164 2164 - uint64_t set:64; 2165 2165 - #else 2166 2166 - uint64_t set:64; 2167 2167 - #endif 2168 2168 - } s; 2169 2169 - struct cvmx_sli_msi_w1s_enb2_s cn61xx; 2170 2170 - struct cvmx_sli_msi_w1s_enb2_s cn63xx; 2171 2171 - struct cvmx_sli_msi_w1s_enb2_s cn63xxp1; 2172 2172 - struct cvmx_sli_msi_w1s_enb2_s cn66xx; 2173 2173 - struct cvmx_sli_msi_w1s_enb2_s cn68xx; 2174 2174 - struct cvmx_sli_msi_w1s_enb2_s cn68xxp1; 2175 2175 - struct cvmx_sli_msi_w1s_enb2_s cnf71xx; 2176 2176 - }; 2177 2177 - 2178 2178 - union cvmx_sli_msi_w1s_enb3 { 2179 2179 - uint64_t u64; 2180 2180 - struct cvmx_sli_msi_w1s_enb3_s { 2181 2181 - #ifdef __BIG_ENDIAN_BITFIELD 2182 2182 - uint64_t set:64; 2183 2183 - #else 2184 2184 - uint64_t set:64; 2185 2185 - #endif 2186 2186 - } s; 2187 2187 - struct cvmx_sli_msi_w1s_enb3_s cn61xx; 2188 2188 - struct cvmx_sli_msi_w1s_enb3_s cn63xx; 2189 2189 - struct cvmx_sli_msi_w1s_enb3_s cn63xxp1; 2190 2190 - struct cvmx_sli_msi_w1s_enb3_s cn66xx; 2191 2191 - struct cvmx_sli_msi_w1s_enb3_s cn68xx; 2192 2192 - struct cvmx_sli_msi_w1s_enb3_s cn68xxp1; 2193 2193 - struct cvmx_sli_msi_w1s_enb3_s cnf71xx; 2194 2194 - }; 2195 2195 - 2196 2196 - union cvmx_sli_msi_wr_map { 2197 2197 - uint64_t u64; 2198 2198 - struct cvmx_sli_msi_wr_map_s { 2199 2199 - #ifdef __BIG_ENDIAN_BITFIELD 2200 2200 - uint64_t reserved_16_63:48; 2201 2201 - uint64_t ciu_int:8; 2202 2202 - uint64_t msi_int:8; 2203 2203 - #else 2204 2204 - uint64_t msi_int:8; 2205 2205 - uint64_t ciu_int:8; 2206 2206 - uint64_t reserved_16_63:48; 2207 2207 - #endif 2208 2208 - } s; 2209 2209 - struct cvmx_sli_msi_wr_map_s cn61xx; 2210 2210 - struct cvmx_sli_msi_wr_map_s cn63xx; 2211 2211 - struct cvmx_sli_msi_wr_map_s cn63xxp1; 2212 2212 - struct cvmx_sli_msi_wr_map_s cn66xx; 2213 2213 - struct cvmx_sli_msi_wr_map_s cn68xx; 2214 2214 - struct cvmx_sli_msi_wr_map_s cn68xxp1; 2215 2215 - struct cvmx_sli_msi_wr_map_s cnf71xx; 2216 2216 - }; 2217 2217 - 2218 2218 - union cvmx_sli_pcie_msi_rcv { 2219 2219 - uint64_t u64; 2220 2220 - struct cvmx_sli_pcie_msi_rcv_s { 2221 2221 - #ifdef __BIG_ENDIAN_BITFIELD 2222 2222 - uint64_t reserved_8_63:56; 2223 2223 - uint64_t intr:8; 2224 2224 - #else 2225 2225 - uint64_t intr:8; 2226 2226 - uint64_t reserved_8_63:56; 2227 2227 - #endif 2228 2228 - } s; 2229 2229 - struct cvmx_sli_pcie_msi_rcv_s cn61xx; 2230 2230 - struct cvmx_sli_pcie_msi_rcv_s cn63xx; 2231 2231 - struct cvmx_sli_pcie_msi_rcv_s cn63xxp1; 2232 2232 - struct cvmx_sli_pcie_msi_rcv_s cn66xx; 2233 2233 - struct cvmx_sli_pcie_msi_rcv_s cn68xx; 2234 2234 - struct cvmx_sli_pcie_msi_rcv_s cn68xxp1; 2235 2235 - struct cvmx_sli_pcie_msi_rcv_s cnf71xx; 2236 2236 - }; 2237 2237 - 2238 2238 - union cvmx_sli_pcie_msi_rcv_b1 { 2239 2239 - uint64_t u64; 2240 2240 - struct cvmx_sli_pcie_msi_rcv_b1_s { 2241 2241 - #ifdef __BIG_ENDIAN_BITFIELD 2242 2242 - uint64_t reserved_16_63:48; 2243 2243 - uint64_t intr:8; 2244 2244 - uint64_t reserved_0_7:8; 2245 2245 - #else 2246 2246 - uint64_t reserved_0_7:8; 2247 2247 - uint64_t intr:8; 2248 2248 - uint64_t reserved_16_63:48; 2249 2249 - #endif 2250 2250 - } s; 2251 2251 - struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx; 2252 2252 - struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; 2253 2253 - struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1; 2254 2254 - struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx; 2255 2255 - struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx; 2256 2256 - struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1; 2257 2257 - struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx; 2258 2258 - }; 2259 2259 - 2260 2260 - union cvmx_sli_pcie_msi_rcv_b2 { 2261 2261 - uint64_t u64; 2262 2262 - struct cvmx_sli_pcie_msi_rcv_b2_s { 2263 2263 - #ifdef __BIG_ENDIAN_BITFIELD 2264 2264 - uint64_t reserved_24_63:40; 2265 2265 - uint64_t intr:8; 2266 2266 - uint64_t reserved_0_15:16; 2267 2267 - #else 2268 2268 - uint64_t reserved_0_15:16; 2269 2269 - uint64_t intr:8; 2270 2270 - uint64_t reserved_24_63:40; 2271 2271 - #endif 2272 2272 - } s; 2273 2273 - struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx; 2274 2274 - struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; 2275 2275 - struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1; 2276 2276 - struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx; 2277 2277 - struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx; 2278 2278 - struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1; 2279 2279 - struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx; 2280 2280 - }; 2281 2281 - 2282 2282 - union cvmx_sli_pcie_msi_rcv_b3 { 2283 2283 - uint64_t u64; 2284 2284 - struct cvmx_sli_pcie_msi_rcv_b3_s { 2285 2285 - #ifdef __BIG_ENDIAN_BITFIELD 2286 2286 - uint64_t reserved_32_63:32; 2287 2287 - uint64_t intr:8; 2288 2288 - uint64_t reserved_0_23:24; 2289 2289 - #else 2290 2290 - uint64_t reserved_0_23:24; 2291 2291 - uint64_t intr:8; 2292 2292 - uint64_t reserved_32_63:32; 2293 2293 - #endif 2294 2294 - } s; 2295 2295 - struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx; 2296 2296 - struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; 2297 2297 - struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1; 2298 2298 - struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx; 2299 2299 - struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx; 2300 2300 - struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1; 2301 2301 - struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx; 2302 2302 - }; 2303 2303 - 2304 2304 - union cvmx_sli_pktx_cnts { 2305 2305 - uint64_t u64; 2306 2306 - struct cvmx_sli_pktx_cnts_s { 2307 2307 - #ifdef __BIG_ENDIAN_BITFIELD 2308 2308 - uint64_t reserved_54_63:10; 2309 2309 - uint64_t timer:22; 2310 2310 - uint64_t cnt:32; 2311 2311 - #else 2312 2312 - uint64_t cnt:32; 2313 2313 - uint64_t timer:22; 2314 2314 - uint64_t reserved_54_63:10; 2315 2315 - #endif 2316 2316 - } s; 2317 2317 - struct cvmx_sli_pktx_cnts_s cn61xx; 2318 2318 - struct cvmx_sli_pktx_cnts_s cn63xx; 2319 2319 - struct cvmx_sli_pktx_cnts_s cn63xxp1; 2320 2320 - struct cvmx_sli_pktx_cnts_s cn66xx; 2321 2321 - struct cvmx_sli_pktx_cnts_s cn68xx; 2322 2322 - struct cvmx_sli_pktx_cnts_s cn68xxp1; 2323 2323 - struct cvmx_sli_pktx_cnts_s cnf71xx; 2324 2324 - }; 2325 2325 - 2326 2326 - union cvmx_sli_pktx_in_bp { 2327 2327 - uint64_t u64; 2328 2328 - struct cvmx_sli_pktx_in_bp_s { 2329 2329 - #ifdef __BIG_ENDIAN_BITFIELD 2330 2330 - uint64_t wmark:32; 2331 2331 - uint64_t cnt:32; 2332 2332 - #else 2333 2333 - uint64_t cnt:32; 2334 2334 - uint64_t wmark:32; 2335 2335 - #endif 2336 2336 - } s; 2337 2337 - struct cvmx_sli_pktx_in_bp_s cn61xx; 2338 2338 - struct cvmx_sli_pktx_in_bp_s cn63xx; 2339 2339 - struct cvmx_sli_pktx_in_bp_s cn63xxp1; 2340 2340 - struct cvmx_sli_pktx_in_bp_s cn66xx; 2341 2341 - struct cvmx_sli_pktx_in_bp_s cnf71xx; 2342 2342 - }; 2343 2343 - 2344 2344 - union cvmx_sli_pktx_instr_baddr { 2345 2345 - uint64_t u64; 2346 2346 - struct cvmx_sli_pktx_instr_baddr_s { 2347 2347 - #ifdef __BIG_ENDIAN_BITFIELD 2348 2348 - uint64_t addr:61; 2349 2349 - uint64_t reserved_0_2:3; 2350 2350 - #else 2351 2351 - uint64_t reserved_0_2:3; 2352 2352 - uint64_t addr:61; 2353 2353 - #endif 2354 2354 - } s; 2355 2355 - struct cvmx_sli_pktx_instr_baddr_s cn61xx; 2356 2356 - struct cvmx_sli_pktx_instr_baddr_s cn63xx; 2357 2357 - struct cvmx_sli_pktx_instr_baddr_s cn63xxp1; 2358 2358 - struct cvmx_sli_pktx_instr_baddr_s cn66xx; 2359 2359 - struct cvmx_sli_pktx_instr_baddr_s cn68xx; 2360 2360 - struct cvmx_sli_pktx_instr_baddr_s cn68xxp1; 2361 2361 - struct cvmx_sli_pktx_instr_baddr_s cnf71xx; 2362 2362 - }; 2363 2363 - 2364 2364 - union cvmx_sli_pktx_instr_baoff_dbell { 2365 2365 - uint64_t u64; 2366 2366 - struct cvmx_sli_pktx_instr_baoff_dbell_s { 2367 2367 - #ifdef __BIG_ENDIAN_BITFIELD 2368 2368 - uint64_t aoff:32; 2369 2369 - uint64_t dbell:32; 2370 2370 - #else 2371 2371 - uint64_t dbell:32; 2372 2372 - uint64_t aoff:32; 2373 2373 - #endif 2374 2374 - } s; 2375 2375 - struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx; 2376 2376 - struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; 2377 2377 - struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1; 2378 2378 - struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx; 2379 2379 - struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx; 2380 2380 - struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1; 2381 2381 - struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx; 2382 2382 - }; 2383 2383 - 2384 2384 - union cvmx_sli_pktx_instr_fifo_rsize { 2385 2385 - uint64_t u64; 2386 2386 - struct cvmx_sli_pktx_instr_fifo_rsize_s { 2387 2387 - #ifdef __BIG_ENDIAN_BITFIELD 2388 2388 - uint64_t max:9; 2389 2389 - uint64_t rrp:9; 2390 2390 - uint64_t wrp:9; 2391 2391 - uint64_t fcnt:5; 2392 2392 - uint64_t rsize:32; 2393 2393 - #else 2394 2394 - uint64_t rsize:32; 2395 2395 - uint64_t fcnt:5; 2396 2396 - uint64_t wrp:9; 2397 2397 - uint64_t rrp:9; 2398 2398 - uint64_t max:9; 2399 2399 - #endif 2400 2400 - } s; 2401 2401 - struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx; 2402 2402 - struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; 2403 2403 - struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1; 2404 2404 - struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx; 2405 2405 - struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx; 2406 2406 - struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1; 2407 2407 - struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx; 2408 2408 - }; 2409 2409 - 2410 2410 - union cvmx_sli_pktx_instr_header { 2411 2411 - uint64_t u64; 2412 2412 - struct cvmx_sli_pktx_instr_header_s { 2413 2413 - #ifdef __BIG_ENDIAN_BITFIELD 2414 2414 - uint64_t reserved_44_63:20; 2415 2415 - uint64_t pbp:1; 2416 2416 - uint64_t reserved_38_42:5; 2417 2417 - uint64_t rparmode:2; 2418 2418 - uint64_t reserved_35_35:1; 2419 2419 - uint64_t rskp_len:7; 2420 2420 - uint64_t rngrpext:2; 2421 2421 - uint64_t rnqos:1; 2422 2422 - uint64_t rngrp:1; 2423 2423 - uint64_t rntt:1; 2424 2424 - uint64_t rntag:1; 2425 2425 - uint64_t use_ihdr:1; 2426 2426 - uint64_t reserved_16_20:5; 2427 2427 - uint64_t par_mode:2; 2428 2428 - uint64_t reserved_13_13:1; 2429 2429 - uint64_t skp_len:7; 2430 2430 - uint64_t ngrpext:2; 2431 2431 - uint64_t nqos:1; 2432 2432 - uint64_t ngrp:1; 2433 2433 - uint64_t ntt:1; 2434 2434 - uint64_t ntag:1; 2435 2435 - #else 2436 2436 - uint64_t ntag:1; 2437 2437 - uint64_t ntt:1; 2438 2438 - uint64_t ngrp:1; 2439 2439 - uint64_t nqos:1; 2440 2440 - uint64_t ngrpext:2; 2441 2441 - uint64_t skp_len:7; 2442 2442 - uint64_t reserved_13_13:1; 2443 2443 - uint64_t par_mode:2; 2444 2444 - uint64_t reserved_16_20:5; 2445 2445 - uint64_t use_ihdr:1; 2446 2446 - uint64_t rntag:1; 2447 2447 - uint64_t rntt:1; 2448 2448 - uint64_t rngrp:1; 2449 2449 - uint64_t rnqos:1; 2450 2450 - uint64_t rngrpext:2; 2451 2451 - uint64_t rskp_len:7; 2452 2452 - uint64_t reserved_35_35:1; 2453 2453 - uint64_t rparmode:2; 2454 2454 - uint64_t reserved_38_42:5; 2455 2455 - uint64_t pbp:1; 2456 2456 - uint64_t reserved_44_63:20; 2457 2457 - #endif 2458 2458 - } s; 2459 2459 - struct cvmx_sli_pktx_instr_header_cn61xx { 2460 2460 - #ifdef __BIG_ENDIAN_BITFIELD 2461 2461 - uint64_t reserved_44_63:20; 2462 2462 - uint64_t pbp:1; 2463 2463 - uint64_t reserved_38_42:5; 2464 2464 - uint64_t rparmode:2; 2465 2465 - uint64_t reserved_35_35:1; 2466 2466 - uint64_t rskp_len:7; 2467 2467 - uint64_t reserved_26_27:2; 2468 2468 - uint64_t rnqos:1; 2469 2469 - uint64_t rngrp:1; 2470 2470 - uint64_t rntt:1; 2471 2471 - uint64_t rntag:1; 2472 2472 - uint64_t use_ihdr:1; 2473 2473 - uint64_t reserved_16_20:5; 2474 2474 - uint64_t par_mode:2; 2475 2475 - uint64_t reserved_13_13:1; 2476 2476 - uint64_t skp_len:7; 2477 2477 - uint64_t reserved_4_5:2; 2478 2478 - uint64_t nqos:1; 2479 2479 - uint64_t ngrp:1; 2480 2480 - uint64_t ntt:1; 2481 2481 - uint64_t ntag:1; 2482 2482 - #else 2483 2483 - uint64_t ntag:1; 2484 2484 - uint64_t ntt:1; 2485 2485 - uint64_t ngrp:1; 2486 2486 - uint64_t nqos:1; 2487 2487 - uint64_t reserved_4_5:2; 2488 2488 - uint64_t skp_len:7; 2489 2489 - uint64_t reserved_13_13:1; 2490 2490 - uint64_t par_mode:2; 2491 2491 - uint64_t reserved_16_20:5; 2492 2492 - uint64_t use_ihdr:1; 2493 2493 - uint64_t rntag:1; 2494 2494 - uint64_t rntt:1; 2495 2495 - uint64_t rngrp:1; 2496 2496 - uint64_t rnqos:1; 2497 2497 - uint64_t reserved_26_27:2; 2498 2498 - uint64_t rskp_len:7; 2499 2499 - uint64_t reserved_35_35:1; 2500 2500 - uint64_t rparmode:2; 2501 2501 - uint64_t reserved_38_42:5; 2502 2502 - uint64_t pbp:1; 2503 2503 - uint64_t reserved_44_63:20; 2504 2504 - #endif 2505 2505 - } cn61xx; 2506 2506 - struct cvmx_sli_pktx_instr_header_cn61xx cn63xx; 2507 2507 - struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1; 2508 2508 - struct cvmx_sli_pktx_instr_header_cn61xx cn66xx; 2509 2509 - struct cvmx_sli_pktx_instr_header_s cn68xx; 2510 2510 - struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1; 2511 2511 - struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx; 2512 2512 - }; 2513 2513 - 2514 2514 - union cvmx_sli_pktx_out_size { 2515 2515 - uint64_t u64; 2516 2516 - struct cvmx_sli_pktx_out_size_s { 2517 2517 - #ifdef __BIG_ENDIAN_BITFIELD 2518 2518 - uint64_t reserved_23_63:41; 2519 2519 - uint64_t isize:7; 2520 2520 - uint64_t bsize:16; 2521 2521 - #else 2522 2522 - uint64_t bsize:16; 2523 2523 - uint64_t isize:7; 2524 2524 - uint64_t reserved_23_63:41; 2525 2525 - #endif 2526 2526 - } s; 2527 2527 - struct cvmx_sli_pktx_out_size_s cn61xx; 2528 2528 - struct cvmx_sli_pktx_out_size_s cn63xx; 2529 2529 - struct cvmx_sli_pktx_out_size_s cn63xxp1; 2530 2530 - struct cvmx_sli_pktx_out_size_s cn66xx; 2531 2531 - struct cvmx_sli_pktx_out_size_s cn68xx; 2532 2532 - struct cvmx_sli_pktx_out_size_s cn68xxp1; 2533 2533 - struct cvmx_sli_pktx_out_size_s cnf71xx; 2534 2534 - }; 2535 2535 - 2536 2536 - union cvmx_sli_pktx_slist_baddr { 2537 2537 - uint64_t u64; 2538 2538 - struct cvmx_sli_pktx_slist_baddr_s { 2539 2539 - #ifdef __BIG_ENDIAN_BITFIELD 2540 2540 - uint64_t addr:60; 2541 2541 - uint64_t reserved_0_3:4; 2542 2542 - #else 2543 2543 - uint64_t reserved_0_3:4; 2544 2544 - uint64_t addr:60; 2545 2545 - #endif 2546 2546 - } s; 2547 2547 - struct cvmx_sli_pktx_slist_baddr_s cn61xx; 2548 2548 - struct cvmx_sli_pktx_slist_baddr_s cn63xx; 2549 2549 - struct cvmx_sli_pktx_slist_baddr_s cn63xxp1; 2550 2550 - struct cvmx_sli_pktx_slist_baddr_s cn66xx; 2551 2551 - struct cvmx_sli_pktx_slist_baddr_s cn68xx; 2552 2552 - struct cvmx_sli_pktx_slist_baddr_s cn68xxp1; 2553 2553 - struct cvmx_sli_pktx_slist_baddr_s cnf71xx; 2554 2554 - }; 2555 2555 - 2556 2556 - union cvmx_sli_pktx_slist_baoff_dbell { 2557 2557 - uint64_t u64; 2558 2558 - struct cvmx_sli_pktx_slist_baoff_dbell_s { 2559 2559 - #ifdef __BIG_ENDIAN_BITFIELD 2560 2560 - uint64_t aoff:32; 2561 2561 - uint64_t dbell:32; 2562 2562 - #else 2563 2563 - uint64_t dbell:32; 2564 2564 - uint64_t aoff:32; 2565 2565 - #endif 2566 2566 - } s; 2567 2567 - struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx; 2568 2568 - struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; 2569 2569 - struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1; 2570 2570 - struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx; 2571 2571 - struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx; 2572 2572 - struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1; 2573 2573 - struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx; 2574 2574 - }; 2575 2575 - 2576 2576 - union cvmx_sli_pktx_slist_fifo_rsize { 2577 2577 - uint64_t u64; 2578 2578 - struct cvmx_sli_pktx_slist_fifo_rsize_s { 2579 2579 - #ifdef __BIG_ENDIAN_BITFIELD 2580 2580 - uint64_t reserved_32_63:32; 2581 2581 - uint64_t rsize:32; 2582 2582 - #else 2583 2583 - uint64_t rsize:32; 2584 2584 - uint64_t reserved_32_63:32; 2585 2585 - #endif 2586 2586 - } s; 2587 2587 - struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx; 2588 2588 - struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; 2589 2589 - struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1; 2590 2590 - struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx; 2591 2591 - struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx; 2592 2592 - struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1; 2593 2593 - struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx; 2594 2594 - }; 2595 2595 - 2596 2596 - union cvmx_sli_pkt_cnt_int { 2597 2597 - uint64_t u64; 2598 2598 - struct cvmx_sli_pkt_cnt_int_s { 2599 2599 - #ifdef __BIG_ENDIAN_BITFIELD 2600 2600 - uint64_t reserved_32_63:32; 2601 2601 - uint64_t port:32; 2602 2602 - #else 2603 2603 - uint64_t port:32; 2604 2604 - uint64_t reserved_32_63:32; 2605 2605 - #endif 2606 2606 - } s; 2607 2607 - struct cvmx_sli_pkt_cnt_int_s cn61xx; 2608 2608 - struct cvmx_sli_pkt_cnt_int_s cn63xx; 2609 2609 - struct cvmx_sli_pkt_cnt_int_s cn63xxp1; 2610 2610 - struct cvmx_sli_pkt_cnt_int_s cn66xx; 2611 2611 - struct cvmx_sli_pkt_cnt_int_s cn68xx; 2612 2612 - struct cvmx_sli_pkt_cnt_int_s cn68xxp1; 2613 2613 - struct cvmx_sli_pkt_cnt_int_s cnf71xx; 2614 2614 - }; 2615 2615 - 2616 2616 - union cvmx_sli_pkt_cnt_int_enb { 2617 2617 - uint64_t u64; 2618 2618 - struct cvmx_sli_pkt_cnt_int_enb_s { 2619 2619 - #ifdef __BIG_ENDIAN_BITFIELD 2620 2620 - uint64_t reserved_32_63:32; 2621 2621 - uint64_t port:32; 2622 2622 - #else 2623 2623 - uint64_t port:32; 2624 2624 - uint64_t reserved_32_63:32; 2625 2625 - #endif 2626 2626 - } s; 2627 2627 - struct cvmx_sli_pkt_cnt_int_enb_s cn61xx; 2628 2628 - struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; 2629 2629 - struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1; 2630 2630 - struct cvmx_sli_pkt_cnt_int_enb_s cn66xx; 2631 2631 - struct cvmx_sli_pkt_cnt_int_enb_s cn68xx; 2632 2632 - struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1; 2633 2633 - struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx; 2634 2634 - }; 2635 2635 - 2636 2636 - union cvmx_sli_pkt_ctl { 2637 2637 - uint64_t u64; 2638 2638 - struct cvmx_sli_pkt_ctl_s { 2639 2639 - #ifdef __BIG_ENDIAN_BITFIELD 2640 2640 - uint64_t reserved_5_63:59; 2641 2641 - uint64_t ring_en:1; 2642 2642 - uint64_t pkt_bp:4; 2643 2643 - #else 2644 2644 - uint64_t pkt_bp:4; 2645 2645 - uint64_t ring_en:1; 2646 2646 - uint64_t reserved_5_63:59; 2647 2647 - #endif 2648 2648 - } s; 2649 2649 - struct cvmx_sli_pkt_ctl_s cn61xx; 2650 2650 - struct cvmx_sli_pkt_ctl_s cn63xx; 2651 2651 - struct cvmx_sli_pkt_ctl_s cn63xxp1; 2652 2652 - struct cvmx_sli_pkt_ctl_s cn66xx; 2653 2653 - struct cvmx_sli_pkt_ctl_s cn68xx; 2654 2654 - struct cvmx_sli_pkt_ctl_s cn68xxp1; 2655 2655 - struct cvmx_sli_pkt_ctl_s cnf71xx; 2656 2656 - }; 2657 2657 - 2658 2658 - union cvmx_sli_pkt_data_out_es { 2659 2659 - uint64_t u64; 2660 2660 - struct cvmx_sli_pkt_data_out_es_s { 2661 2661 - #ifdef __BIG_ENDIAN_BITFIELD 2662 2662 - uint64_t es:64; 2663 2663 - #else 2664 2664 - uint64_t es:64; 2665 2665 - #endif 2666 2666 - } s; 2667 2667 - struct cvmx_sli_pkt_data_out_es_s cn61xx; 2668 2668 - struct cvmx_sli_pkt_data_out_es_s cn63xx; 2669 2669 - struct cvmx_sli_pkt_data_out_es_s cn63xxp1; 2670 2670 - struct cvmx_sli_pkt_data_out_es_s cn66xx; 2671 2671 - struct cvmx_sli_pkt_data_out_es_s cn68xx; 2672 2672 - struct cvmx_sli_pkt_data_out_es_s cn68xxp1; 2673 2673 - struct cvmx_sli_pkt_data_out_es_s cnf71xx; 2674 2674 - }; 2675 2675 - 2676 2676 - union cvmx_sli_pkt_data_out_ns { 2677 2677 - uint64_t u64; 2678 2678 - struct cvmx_sli_pkt_data_out_ns_s { 2679 2679 - #ifdef __BIG_ENDIAN_BITFIELD 2680 2680 - uint64_t reserved_32_63:32; 2681 2681 - uint64_t nsr:32; 2682 2682 - #else 2683 2683 - uint64_t nsr:32; 2684 2684 - uint64_t reserved_32_63:32; 2685 2685 - #endif 2686 2686 - } s; 2687 2687 - struct cvmx_sli_pkt_data_out_ns_s cn61xx; 2688 2688 - struct cvmx_sli_pkt_data_out_ns_s cn63xx; 2689 2689 - struct cvmx_sli_pkt_data_out_ns_s cn63xxp1; 2690 2690 - struct cvmx_sli_pkt_data_out_ns_s cn66xx; 2691 2691 - struct cvmx_sli_pkt_data_out_ns_s cn68xx; 2692 2692 - struct cvmx_sli_pkt_data_out_ns_s cn68xxp1; 2693 2693 - struct cvmx_sli_pkt_data_out_ns_s cnf71xx; 2694 2694 - }; 2695 2695 - 2696 2696 - union cvmx_sli_pkt_data_out_ror { 2697 2697 - uint64_t u64; 2698 2698 - struct cvmx_sli_pkt_data_out_ror_s { 2699 2699 - #ifdef __BIG_ENDIAN_BITFIELD 2700 2700 - uint64_t reserved_32_63:32; 2701 2701 - uint64_t ror:32; 2702 2702 - #else 2703 2703 - uint64_t ror:32; 2704 2704 - uint64_t reserved_32_63:32; 2705 2705 - #endif 2706 2706 - } s; 2707 2707 - struct cvmx_sli_pkt_data_out_ror_s cn61xx; 2708 2708 - struct cvmx_sli_pkt_data_out_ror_s cn63xx; 2709 2709 - struct cvmx_sli_pkt_data_out_ror_s cn63xxp1; 2710 2710 - struct cvmx_sli_pkt_data_out_ror_s cn66xx; 2711 2711 - struct cvmx_sli_pkt_data_out_ror_s cn68xx; 2712 2712 - struct cvmx_sli_pkt_data_out_ror_s cn68xxp1; 2713 2713 - struct cvmx_sli_pkt_data_out_ror_s cnf71xx; 2714 2714 - }; 2715 2715 - 2716 2716 - union cvmx_sli_pkt_dpaddr { 2717 2717 - uint64_t u64; 2718 2718 - struct cvmx_sli_pkt_dpaddr_s { 2719 2719 - #ifdef __BIG_ENDIAN_BITFIELD 2720 2720 - uint64_t reserved_32_63:32; 2721 2721 - uint64_t dptr:32; 2722 2722 - #else 2723 2723 - uint64_t dptr:32; 2724 2724 - uint64_t reserved_32_63:32; 2725 2725 - #endif 2726 2726 - } s; 2727 2727 - struct cvmx_sli_pkt_dpaddr_s cn61xx; 2728 2728 - struct cvmx_sli_pkt_dpaddr_s cn63xx; 2729 2729 - struct cvmx_sli_pkt_dpaddr_s cn63xxp1; 2730 2730 - struct cvmx_sli_pkt_dpaddr_s cn66xx; 2731 2731 - struct cvmx_sli_pkt_dpaddr_s cn68xx; 2732 2732 - struct cvmx_sli_pkt_dpaddr_s cn68xxp1; 2733 2733 - struct cvmx_sli_pkt_dpaddr_s cnf71xx; 2734 2734 - }; 2735 2735 - 2736 2736 - union cvmx_sli_pkt_in_bp { 2737 2737 - uint64_t u64; 2738 2738 - struct cvmx_sli_pkt_in_bp_s { 2739 2739 - #ifdef __BIG_ENDIAN_BITFIELD 2740 2740 - uint64_t reserved_32_63:32; 2741 2741 - uint64_t bp:32; 2742 2742 - #else 2743 2743 - uint64_t bp:32; 2744 2744 - uint64_t reserved_32_63:32; 2745 2745 - #endif 2746 2746 - } s; 2747 2747 - struct cvmx_sli_pkt_in_bp_s cn61xx; 2748 2748 - struct cvmx_sli_pkt_in_bp_s cn63xx; 2749 2749 - struct cvmx_sli_pkt_in_bp_s cn63xxp1; 2750 2750 - struct cvmx_sli_pkt_in_bp_s cn66xx; 2751 2751 - struct cvmx_sli_pkt_in_bp_s cnf71xx; 2752 2752 - }; 2753 2753 - 2754 2754 - union cvmx_sli_pkt_in_donex_cnts { 2755 2755 - uint64_t u64; 2756 2756 - struct cvmx_sli_pkt_in_donex_cnts_s { 2757 2757 - #ifdef __BIG_ENDIAN_BITFIELD 2758 2758 - uint64_t reserved_32_63:32; 2759 2759 - uint64_t cnt:32; 2760 2760 - #else 2761 2761 - uint64_t cnt:32; 2762 2762 - uint64_t reserved_32_63:32; 2763 2763 - #endif 2764 2764 - } s; 2765 2765 - struct cvmx_sli_pkt_in_donex_cnts_s cn61xx; 2766 2766 - struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; 2767 2767 - struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1; 2768 2768 - struct cvmx_sli_pkt_in_donex_cnts_s cn66xx; 2769 2769 - struct cvmx_sli_pkt_in_donex_cnts_s cn68xx; 2770 2770 - struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1; 2771 2771 - struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx; 2772 2772 - }; 2773 2773 - 2774 2774 - union cvmx_sli_pkt_in_instr_counts { 2775 2775 - uint64_t u64; 2776 2776 - struct cvmx_sli_pkt_in_instr_counts_s { 2777 2777 - #ifdef __BIG_ENDIAN_BITFIELD 2778 2778 - uint64_t wr_cnt:32; 2779 2779 - uint64_t rd_cnt:32; 2780 2780 - #else 2781 2781 - uint64_t rd_cnt:32; 2782 2782 - uint64_t wr_cnt:32; 2783 2783 - #endif 2784 2784 - } s; 2785 2785 - struct cvmx_sli_pkt_in_instr_counts_s cn61xx; 2786 2786 - struct cvmx_sli_pkt_in_instr_counts_s cn63xx; 2787 2787 - struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1; 2788 2788 - struct cvmx_sli_pkt_in_instr_counts_s cn66xx; 2789 2789 - struct cvmx_sli_pkt_in_instr_counts_s cn68xx; 2790 2790 - struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1; 2791 2791 - struct cvmx_sli_pkt_in_instr_counts_s cnf71xx; 2792 2792 - }; 2793 2793 - 2794 2794 - union cvmx_sli_pkt_in_pcie_port { 2795 2795 - uint64_t u64; 2796 2796 - struct cvmx_sli_pkt_in_pcie_port_s { 2797 2797 - #ifdef __BIG_ENDIAN_BITFIELD 2798 2798 - uint64_t pp:64; 2799 2799 - #else 2800 2800 - uint64_t pp:64; 2801 2801 - #endif 2802 2802 - } s; 2803 2803 - struct cvmx_sli_pkt_in_pcie_port_s cn61xx; 2804 2804 - struct cvmx_sli_pkt_in_pcie_port_s cn63xx; 2805 2805 - struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1; 2806 2806 - struct cvmx_sli_pkt_in_pcie_port_s cn66xx; 2807 2807 - struct cvmx_sli_pkt_in_pcie_port_s cn68xx; 2808 2808 - struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1; 2809 2809 - struct cvmx_sli_pkt_in_pcie_port_s cnf71xx; 2810 2810 - }; 2811 2811 - 2812 2812 - union cvmx_sli_pkt_input_control { 2813 2813 - uint64_t u64; 2814 2814 - struct cvmx_sli_pkt_input_control_s { 2815 2815 - #ifdef __BIG_ENDIAN_BITFIELD 2816 2816 - uint64_t prd_erst:1; 2817 2817 - uint64_t prd_rds:7; 2818 2818 - uint64_t gii_erst:1; 2819 2819 - uint64_t gii_rds:7; 2820 2820 - uint64_t reserved_41_47:7; 2821 2821 - uint64_t prc_idle:1; 2822 2822 - uint64_t reserved_24_39:16; 2823 2823 - uint64_t pin_rst:1; 2824 2824 - uint64_t pkt_rr:1; 2825 2825 - uint64_t pbp_dhi:13; 2826 2826 - uint64_t d_nsr:1; 2827 2827 - uint64_t d_esr:2; 2828 2828 - uint64_t d_ror:1; 2829 2829 - uint64_t use_csr:1; 2830 2830 - uint64_t nsr:1; 2831 2831 - uint64_t esr:2; 2832 2832 - uint64_t ror:1; 2833 2833 - #else 2834 2834 - uint64_t ror:1; 2835 2835 - uint64_t esr:2; 2836 2836 - uint64_t nsr:1; 2837 2837 - uint64_t use_csr:1; 2838 2838 - uint64_t d_ror:1; 2839 2839 - uint64_t d_esr:2; 2840 2840 - uint64_t d_nsr:1; 2841 2841 - uint64_t pbp_dhi:13; 2842 2842 - uint64_t pkt_rr:1; 2843 2843 - uint64_t pin_rst:1; 2844 2844 - uint64_t reserved_24_39:16; 2845 2845 - uint64_t prc_idle:1; 2846 2846 - uint64_t reserved_41_47:7; 2847 2847 - uint64_t gii_rds:7; 2848 2848 - uint64_t gii_erst:1; 2849 2849 - uint64_t prd_rds:7; 2850 2850 - uint64_t prd_erst:1; 2851 2851 - #endif 2852 2852 - } s; 2853 2853 - struct cvmx_sli_pkt_input_control_s cn61xx; 2854 2854 - struct cvmx_sli_pkt_input_control_cn63xx { 2855 2855 - #ifdef __BIG_ENDIAN_BITFIELD 2856 2856 - uint64_t reserved_23_63:41; 2857 2857 - uint64_t pkt_rr:1; 2858 2858 - uint64_t pbp_dhi:13; 2859 2859 - uint64_t d_nsr:1; 2860 2860 - uint64_t d_esr:2; 2861 2861 - uint64_t d_ror:1; 2862 2862 - uint64_t use_csr:1; 2863 2863 - uint64_t nsr:1; 2864 2864 - uint64_t esr:2; 2865 2865 - uint64_t ror:1; 2866 2866 - #else 2867 2867 - uint64_t ror:1; 2868 2868 - uint64_t esr:2; 2869 2869 - uint64_t nsr:1; 2870 2870 - uint64_t use_csr:1; 2871 2871 - uint64_t d_ror:1; 2872 2872 - uint64_t d_esr:2; 2873 2873 - uint64_t d_nsr:1; 2874 2874 - uint64_t pbp_dhi:13; 2875 2875 - uint64_t pkt_rr:1; 2876 2876 - uint64_t reserved_23_63:41; 2877 2877 - #endif 2878 2878 - } cn63xx; 2879 2879 - struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1; 2880 2880 - struct cvmx_sli_pkt_input_control_s cn66xx; 2881 2881 - struct cvmx_sli_pkt_input_control_s cn68xx; 2882 2882 - struct cvmx_sli_pkt_input_control_s cn68xxp1; 2883 2883 - struct cvmx_sli_pkt_input_control_s cnf71xx; 2884 2884 - }; 2885 2885 - 2886 2886 - union cvmx_sli_pkt_instr_enb { 2887 2887 - uint64_t u64; 2888 2888 - struct cvmx_sli_pkt_instr_enb_s { 2889 2889 - #ifdef __BIG_ENDIAN_BITFIELD 2890 2890 - uint64_t reserved_32_63:32; 2891 2891 - uint64_t enb:32; 2892 2892 - #else 2893 2893 - uint64_t enb:32; 2894 2894 - uint64_t reserved_32_63:32; 2895 2895 - #endif 2896 2896 - } s; 2897 2897 - struct cvmx_sli_pkt_instr_enb_s cn61xx; 2898 2898 - struct cvmx_sli_pkt_instr_enb_s cn63xx; 2899 2899 - struct cvmx_sli_pkt_instr_enb_s cn63xxp1; 2900 2900 - struct cvmx_sli_pkt_instr_enb_s cn66xx; 2901 2901 - struct cvmx_sli_pkt_instr_enb_s cn68xx; 2902 2902 - struct cvmx_sli_pkt_instr_enb_s cn68xxp1; 2903 2903 - struct cvmx_sli_pkt_instr_enb_s cnf71xx; 2904 2904 - }; 2905 2905 - 2906 2906 - union cvmx_sli_pkt_instr_rd_size { 2907 2907 - uint64_t u64; 2908 2908 - struct cvmx_sli_pkt_instr_rd_size_s { 2909 2909 - #ifdef __BIG_ENDIAN_BITFIELD 2910 2910 - uint64_t rdsize:64; 2911 2911 - #else 2912 2912 - uint64_t rdsize:64; 2913 2913 - #endif 2914 2914 - } s; 2915 2915 - struct cvmx_sli_pkt_instr_rd_size_s cn61xx; 2916 2916 - struct cvmx_sli_pkt_instr_rd_size_s cn63xx; 2917 2917 - struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1; 2918 2918 - struct cvmx_sli_pkt_instr_rd_size_s cn66xx; 2919 2919 - struct cvmx_sli_pkt_instr_rd_size_s cn68xx; 2920 2920 - struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1; 2921 2921 - struct cvmx_sli_pkt_instr_rd_size_s cnf71xx; 2922 2922 - }; 2923 2923 - 2924 2924 - union cvmx_sli_pkt_instr_size { 2925 2925 - uint64_t u64; 2926 2926 - struct cvmx_sli_pkt_instr_size_s { 2927 2927 - #ifdef __BIG_ENDIAN_BITFIELD 2928 2928 - uint64_t reserved_32_63:32; 2929 2929 - uint64_t is_64b:32; 2930 2930 - #else 2931 2931 - uint64_t is_64b:32; 2932 2932 - uint64_t reserved_32_63:32; 2933 2933 - #endif 2934 2934 - } s; 2935 2935 - struct cvmx_sli_pkt_instr_size_s cn61xx; 2936 2936 - struct cvmx_sli_pkt_instr_size_s cn63xx; 2937 2937 - struct cvmx_sli_pkt_instr_size_s cn63xxp1; 2938 2938 - struct cvmx_sli_pkt_instr_size_s cn66xx; 2939 2939 - struct cvmx_sli_pkt_instr_size_s cn68xx; 2940 2940 - struct cvmx_sli_pkt_instr_size_s cn68xxp1; 2941 2941 - struct cvmx_sli_pkt_instr_size_s cnf71xx; 2942 2942 - }; 2943 2943 - 2944 2944 - union cvmx_sli_pkt_int_levels { 2945 2945 - uint64_t u64; 2946 2946 - struct cvmx_sli_pkt_int_levels_s { 2947 2947 - #ifdef __BIG_ENDIAN_BITFIELD 2948 2948 - uint64_t reserved_54_63:10; 2949 2949 - uint64_t time:22; 2950 2950 - uint64_t cnt:32; 2951 2951 - #else 2952 2952 - uint64_t cnt:32; 2953 2953 - uint64_t time:22; 2954 2954 - uint64_t reserved_54_63:10; 2955 2955 - #endif 2956 2956 - } s; 2957 2957 - struct cvmx_sli_pkt_int_levels_s cn61xx; 2958 2958 - struct cvmx_sli_pkt_int_levels_s cn63xx; 2959 2959 - struct cvmx_sli_pkt_int_levels_s cn63xxp1; 2960 2960 - struct cvmx_sli_pkt_int_levels_s cn66xx; 2961 2961 - struct cvmx_sli_pkt_int_levels_s cn68xx; 2962 2962 - struct cvmx_sli_pkt_int_levels_s cn68xxp1; 2963 2963 - struct cvmx_sli_pkt_int_levels_s cnf71xx; 2964 2964 - }; 2965 2965 - 2966 2966 - union cvmx_sli_pkt_iptr { 2967 2967 - uint64_t u64; 2968 2968 - struct cvmx_sli_pkt_iptr_s { 2969 2969 - #ifdef __BIG_ENDIAN_BITFIELD 2970 2970 - uint64_t reserved_32_63:32; 2971 2971 - uint64_t iptr:32; 2972 2972 - #else 2973 2973 - uint64_t iptr:32; 2974 2974 - uint64_t reserved_32_63:32; 2975 2975 - #endif 2976 2976 - } s; 2977 2977 - struct cvmx_sli_pkt_iptr_s cn61xx; 2978 2978 - struct cvmx_sli_pkt_iptr_s cn63xx; 2979 2979 - struct cvmx_sli_pkt_iptr_s cn63xxp1; 2980 2980 - struct cvmx_sli_pkt_iptr_s cn66xx; 2981 2981 - struct cvmx_sli_pkt_iptr_s cn68xx; 2982 2982 - struct cvmx_sli_pkt_iptr_s cn68xxp1; 2983 2983 - struct cvmx_sli_pkt_iptr_s cnf71xx; 2984 2984 - }; 2985 2985 - 2986 2986 - union cvmx_sli_pkt_out_bmode { 2987 2987 - uint64_t u64; 2988 2988 - struct cvmx_sli_pkt_out_bmode_s { 2989 2989 - #ifdef __BIG_ENDIAN_BITFIELD 2990 2990 - uint64_t reserved_32_63:32; 2991 2991 - uint64_t bmode:32; 2992 2992 - #else 2993 2993 - uint64_t bmode:32; 2994 2994 - uint64_t reserved_32_63:32; 2995 2995 - #endif 2996 2996 - } s; 2997 2997 - struct cvmx_sli_pkt_out_bmode_s cn61xx; 2998 2998 - struct cvmx_sli_pkt_out_bmode_s cn63xx; 2999 2999 - struct cvmx_sli_pkt_out_bmode_s cn63xxp1; 3000 3000 - struct cvmx_sli_pkt_out_bmode_s cn66xx; 3001 3001 - struct cvmx_sli_pkt_out_bmode_s cn68xx; 3002 3002 - struct cvmx_sli_pkt_out_bmode_s cn68xxp1; 3003 3003 - struct cvmx_sli_pkt_out_bmode_s cnf71xx; 3004 3004 - }; 3005 3005 - 3006 3006 - union cvmx_sli_pkt_out_bp_en { 3007 3007 - uint64_t u64; 3008 3008 - struct cvmx_sli_pkt_out_bp_en_s { 3009 3009 - #ifdef __BIG_ENDIAN_BITFIELD 3010 3010 - uint64_t reserved_32_63:32; 3011 3011 - uint64_t bp_en:32; 3012 3012 - #else 3013 3013 - uint64_t bp_en:32; 3014 3014 - uint64_t reserved_32_63:32; 3015 3015 - #endif 3016 3016 - } s; 3017 3017 - struct cvmx_sli_pkt_out_bp_en_s cn68xx; 3018 3018 - struct cvmx_sli_pkt_out_bp_en_s cn68xxp1; 3019 3019 - }; 3020 3020 - 3021 3021 - union cvmx_sli_pkt_out_enb { 3022 3022 - uint64_t u64; 3023 3023 - struct cvmx_sli_pkt_out_enb_s { 3024 3024 - #ifdef __BIG_ENDIAN_BITFIELD 3025 3025 - uint64_t reserved_32_63:32; 3026 3026 - uint64_t enb:32; 3027 3027 - #else 3028 3028 - uint64_t enb:32; 3029 3029 - uint64_t reserved_32_63:32; 3030 3030 - #endif 3031 3031 - } s; 3032 3032 - struct cvmx_sli_pkt_out_enb_s cn61xx; 3033 3033 - struct cvmx_sli_pkt_out_enb_s cn63xx; 3034 3034 - struct cvmx_sli_pkt_out_enb_s cn63xxp1; 3035 3035 - struct cvmx_sli_pkt_out_enb_s cn66xx; 3036 3036 - struct cvmx_sli_pkt_out_enb_s cn68xx; 3037 3037 - struct cvmx_sli_pkt_out_enb_s cn68xxp1; 3038 3038 - struct cvmx_sli_pkt_out_enb_s cnf71xx; 3039 3039 - }; 3040 3040 - 3041 3041 - union cvmx_sli_pkt_output_wmark { 3042 3042 - uint64_t u64; 3043 3043 - struct cvmx_sli_pkt_output_wmark_s { 3044 3044 - #ifdef __BIG_ENDIAN_BITFIELD 3045 3045 - uint64_t reserved_32_63:32; 3046 3046 - uint64_t wmark:32; 3047 3047 - #else 3048 3048 - uint64_t wmark:32; 3049 3049 - uint64_t reserved_32_63:32; 3050 3050 - #endif 3051 3051 - } s; 3052 3052 - struct cvmx_sli_pkt_output_wmark_s cn61xx; 3053 3053 - struct cvmx_sli_pkt_output_wmark_s cn63xx; 3054 3054 - struct cvmx_sli_pkt_output_wmark_s cn63xxp1; 3055 3055 - struct cvmx_sli_pkt_output_wmark_s cn66xx; 3056 3056 - struct cvmx_sli_pkt_output_wmark_s cn68xx; 3057 3057 - struct cvmx_sli_pkt_output_wmark_s cn68xxp1; 3058 3058 - struct cvmx_sli_pkt_output_wmark_s cnf71xx; 3059 3059 - }; 3060 3060 - 3061 3061 - union cvmx_sli_pkt_pcie_port { 3062 3062 - uint64_t u64; 3063 3063 - struct cvmx_sli_pkt_pcie_port_s { 3064 3064 - #ifdef __BIG_ENDIAN_BITFIELD 3065 3065 - uint64_t pp:64; 3066 3066 - #else 3067 3067 - uint64_t pp:64; 3068 3068 - #endif 3069 3069 - } s; 3070 3070 - struct cvmx_sli_pkt_pcie_port_s cn61xx; 3071 3071 - struct cvmx_sli_pkt_pcie_port_s cn63xx; 3072 3072 - struct cvmx_sli_pkt_pcie_port_s cn63xxp1; 3073 3073 - struct cvmx_sli_pkt_pcie_port_s cn66xx; 3074 3074 - struct cvmx_sli_pkt_pcie_port_s cn68xx; 3075 3075 - struct cvmx_sli_pkt_pcie_port_s cn68xxp1; 3076 3076 - struct cvmx_sli_pkt_pcie_port_s cnf71xx; 3077 3077 - }; 3078 3078 - 3079 3079 - union cvmx_sli_pkt_port_in_rst { 3080 3080 - uint64_t u64; 3081 3081 - struct cvmx_sli_pkt_port_in_rst_s { 3082 3082 - #ifdef __BIG_ENDIAN_BITFIELD 3083 3083 - uint64_t in_rst:32; 3084 3084 - uint64_t out_rst:32; 3085 3085 - #else 3086 3086 - uint64_t out_rst:32; 3087 3087 - uint64_t in_rst:32; 3088 3088 - #endif 3089 3089 - } s; 3090 3090 - struct cvmx_sli_pkt_port_in_rst_s cn61xx; 3091 3091 - struct cvmx_sli_pkt_port_in_rst_s cn63xx; 3092 3092 - struct cvmx_sli_pkt_port_in_rst_s cn63xxp1; 3093 3093 - struct cvmx_sli_pkt_port_in_rst_s cn66xx; 3094 3094 - struct cvmx_sli_pkt_port_in_rst_s cn68xx; 3095 3095 - struct cvmx_sli_pkt_port_in_rst_s cn68xxp1; 3096 3096 - struct cvmx_sli_pkt_port_in_rst_s cnf71xx; 3097 3097 - }; 3098 3098 - 3099 3099 - union cvmx_sli_pkt_slist_es { 3100 3100 - uint64_t u64; 3101 3101 - struct cvmx_sli_pkt_slist_es_s { 3102 3102 - #ifdef __BIG_ENDIAN_BITFIELD 3103 3103 - uint64_t es:64; 3104 3104 - #else 3105 3105 - uint64_t es:64; 3106 3106 - #endif 3107 3107 - } s; 3108 3108 - struct cvmx_sli_pkt_slist_es_s cn61xx; 3109 3109 - struct cvmx_sli_pkt_slist_es_s cn63xx; 3110 3110 - struct cvmx_sli_pkt_slist_es_s cn63xxp1; 3111 3111 - struct cvmx_sli_pkt_slist_es_s cn66xx; 3112 3112 - struct cvmx_sli_pkt_slist_es_s cn68xx; 3113 3113 - struct cvmx_sli_pkt_slist_es_s cn68xxp1; 3114 3114 - struct cvmx_sli_pkt_slist_es_s cnf71xx; 3115 3115 - }; 3116 3116 - 3117 3117 - union cvmx_sli_pkt_slist_ns { 3118 3118 - uint64_t u64; 3119 3119 - struct cvmx_sli_pkt_slist_ns_s { 3120 3120 - #ifdef __BIG_ENDIAN_BITFIELD 3121 3121 - uint64_t reserved_32_63:32; 3122 3122 - uint64_t nsr:32; 3123 3123 - #else 3124 3124 - uint64_t nsr:32; 3125 3125 - uint64_t reserved_32_63:32; 3126 3126 - #endif 3127 3127 - } s; 3128 3128 - struct cvmx_sli_pkt_slist_ns_s cn61xx; 3129 3129 - struct cvmx_sli_pkt_slist_ns_s cn63xx; 3130 3130 - struct cvmx_sli_pkt_slist_ns_s cn63xxp1; 3131 3131 - struct cvmx_sli_pkt_slist_ns_s cn66xx; 3132 3132 - struct cvmx_sli_pkt_slist_ns_s cn68xx; 3133 3133 - struct cvmx_sli_pkt_slist_ns_s cn68xxp1; 3134 3134 - struct cvmx_sli_pkt_slist_ns_s cnf71xx; 3135 3135 - }; 3136 3136 - 3137 3137 - union cvmx_sli_pkt_slist_ror { 3138 3138 - uint64_t u64; 3139 3139 - struct cvmx_sli_pkt_slist_ror_s { 3140 3140 - #ifdef __BIG_ENDIAN_BITFIELD 3141 3141 - uint64_t reserved_32_63:32; 3142 3142 - uint64_t ror:32; 3143 3143 - #else 3144 3144 - uint64_t ror:32; 3145 3145 - uint64_t reserved_32_63:32; 3146 3146 - #endif 3147 3147 - } s; 3148 3148 - struct cvmx_sli_pkt_slist_ror_s cn61xx; 3149 3149 - struct cvmx_sli_pkt_slist_ror_s cn63xx; 3150 3150 - struct cvmx_sli_pkt_slist_ror_s cn63xxp1; 3151 3151 - struct cvmx_sli_pkt_slist_ror_s cn66xx; 3152 3152 - struct cvmx_sli_pkt_slist_ror_s cn68xx; 3153 3153 - struct cvmx_sli_pkt_slist_ror_s cn68xxp1; 3154 3154 - struct cvmx_sli_pkt_slist_ror_s cnf71xx; 3155 3155 - }; 3156 3156 - 3157 3157 - union cvmx_sli_pkt_time_int { 3158 3158 - uint64_t u64; 3159 3159 - struct cvmx_sli_pkt_time_int_s { 3160 3160 - #ifdef __BIG_ENDIAN_BITFIELD 3161 3161 - uint64_t reserved_32_63:32; 3162 3162 - uint64_t port:32; 3163 3163 - #else 3164 3164 - uint64_t port:32; 3165 3165 - uint64_t reserved_32_63:32; 3166 3166 - #endif 3167 3167 - } s; 3168 3168 - struct cvmx_sli_pkt_time_int_s cn61xx; 3169 3169 - struct cvmx_sli_pkt_time_int_s cn63xx; 3170 3170 - struct cvmx_sli_pkt_time_int_s cn63xxp1; 3171 3171 - struct cvmx_sli_pkt_time_int_s cn66xx; 3172 3172 - struct cvmx_sli_pkt_time_int_s cn68xx; 3173 3173 - struct cvmx_sli_pkt_time_int_s cn68xxp1; 3174 3174 - struct cvmx_sli_pkt_time_int_s cnf71xx; 3175 3175 - }; 3176 3176 - 3177 3177 - union cvmx_sli_pkt_time_int_enb { 3178 3178 - uint64_t u64; 3179 3179 - struct cvmx_sli_pkt_time_int_enb_s { 3180 3180 - #ifdef __BIG_ENDIAN_BITFIELD 3181 3181 - uint64_t reserved_32_63:32; 3182 3182 - uint64_t port:32; 3183 3183 - #else 3184 3184 - uint64_t port:32; 3185 3185 - uint64_t reserved_32_63:32; 3186 3186 - #endif 3187 3187 - } s; 3188 3188 - struct cvmx_sli_pkt_time_int_enb_s cn61xx; 3189 3189 - struct cvmx_sli_pkt_time_int_enb_s cn63xx; 3190 3190 - struct cvmx_sli_pkt_time_int_enb_s cn63xxp1; 3191 3191 - struct cvmx_sli_pkt_time_int_enb_s cn66xx; 3192 3192 - struct cvmx_sli_pkt_time_int_enb_s cn68xx; 3193 3193 - struct cvmx_sli_pkt_time_int_enb_s cn68xxp1; 3194 3194 - struct cvmx_sli_pkt_time_int_enb_s cnf71xx; 3195 3195 - }; 3196 3196 - 3197 3197 - union cvmx_sli_portx_pkind { 3198 3198 - uint64_t u64; 3199 3199 - struct cvmx_sli_portx_pkind_s { 3200 3200 - #ifdef __BIG_ENDIAN_BITFIELD 3201 3201 - uint64_t reserved_25_63:39; 3202 3202 - uint64_t rpk_enb:1; 3203 3203 - uint64_t reserved_22_23:2; 3204 3204 - uint64_t pkindr:6; 3205 3205 - uint64_t reserved_14_15:2; 3206 3206 - uint64_t bpkind:6; 3207 3207 - uint64_t reserved_6_7:2; 3208 3208 - uint64_t pkind:6; 3209 3209 - #else 3210 3210 - uint64_t pkind:6; 3211 3211 - uint64_t reserved_6_7:2; 3212 3212 - uint64_t bpkind:6; 3213 3213 - uint64_t reserved_14_15:2; 3214 3214 - uint64_t pkindr:6; 3215 3215 - uint64_t reserved_22_23:2; 3216 3216 - uint64_t rpk_enb:1; 3217 3217 - uint64_t reserved_25_63:39; 3218 3218 - #endif 3219 3219 - } s; 3220 3220 - struct cvmx_sli_portx_pkind_s cn68xx; 3221 3221 - struct cvmx_sli_portx_pkind_cn68xxp1 { 3222 3222 - #ifdef __BIG_ENDIAN_BITFIELD 3223 3223 - uint64_t reserved_14_63:50; 3224 3224 - uint64_t bpkind:6; 3225 3225 - uint64_t reserved_6_7:2; 3226 3226 - uint64_t pkind:6; 3227 3227 - #else 3228 3228 - uint64_t pkind:6; 3229 3229 - uint64_t reserved_6_7:2; 3230 3230 - uint64_t bpkind:6; 3231 3231 - uint64_t reserved_14_63:50; 3232 3232 - #endif 3233 3233 - } cn68xxp1; 3234 86 }; 3235 87 3236 88 union cvmx_sli_s2m_portx_ctl { 3237 89 uint64_t u64; 3238 90 struct cvmx_sli_s2m_portx_ctl_s { 3239 3239 - #ifdef __BIG_ENDIAN_BITFIELD 3240 3240 - uint64_t reserved_5_63:59; 3241 3241 - uint64_t wind_d:1; 3242 3242 - uint64_t bar0_d:1; 3243 3243 - uint64_t mrrs:3; 3244 3244 - #else 3245 3245 - uint64_t mrrs:3; 3246 3246 - uint64_t bar0_d:1; 3247 3247 - uint64_t wind_d:1; 3248 3248 - uint64_t reserved_5_63:59; 3249 3249 - #endif 91 91 + __BITFIELD_FIELD(uint64_t reserved_5_63:59, 92 92 + __BITFIELD_FIELD(uint64_t wind_d:1, 93 93 + __BITFIELD_FIELD(uint64_t bar0_d:1, 94 94 + __BITFIELD_FIELD(uint64_t mrrs:3, 95 95 + ;)))) 3250 96 } s; 3251 3251 - struct cvmx_sli_s2m_portx_ctl_s cn61xx; 3252 3252 - struct cvmx_sli_s2m_portx_ctl_s cn63xx; 3253 3253 - struct cvmx_sli_s2m_portx_ctl_s cn63xxp1; 3254 3254 - struct cvmx_sli_s2m_portx_ctl_s cn66xx; 3255 3255 - struct cvmx_sli_s2m_portx_ctl_s cn68xx; 3256 3256 - struct cvmx_sli_s2m_portx_ctl_s cn68xxp1; 3257 3257 - struct cvmx_sli_s2m_portx_ctl_s cnf71xx; 3258 97 }; 3259 98 3260 3260 - union cvmx_sli_scratch_1 { 99 99 + union cvmx_sli_mem_access_subidx { 3261 100 uint64_t u64; 3262 3262 - struct cvmx_sli_scratch_1_s { 3263 3263 - #ifdef __BIG_ENDIAN_BITFIELD 3264 3264 - uint64_t data:64; 3265 3265 - #else 3266 3266 - uint64_t data:64; 3267 3267 - #endif 101 101 + struct cvmx_sli_mem_access_subidx_s { 102 102 + __BITFIELD_FIELD(uint64_t reserved_43_63:21, 103 103 + __BITFIELD_FIELD(uint64_t zero:1, 104 104 + __BITFIELD_FIELD(uint64_t port:3, 105 105 + __BITFIELD_FIELD(uint64_t nmerge:1, 106 106 + __BITFIELD_FIELD(uint64_t esr:2, 107 107 + __BITFIELD_FIELD(uint64_t esw:2, 108 108 + __BITFIELD_FIELD(uint64_t wtype:2, 109 109 + __BITFIELD_FIELD(uint64_t rtype:2, 110 110 + __BITFIELD_FIELD(uint64_t ba:30, 111 111 + ;))))))))) 3268 112 } s; 3269 3269 - struct cvmx_sli_scratch_1_s cn61xx; 3270 3270 - struct cvmx_sli_scratch_1_s cn63xx; 3271 3271 - struct cvmx_sli_scratch_1_s cn63xxp1; 3272 3272 - struct cvmx_sli_scratch_1_s cn66xx; 3273 3273 - struct cvmx_sli_scratch_1_s cn68xx; 3274 3274 - struct cvmx_sli_scratch_1_s cn68xxp1; 3275 3275 - struct cvmx_sli_scratch_1_s cnf71xx; 3276 3276 - }; 3277 3277 - 3278 3278 - union cvmx_sli_scratch_2 { 3279 3279 - uint64_t u64; 3280 3280 - struct cvmx_sli_scratch_2_s { 3281 3281 - #ifdef __BIG_ENDIAN_BITFIELD 3282 3282 - uint64_t data:64; 3283 3283 - #else 3284 3284 - uint64_t data:64; 3285 3285 - #endif 3286 3286 - } s; 3287 3287 - struct cvmx_sli_scratch_2_s cn61xx; 3288 3288 - struct cvmx_sli_scratch_2_s cn63xx; 3289 3289 - struct cvmx_sli_scratch_2_s cn63xxp1; 3290 3290 - struct cvmx_sli_scratch_2_s cn66xx; 3291 3291 - struct cvmx_sli_scratch_2_s cn68xx; 3292 3292 - struct cvmx_sli_scratch_2_s cn68xxp1; 3293 3293 - struct cvmx_sli_scratch_2_s cnf71xx; 3294 3294 - }; 3295 3295 - 3296 3296 - union cvmx_sli_state1 { 3297 3297 - uint64_t u64; 3298 3298 - struct cvmx_sli_state1_s { 3299 3299 - #ifdef __BIG_ENDIAN_BITFIELD 3300 3300 - uint64_t cpl1:12; 3301 3301 - uint64_t cpl0:12; 3302 3302 - uint64_t arb:1; 3303 3303 - uint64_t csr:39; 3304 3304 - #else 3305 3305 - uint64_t csr:39; 3306 3306 - uint64_t arb:1; 3307 3307 - uint64_t cpl0:12; 3308 3308 - uint64_t cpl1:12; 3309 3309 - #endif 3310 3310 - } s; 3311 3311 - struct cvmx_sli_state1_s cn61xx; 3312 3312 - struct cvmx_sli_state1_s cn63xx; 3313 3313 - struct cvmx_sli_state1_s cn63xxp1; 3314 3314 - struct cvmx_sli_state1_s cn66xx; 3315 3315 - struct cvmx_sli_state1_s cn68xx; 3316 3316 - struct cvmx_sli_state1_s cn68xxp1; 3317 3317 - struct cvmx_sli_state1_s cnf71xx; 3318 3318 - }; 3319 3319 - 3320 3320 - union cvmx_sli_state2 { 3321 3321 - uint64_t u64; 3322 3322 - struct cvmx_sli_state2_s { 3323 3323 - #ifdef __BIG_ENDIAN_BITFIELD 3324 3324 - uint64_t reserved_56_63:8; 3325 3325 - uint64_t nnp1:8; 3326 3326 - uint64_t reserved_47_47:1; 3327 3327 - uint64_t rac:1; 3328 3328 - uint64_t csm1:15; 3329 3329 - uint64_t csm0:15; 3330 3330 - uint64_t nnp0:8; 3331 3331 - uint64_t nnd:8; 3332 3332 - #else 3333 3333 - uint64_t nnd:8; 3334 3334 - uint64_t nnp0:8; 3335 3335 - uint64_t csm0:15; 3336 3336 - uint64_t csm1:15; 3337 3337 - uint64_t rac:1; 3338 3338 - uint64_t reserved_47_47:1; 3339 3339 - uint64_t nnp1:8; 3340 3340 - uint64_t reserved_56_63:8; 3341 3341 - #endif 3342 3342 - } s; 3343 3343 - struct cvmx_sli_state2_s cn61xx; 3344 3344 - struct cvmx_sli_state2_s cn63xx; 3345 3345 - struct cvmx_sli_state2_s cn63xxp1; 3346 3346 - struct cvmx_sli_state2_s cn66xx; 3347 3347 - struct cvmx_sli_state2_s cn68xx; 3348 3348 - struct cvmx_sli_state2_s cn68xxp1; 3349 3349 - struct cvmx_sli_state2_s cnf71xx; 3350 3350 - }; 3351 3351 - 3352 3352 - union cvmx_sli_state3 { 3353 3353 - uint64_t u64; 3354 3354 - struct cvmx_sli_state3_s { 3355 3355 - #ifdef __BIG_ENDIAN_BITFIELD 3356 3356 - uint64_t reserved_56_63:8; 3357 3357 - uint64_t psm1:15; 3358 3358 - uint64_t psm0:15; 3359 3359 - uint64_t nsm1:13; 3360 3360 - uint64_t nsm0:13; 3361 3361 - #else 3362 3362 - uint64_t nsm0:13; 3363 3363 - uint64_t nsm1:13; 3364 3364 - uint64_t psm0:15; 3365 3365 - uint64_t psm1:15; 3366 3366 - uint64_t reserved_56_63:8; 3367 3367 - #endif 3368 3368 - } s; 3369 3369 - struct cvmx_sli_state3_s cn61xx; 3370 3370 - struct cvmx_sli_state3_s cn63xx; 3371 3371 - struct cvmx_sli_state3_s cn63xxp1; 3372 3372 - struct cvmx_sli_state3_s cn66xx; 3373 3373 - struct cvmx_sli_state3_s cn68xx; 3374 3374 - struct cvmx_sli_state3_s cn68xxp1; 3375 3375 - struct cvmx_sli_state3_s cnf71xx; 3376 3376 - }; 3377 3377 - 3378 3378 - union cvmx_sli_tx_pipe { 3379 3379 - uint64_t u64; 3380 3380 - struct cvmx_sli_tx_pipe_s { 3381 3381 - #ifdef __BIG_ENDIAN_BITFIELD 3382 3382 - uint64_t reserved_24_63:40; 3383 3383 - uint64_t nump:8; 3384 3384 - uint64_t reserved_7_15:9; 3385 3385 - uint64_t base:7; 3386 3386 - #else 3387 3387 - uint64_t base:7; 3388 3388 - uint64_t reserved_7_15:9; 3389 3389 - uint64_t nump:8; 3390 3390 - uint64_t reserved_24_63:40; 3391 3391 - #endif 3392 3392 - } s; 3393 3393 - struct cvmx_sli_tx_pipe_s cn68xx; 3394 3394 - struct cvmx_sli_tx_pipe_s cn68xxp1; 3395 3395 - }; 3396 3396 - 3397 3397 - union cvmx_sli_win_rd_addr { 3398 3398 - uint64_t u64; 3399 3399 - struct cvmx_sli_win_rd_addr_s { 3400 3400 - #ifdef __BIG_ENDIAN_BITFIELD 3401 3401 - uint64_t reserved_51_63:13; 3402 3402 - uint64_t ld_cmd:2; 3403 3403 - uint64_t iobit:1; 3404 3404 - uint64_t rd_addr:48; 3405 3405 - #else 3406 3406 - uint64_t rd_addr:48; 3407 3407 - uint64_t iobit:1; 3408 3408 - uint64_t ld_cmd:2; 3409 3409 - uint64_t reserved_51_63:13; 3410 3410 - #endif 3411 3411 - } s; 3412 3412 - struct cvmx_sli_win_rd_addr_s cn61xx; 3413 3413 - struct cvmx_sli_win_rd_addr_s cn63xx; 3414 3414 - struct cvmx_sli_win_rd_addr_s cn63xxp1; 3415 3415 - struct cvmx_sli_win_rd_addr_s cn66xx; 3416 3416 - struct cvmx_sli_win_rd_addr_s cn68xx; 3417 3417 - struct cvmx_sli_win_rd_addr_s cn68xxp1; 3418 3418 - struct cvmx_sli_win_rd_addr_s cnf71xx; 3419 3419 - }; 3420 3420 - 3421 3421 - union cvmx_sli_win_rd_data { 3422 3422 - uint64_t u64; 3423 3423 - struct cvmx_sli_win_rd_data_s { 3424 3424 - #ifdef __BIG_ENDIAN_BITFIELD 3425 3425 - uint64_t rd_data:64; 3426 3426 - #else 3427 3427 - uint64_t rd_data:64; 3428 3428 - #endif 3429 3429 - } s; 3430 3430 - struct cvmx_sli_win_rd_data_s cn61xx; 3431 3431 - struct cvmx_sli_win_rd_data_s cn63xx; 3432 3432 - struct cvmx_sli_win_rd_data_s cn63xxp1; 3433 3433 - struct cvmx_sli_win_rd_data_s cn66xx; 3434 3434 - struct cvmx_sli_win_rd_data_s cn68xx; 3435 3435 - struct cvmx_sli_win_rd_data_s cn68xxp1; 3436 3436 - struct cvmx_sli_win_rd_data_s cnf71xx; 3437 3437 - }; 3438 3438 - 3439 3439 - union cvmx_sli_win_wr_addr { 3440 3440 - uint64_t u64; 3441 3441 - struct cvmx_sli_win_wr_addr_s { 3442 3442 - #ifdef __BIG_ENDIAN_BITFIELD 3443 3443 - uint64_t reserved_49_63:15; 3444 3444 - uint64_t iobit:1; 3445 3445 - uint64_t wr_addr:45; 3446 3446 - uint64_t reserved_0_2:3; 3447 3447 - #else 3448 3448 - uint64_t reserved_0_2:3; 3449 3449 - uint64_t wr_addr:45; 3450 3450 - uint64_t iobit:1; 3451 3451 - uint64_t reserved_49_63:15; 3452 3452 - #endif 3453 3453 - } s; 3454 3454 - struct cvmx_sli_win_wr_addr_s cn61xx; 3455 3455 - struct cvmx_sli_win_wr_addr_s cn63xx; 3456 3456 - struct cvmx_sli_win_wr_addr_s cn63xxp1; 3457 3457 - struct cvmx_sli_win_wr_addr_s cn66xx; 3458 3458 - struct cvmx_sli_win_wr_addr_s cn68xx; 3459 3459 - struct cvmx_sli_win_wr_addr_s cn68xxp1; 3460 3460 - struct cvmx_sli_win_wr_addr_s cnf71xx; 3461 3461 - }; 3462 3462 - 3463 3463 - union cvmx_sli_win_wr_data { 3464 3464 - uint64_t u64; 3465 3465 - struct cvmx_sli_win_wr_data_s { 3466 3466 - #ifdef __BIG_ENDIAN_BITFIELD 3467 3467 - uint64_t wr_data:64; 3468 3468 - #else 3469 3469 - uint64_t wr_data:64; 3470 3470 - #endif 3471 3471 - } s; 3472 3472 - struct cvmx_sli_win_wr_data_s cn61xx; 3473 3473 - struct cvmx_sli_win_wr_data_s cn63xx; 3474 3474 - struct cvmx_sli_win_wr_data_s cn63xxp1; 3475 3475 - struct cvmx_sli_win_wr_data_s cn66xx; 3476 3476 - struct cvmx_sli_win_wr_data_s cn68xx; 3477 3477 - struct cvmx_sli_win_wr_data_s cn68xxp1; 3478 3478 - struct cvmx_sli_win_wr_data_s cnf71xx; 3479 3479 - }; 3480 3480 - 3481 3481 - union cvmx_sli_win_wr_mask { 3482 3482 - uint64_t u64; 3483 3483 - struct cvmx_sli_win_wr_mask_s { 3484 3484 - #ifdef __BIG_ENDIAN_BITFIELD 3485 3485 - uint64_t reserved_8_63:56; 3486 3486 - uint64_t wr_mask:8; 3487 3487 - #else 3488 3488 - uint64_t wr_mask:8; 3489 3489 - uint64_t reserved_8_63:56; 3490 3490 - #endif 3491 3491 - } s; 3492 3492 - struct cvmx_sli_win_wr_mask_s cn61xx; 3493 3493 - struct cvmx_sli_win_wr_mask_s cn63xx; 3494 3494 - struct cvmx_sli_win_wr_mask_s cn63xxp1; 3495 3495 - struct cvmx_sli_win_wr_mask_s cn66xx; 3496 3496 - struct cvmx_sli_win_wr_mask_s cn68xx; 3497 3497 - struct cvmx_sli_win_wr_mask_s cn68xxp1; 3498 3498 - struct cvmx_sli_win_wr_mask_s cnf71xx; 3499 3499 - }; 3500 3500 - 3501 3501 - union cvmx_sli_window_ctl { 3502 3502 - uint64_t u64; 3503 3503 - struct cvmx_sli_window_ctl_s { 3504 3504 - #ifdef __BIG_ENDIAN_BITFIELD 3505 3505 - uint64_t reserved_32_63:32; 3506 3506 - uint64_t time:32; 3507 3507 - #else 3508 3508 - uint64_t time:32; 3509 3509 - uint64_t reserved_32_63:32; 3510 3510 - #endif 3511 3511 - } s; 3512 3512 - struct cvmx_sli_window_ctl_s cn61xx; 3513 3513 - struct cvmx_sli_window_ctl_s cn63xx; 3514 3514 - struct cvmx_sli_window_ctl_s cn63xxp1; 3515 3515 - struct cvmx_sli_window_ctl_s cn66xx; 3516 3516 - struct cvmx_sli_window_ctl_s cn68xx; 3517 3517 - struct cvmx_sli_window_ctl_s cn68xxp1; 3518 3518 - struct cvmx_sli_window_ctl_s cnf71xx; 113 113 + struct cvmx_sli_mem_access_subidx_cn68xx { 114 114 + __BITFIELD_FIELD(uint64_t reserved_43_63:21, 115 115 + __BITFIELD_FIELD(uint64_t zero:1, 116 116 + __BITFIELD_FIELD(uint64_t port:3, 117 117 + __BITFIELD_FIELD(uint64_t nmerge:1, 118 118 + __BITFIELD_FIELD(uint64_t esr:2, 119 119 + __BITFIELD_FIELD(uint64_t esw:2, 120 120 + __BITFIELD_FIELD(uint64_t wtype:2, 121 121 + __BITFIELD_FIELD(uint64_t rtype:2, 122 122 + __BITFIELD_FIELD(uint64_t ba:28, 123 123 + __BITFIELD_FIELD(uint64_t reserved_0_1:2, 124 124 + ;)))))))))) 125 125 + } cn68xx; 3519 126 }; 3520 127 3521 128 #endif

+1 -2

arch/mips/include/asm/octeon/cvmx.h

reviewed

··· 4 4 * Contact: support@caviumnetworks.com 5 5 * This file is part of the OCTEON SDK 6 6 * 7 7 - * Copyright (c) 2003-2008 Cavium Networks 7 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 8 * 9 9 * This file is free software; you can redistribute it and/or modify 10 10 * it under the terms of the GNU General Public License, Version 2, as ··· 62 62 #include <asm/octeon/cvmx-iob-defs.h> 63 63 #include <asm/octeon/cvmx-ipd-defs.h> 64 64 #include <asm/octeon/cvmx-l2c-defs.h> 65 65 - #include <asm/octeon/cvmx-l2d-defs.h> 66 65 #include <asm/octeon/cvmx-l2t-defs.h> 67 66 #include <asm/octeon/cvmx-led-defs.h> 68 67 #include <asm/octeon/cvmx-mio-defs.h>

+26

arch/mips/include/asm/pgalloc.h

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··· 110 110 111 111 #endif 112 112 113 113 + #ifndef __PAGETABLE_PUD_FOLDED 114 114 + 115 115 + static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address) 116 116 + { 117 117 + pud_t *pud; 118 118 + 119 119 + pud = (pud_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PUD_ORDER); 120 120 + if (pud) 121 121 + pud_init((unsigned long)pud, (unsigned long)invalid_pmd_table); 122 122 + return pud; 123 123 + } 124 124 + 125 125 + static inline void pud_free(struct mm_struct *mm, pud_t *pud) 126 126 + { 127 127 + free_pages((unsigned long)pud, PUD_ORDER); 128 128 + } 129 129 + 130 130 + static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud) 131 131 + { 132 132 + set_pgd(pgd, __pgd((unsigned long)pud)); 133 133 + } 134 134 + 135 135 + #define __pud_free_tlb(tlb, x, addr) pud_free((tlb)->mm, x) 136 136 + 137 137 + #endif /* __PAGETABLE_PUD_FOLDED */ 138 138 + 113 139 #define check_pgt_cache() do { } while (0) 114 140 115 141 extern void pagetable_init(void);

+84 -6

arch/mips/include/asm/pgtable-64.h

reviewed

··· 20 20 #define __ARCH_USE_5LEVEL_HACK 21 21 #if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_MIPS_VA_BITS_48) 22 22 #include <asm-generic/pgtable-nopmd.h> 23 23 - #else 23 23 + #elif !(defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS_VA_BITS_48)) 24 24 #include <asm-generic/pgtable-nopud.h> 25 25 #endif 26 26 ··· 54 54 #define PMD_SIZE (1UL << PMD_SHIFT) 55 55 #define PMD_MASK (~(PMD_SIZE-1)) 56 56 57 57 - 58 58 - #define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) 57 57 + # ifdef __PAGETABLE_PUD_FOLDED 58 58 + # define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) 59 59 + # endif 59 60 #endif 61 61 + 62 62 + #ifndef __PAGETABLE_PUD_FOLDED 63 63 + #define PUD_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) 64 64 + #define PUD_SIZE (1UL << PUD_SHIFT) 65 65 + #define PUD_MASK (~(PUD_SIZE-1)) 66 66 + #define PGDIR_SHIFT (PUD_SHIFT + (PAGE_SHIFT + PUD_ORDER - 3)) 67 67 + #endif 68 68 + 60 69 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 61 70 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 62 71 ··· 88 79 * of virtual address space. 89 80 */ 90 81 #ifdef CONFIG_PAGE_SIZE_4KB 91 91 - #define PGD_ORDER 1 92 92 - #define PUD_ORDER aieeee_attempt_to_allocate_pud 82 82 + # ifdef CONFIG_MIPS_VA_BITS_48 83 83 + # define PGD_ORDER 0 84 84 + # define PUD_ORDER 0 85 85 + # else 86 86 + # define PGD_ORDER 1 87 87 + # define PUD_ORDER aieeee_attempt_to_allocate_pud 88 88 + # endif 93 89 #define PMD_ORDER 0 94 90 #define PTE_ORDER 0 95 91 #endif ··· 132 118 #endif 133 119 134 120 #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 121 121 + #ifndef __PAGETABLE_PUD_FOLDED 122 122 + #define PTRS_PER_PUD ((PAGE_SIZE << PUD_ORDER) / sizeof(pud_t)) 123 123 + #endif 135 124 #ifndef __PAGETABLE_PMD_FOLDED 136 125 #define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) 137 126 #endif ··· 151 134 #define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) 152 135 #define VMALLOC_END \ 153 136 (MAP_BASE + \ 154 154 - min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ 137 137 + min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ 155 138 (1UL << cpu_vmbits)) - (1UL << 32)) 156 139 157 140 #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ ··· 167 150 #define pmd_ERROR(e) \ 168 151 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 169 152 #endif 153 153 + #ifndef __PAGETABLE_PUD_FOLDED 154 154 + #define pud_ERROR(e) \ 155 155 + printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 156 156 + #endif 170 157 #define pgd_ERROR(e) \ 171 158 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 172 159 173 160 extern pte_t invalid_pte_table[PTRS_PER_PTE]; 174 161 extern pte_t empty_bad_page_table[PTRS_PER_PTE]; 175 162 163 163 + #ifndef __PAGETABLE_PUD_FOLDED 164 164 + /* 165 165 + * For 4-level pagetables we defines these ourselves, for 3-level the 166 166 + * definitions are below, for 2-level the 167 167 + * definitions are supplied by <asm-generic/pgtable-nopmd.h>. 168 168 + */ 169 169 + typedef struct { unsigned long pud; } pud_t; 170 170 + #define pud_val(x) ((x).pud) 171 171 + #define __pud(x) ((pud_t) { (x) }) 172 172 + 173 173 + extern pud_t invalid_pud_table[PTRS_PER_PUD]; 174 174 + 175 175 + /* 176 176 + * Empty pgd entries point to the invalid_pud_table. 177 177 + */ 178 178 + static inline int pgd_none(pgd_t pgd) 179 179 + { 180 180 + return pgd_val(pgd) == (unsigned long)invalid_pud_table; 181 181 + } 182 182 + 183 183 + static inline int pgd_bad(pgd_t pgd) 184 184 + { 185 185 + if (unlikely(pgd_val(pgd) & ~PAGE_MASK)) 186 186 + return 1; 187 187 + 188 188 + return 0; 189 189 + } 190 190 + 191 191 + static inline int pgd_present(pgd_t pgd) 192 192 + { 193 193 + return pgd_val(pgd) != (unsigned long)invalid_pud_table; 194 194 + } 195 195 + 196 196 + static inline void pgd_clear(pgd_t *pgdp) 197 197 + { 198 198 + pgd_val(*pgdp) = (unsigned long)invalid_pud_table; 199 199 + } 200 200 + 201 201 + #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 202 202 + 203 203 + static inline unsigned long pgd_page_vaddr(pgd_t pgd) 204 204 + { 205 205 + return pgd_val(pgd); 206 206 + } 207 207 + 208 208 + static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 209 209 + { 210 210 + return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(address); 211 211 + } 212 212 + 213 213 + static inline void set_pgd(pgd_t *pgd, pgd_t pgdval) 214 214 + { 215 215 + *pgd = pgdval; 216 216 + } 217 217 + 218 218 + #endif 176 219 177 220 #ifndef __PAGETABLE_PMD_FOLDED 178 221 /* ··· 358 281 * Initialize a new pgd / pmd table with invalid pointers. 359 282 */ 360 283 extern void pgd_init(unsigned long page); 284 284 + extern void pud_init(unsigned long page, unsigned long pagetable); 361 285 extern void pmd_init(unsigned long page, unsigned long pagetable); 362 286 363 287 /*

+29 -59

arch/mips/include/asm/uasm.h

reviewed

··· 21 21 #define UASM_EXPORT_SYMBOL(sym) 22 22 #endif 23 23 24 24 - #define _UASM_ISA_CLASSIC 0 25 25 - #define _UASM_ISA_MICROMIPS 1 26 26 - 27 27 - #ifndef UASM_ISA 28 28 - #ifdef CONFIG_CPU_MICROMIPS 29 29 - #define UASM_ISA _UASM_ISA_MICROMIPS 30 30 - #else 31 31 - #define UASM_ISA _UASM_ISA_CLASSIC 32 32 - #endif 33 33 - #endif 34 34 - 35 35 - #if (UASM_ISA == _UASM_ISA_CLASSIC) 36 36 - #ifdef CONFIG_CPU_MICROMIPS 37 37 - #define ISAOPC(op) CL_uasm_i##op 38 38 - #define ISAFUNC(x) CL_##x 39 39 - #else 40 40 - #define ISAOPC(op) uasm_i##op 41 41 - #define ISAFUNC(x) x 42 42 - #endif 43 43 - #elif (UASM_ISA == _UASM_ISA_MICROMIPS) 44 44 - #ifdef CONFIG_CPU_MICROMIPS 45 45 - #define ISAOPC(op) uasm_i##op 46 46 - #define ISAFUNC(x) x 47 47 - #else 48 48 - #define ISAOPC(op) MM_uasm_i##op 49 49 - #define ISAFUNC(x) MM_##x 50 50 - #endif 51 51 - #else 52 52 - #error Unsupported micro-assembler ISA!!! 53 53 - #endif 54 54 - 55 24 #define Ip_u1u2u3(op) \ 56 56 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 25 25 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 57 26 58 27 #define Ip_u2u1u3(op) \ 59 59 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 28 28 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 60 29 61 30 #define Ip_u3u2u1(op) \ 62 62 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 31 31 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 63 32 64 33 #define Ip_u3u1u2(op) \ 65 65 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 34 34 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 66 35 67 36 #define Ip_u1u2s3(op) \ 68 68 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) 37 37 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 69 38 70 39 #define Ip_u2s3u1(op) \ 71 71 - void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c) 40 40 + void uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) 72 41 73 42 #define Ip_s3s1s2(op) \ 74 74 - void ISAOPC(op)(u32 **buf, int a, int b, int c) 43 43 + void uasm_i##op(u32 **buf, int a, int b, int c) 75 44 76 45 #define Ip_u2u1s3(op) \ 77 77 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) 46 46 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 78 47 79 48 #define Ip_u2u1msbu3(op) \ 80 80 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ 49 49 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ 81 50 unsigned int d) 82 51 83 52 #define Ip_u1u2(op) \ 84 84 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) 53 53 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 85 54 86 55 #define Ip_u2u1(op) \ 87 87 - void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) 56 56 + void uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 88 57 89 58 #define Ip_u1s2(op) \ 90 90 - void ISAOPC(op)(u32 **buf, unsigned int a, signed int b) 59 59 + void uasm_i##op(u32 **buf, unsigned int a, signed int b) 91 60 92 92 - #define Ip_u1(op) void ISAOPC(op)(u32 **buf, unsigned int a) 61 61 + #define Ip_u1(op) void uasm_i##op(u32 **buf, unsigned int a) 93 62 94 94 - #define Ip_0(op) void ISAOPC(op)(u32 **buf) 63 63 + #define Ip_0(op) void uasm_i##op(u32 **buf) 95 64 96 65 Ip_u2u1s3(_addiu); 97 66 Ip_u3u1u2(_addu); ··· 107 138 Ip_u2s3u1(_ld); 108 139 Ip_u3u1u2(_ldx); 109 140 Ip_u2s3u1(_lh); 141 141 + Ip_u2s3u1(_lhu); 110 142 Ip_u2s3u1(_ll); 111 143 Ip_u2s3u1(_lld); 112 144 Ip_u1s2(_lui); ··· 160 190 int lab; 161 191 }; 162 192 163 163 - void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, 193 193 + void uasm_build_label(struct uasm_label **lab, u32 *addr, 164 194 int lid); 165 195 #ifdef CONFIG_64BIT 166 166 - int ISAFUNC(uasm_in_compat_space_p)(long addr); 196 196 + int uasm_in_compat_space_p(long addr); 167 197 #endif 168 168 - int ISAFUNC(uasm_rel_hi)(long val); 169 169 - int ISAFUNC(uasm_rel_lo)(long val); 170 170 - void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr); 171 171 - void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); 198 198 + int uasm_rel_hi(long val); 199 199 + int uasm_rel_lo(long val); 200 200 + void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); 201 201 + void UASM_i_LA(u32 **buf, unsigned int rs, long addr); 172 202 173 203 #define UASM_L_LA(lb) \ 174 174 - static inline void ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \ 204 204 + static inline void uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 175 205 { \ 176 176 - ISAFUNC(uasm_build_label)(lab, addr, label##lb); \ 206 206 + uasm_build_label(lab, addr, label##lb); \ 177 207 } 178 208 179 209 /* convenience macros for instructions */ ··· 225 255 unsigned int a2, unsigned int a3) 226 256 { 227 257 if (a3 < 32) 228 228 - ISAOPC(_drotr)(p, a1, a2, a3); 258 258 + uasm_i_drotr(p, a1, a2, a3); 229 259 else 230 230 - ISAOPC(_drotr32)(p, a1, a2, a3 - 32); 260 260 + uasm_i_drotr32(p, a1, a2, a3 - 32); 231 261 } 232 262 233 263 static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, 234 264 unsigned int a2, unsigned int a3) 235 265 { 236 266 if (a3 < 32) 237 237 - ISAOPC(_dsll)(p, a1, a2, a3); 267 267 + uasm_i_dsll(p, a1, a2, a3); 238 268 else 239 239 - ISAOPC(_dsll32)(p, a1, a2, a3 - 32); 269 269 + uasm_i_dsll32(p, a1, a2, a3 - 32); 240 270 } 241 271 242 272 static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, 243 273 unsigned int a2, unsigned int a3) 244 274 { 245 275 if (a3 < 32) 246 246 - ISAOPC(_dsrl)(p, a1, a2, a3); 276 276 + uasm_i_dsrl(p, a1, a2, a3); 247 277 else 248 248 - ISAOPC(_dsrl32)(p, a1, a2, a3 - 32); 278 278 + uasm_i_dsrl32(p, a1, a2, a3 - 32); 249 279 } 250 280 251 281 /* Handle relocations. */

+7

arch/mips/kernel/cpu-probe.c

reviewed

··· 34 34 35 35 /* Hardware capabilities */ 36 36 unsigned int elf_hwcap __read_mostly; 37 37 + EXPORT_SYMBOL_GPL(elf_hwcap); 37 38 38 39 /* 39 40 * Get the FPU Implementation/Revision. ··· 1955 1954 { 1956 1955 struct cpuinfo_mips *c = &current_cpu_data; 1957 1956 unsigned int cpu = smp_processor_id(); 1957 1957 + 1958 1958 + /* 1959 1959 + * Set a default elf platform, cpu probe may later 1960 1960 + * overwrite it with a more precise value 1961 1961 + */ 1962 1962 + set_elf_platform(cpu, "mips"); 1958 1963 1959 1964 c->processor_id = PRID_IMP_UNKNOWN; 1960 1965 c->fpu_id = FPIR_IMP_NONE;

+14 -2

arch/mips/kernel/mips-r2-to-r6-emul.c

reviewed

··· 1096 1096 } 1097 1097 break; 1098 1098 1099 1099 - case beql_op: 1100 1100 - case bnel_op: 1101 1099 case blezl_op: 1102 1100 case bgtzl_op: 1101 1101 + /* 1102 1102 + * For BLEZL and BGTZL, rt field must be set to 0. If this 1103 1103 + * is not the case, this may be an encoding of a MIPS R6 1104 1104 + * instruction, so return to CPU execution if this occurs 1105 1105 + */ 1106 1106 + if (MIPSInst_RT(inst)) { 1107 1107 + err = SIGILL; 1108 1108 + break; 1109 1109 + } 1110 1110 + /* fall through */ 1111 1111 + case beql_op: 1112 1112 + case bnel_op: 1103 1113 if (delay_slot(regs)) { 1104 1114 err = SIGILL; 1105 1115 break; ··· 2339 2329 __this_cpu_write((mipsr2bremustats).bgezl, 0); 2340 2330 __this_cpu_write((mipsr2bremustats).bltzll, 0); 2341 2331 __this_cpu_write((mipsr2bremustats).bgezll, 0); 2332 2332 + __this_cpu_write((mipsr2bremustats).bltzall, 0); 2333 2333 + __this_cpu_write((mipsr2bremustats).bgezall, 0); 2342 2334 __this_cpu_write((mipsr2bremustats).bltzal, 0); 2343 2335 __this_cpu_write((mipsr2bremustats).bgezal, 0); 2344 2336 __this_cpu_write((mipsr2bremustats).beql, 0);

+3 -3

arch/mips/kernel/process.c

reviewed

··· 114 114 /* 115 115 * Copy architecture-specific thread state 116 116 */ 117 117 - int copy_thread(unsigned long clone_flags, unsigned long usp, 118 118 - unsigned long kthread_arg, struct task_struct *p) 117 117 + int copy_thread_tls(unsigned long clone_flags, unsigned long usp, 118 118 + unsigned long kthread_arg, struct task_struct *p, unsigned long tls) 119 119 { 120 120 struct thread_info *ti = task_thread_info(p); 121 121 struct pt_regs *childregs, *regs = current_pt_regs(); ··· 176 176 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); 177 177 178 178 if (clone_flags & CLONE_SETTLS) 179 179 - ti->tp_value = regs->regs[7]; 179 179 + ti->tp_value = tls; 180 180 181 181 return 0; 182 182 }

-6

arch/mips/kernel/r4k_switch.S

reviewed

··· 25 25 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 26 26 #undef fp 27 27 28 28 - /* 29 29 - * Offset to the current process status flags, the first 32 bytes of the 30 30 - * stack are not used. 31 31 - */ 32 32 - #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) 33 33 - 34 28 #ifndef USE_ALTERNATE_RESUME_IMPL 35 29 /* 36 30 * task_struct *resume(task_struct *prev, task_struct *next,

+3 -4

arch/mips/kernel/smp-cps.c

reviewed

··· 8 8 * option) any later version. 9 9 */ 10 10 11 11 + #include <linux/cpu.h> 11 12 #include <linux/delay.h> 12 13 #include <linux/io.h> 13 14 #include <linux/irqchip/mips-gic.h> ··· 409 408 return 0; 410 409 } 411 410 412 412 - static DECLARE_COMPLETION(cpu_death_chosen); 413 411 static unsigned cpu_death_sibling; 414 412 static enum { 415 413 CPU_DEATH_HALT, ··· 443 443 } 444 444 445 445 /* This CPU has chosen its way out */ 446 446 - complete(&cpu_death_chosen); 446 446 + (void)cpu_report_death(); 447 447 448 448 if (cpu_death == CPU_DEATH_HALT) { 449 449 vpe_id = cpu_vpe_id(&cpu_data[cpu]); ··· 492 492 int err; 493 493 494 494 /* Wait for the cpu to choose its way out */ 495 495 - if (!wait_for_completion_timeout(&cpu_death_chosen, 496 496 - msecs_to_jiffies(5000))) { 495 495 + if (!cpu_wait_death(cpu, 5)) { 497 496 pr_err("CPU%u: didn't offline\n", cpu); 498 497 return; 499 498 }

+4 -45

arch/mips/kernel/smp-mt.c

reviewed

··· 83 83 if (tc != 0) 84 84 smvp_copy_vpe_config(); 85 85 86 86 + cpu_data[ncpu].vpe_id = tc; 87 87 + 86 88 return ncpu; 87 89 } 88 90 ··· 114 112 write_tc_c0_tcstatus(tmp); 115 113 116 114 write_tc_c0_tchalt(TCHALT_H); 117 117 - } 118 118 - 119 119 - static void vsmp_send_ipi_single(int cpu, unsigned int action) 120 120 - { 121 121 - int i; 122 122 - unsigned long flags; 123 123 - int vpflags; 124 124 - 125 125 - #ifdef CONFIG_MIPS_GIC 126 126 - if (gic_present) { 127 127 - mips_smp_send_ipi_single(cpu, action); 128 128 - return; 129 129 - } 130 130 - #endif 131 131 - local_irq_save(flags); 132 132 - 133 133 - vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ 134 134 - 135 135 - switch (action) { 136 136 - case SMP_CALL_FUNCTION: 137 137 - i = C_SW1; 138 138 - break; 139 139 - 140 140 - case SMP_RESCHEDULE_YOURSELF: 141 141 - default: 142 142 - i = C_SW0; 143 143 - break; 144 144 - } 145 145 - 146 146 - /* 1:1 mapping of vpe and tc... */ 147 147 - settc(cpu); 148 148 - write_vpe_c0_cause(read_vpe_c0_cause() | i); 149 149 - evpe(vpflags); 150 150 - 151 151 - local_irq_restore(flags); 152 152 - } 153 153 - 154 154 - static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) 155 155 - { 156 156 - unsigned int i; 157 157 - 158 158 - for_each_cpu(i, mask) 159 159 - vsmp_send_ipi_single(i, action); 160 115 } 161 116 162 117 static void vsmp_init_secondary(void) ··· 240 281 } 241 282 242 283 struct plat_smp_ops vsmp_smp_ops = { 243 243 - .send_ipi_single = vsmp_send_ipi_single, 244 244 - .send_ipi_mask = vsmp_send_ipi_mask, 284 284 + .send_ipi_single = mips_smp_send_ipi_single, 285 285 + .send_ipi_mask = mips_smp_send_ipi_mask, 245 286 .init_secondary = vsmp_init_secondary, 246 287 .smp_finish = vsmp_smp_finish, 247 288 .boot_secondary = vsmp_boot_secondary,

+12 -8

arch/mips/kernel/smp.c

reviewed

··· 261 261 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); 262 262 263 263 /* 264 264 - * There are systems which only use IPI domains some of the time, 265 265 - * depending upon configuration we don't know until runtime. An 266 266 - * example is Malta where we may compile in support for GIC & the 267 267 - * MT ASE, but run on a system which has multiple VPEs in a single 268 268 - * core and doesn't include a GIC. Until all IPI implementations 269 269 - * have been converted to use IPI domains the best we can do here 270 270 - * is to return & hope some other code sets up the IPIs. 264 264 + * There are systems which use IPI IRQ domains, but only have one 265 265 + * registered when some runtime condition is met. For example a Malta 266 266 + * kernel may include support for GIC & CPU interrupt controller IPI 267 267 + * IRQ domains, but if run on a system with no GIC & no MT ASE then 268 268 + * neither will be supported or registered. 269 269 + * 270 270 + * We only have a problem if we're actually using multiple CPUs so fail 271 271 + * loudly if that is the case. Otherwise simply return, skipping IPI 272 272 + * setup, if we're running with only a single CPU. 271 273 */ 272 272 - if (!ipidomain) 274 274 + if (!ipidomain) { 275 275 + BUG_ON(num_present_cpus() > 1); 273 276 return 0; 277 277 + } 274 278 275 279 virq = irq_reserve_ipi(ipidomain, mask); 276 280 BUG_ON(!virq);

-52

arch/mips/lantiq/irq.c

reviewed

··· 274 274 ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); 275 275 } 276 276 277 277 - #ifdef CONFIG_MIPS_MT_SMP 278 278 - void __init arch_init_ipiirq(int irq, struct irqaction *action) 279 279 - { 280 280 - setup_irq(irq, action); 281 281 - irq_set_handler(irq, handle_percpu_irq); 282 282 - } 283 283 - 284 284 - static void ltq_sw0_irqdispatch(void) 285 285 - { 286 286 - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 287 287 - } 288 288 - 289 289 - static void ltq_sw1_irqdispatch(void) 290 290 - { 291 291 - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); 292 292 - } 293 293 - static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 294 294 - { 295 295 - scheduler_ipi(); 296 296 - return IRQ_HANDLED; 297 297 - } 298 298 - 299 299 - static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) 300 300 - { 301 301 - generic_smp_call_function_interrupt(); 302 302 - return IRQ_HANDLED; 303 303 - } 304 304 - 305 305 - static struct irqaction irq_resched = { 306 306 - .handler = ipi_resched_interrupt, 307 307 - .flags = IRQF_PERCPU, 308 308 - .name = "IPI_resched" 309 309 - }; 310 310 - 311 311 - static struct irqaction irq_call = { 312 312 - .handler = ipi_call_interrupt, 313 313 - .flags = IRQF_PERCPU, 314 314 - .name = "IPI_call" 315 315 - }; 316 316 - #endif 317 317 - 318 277 asmlinkage void plat_irq_dispatch(void) 319 278 { 320 279 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; ··· 360 401 ltq_domain = irq_domain_add_linear(node, 361 402 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE, 362 403 &irq_domain_ops, 0); 363 363 - 364 364 - #if defined(CONFIG_MIPS_MT_SMP) 365 365 - if (cpu_has_vint) { 366 366 - pr_info("Setting up IPI vectored interrupts\n"); 367 367 - set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch); 368 368 - set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch); 369 369 - } 370 370 - arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ, 371 371 - &irq_resched); 372 372 - arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call); 373 373 - #endif 374 404 375 405 #ifndef CONFIG_MIPS_MT_SMP 376 406 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |

+6 -4

arch/mips/math-emu/cp1emu.c

reviewed

··· 439 439 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 440 440 unsigned int fcr31; 441 441 unsigned int bit = 0; 442 442 + unsigned int bit0; 443 443 + union fpureg *fpr; 442 444 443 445 switch (insn.i_format.opcode) { 444 446 case spec_op: ··· 708 706 ((insn.i_format.rs == bc1eqz_op) || 709 707 (insn.i_format.rs == bc1nez_op))) { 710 708 bit = 0; 709 709 + fpr = &current->thread.fpu.fpr[insn.i_format.rt]; 710 710 + bit0 = get_fpr32(fpr, 0) & 0x1; 711 711 switch (insn.i_format.rs) { 712 712 case bc1eqz_op: 713 713 - if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 714 714 - bit = 1; 713 713 + bit = bit0 == 0; 715 714 break; 716 715 case bc1nez_op: 717 717 - if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 718 718 - bit = 1; 716 716 + bit = bit0 != 0; 719 717 break; 720 718 } 721 719 if (bit)

+8 -8

arch/mips/mm/fault.c

reviewed

··· 267 267 /* Kernel mode? Handle exceptions or die */ 268 268 if (!user_mode(regs)) 269 269 goto no_context; 270 270 - else 270 270 + 271 271 /* 272 272 * Send a sigbus, regardless of whether we were in kernel 273 273 * or user mode. 274 274 */ 275 275 #if 0 276 276 - printk("do_page_fault() #3: sending SIGBUS to %s for " 277 277 - "invalid %s\n%0*lx (epc == %0*lx, ra == %0*lx)\n", 278 278 - tsk->comm, 279 279 - write ? "write access to" : "read access from", 280 280 - field, address, 281 281 - field, (unsigned long) regs->cp0_epc, 282 282 - field, (unsigned long) regs->regs[31]); 276 276 + printk("do_page_fault() #3: sending SIGBUS to %s for " 277 277 + "invalid %s\n%0*lx (epc == %0*lx, ra == %0*lx)\n", 278 278 + tsk->comm, 279 279 + write ? "write access to" : "read access from", 280 280 + field, address, 281 281 + field, (unsigned long) regs->cp0_epc, 282 282 + field, (unsigned long) regs->regs[31]); 283 283 #endif 284 284 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 285 285 tsk->thread.cp0_badvaddr = address;

+3

arch/mips/mm/init.c

reviewed

··· 537 537 * it in the linker script. 538 538 */ 539 539 pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir); 540 540 + #ifndef __PAGETABLE_PUD_FOLDED 541 541 + pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss; 542 542 + #endif 540 543 #ifndef __PAGETABLE_PMD_FOLDED 541 544 pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss; 542 545 EXPORT_SYMBOL_GPL(invalid_pmd_table);

+30 -3

arch/mips/mm/pgtable-64.c

reviewed

··· 19 19 unsigned long *p, *end; 20 20 unsigned long entry; 21 21 22 22 - #ifdef __PAGETABLE_PMD_FOLDED 23 23 - entry = (unsigned long)invalid_pte_table; 24 24 - #else 22 22 + #if !defined(__PAGETABLE_PUD_FOLDED) 23 23 + entry = (unsigned long)invalid_pud_table; 24 24 + #elif !defined(__PAGETABLE_PMD_FOLDED) 25 25 entry = (unsigned long)invalid_pmd_table; 26 26 + #else 27 27 + entry = (unsigned long)invalid_pte_table; 26 28 #endif 27 29 28 30 p = (unsigned long *) page; ··· 66 64 EXPORT_SYMBOL_GPL(pmd_init); 67 65 #endif 68 66 67 67 + #ifndef __PAGETABLE_PUD_FOLDED 68 68 + void pud_init(unsigned long addr, unsigned long pagetable) 69 69 + { 70 70 + unsigned long *p, *end; 71 71 + 72 72 + p = (unsigned long *)addr; 73 73 + end = p + PTRS_PER_PUD; 74 74 + 75 75 + do { 76 76 + p[0] = pagetable; 77 77 + p[1] = pagetable; 78 78 + p[2] = pagetable; 79 79 + p[3] = pagetable; 80 80 + p[4] = pagetable; 81 81 + p += 8; 82 82 + p[-3] = pagetable; 83 83 + p[-2] = pagetable; 84 84 + p[-1] = pagetable; 85 85 + } while (p != end); 86 86 + } 87 87 + #endif 88 88 + 69 89 pmd_t mk_pmd(struct page *page, pgprot_t prot) 70 90 { 71 91 pmd_t pmd; ··· 111 87 112 88 /* Initialize the entire pgd. */ 113 89 pgd_init((unsigned long)swapper_pg_dir); 90 90 + #ifndef __PAGETABLE_PUD_FOLDED 91 91 + pud_init((unsigned long)invalid_pud_table, (unsigned long)invalid_pmd_table); 92 92 + #endif 114 93 #ifndef __PAGETABLE_PMD_FOLDED 115 94 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); 116 95 #endif

+22

arch/mips/mm/tlbex.c

reviewed

··· 865 865 866 866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 867 867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 868 868 + #ifndef __PAGETABLE_PUD_FOLDED 869 869 + uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 870 870 + uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 871 871 + uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 872 872 + uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 873 873 + uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 874 874 + #endif 868 875 #ifndef __PAGETABLE_PMD_FOLDED 869 876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 870 877 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ ··· 1190 1183 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1191 1184 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1192 1185 } 1186 1186 + 1187 1187 + #ifndef __PAGETABLE_PUD_FOLDED 1188 1188 + /* get pud offset in bytes */ 1189 1189 + uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1190 1190 + uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1191 1191 + 1192 1192 + if (use_lwx_insns()) { 1193 1193 + UASM_i_LWX(p, ptr, scratch, ptr); 1194 1194 + } else { 1195 1195 + uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1196 1196 + UASM_i_LW(p, ptr, 0, ptr); 1197 1197 + } 1198 1198 + /* ptr contains a pointer to PMD entry */ 1199 1199 + /* tmp contains the address */ 1200 1200 + #endif 1193 1201 1194 1202 #ifndef __PAGETABLE_PMD_FOLDED 1195 1203 /* get pmd offset in bytes */

+1

arch/mips/mm/uasm-mips.c

reviewed

··· 103 103 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 104 104 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD }, 105 105 { insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 106 106 + { insn_lhu, M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 106 107 #ifndef CONFIG_CPU_MIPSR6 107 108 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 108 109 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },

+80 -79

arch/mips/mm/uasm.c

reviewed

··· 61 61 insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl, 62 62 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, 63 63 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, 64 64 - insn_xori, insn_yield, insn_lddir, insn_ldpte, 64 64 + insn_xori, insn_yield, insn_lddir, insn_ldpte, insn_lhu, 65 65 }; 66 66 67 67 struct insn { ··· 297 297 I_u2s3u1(_lb) 298 298 I_u2s3u1(_ld) 299 299 I_u2s3u1(_lh) 300 300 + I_u2s3u1(_lhu) 300 301 I_u2s3u1(_ll) 301 302 I_u2s3u1(_lld) 302 303 I_u1s2(_lui) ··· 350 349 351 350 #ifdef CONFIG_CPU_CAVIUM_OCTEON 352 351 #include <asm/octeon/octeon.h> 353 353 - void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, 352 352 + void uasm_i_pref(u32 **buf, unsigned int a, signed int b, 354 353 unsigned int c) 355 354 { 356 355 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) ··· 362 361 else 363 362 build_insn(buf, insn_pref, c, a, b); 364 363 } 365 365 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); 364 364 + UASM_EXPORT_SYMBOL(uasm_i_pref); 366 365 #else 367 366 I_u2s3u1(_pref) 368 367 #endif 369 368 370 369 /* Handle labels. */ 371 371 - void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) 370 370 + void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 372 371 { 373 372 (*lab)->addr = addr; 374 373 (*lab)->lab = lid; 375 374 (*lab)++; 376 375 } 377 377 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); 376 376 + UASM_EXPORT_SYMBOL(uasm_build_label); 378 377 379 379 - int ISAFUNC(uasm_in_compat_space_p)(long addr) 378 378 + int uasm_in_compat_space_p(long addr) 380 379 { 381 380 /* Is this address in 32bit compat space? */ 382 381 return addr == (int)addr; 383 382 } 384 384 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); 383 383 + UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); 385 384 386 385 static int uasm_rel_highest(long val) 387 386 { ··· 401 400 #endif 402 401 } 403 402 404 404 - int ISAFUNC(uasm_rel_hi)(long val) 403 403 + int uasm_rel_hi(long val) 405 404 { 406 405 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 407 406 } 408 408 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); 407 407 + UASM_EXPORT_SYMBOL(uasm_rel_hi); 409 408 410 410 - int ISAFUNC(uasm_rel_lo)(long val) 409 409 + int uasm_rel_lo(long val) 411 410 { 412 411 return ((val & 0xffff) ^ 0x8000) - 0x8000; 413 412 } 414 414 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); 413 413 + UASM_EXPORT_SYMBOL(uasm_rel_lo); 415 414 416 416 - void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) 415 415 + void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 417 416 { 418 418 - if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { 419 419 - ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); 417 417 + if (!uasm_in_compat_space_p(addr)) { 418 418 + uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 420 419 if (uasm_rel_higher(addr)) 421 421 - ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); 422 422 - if (ISAFUNC(uasm_rel_hi(addr))) { 423 423 - ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 424 424 - ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 425 425 - ISAFUNC(uasm_rel_hi)(addr)); 426 426 - ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); 420 420 + uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); 421 421 + if (uasm_rel_hi(addr)) { 422 422 + uasm_i_dsll(buf, rs, rs, 16); 423 423 + uasm_i_daddiu(buf, rs, rs, 424 424 + uasm_rel_hi(addr)); 425 425 + uasm_i_dsll(buf, rs, rs, 16); 427 426 } else 428 428 - ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); 427 427 + uasm_i_dsll32(buf, rs, rs, 0); 429 428 } else 430 430 - ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); 429 429 + uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 431 430 } 432 432 - UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); 431 431 + UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); 433 432 434 434 - void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) 433 433 + void UASM_i_LA(u32 **buf, unsigned int rs, long addr) 435 434 { 436 436 - ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); 437 437 - if (ISAFUNC(uasm_rel_lo(addr))) { 438 438 - if (!ISAFUNC(uasm_in_compat_space_p)(addr)) 439 439 - ISAFUNC(uasm_i_daddiu)(buf, rs, rs, 440 440 - ISAFUNC(uasm_rel_lo(addr))); 435 435 + UASM_i_LA_mostly(buf, rs, addr); 436 436 + if (uasm_rel_lo(addr)) { 437 437 + if (!uasm_in_compat_space_p(addr)) 438 438 + uasm_i_daddiu(buf, rs, rs, 439 439 + uasm_rel_lo(addr)); 441 440 else 442 442 - ISAFUNC(uasm_i_addiu)(buf, rs, rs, 443 443 - ISAFUNC(uasm_rel_lo(addr))); 441 441 + uasm_i_addiu(buf, rs, rs, 442 442 + uasm_rel_lo(addr)); 444 443 } 445 444 } 446 446 - UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); 445 445 + UASM_EXPORT_SYMBOL(UASM_i_LA); 447 446 448 447 /* Handle relocations. */ 449 449 - void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) 448 448 + void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 450 449 { 451 450 (*rel)->addr = addr; 452 451 (*rel)->type = R_MIPS_PC16; 453 452 (*rel)->lab = lid; 454 453 (*rel)++; 455 454 } 456 456 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); 455 455 + UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); 457 456 458 457 static inline void __resolve_relocs(struct uasm_reloc *rel, 459 458 struct uasm_label *lab); 460 459 461 461 - void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, 460 460 + void uasm_resolve_relocs(struct uasm_reloc *rel, 462 461 struct uasm_label *lab) 463 462 { 464 463 struct uasm_label *l; ··· 468 467 if (rel->lab == l->lab) 469 468 __resolve_relocs(rel, l); 470 469 } 471 471 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); 470 470 + UASM_EXPORT_SYMBOL(uasm_resolve_relocs); 472 471 473 473 - void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, 472 472 + void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, 474 473 long off) 475 474 { 476 475 for (; rel->lab != UASM_LABEL_INVALID; rel++) 477 476 if (rel->addr >= first && rel->addr < end) 478 477 rel->addr += off; 479 478 } 480 480 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); 479 479 + UASM_EXPORT_SYMBOL(uasm_move_relocs); 481 480 482 482 - void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, 481 481 + void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, 483 482 long off) 484 483 { 485 484 for (; lab->lab != UASM_LABEL_INVALID; lab++) 486 485 if (lab->addr >= first && lab->addr < end) 487 486 lab->addr += off; 488 487 } 489 489 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); 488 488 + UASM_EXPORT_SYMBOL(uasm_move_labels); 490 489 491 491 - void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, 490 490 + void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, 492 491 u32 *first, u32 *end, u32 *target) 493 492 { 494 493 long off = (long)(target - first); 495 494 496 495 memcpy(target, first, (end - first) * sizeof(u32)); 497 496 498 498 - ISAFUNC(uasm_move_relocs(rel, first, end, off)); 499 499 - ISAFUNC(uasm_move_labels(lab, first, end, off)); 497 497 + uasm_move_relocs(rel, first, end, off); 498 498 + uasm_move_labels(lab, first, end, off); 500 499 } 501 501 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); 500 500 + UASM_EXPORT_SYMBOL(uasm_copy_handler); 502 501 503 503 - int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) 502 502 + int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 504 503 { 505 504 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 506 505 if (rel->addr == addr ··· 511 510 512 511 return 0; 513 512 } 514 514 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); 513 513 + UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); 515 514 516 515 /* Convenience functions for labeled branches. */ 517 517 - void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 516 516 + void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, 518 517 int lid) 519 518 { 520 519 uasm_r_mips_pc16(r, *p, lid); 521 521 - ISAFUNC(uasm_i_bltz)(p, reg, 0); 520 520 + uasm_i_bltz(p, reg, 0); 522 521 } 523 523 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); 522 522 + UASM_EXPORT_SYMBOL(uasm_il_bltz); 524 523 525 525 - void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) 524 524 + void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 526 525 { 527 526 uasm_r_mips_pc16(r, *p, lid); 528 528 - ISAFUNC(uasm_i_b)(p, 0); 527 527 + uasm_i_b(p, 0); 529 528 } 530 530 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); 529 529 + UASM_EXPORT_SYMBOL(uasm_il_b); 531 530 532 532 - void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, 531 531 + void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1, 533 532 unsigned int r2, int lid) 534 533 { 535 534 uasm_r_mips_pc16(r, *p, lid); 536 536 - ISAFUNC(uasm_i_beq)(p, r1, r2, 0); 535 535 + uasm_i_beq(p, r1, r2, 0); 537 536 } 538 538 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); 537 537 + UASM_EXPORT_SYMBOL(uasm_il_beq); 539 538 540 540 - void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, 539 539 + void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, 541 540 int lid) 542 541 { 543 542 uasm_r_mips_pc16(r, *p, lid); 544 544 - ISAFUNC(uasm_i_beqz)(p, reg, 0); 543 543 + uasm_i_beqz(p, reg, 0); 545 544 } 546 546 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); 545 545 + UASM_EXPORT_SYMBOL(uasm_il_beqz); 547 546 548 548 - void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 547 547 + void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, 549 548 int lid) 550 549 { 551 550 uasm_r_mips_pc16(r, *p, lid); 552 552 - ISAFUNC(uasm_i_beqzl)(p, reg, 0); 551 551 + uasm_i_beqzl(p, reg, 0); 553 552 } 554 554 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); 553 553 + UASM_EXPORT_SYMBOL(uasm_il_beqzl); 555 554 556 556 - void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, 555 555 + void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 557 556 unsigned int reg2, int lid) 558 557 { 559 558 uasm_r_mips_pc16(r, *p, lid); 560 560 - ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); 559 559 + uasm_i_bne(p, reg1, reg2, 0); 561 560 } 562 562 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); 561 561 + UASM_EXPORT_SYMBOL(uasm_il_bne); 563 562 564 564 - void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 563 563 + void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, 565 564 int lid) 566 565 { 567 566 uasm_r_mips_pc16(r, *p, lid); 568 568 - ISAFUNC(uasm_i_bnez)(p, reg, 0); 567 567 + uasm_i_bnez(p, reg, 0); 569 568 } 570 570 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); 569 569 + UASM_EXPORT_SYMBOL(uasm_il_bnez); 571 570 572 572 - void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, 571 571 + void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, 573 572 int lid) 574 573 { 575 574 uasm_r_mips_pc16(r, *p, lid); 576 576 - ISAFUNC(uasm_i_bgezl)(p, reg, 0); 575 575 + uasm_i_bgezl(p, reg, 0); 577 576 } 578 578 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); 577 577 + UASM_EXPORT_SYMBOL(uasm_il_bgezl); 579 578 580 580 - void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, 579 579 + void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, 581 580 int lid) 582 581 { 583 582 uasm_r_mips_pc16(r, *p, lid); 584 584 - ISAFUNC(uasm_i_bgez)(p, reg, 0); 583 583 + uasm_i_bgez(p, reg, 0); 585 584 } 586 586 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); 585 585 + UASM_EXPORT_SYMBOL(uasm_il_bgez); 587 586 588 588 - void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, 587 587 + void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, 589 588 unsigned int bit, int lid) 590 589 { 591 590 uasm_r_mips_pc16(r, *p, lid); 592 592 - ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); 591 591 + uasm_i_bbit0(p, reg, bit, 0); 593 592 } 594 594 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); 593 593 + UASM_EXPORT_SYMBOL(uasm_il_bbit0); 595 594 596 596 - void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, 595 595 + void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, 597 596 unsigned int bit, int lid) 598 597 { 599 598 uasm_r_mips_pc16(r, *p, lid); 600 600 - ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); 599 599 + uasm_i_bbit1(p, reg, bit, 0); 601 600 } 602 602 - UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); 601 601 + UASM_EXPORT_SYMBOL(uasm_il_bbit1);

+4 -79

arch/mips/mti-malta/malta-int.c

reviewed

··· 145 145 return IRQ_HANDLED; 146 146 } 147 147 148 148 - #ifdef CONFIG_MIPS_MT_SMP 149 149 - 150 150 - #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ 151 151 - #define C_RESCHED C_SW0 152 152 - #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ 153 153 - #define C_CALL C_SW1 154 154 - static int cpu_ipi_resched_irq, cpu_ipi_call_irq; 155 155 - 156 156 - static void ipi_resched_dispatch(void) 157 157 - { 158 158 - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 159 159 - } 160 160 - 161 161 - static void ipi_call_dispatch(void) 162 162 - { 163 163 - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); 164 164 - } 165 165 - 166 166 - static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 167 167 - { 168 168 - #ifdef CONFIG_MIPS_VPE_APSP_API_CMP 169 169 - if (aprp_hook) 170 170 - aprp_hook(); 171 171 - #endif 172 172 - 173 173 - scheduler_ipi(); 174 174 - 175 175 - return IRQ_HANDLED; 176 176 - } 177 177 - 178 178 - static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) 179 179 - { 180 180 - generic_smp_call_function_interrupt(); 181 181 - 182 182 - return IRQ_HANDLED; 183 183 - } 184 184 - 185 185 - static struct irqaction irq_resched = { 186 186 - .handler = ipi_resched_interrupt, 187 187 - .flags = IRQF_PERCPU, 188 188 - .name = "IPI_resched" 189 189 - }; 190 190 - 191 191 - static struct irqaction irq_call = { 192 192 - .handler = ipi_call_interrupt, 193 193 - .flags = IRQF_PERCPU, 194 194 - .name = "IPI_call" 195 195 - }; 196 196 - #endif /* CONFIG_MIPS_MT_SMP */ 197 197 - 198 148 static struct irqaction corehi_irqaction = { 199 149 .handler = corehi_handler, 200 150 .name = "CoreHi", ··· 171 221 }; 172 222 173 223 static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap); 174 174 - 175 175 - void __init arch_init_ipiirq(int irq, struct irqaction *action) 176 176 - { 177 177 - setup_irq(irq, action); 178 178 - irq_set_handler(irq, handle_percpu_irq); 179 179 - } 180 224 181 225 void __init arch_init_irq(void) 182 226 { ··· 217 273 218 274 if (gic_present) { 219 275 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; 276 276 + } else if (cpu_has_veic) { 277 277 + set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 278 278 + corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; 220 279 } else { 221 221 - #if defined(CONFIG_MIPS_MT_SMP) 222 222 - /* set up ipi interrupts */ 223 223 - if (cpu_has_veic) { 224 224 - set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); 225 225 - set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); 226 226 - cpu_ipi_resched_irq = MSC01E_INT_SW0; 227 227 - cpu_ipi_call_irq = MSC01E_INT_SW1; 228 228 - } else { 229 229 - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + 230 230 - MIPS_CPU_IPI_RESCHED_IRQ; 231 231 - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + 232 232 - MIPS_CPU_IPI_CALL_IRQ; 233 233 - } 234 234 - arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 235 235 - arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); 236 236 - #endif 237 237 - if (cpu_has_veic) { 238 238 - set_vi_handler(MSC01E_INT_COREHI, 239 239 - corehi_irqdispatch); 240 240 - corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; 241 241 - } else { 242 242 - corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; 243 243 - } 280 280 + corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; 244 281 } 245 282 246 283 setup_irq(corehi_irq, &corehi_irqaction);

+31 -10

arch/mips/net/bpf_jit.c

reviewed

··· 365 365 emit_instr(ctx, lh, reg, offset, base); 366 366 } 367 367 368 368 + static inline void emit_half_load_unsigned(unsigned int reg, unsigned int base, 369 369 + unsigned int offset, struct jit_ctx *ctx) 370 370 + { 371 371 + emit_instr(ctx, lhu, reg, offset, base); 372 372 + } 373 373 + 368 374 static inline void emit_mul(unsigned int dst, unsigned int src1, 369 375 unsigned int src2, struct jit_ctx *ctx) 370 376 { ··· 532 526 u32 sflags, tmp_flags; 533 527 534 528 /* Adjust the stack pointer */ 535 535 - emit_stack_offset(-align_sp(offset), ctx); 529 529 + if (offset) 530 530 + emit_stack_offset(-align_sp(offset), ctx); 536 531 537 532 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; 538 533 /* sflags is essentially a bitmap */ ··· 585 578 emit_load_stack_reg(r_ra, r_sp, real_off, ctx); 586 579 587 580 /* Restore the sp and discard the scrach memory */ 588 588 - emit_stack_offset(align_sp(offset), ctx); 581 581 + if (offset) 582 582 + emit_stack_offset(align_sp(offset), ctx); 589 583 } 590 584 591 585 static unsigned int get_stack_depth(struct jit_ctx *ctx) ··· 633 625 if (ctx->flags & SEEN_X) 634 626 emit_jit_reg_move(r_X, r_zero, ctx); 635 627 636 636 - /* Do not leak kernel data to userspace */ 637 637 - if (bpf_needs_clear_a(&ctx->skf->insns[0])) 628 628 + /* 629 629 + * Do not leak kernel data to userspace, we only need to clear 630 630 + * r_A if it is ever used. In fact if it is never used, we 631 631 + * will not save/restore it, so clearing it in this case would 632 632 + * corrupt the state of the caller. 633 633 + */ 634 634 + if (bpf_needs_clear_a(&ctx->skf->insns[0]) && 635 635 + (ctx->flags & SEEN_A)) 638 636 emit_jit_reg_move(r_A, r_zero, ctx); 639 637 } 640 638 ··· 1126 1112 break; 1127 1113 case BPF_ANC | SKF_AD_IFINDEX: 1128 1114 /* A = skb->dev->ifindex */ 1115 1115 + case BPF_ANC | SKF_AD_HATYPE: 1116 1116 + /* A = skb->dev->type */ 1129 1117 ctx->flags |= SEEN_SKB | SEEN_A; 1130 1118 off = offsetof(struct sk_buff, dev); 1131 1119 /* Load *dev pointer */ ··· 1136 1120 emit_bcond(MIPS_COND_EQ, r_s0, r_zero, 1137 1121 b_imm(prog->len, ctx), ctx); 1138 1122 emit_reg_move(r_ret, r_zero, ctx); 1139 1139 - BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, 1140 1140 - ifindex) != 4); 1141 1141 - off = offsetof(struct net_device, ifindex); 1142 1142 - emit_load(r_A, r_s0, off, ctx); 1123 1123 + if (code == (BPF_ANC | SKF_AD_IFINDEX)) { 1124 1124 + BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, ifindex) != 4); 1125 1125 + off = offsetof(struct net_device, ifindex); 1126 1126 + emit_load(r_A, r_s0, off, ctx); 1127 1127 + } else { /* (code == (BPF_ANC | SKF_AD_HATYPE) */ 1128 1128 + BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, type) != 2); 1129 1129 + off = offsetof(struct net_device, type); 1130 1130 + emit_half_load_unsigned(r_A, r_s0, off, ctx); 1131 1131 + } 1143 1132 break; 1144 1133 case BPF_ANC | SKF_AD_MARK: 1145 1134 ctx->flags |= SEEN_SKB | SEEN_A; ··· 1164 1143 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, 1165 1144 vlan_tci) != 2); 1166 1145 off = offsetof(struct sk_buff, vlan_tci); 1167 1167 - emit_half_load(r_s0, r_skb, off, ctx); 1146 1146 + emit_half_load_unsigned(r_s0, r_skb, off, ctx); 1168 1147 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) { 1169 1148 emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx); 1170 1149 } else { ··· 1191 1170 BUILD_BUG_ON(offsetof(struct sk_buff, 1192 1171 queue_mapping) > 0xff); 1193 1172 off = offsetof(struct sk_buff, queue_mapping); 1194 1194 - emit_half_load(r_A, r_skb, off, ctx); 1173 1173 + emit_half_load_unsigned(r_A, r_skb, off, ctx); 1195 1174 break; 1196 1175 default: 1197 1176 pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__,

+12 -11

arch/mips/net/bpf_jit_asm.S

reviewed

··· 90 90 is_offset_in_header(2, half) 91 91 /* Offset within header boundaries */ 92 92 PTR_ADDU t1, $r_skb_data, offset 93 93 - .set reorder 94 94 - lh $r_A, 0(t1) 95 95 - .set noreorder 93 93 + lhu $r_A, 0(t1) 96 94 #ifdef CONFIG_CPU_LITTLE_ENDIAN 97 95 # if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 98 98 - wsbh t0, $r_A 99 99 - seh $r_A, t0 96 96 + wsbh $r_A, $r_A 100 97 # else 101 101 - sll t0, $r_A, 24 102 102 - andi t1, $r_A, 0xff00 103 103 - sra t0, t0, 16 104 104 - srl t1, t1, 8 98 98 + sll t0, $r_A, 8 99 99 + srl t1, $r_A, 8 100 100 + andi t0, t0, 0xff00 105 101 or $r_A, t0, t1 106 102 # endif 107 103 #endif ··· 111 115 is_offset_in_header(1, byte) 112 116 /* Offset within header boundaries */ 113 117 PTR_ADDU t1, $r_skb_data, offset 114 114 - lb $r_A, 0(t1) 118 118 + lbu $r_A, 0(t1) 115 119 jr $r_ra 116 120 move $r_ret, zero 117 121 END(sk_load_byte) ··· 135 139 * (void *to) is returned in r_s0 136 140 * 137 141 */ 142 142 + #ifdef CONFIG_CPU_LITTLE_ENDIAN 143 143 + #define DS_OFFSET(SIZE) (4 * SZREG) 144 144 + #else 145 145 + #define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE)) 146 146 + #endif 138 147 #define bpf_slow_path_common(SIZE) \ 139 148 /* Quick check. Are we within reasonable boundaries? */ \ 140 149 LONG_ADDIU $r_s1, $r_skb_len, -SIZE; \ ··· 151 150 PTR_LA t0, skb_copy_bits; \ 152 151 PTR_S $r_ra, (5 * SZREG)($r_sp); \ 153 152 /* Assign low slot to a2 */ \ 154 154 - move a2, $r_sp; \ 153 153 + PTR_ADDIU a2, $r_sp, DS_OFFSET(SIZE); \ 155 154 jalr t0; \ 156 155 /* Reset our destination slot (DS but it's ok) */ \ 157 156 INT_S zero, (4 * SZREG)($r_sp); \

+2 -2

arch/mips/pci/pcie-octeon.c

reviewed

··· 679 679 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 680 680 pmas->cn68xx.ba++; 681 681 else 682 682 - pmas->cn63xx.ba++; 682 682 + pmas->s.ba++; 683 683 } 684 684 685 685 /** ··· 1351 1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 1352 1352 mem_access_subid.cn68xx.ba = 0; 1353 1353 else 1354 1354 - mem_access_subid.cn63xx.ba = 0; 1354 1354 + mem_access_subid.s.ba = 0; 1355 1355 1356 1356 /* 1357 1357 * Setup mem access 12-15 for port 0, 16-19 for port 1,

+1

arch/mips/sibyte/bcm1480/setup.c

reviewed

··· 36 36 unsigned int soc_type; 37 37 EXPORT_SYMBOL(soc_type); 38 38 unsigned int periph_rev; 39 39 + EXPORT_SYMBOL_GPL(periph_rev); 39 40 unsigned int zbbus_mhz; 40 41 EXPORT_SYMBOL(zbbus_mhz); 41 42

+1

arch/mips/sibyte/sb1250/setup.c

reviewed

··· 34 34 unsigned int soc_type; 35 35 EXPORT_SYMBOL(soc_type); 36 36 unsigned int periph_rev; 37 37 + EXPORT_SYMBOL_GPL(periph_rev); 37 38 unsigned int zbbus_mhz; 38 39 EXPORT_SYMBOL(zbbus_mhz); 39 40

-7

drivers/cpufreq/loongson2_cpufreq.c

reviewed

··· 51 51 static int loongson2_cpufreq_target(struct cpufreq_policy *policy, 52 52 unsigned int index) 53 53 { 54 54 - unsigned int cpu = policy->cpu; 55 55 - cpumask_t cpus_allowed; 56 54 unsigned int freq; 57 57 - 58 58 - cpus_allowed = current->cpus_allowed; 59 59 - set_cpus_allowed_ptr(current, cpumask_of(cpu)); 60 55 61 56 freq = 62 57 ((cpu_clock_freq / 1000) * 63 58 loongson2_clockmod_table[index].driver_data) / 8; 64 64 - 65 65 - set_cpus_allowed_ptr(current, &cpus_allowed); 66 59 67 60 /* setting the cpu frequency */ 68 61 clk_set_rate(policy->clk, freq * 1000);

+2

drivers/irqchip/Kconfig

reviewed

··· 134 134 config IRQ_MIPS_CPU 135 135 bool 136 136 select GENERIC_IRQ_CHIP 137 137 + select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 137 138 select IRQ_DOMAIN 139 139 + select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 138 140 139 141 config CLPS711X_IRQCHIP 140 142 bool

+129 -17

drivers/irqchip/irq-mips-cpu.c

reviewed

··· 17 17 /* 18 18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically 19 19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from 20 20 - * device). The first two are software interrupts which we don't really 21 21 - * use or support. The last one is usually the CPU timer interrupt if 22 22 - * counter register is present or, for CPUs with an external FPU, by 23 23 - * convention it's the FPU exception interrupt. 20 20 + * device). 24 21 * 25 25 - * Don't even think about using this on SMP. You have been warned. 22 22 + * The first two are software interrupts (i.e. not exposed as pins) which 23 23 + * may be used for IPIs in multi-threaded single-core systems. 26 24 * 27 27 - * This file exports one global function: 28 28 - * void mips_cpu_irq_init(void); 25 25 + * The last one is usually the CPU timer interrupt if the counter register 26 26 + * is present, or for old CPUs with an external FPU by convention it's the 27 27 + * FPU exception interrupt. 29 28 */ 30 29 #include <linux/init.h> 31 30 #include <linux/interrupt.h> ··· 38 39 #include <asm/mipsmtregs.h> 39 40 #include <asm/setup.h> 40 41 42 42 + static struct irq_domain *irq_domain; 43 43 + static struct irq_domain *ipi_domain; 44 44 + 41 45 static inline void unmask_mips_irq(struct irq_data *d) 42 46 { 43 43 - set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 47 47 + set_c0_status(IE_SW0 << d->hwirq); 44 48 irq_enable_hazard(); 45 49 } 46 50 47 51 static inline void mask_mips_irq(struct irq_data *d) 48 52 { 49 49 - clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 53 53 + clear_c0_status(IE_SW0 << d->hwirq); 50 54 irq_disable_hazard(); 51 55 } 52 56 ··· 72 70 { 73 71 unsigned int vpflags = dvpe(); 74 72 75 75 - clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 73 73 + clear_c0_cause(C_SW0 << d->hwirq); 76 74 evpe(vpflags); 77 75 unmask_mips_irq(d); 78 76 return 0; ··· 85 83 static void mips_mt_cpu_irq_ack(struct irq_data *d) 86 84 { 87 85 unsigned int vpflags = dvpe(); 88 88 - clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 86 86 + clear_c0_cause(C_SW0 << d->hwirq); 89 87 evpe(vpflags); 90 88 mask_mips_irq(d); 91 89 } 90 90 + 91 91 + #ifdef CONFIG_GENERIC_IRQ_IPI 92 92 + 93 93 + static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu) 94 94 + { 95 95 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 96 96 + unsigned long flags; 97 97 + int vpflags; 98 98 + 99 99 + local_irq_save(flags); 100 100 + 101 101 + /* We can only send IPIs to VPEs within the local core */ 102 102 + WARN_ON(cpu_data[cpu].core != current_cpu_data.core); 103 103 + 104 104 + vpflags = dvpe(); 105 105 + settc(cpu_vpe_id(&cpu_data[cpu])); 106 106 + write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq)); 107 107 + evpe(vpflags); 108 108 + 109 109 + local_irq_restore(flags); 110 110 + } 111 111 + 112 112 + #endif /* CONFIG_GENERIC_IRQ_IPI */ 92 113 93 114 static struct irq_chip mips_mt_cpu_irq_controller = { 94 115 .name = "MIPS", ··· 123 98 .irq_eoi = unmask_mips_irq, 124 99 .irq_disable = mask_mips_irq, 125 100 .irq_enable = unmask_mips_irq, 101 101 + #ifdef CONFIG_GENERIC_IRQ_IPI 102 102 + .ipi_send_single = mips_mt_send_ipi, 103 103 + #endif 126 104 }; 127 105 128 106 asmlinkage void __weak plat_irq_dispatch(void) 129 107 { 130 108 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM; 109 109 + unsigned int virq; 131 110 int irq; 132 111 133 112 if (!pending) { ··· 142 113 pending >>= CAUSEB_IP; 143 114 while (pending) { 144 115 irq = fls(pending) - 1; 145 145 - do_IRQ(MIPS_CPU_IRQ_BASE + irq); 116 116 + if (IS_ENABLED(CONFIG_GENERIC_IRQ_IPI) && irq < 2) 117 117 + virq = irq_linear_revmap(ipi_domain, irq); 118 118 + else 119 119 + virq = irq_linear_revmap(irq_domain, irq); 120 120 + do_IRQ(virq); 146 121 pending &= ~BIT(irq); 147 122 } 148 123 } ··· 176 143 .xlate = irq_domain_xlate_onecell, 177 144 }; 178 145 146 146 + #ifdef CONFIG_GENERIC_IRQ_IPI 147 147 + 148 148 + struct cpu_ipi_domain_state { 149 149 + DECLARE_BITMAP(allocated, 2); 150 150 + }; 151 151 + 152 152 + static int mips_cpu_ipi_alloc(struct irq_domain *domain, unsigned int virq, 153 153 + unsigned int nr_irqs, void *arg) 154 154 + { 155 155 + struct cpu_ipi_domain_state *state = domain->host_data; 156 156 + unsigned int i, hwirq; 157 157 + int ret; 158 158 + 159 159 + for (i = 0; i < nr_irqs; i++) { 160 160 + hwirq = find_first_zero_bit(state->allocated, 2); 161 161 + if (hwirq == 2) 162 162 + return -EBUSY; 163 163 + bitmap_set(state->allocated, hwirq, 1); 164 164 + 165 165 + ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq, 166 166 + &mips_mt_cpu_irq_controller, 167 167 + NULL); 168 168 + if (ret) 169 169 + return ret; 170 170 + 171 171 + ret = irq_set_irq_type(virq + i, IRQ_TYPE_LEVEL_HIGH); 172 172 + if (ret) 173 173 + return ret; 174 174 + } 175 175 + 176 176 + return 0; 177 177 + } 178 178 + 179 179 + static int mips_cpu_ipi_match(struct irq_domain *d, struct device_node *node, 180 180 + enum irq_domain_bus_token bus_token) 181 181 + { 182 182 + bool is_ipi; 183 183 + 184 184 + switch (bus_token) { 185 185 + case DOMAIN_BUS_IPI: 186 186 + is_ipi = d->bus_token == bus_token; 187 187 + return (!node || (to_of_node(d->fwnode) == node)) && is_ipi; 188 188 + default: 189 189 + return 0; 190 190 + } 191 191 + } 192 192 + 193 193 + static const struct irq_domain_ops mips_cpu_ipi_chip_ops = { 194 194 + .alloc = mips_cpu_ipi_alloc, 195 195 + .match = mips_cpu_ipi_match, 196 196 + }; 197 197 + 198 198 + static void mips_cpu_register_ipi_domain(struct device_node *of_node) 199 199 + { 200 200 + struct cpu_ipi_domain_state *ipi_domain_state; 201 201 + 202 202 + ipi_domain_state = kzalloc(sizeof(*ipi_domain_state), GFP_KERNEL); 203 203 + ipi_domain = irq_domain_add_hierarchy(irq_domain, 204 204 + IRQ_DOMAIN_FLAG_IPI_SINGLE, 205 205 + 2, of_node, 206 206 + &mips_cpu_ipi_chip_ops, 207 207 + ipi_domain_state); 208 208 + if (!ipi_domain) 209 209 + panic("Failed to add MIPS CPU IPI domain"); 210 210 + ipi_domain->bus_token = DOMAIN_BUS_IPI; 211 211 + } 212 212 + 213 213 + #else /* !CONFIG_GENERIC_IRQ_IPI */ 214 214 + 215 215 + static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {} 216 216 + 217 217 + #endif /* !CONFIG_GENERIC_IRQ_IPI */ 218 218 + 179 219 static void __init __mips_cpu_irq_init(struct device_node *of_node) 180 220 { 181 181 - struct irq_domain *domain; 182 182 - 183 221 /* Mask interrupts. */ 184 222 clear_c0_status(ST0_IM); 185 223 clear_c0_cause(CAUSEF_IP); 186 224 187 187 - domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, 188 188 - &mips_cpu_intc_irq_domain_ops, NULL); 189 189 - if (!domain) 225 225 + irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, 226 226 + &mips_cpu_intc_irq_domain_ops, 227 227 + NULL); 228 228 + if (!irq_domain) 190 229 panic("Failed to add irqdomain for MIPS CPU"); 230 230 + 231 231 + /* 232 232 + * Only proceed to register the software interrupt IPI implementation 233 233 + * for CPUs which implement the MIPS MT (multi-threading) ASE. 234 234 + */ 235 235 + if (cpu_has_mipsmt) 236 236 + mips_cpu_register_ipi_domain(of_node); 191 237 } 192 238 193 239 void __init mips_cpu_irq_init(void)

+1

drivers/net/ethernet/broadcom/sb1250-mac.c

reviewed

··· 2641 2641 }; 2642 2642 2643 2643 module_platform_driver(sbmac_driver); 2644 2644 + MODULE_LICENSE("GPL");