+3 -3

arch/x86/events/amd/ibs.c

reviewed

··· 1748 1748 1749 1749 static inline int get_eilvt(int offset) 1750 1750 { 1751 1751 - return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1); 1751 1751 + return !setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 1); 1752 1752 } 1753 1753 1754 1754 static inline int put_eilvt(int offset) ··· 1897 1897 if (offset < 0) 1898 1898 goto failed; 1899 1899 1900 1900 - if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0)) 1900 1900 + if (!setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 0)) 1901 1901 return; 1902 1902 failed: 1903 1903 pr_warn("perf: IBS APIC setup failed on cpu #%d\n", ··· 1910 1910 1911 1911 offset = get_ibs_lvt_offset(); 1912 1912 if (offset >= 0) 1913 1913 - setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1); 1913 1913 + setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_FIXED, 1); 1914 1914 } 1915 1915 1916 1916 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)

-7

arch/x86/include/asm/apicdef.h

reviewed

··· 138 138 #define APIC_SEOI 0x420 139 139 #define APIC_IER 0x480 140 140 #define APIC_EILVTn(n) (0x500 + 0x10 * n) 141 141 - #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 142 141 #define APIC_EILVT_NR_AMD_10H 4 143 142 #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H 144 144 - #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 145 145 - #define APIC_EILVT_MSG_FIX 0x0 146 146 - #define APIC_EILVT_MSG_SMI 0x2 147 147 - #define APIC_EILVT_MSG_NMI 0x4 148 148 - #define APIC_EILVT_MSG_EXT 0x7 149 149 - #define APIC_EILVT_MASKED (1 << 16) 150 143 151 144 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 152 145 #define APIC_BASE_MSR 0x800

+22 -5

arch/x86/include/asm/floppy.h

reviewed

··· 29 29 #define CSW fd_routine[can_use_virtual_dma & 1] 30 30 31 31 32 32 - #define fd_inb(base, reg) inb_p((base) + (reg)) 33 33 - #define fd_outb(value, base, reg) outb_p(value, (base) + (reg)) 34 34 - 35 32 #define fd_request_dma() CSW._request_dma(FLOPPY_DMA, "floppy") 36 33 #define fd_free_dma() CSW._free_dma(FLOPPY_DMA) 37 34 #define fd_enable_irq() enable_irq(FLOPPY_IRQ) ··· 45 48 static char *virtual_dma_addr; 46 49 static int virtual_dma_mode; 47 50 static int doing_pdma; 51 51 + 52 52 + static inline u8 fd_inb(u16 base, u16 reg) 53 53 + { 54 54 + u8 ret = inb_p(base + reg); 55 55 + 56 56 + native_io_delay(); 57 57 + native_io_delay(); 58 58 + native_io_delay(); 59 59 + 60 60 + return ret; 61 61 + } 62 62 + 63 63 + static inline void fd_outb(u8 value, u16 base, u16 reg) 64 64 + { 65 65 + outb_p(value, base + reg); 66 66 + 67 67 + native_io_delay(); 68 68 + native_io_delay(); 69 69 + native_io_delay(); 70 70 + } 48 71 49 72 static irqreturn_t floppy_hardint(int irq, void *dev_id) 50 73 { ··· 96 79 if (st != (STATUS_DMA | STATUS_READY)) 97 80 break; 98 81 if (virtual_dma_mode) 99 99 - outb_p(*lptr, virtual_dma_port + FD_DATA); 82 82 + fd_outb(*lptr, virtual_dma_port, FD_DATA); 100 83 else 101 101 - *lptr = inb_p(virtual_dma_port + FD_DATA); 84 84 + *lptr = fd_inb(virtual_dma_port, FD_DATA); 102 85 } 103 86 virtual_dma_count = lcount; 104 87 virtual_dma_addr = lptr;

+1 -1

arch/x86/include/asm/fpu/xcr.h

reviewed

··· 23 23 24 24 /* 25 25 * Return a mask of xfeatures which are currently being tracked 26 26 - * by the processor as being in the initial configuration. 26 26 + * by the processor as being not in the initial configuration. 27 27 * 28 28 * Callers should check X86_FEATURE_XGETBV1. 29 29 */

+9 -12

arch/x86/include/asm/io.h

reviewed

··· 218 218 size_t count) 219 219 { 220 220 asm volatile("rep movsl" 221 221 - : "=&c"(count), "=&D"(to), "=&S"(from) 222 222 - : "0"(count), "1"(to), "2"(from) 223 223 - : "memory"); 221 221 + : "+D"(to), "+S"(from), "+c"(count) 222 222 + : : "memory"); 224 223 } 225 224 #define __iowrite32_copy __iowrite32_copy 226 225 #endif ··· 242 243 extern void io_delay_init(void); 243 244 244 245 #if defined(CONFIG_PARAVIRT) 245 245 - #include <asm/paravirt.h> 246 246 + #include <asm/paravirt-base.h> 246 247 #else 248 248 + #define call_io_delay() true 249 249 + #endif 247 250 248 251 static inline void slow_down_io(void) 249 252 { 250 250 - native_io_delay(); 251 251 - #ifdef REALLY_SLOW_IO 252 252 - native_io_delay(); 253 253 - native_io_delay(); 254 254 - native_io_delay(); 255 255 - #endif 256 256 - } 253 253 + if (!call_io_delay()) 254 254 + return; 257 255 258 258 - #endif 256 256 + native_io_delay(); 257 257 + } 259 258 260 259 #define BUILDIO(bwl, type) \ 261 260 static inline void out##bwl##_p(type value, u16 port) \

+3 -3

arch/x86/include/asm/irqflags.h

reviewed

··· 96 96 native_halt(); 97 97 } 98 98 #endif /* __ASSEMBLER__ */ 99 99 + #else 100 100 + #include <asm/paravirt.h> 99 101 #endif /* CONFIG_PARAVIRT */ 100 102 101 101 - #ifdef CONFIG_PARAVIRT_XXL 102 102 - #include <asm/paravirt.h> 103 103 - #else 103 103 + #ifndef CONFIG_PARAVIRT_XXL 104 104 #ifndef __ASSEMBLER__ 105 105 #include <linux/types.h> 106 106

+1 -1

arch/x86/include/asm/local.h

reviewed

··· 106 106 static inline long local_add_return(long i, local_t *l) 107 107 { 108 108 long __i = i; 109 109 - asm volatile(_ASM_XADD "%0, %1;" 109 109 + asm volatile(_ASM_XADD "%0, %1" 110 110 : "+r" (i), "+m" (l->a.counter) 111 111 : : "memory"); 112 112 return i + __i;

+6

arch/x86/include/asm/paravirt-base.h

reviewed

··· 15 15 #ifdef CONFIG_PARAVIRT_XXL 16 16 u16 extra_user_64bit_cs; /* __USER_CS if none */ 17 17 #endif 18 18 + bool io_delay; 19 19 + 18 20 const char *name; 19 21 }; 20 22 ··· 27 25 u64 _paravirt_ident_64(u64); 28 26 #endif 29 27 #define paravirt_nop ((void *)nop_func) 28 28 + 29 29 + #ifdef CONFIG_PARAVIRT 30 30 + #define call_io_delay() pv_info.io_delay 31 31 + #endif 30 32 31 33 #ifdef CONFIG_PARAVIRT_SPINLOCKS 32 34 void paravirt_set_cap(void);

-11

arch/x86/include/asm/paravirt.h

reviewed

··· 19 19 #include <linux/cpumask.h> 20 20 #include <asm/frame.h> 21 21 22 22 - /* The paravirtualized I/O functions */ 23 23 - static inline void slow_down_io(void) 24 24 - { 25 25 - PVOP_VCALL0(pv_ops, cpu.io_delay); 26 26 - #ifdef REALLY_SLOW_IO 27 27 - PVOP_VCALL0(pv_ops, cpu.io_delay); 28 28 - PVOP_VCALL0(pv_ops, cpu.io_delay); 29 29 - PVOP_VCALL0(pv_ops, cpu.io_delay); 30 30 - #endif 31 31 - } 32 32 - 33 22 void native_flush_tlb_local(void); 34 23 void native_flush_tlb_global(void); 35 24 void native_flush_tlb_one_user(unsigned long addr);

-2

arch/x86/include/asm/paravirt_types.h

reviewed

··· 30 30 31 31 struct pv_cpu_ops { 32 32 /* hooks for various privileged instructions */ 33 33 - void (*io_delay)(void); 34 34 - 35 33 #ifdef CONFIG_PARAVIRT_XXL 36 34 unsigned long (*get_debugreg)(int regno); 37 35 void (*set_debugreg)(int regno, unsigned long value);

+6 -6

arch/x86/kernel/apic/apic.c

reviewed

··· 332 332 * Since the offsets must be consistent for all cores, we keep track 333 333 * of the LVT offsets in software and reserve the offset for the same 334 334 * vector also to be used on other cores. An offset is freed by 335 335 - * setting the entry to APIC_EILVT_MASKED. 335 335 + * setting the entry to APIC_LVT_MASKED. 336 336 * 337 337 * If the BIOS is right, there should be no conflicts. Otherwise a 338 338 * "[Firmware Bug]: ..." error message is generated. However, if ··· 344 344 345 345 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 346 346 { 347 347 - return (old & APIC_EILVT_MASKED) 348 348 - || (new == APIC_EILVT_MASKED) 349 349 - || ((new & ~APIC_EILVT_MASKED) == old); 347 347 + return (old & APIC_LVT_MASKED) 348 348 + || (new == APIC_LVT_MASKED) 349 349 + || ((new & ~APIC_LVT_MASKED) == old); 350 350 } 351 351 352 352 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) ··· 358 358 359 359 rsvd = atomic_read(&eilvt_offsets[offset]); 360 360 do { 361 361 - vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 361 361 + vector = rsvd & ~APIC_LVT_MASKED; /* 0: unassigned */ 362 362 if (vector && !eilvt_entry_is_changeable(vector, new)) 363 363 /* may not change if vectors are different */ 364 364 return rsvd; 365 365 } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); 366 366 367 367 - rsvd = new & ~APIC_EILVT_MASKED; 367 367 + rsvd = new & ~APIC_LVT_MASKED; 368 368 if (rsvd && rsvd != vector) 369 369 pr_info("LVT offset %d assigned for vector 0x%02x\n", 370 370 offset, rsvd);

+31 -24

arch/x86/kernel/cpu/bus_lock.c

reviewed

··· 132 132 sld_state = state; 133 133 } 134 134 135 135 + static __init int setup_split_lock_detect(char *arg) 136 136 + { 137 137 + return 1; 138 138 + } 139 139 + __setup("split_lock_detect=", setup_split_lock_detect); 140 140 + 135 141 static void __init __split_lock_setup(void) 136 142 { 137 143 if (!split_lock_verify_msr(false)) { ··· 397 391 398 392 static void sld_state_show(void) 399 393 { 400 400 - if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) && 401 401 - !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 394 394 + const char *action = "warning"; 395 395 + 396 396 + if ((!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) && 397 397 + !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) || 398 398 + (sld_state == sld_off)) 402 399 return; 403 400 404 404 - switch (sld_state) { 405 405 - case sld_off: 406 406 - pr_info("disabled\n"); 407 407 - break; 408 408 - case sld_warn: 409 409 - if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { 410 410 - pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n"); 411 411 - if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 412 412 - "x86/splitlock", NULL, splitlock_cpu_offline) < 0) 413 413 - pr_warn("No splitlock CPU offline handler\n"); 414 414 - } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) { 415 415 - pr_info("#DB: warning on user-space bus_locks\n"); 416 416 - } 417 417 - break; 418 418 - case sld_fatal: 419 419 - if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 420 420 - pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n"); 421 421 - else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 422 422 - pr_info("#DB: sending SIGBUS on user-space bus_locks\n"); 423 423 - break; 424 424 - case sld_ratelimit: 401 401 + if (sld_state == sld_ratelimit) { 425 402 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 426 403 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst); 427 427 - break; 404 404 + return; 405 405 + } else if (sld_state == sld_fatal) { 406 406 + action = "sending SIGBUS"; 407 407 + } 408 408 + 409 409 + if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { 410 410 + pr_info("#AC: crashing the kernel on kernel split_locks and %s on user-space split_locks\n", action); 411 411 + 412 412 + /* 413 413 + * This is handling the case where a CPU goes offline at the 414 414 + * moment where split lock detection is disabled in the warn 415 415 + * setting, see split_lock_warn(). It doesn't have any effect 416 416 + * in the fatal case. 417 417 + */ 418 418 + if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/splitlock", NULL, splitlock_cpu_offline) < 0) 419 419 + pr_warn("No splitlock CPU offline handler\n"); 420 420 + 421 421 + } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) { 422 422 + pr_info("#DB: %s on user-space bus_locks\n", action); 428 423 } 429 424 } 430 425

+3 -3

arch/x86/kernel/cpu/mce/amd.c

reviewed

··· 521 521 static int setup_APIC_mce_threshold(int reserved, int new) 522 522 { 523 523 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 524 524 - APIC_EILVT_MSG_FIX, 0)) 524 524 + APIC_DELIVERY_MODE_FIXED, 0)) 525 525 return new; 526 526 527 527 return reserved; ··· 712 712 return; 713 713 714 714 offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; 715 715 - if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0)) 715 715 + if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_FIXED, 0)) 716 716 data->thr_intr_en = 1; 717 717 718 718 offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; 719 719 - if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) 719 719 + if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_FIXED, 0)) 720 720 data->dfr_intr_en = 1; 721 721 } 722 722

+2 -6

arch/x86/kernel/cpu/topology_common.c

reviewed

··· 157 157 158 158 switch (c->x86_vendor) { 159 159 case X86_VENDOR_AMD: 160 160 - if (IS_ENABLED(CONFIG_CPU_SUP_AMD)) 161 161 - cpu_parse_topology_amd(tscan); 160 160 + case X86_VENDOR_HYGON: 161 161 + cpu_parse_topology_amd(tscan); 162 162 break; 163 163 case X86_VENDOR_CENTAUR: 164 164 case X86_VENDOR_ZHAOXIN: ··· 169 169 parse_legacy(tscan); 170 170 if (c->cpuid_level >= 0x1a) 171 171 c->topo.cpu_type = cpuid_eax(0x1a); 172 172 - break; 173 173 - case X86_VENDOR_HYGON: 174 174 - if (IS_ENABLED(CONFIG_CPU_SUP_HYGON)) 175 175 - cpu_parse_topology_amd(tscan); 176 172 break; 177 173 } 178 174 }

+1 -1

arch/x86/kernel/cpu/vmware.c

reviewed

··· 339 339 static void __init vmware_paravirt_ops_setup(void) 340 340 { 341 341 pv_info.name = "VMware hypervisor"; 342 342 - pv_ops.cpu.io_delay = paravirt_nop; 342 342 + pv_info.io_delay = false; 343 343 344 344 if (vmware_tsc_khz == 0) 345 345 return;

+4 -4

arch/x86/kernel/fpu/xstate.h

reviewed

··· 267 267 */ 268 268 static inline u64 xfeatures_need_sigframe_write(void) 269 269 { 270 270 - u64 xfeaures_to_write; 270 270 + u64 xfeatures_to_write; 271 271 272 272 /* In-use features must be written: */ 273 273 - xfeaures_to_write = xfeatures_in_use(); 273 273 + xfeatures_to_write = xfeatures_in_use(); 274 274 275 275 /* Also write all non-optimizable sigframe features: */ 276 276 - xfeaures_to_write |= XFEATURE_MASK_USER_SUPPORTED & 276 276 + xfeatures_to_write |= XFEATURE_MASK_USER_SUPPORTED & 277 277 ~XFEATURE_MASK_SIGFRAME_INITOPT; 278 278 279 279 - return xfeaures_to_write; 279 279 + return xfeatures_to_write; 280 280 } 281 281 282 282 /*

+1 -7

arch/x86/kernel/kvm.c

reviewed

··· 75 75 static int has_steal_clock = 0; 76 76 77 77 static int has_guest_poll = 0; 78 78 - /* 79 79 - * No need for any "IO delay" on KVM 80 80 - */ 81 81 - static void kvm_io_delay(void) 82 82 - { 83 83 - } 84 78 85 79 #define KVM_TASK_SLEEP_HASHBITS 8 86 80 #define KVM_TASK_SLEEP_HASHSIZE (1<<KVM_TASK_SLEEP_HASHBITS) ··· 321 327 pv_info.name = "KVM"; 322 328 323 329 if (kvm_para_has_feature(KVM_FEATURE_NOP_IO_DELAY)) 324 324 - pv_ops.cpu.io_delay = kvm_io_delay; 330 330 + pv_info.io_delay = false; 325 331 326 332 #ifdef CONFIG_X86_IO_APIC 327 333 no_timer_check = 1;

+1 -2

arch/x86/kernel/paravirt.c

reviewed

··· 94 94 #ifdef CONFIG_PARAVIRT_XXL 95 95 .extra_user_64bit_cs = __USER_CS, 96 96 #endif 97 97 + .io_delay = true, 97 98 }; 98 99 99 100 /* 64-bit pagetable entries */ ··· 102 101 103 102 struct paravirt_patch_template pv_ops = { 104 103 /* Cpu ops. */ 105 105 - .cpu.io_delay = native_io_delay, 106 106 - 107 104 #ifdef CONFIG_PARAVIRT_XXL 108 105 .cpu.cpuid = native_cpuid, 109 106 .cpu.get_debugreg = pv_native_get_debugreg,

+1 -5

arch/x86/xen/enlighten_pv.c

reviewed

··· 1045 1045 } 1046 1046 #endif 1047 1047 1048 1048 - static void xen_io_delay(void) 1049 1049 - { 1050 1050 - } 1051 1051 - 1052 1048 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 1053 1049 1054 1050 static unsigned long xen_read_cr0(void) ··· 1204 1208 1205 1209 static const struct pv_info xen_info __initconst = { 1206 1210 .extra_user_64bit_cs = FLAT_USER_CS64, 1211 1211 + .io_delay = false, 1207 1212 .name = "Xen", 1208 1213 }; 1209 1214 ··· 1388 1391 pv_ops.cpu.invalidate_io_bitmap = xen_invalidate_io_bitmap; 1389 1392 pv_ops.cpu.update_io_bitmap = xen_update_io_bitmap; 1390 1393 #endif 1391 1391 - pv_ops.cpu.io_delay = xen_io_delay; 1392 1394 pv_ops.cpu.start_context_switch = xen_start_context_switch; 1393 1395 pv_ops.cpu.end_context_switch = xen_end_context_switch; 1394 1396

-2

drivers/block/floppy.c

reviewed

··· 145 145 * Better audit of register_blkdev. 146 146 */ 147 147 148 148 - #define REALLY_SLOW_IO 149 149 - 150 148 #define DEBUGT 2 151 149 152 150 #define DPRINT(format, args...) \