Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2023-04-06' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Daniel Vetter:
"Mostly i915 fixes: dp mst for compression/dsc, perf ioctl uaf, ctx rpm
accounting, gt reset vs huc loading.
And a few individual driver fixes: ivpu dma fence&suspend, panfrost
mmap, nouveau color depth"
* tag 'drm-fixes-2023-04-06' of git://anongit.freedesktop.org/drm/drm:
accel/ivpu: Fix S3 system suspend when not idle
accel/ivpu: Add dma fence to command buffers only
drm/i915: Fix context runtime accounting
drm/i915: fix race condition UAF in i915_perf_add_config_ioctl
drm/i915: Use compressed bpp when calculating m/n value for DP MST DSC
drm/i915/huc: Cancel HuC delayed load timer on reset.
drm/i915/ttm: fix sparse warning
drm/panfrost: Fix the panfrost_mmu_map_fault_addr() error path
drm/nouveau/disp: Support more modes by checking with lower bpc
+81
-43
+7
-11
drivers/accel/ivpu/ivpu_job.c
+7
-11
drivers/accel/ivpu/ivpu_job.c
···
461
461
462
462
job->cmd_buf_vpu_addr = bo->vpu_addr + commands_offset;
463
463
464
-
ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, buf_count,
465
-
&acquire_ctx);
464
+
ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, 1, &acquire_ctx);
466
465
if (ret) {
467
466
ivpu_warn(vdev, "Failed to lock reservations: %d\n", ret);
468
467
return ret;
469
468
}
470
469
471
-
for (i = 0; i < buf_count; i++) {
472
-
ret = dma_resv_reserve_fences(job->bos[i]->base.resv, 1);
473
-
if (ret) {
474
-
ivpu_warn(vdev, "Failed to reserve fences: %d\n", ret);
475
-
goto unlock_reservations;
476
-
}
470
+
ret = dma_resv_reserve_fences(bo->base.resv, 1);
471
+
if (ret) {
472
+
ivpu_warn(vdev, "Failed to reserve fences: %d\n", ret);
473
+
goto unlock_reservations;
477
474
}
478
475
479
-
for (i = 0; i < buf_count; i++)
480
-
dma_resv_add_fence(job->bos[i]->base.resv, job->done_fence, DMA_RESV_USAGE_WRITE);
476
+
dma_resv_add_fence(bo->base.resv, job->done_fence, DMA_RESV_USAGE_WRITE);
481
477
482
478
unlock_reservations:
483
-
drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, buf_count, &acquire_ctx);
479
+
drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, 1, &acquire_ctx);
484
480
485
481
wmb(); /* Flush write combining buffers */
486
482
+11
-15
drivers/accel/ivpu/ivpu_pm.c
+11
-15
drivers/accel/ivpu/ivpu_pm.c
···
140
140
{
141
141
struct drm_device *drm = dev_get_drvdata(dev);
142
142
struct ivpu_device *vdev = to_ivpu_device(drm);
143
-
int ret;
143
+
unsigned long timeout;
144
144
145
145
ivpu_dbg(vdev, PM, "Suspend..\n");
146
146
147
-
ret = ivpu_suspend(vdev);
148
-
if (ret && vdev->pm->suspend_reschedule_counter) {
149
-
ivpu_dbg(vdev, PM, "Failed to enter idle, rescheduling suspend, retries left %d\n",
150
-
vdev->pm->suspend_reschedule_counter);
151
-
pm_schedule_suspend(dev, vdev->timeout.reschedule_suspend);
152
-
vdev->pm->suspend_reschedule_counter--;
153
-
return -EBUSY;
154
-
} else if (!vdev->pm->suspend_reschedule_counter) {
155
-
ivpu_warn(vdev, "Failed to enter idle, force suspend\n");
156
-
ivpu_pm_prepare_cold_boot(vdev);
157
-
} else {
158
-
ivpu_pm_prepare_warm_boot(vdev);
147
+
timeout = jiffies + msecs_to_jiffies(vdev->timeout.tdr);
148
+
while (!ivpu_hw_is_idle(vdev)) {
149
+
cond_resched();
150
+
if (time_after_eq(jiffies, timeout)) {
151
+
ivpu_err(vdev, "Failed to enter idle on system suspend\n");
152
+
return -EBUSY;
153
+
}
159
154
}
160
155
161
-
vdev->pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT;
156
+
ivpu_suspend(vdev);
157
+
ivpu_pm_prepare_warm_boot(vdev);
162
158
163
159
pci_save_state(to_pci_dev(dev));
164
160
pci_set_power_state(to_pci_dev(dev), PCI_D3hot);
165
161
166
162
ivpu_dbg(vdev, PM, "Suspend done.\n");
167
163
168
-
return ret;
164
+
return 0;
169
165
}
170
166
171
167
int ivpu_pm_resume_cb(struct device *dev)
+1
-1
drivers/gpu/drm/i915/display/intel_dp_mst.c
+1
-1
drivers/gpu/drm/i915/display/intel_dp_mst.c
+3
-2
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+3
-2
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
···
1067
1067
.interruptible = true,
1068
1068
.no_wait_gpu = true, /* should be idle already */
1069
1069
};
1070
+
int err;
1070
1071
1071
1072
GEM_BUG_ON(!bo->ttm || !(bo->ttm->page_flags & TTM_TT_FLAG_SWAPPED));
1072
1073
1073
-
ret = ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
1074
-
if (ret) {
1074
+
err = ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
1075
+
if (err) {
1075
1076
dma_resv_unlock(bo->base.resv);
1076
1077
return VM_FAULT_SIGBUS;
1077
1078
}
+10
-2
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+10
-2
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
···
2018
2018
* inspecting the queue to see if we need to resumbit.
2019
2019
*/
2020
2020
if (*prev != *execlists->active) { /* elide lite-restores */
2021
+
struct intel_context *prev_ce = NULL, *active_ce = NULL;
2022
+
2021
2023
/*
2022
2024
* Note the inherent discrepancy between the HW runtime,
2023
2025
* recorded as part of the context switch, and the CPU
···
2031
2029
* and correct overselves later when updating from HW.
2032
2030
*/
2033
2031
if (*prev)
2034
-
lrc_runtime_stop((*prev)->context);
2032
+
prev_ce = (*prev)->context;
2035
2033
if (*execlists->active)
2036
-
lrc_runtime_start((*execlists->active)->context);
2034
+
active_ce = (*execlists->active)->context;
2035
+
if (prev_ce != active_ce) {
2036
+
if (prev_ce)
2037
+
lrc_runtime_stop(prev_ce);
2038
+
if (active_ce)
2039
+
lrc_runtime_start(active_ce);
2040
+
}
2037
2041
new_timeslice(execlists);
2038
2042
}
2039
2043
+7
drivers/gpu/drm/i915/gt/uc/intel_huc.c
+7
drivers/gpu/drm/i915/gt/uc/intel_huc.c
···
235
235
i915_sw_fence_fini(&huc->delayed_load.fence);
236
236
}
237
237
238
+
int intel_huc_sanitize(struct intel_huc *huc)
239
+
{
240
+
delayed_huc_load_complete(huc);
241
+
intel_uc_fw_sanitize(&huc->fw);
242
+
return 0;
243
+
}
244
+
238
245
static bool vcs_supported(struct intel_gt *gt)
239
246
{
240
247
intel_engine_mask_t mask = gt->info.engine_mask;
+1
-6
drivers/gpu/drm/i915/gt/uc/intel_huc.h
+1
-6
drivers/gpu/drm/i915/gt/uc/intel_huc.h
···
41
41
} delayed_load;
42
42
};
43
43
44
+
int intel_huc_sanitize(struct intel_huc *huc);
44
45
void intel_huc_init_early(struct intel_huc *huc);
45
46
int intel_huc_init(struct intel_huc *huc);
46
47
void intel_huc_fini(struct intel_huc *huc);
···
54
53
55
54
void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus);
56
55
void intel_huc_unregister_gsc_notifier(struct intel_huc *huc, struct bus_type *bus);
57
-
58
-
static inline int intel_huc_sanitize(struct intel_huc *huc)
59
-
{
60
-
intel_uc_fw_sanitize(&huc->fw);
61
-
return 0;
62
-
}
63
56
64
57
static inline bool intel_huc_is_supported(struct intel_huc *huc)
65
58
{
+3
-3
drivers/gpu/drm/i915/i915_perf.c
+3
-3
drivers/gpu/drm/i915/i915_perf.c
···
4638
4638
err = oa_config->id;
4639
4639
goto sysfs_err;
4640
4640
}
4641
-
4642
-
mutex_unlock(&perf->metrics_lock);
4641
+
id = oa_config->id;
4643
4642
4644
4643
drm_dbg(&perf->i915->drm,
4645
4644
"Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4645
+
mutex_unlock(&perf->metrics_lock);
4646
4646
4647
-
return oa_config->id;
4647
+
return id;
4648
4648
4649
4649
sysfs_err:
4650
4650
mutex_unlock(&perf->metrics_lock);
+32
drivers/gpu/drm/nouveau/dispnv50/disp.c
+32
drivers/gpu/drm/nouveau/dispnv50/disp.c
···
363
363
return 0;
364
364
}
365
365
366
+
static void
367
+
nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
368
+
{
369
+
struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
370
+
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
371
+
struct drm_display_mode *mode = &asyh->state.adjusted_mode;
372
+
unsigned int max_rate, mode_rate;
373
+
374
+
switch (nv_encoder->dcb->type) {
375
+
case DCB_OUTPUT_DP:
376
+
max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
377
+
378
+
/* we don't support more than 10 anyway */
379
+
asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
380
+
381
+
/* reduce the bpc until it works out */
382
+
while (asyh->or.bpc > 6) {
383
+
mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
384
+
if (mode_rate <= max_rate)
385
+
break;
386
+
387
+
asyh->or.bpc -= 2;
388
+
}
389
+
break;
390
+
default:
391
+
break;
392
+
}
393
+
}
394
+
366
395
static int
367
396
nv50_outp_atomic_check(struct drm_encoder *encoder,
368
397
struct drm_crtc_state *crtc_state,
···
409
380
410
381
if (crtc_state->mode_changed || crtc_state->connectors_changed)
411
382
asyh->or.bpc = connector->display_info.bpc;
383
+
384
+
/* We might have to reduce the bpc */
385
+
nv50_outp_atomic_fix_depth(encoder, crtc_state);
412
386
413
387
return 0;
414
388
}
+5
-3
drivers/gpu/drm/nouveau/nouveau_dp.c
+5
-3
drivers/gpu/drm/nouveau/nouveau_dp.c
···
263
263
}
264
264
265
265
/* TODO:
266
-
* - Use the minimum possible BPC here, once we add support for the max bpc
267
-
* property.
268
266
* - Validate against the DP caps advertised by the GPU (we don't check these
269
267
* yet)
270
268
*/
···
274
276
{
275
277
const unsigned int min_clock = 25000;
276
278
unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock;
277
-
const u8 bpp = connector->display_info.bpc * 3;
279
+
/* Check with the minmum bpc always, so we can advertise better modes.
280
+
* In particlar not doing this causes modes to be dropped on HDR
281
+
* displays as we might check with a bpc of 16 even.
282
+
*/
283
+
const u8 bpp = 6 * 3;
278
284
279
285
if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
280
286
return MODE_NO_INTERLACE;