Merge tag 'pwm/for-6.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

+4

Documentation/devicetree/bindings/pwm/imx-pwm.yaml

··· 43 43 - fsl,imx8mn-pwm 44 44 - fsl,imx8mp-pwm 45 45 - fsl,imx8mq-pwm 46 + - fsl,imx8qxp-pwm 46 47 - const: fsl,imx27-pwm 47 48 48 49 reg: ··· 60 59 - const: per 61 60 62 61 interrupts: 62 + maxItems: 1 63 + 64 + power-domains: 63 65 maxItems: 1 64 66 65 67 required:

+1

Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml

··· 22 22 - mediatek,mt7623-pwm 23 23 - mediatek,mt7628-pwm 24 24 - mediatek,mt7629-pwm 25 + - mediatek,mt7981-pwm 25 26 - mediatek,mt7986-pwm 26 27 - mediatek,mt8183-pwm 27 28 - mediatek,mt8365-pwm

-30

Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt

··· 1 - BCM2835 PWM controller (Raspberry Pi controller) 2 - 3 - Required properties: 4 - - compatible: should be "brcm,bcm2835-pwm" 5 - - reg: physical base address and length of the controller's registers 6 - - clocks: This clock defines the base clock frequency of the PWM hardware 7 - system, the period and the duty_cycle of the PWM signal is a multiple of 8 - the base period. 9 - - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of 10 - the cells format. 11 - 12 - Examples: 13 - 14 - pwm@2020c000 { 15 - compatible = "brcm,bcm2835-pwm"; 16 - reg = <0x2020c000 0x28>; 17 - clocks = <&clk_pwm>; 18 - #pwm-cells = <3>; 19 - }; 20 - 21 - clocks { 22 - .... 23 - clk_pwm: pwm { 24 - compatible = "fixed-clock"; 25 - reg = <3>; 26 - #clock-cells = <0>; 27 - clock-frequency = <9200000>; 28 - }; 29 - .... 30 - };

+43

Documentation/devicetree/bindings/pwm/pwm-bcm2835.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pwm/pwm-bcm2835.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: BCM2835 PWM controller (Raspberry Pi controller) 8 + 9 + maintainers: 10 + - Stefan Wahren <stefan.wahren@i2se.com> 11 + 12 + allOf: 13 + - $ref: pwm.yaml# 14 + 15 + properties: 16 + compatible: 17 + const: brcm,bcm2835-pwm 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + clocks: 23 + maxItems: 1 24 + 25 + "#pwm-cells": 26 + const: 3 27 + 28 + required: 29 + - compatible 30 + - reg 31 + - clocks 32 + - "#pwm-cells" 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + pwm@2020c000 { 39 + compatible = "brcm,bcm2835-pwm"; 40 + reg = <0x2020c000 0x28>; 41 + clocks = <&clk_pwm>; 42 + #pwm-cells = <3>; 43 + };

+1 -1

Documentation/devicetree/bindings/pwm/pwm.yaml

··· 13 13 14 14 properties: 15 15 $nodename: 16 - pattern: "^pwm(@.*|-[0-9a-f])*$" 16 + pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$" 17 17 18 18 "#pwm-cells": 19 19 description:

+1

Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml

··· 35 35 - renesas,pwm-r8a77980 # R-Car V3H 36 36 - renesas,pwm-r8a77990 # R-Car E3 37 37 - renesas,pwm-r8a77995 # R-Car D3 38 + - renesas,pwm-r8a779a0 # R-Car V3U 38 39 - renesas,pwm-r8a779g0 # R-Car V4H 39 40 - const: renesas,pwm-rcar 40 41

+1

MAINTAINERS

··· 18337 18337 F: drivers/i2c/busses/i2c-microchip-corei2c.c 18338 18338 F: drivers/mailbox/mailbox-mpfs.c 18339 18339 F: drivers/pci/controller/pcie-microchip-host.c 18340 + F: drivers/pwm/pwm-microchip-core.c 18340 18341 F: drivers/reset/reset-mpfs.c 18341 18342 F: drivers/rtc/rtc-mpfs.c 18342 18343 F: drivers/soc/microchip/mpfs-sys-controller.c

+21

drivers/pwm/Kconfig

··· 405 405 To compile this driver as a module, choose M here: the module 406 406 will be called pwm-mediatek. 407 407 408 + config PWM_MICROCHIP_CORE 409 + tristate "Microchip corePWM PWM support" 410 + depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST 411 + depends on HAS_IOMEM && OF 412 + help 413 + PWM driver for Microchip FPGA soft IP core. 414 + 415 + To compile this driver as a module, choose M here: the module 416 + will be called pwm-microchip-core. 417 + 408 418 config PWM_MXS 409 419 tristate "Freescale MXS PWM support" 410 420 depends on ARCH_MXS || COMPILE_TEST ··· 502 492 help 503 493 Generic PWM framework driver for the PWM controller found on 504 494 Rockchip SoCs. 495 + 496 + config PWM_RZ_MTU3 497 + tristate "Renesas RZ/G2L MTU3a PWM Timer support" 498 + depends on RZ_MTU3 || COMPILE_TEST 499 + depends on HAS_IOMEM 500 + help 501 + This driver exposes the MTU3a PWM Timer controller found in Renesas 502 + RZ/G2L like chips through the PWM API. 503 + 504 + To compile this driver as a module, choose M here: the module 505 + will be called pwm-rz-mtu3. 505 506 506 507 config PWM_SAMSUNG 507 508 tristate "Samsung PWM support"

+2

drivers/pwm/Makefile

··· 35 35 obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o 36 36 obj-$(CONFIG_PWM_MESON) += pwm-meson.o 37 37 obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o 38 + obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o 38 39 obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o 39 40 obj-$(CONFIG_PWM_MXS) += pwm-mxs.o 40 41 obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o ··· 46 45 obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o 47 46 obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o 48 47 obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o 48 + obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o 49 49 obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o 50 50 obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o 51 51 obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o

+1 -1

drivers/pwm/pwm-ab8500.c

··· 190 190 int err; 191 191 192 192 if (pdev->id < 1 || pdev->id > 31) 193 - return dev_err_probe(&pdev->dev, EINVAL, "Invalid device id %d\n", pdev->id); 193 + return dev_err_probe(&pdev->dev, -EINVAL, "Invalid device id %d\n", pdev->id); 194 194 195 195 /* 196 196 * Nothing to be done in probe, this is required to get the

+2 -10

drivers/pwm/pwm-clk.c

··· 89 89 if (!pcchip) 90 90 return -ENOMEM; 91 91 92 - pcchip->clk = devm_clk_get(&pdev->dev, NULL); 92 + pcchip->clk = devm_clk_get_prepared(&pdev->dev, NULL); 93 93 if (IS_ERR(pcchip->clk)) 94 94 return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk), 95 95 "Failed to get clock\n"); ··· 98 98 pcchip->chip.ops = &pwm_clk_ops; 99 99 pcchip->chip.npwm = 1; 100 100 101 - ret = clk_prepare(pcchip->clk); 102 - if (ret < 0) 103 - return dev_err_probe(&pdev->dev, ret, "Failed to prepare clock\n"); 104 - 105 101 ret = pwmchip_add(&pcchip->chip); 106 - if (ret < 0) { 107 - clk_unprepare(pcchip->clk); 102 + if (ret < 0) 108 103 return dev_err_probe(&pdev->dev, ret, "Failed to add pwm chip\n"); 109 - } 110 104 111 105 platform_set_drvdata(pdev, pcchip); 112 106 return 0; ··· 114 120 115 121 if (pcchip->clk_enabled) 116 122 clk_disable(pcchip->clk); 117 - 118 - clk_unprepare(pcchip->clk); 119 123 } 120 124 121 125 static const struct of_device_id pwm_clk_dt_ids[] = {

+7

drivers/pwm/pwm-imx-tpm.c

··· 397 397 if (tpm->enable_count > 0) 398 398 return -EBUSY; 399 399 400 + /* 401 + * Force 'real_period' to be zero to force period update code 402 + * can be executed after system resume back, since suspend causes 403 + * the period related registers to become their reset values. 404 + */ 405 + tpm->real_period = 0; 406 + 400 407 clk_disable_unprepare(tpm->clk); 401 408 402 409 return 0;

+32 -9

drivers/pwm/pwm-mediatek.c

··· 38 38 unsigned int num_pwms; 39 39 bool pwm45_fixup; 40 40 bool has_ck_26m_sel; 41 + const unsigned int *reg_offset; 41 42 }; 42 43 43 44 /** ··· 60 59 const struct pwm_mediatek_of_data *soc; 61 60 }; 62 61 63 - static const unsigned int pwm_mediatek_reg_offset[] = { 62 + static const unsigned int mtk_pwm_reg_offset_v1[] = { 64 63 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 64 + }; 65 + 66 + static const unsigned int mtk_pwm_reg_offset_v2[] = { 67 + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 65 68 }; 66 69 67 70 static inline struct pwm_mediatek_chip * ··· 116 111 unsigned int num, unsigned int offset, 117 112 u32 value) 118 113 { 119 - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); 114 + writel(value, chip->regs + chip->soc->reg_offset[num] + offset); 120 115 } 121 116 122 117 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, ··· 290 285 .num_pwms = 8, 291 286 .pwm45_fixup = false, 292 287 .has_ck_26m_sel = false, 288 + .reg_offset = mtk_pwm_reg_offset_v1, 293 289 }; 294 290 295 291 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 296 292 .num_pwms = 7, 297 293 .pwm45_fixup = false, 298 294 .has_ck_26m_sel = false, 295 + .reg_offset = mtk_pwm_reg_offset_v1, 299 296 }; 300 297 301 298 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 302 299 .num_pwms = 6, 303 300 .pwm45_fixup = false, 304 301 .has_ck_26m_sel = true, 302 + .reg_offset = mtk_pwm_reg_offset_v1, 305 303 }; 306 304 307 305 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 308 306 .num_pwms = 5, 309 307 .pwm45_fixup = true, 310 308 .has_ck_26m_sel = false, 309 + .reg_offset = mtk_pwm_reg_offset_v1, 311 310 }; 312 311 313 312 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 314 313 .num_pwms = 4, 315 314 .pwm45_fixup = true, 316 315 .has_ck_26m_sel = false, 316 + .reg_offset = mtk_pwm_reg_offset_v1, 317 317 }; 318 318 319 319 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 320 320 .num_pwms = 1, 321 321 .pwm45_fixup = false, 322 322 .has_ck_26m_sel = false, 323 + .reg_offset = mtk_pwm_reg_offset_v1, 323 324 }; 324 325 325 - static const struct pwm_mediatek_of_data mt8183_pwm_data = { 326 - .num_pwms = 4, 327 - .pwm45_fixup = false, 328 - .has_ck_26m_sel = true, 329 - }; 330 - 331 - static const struct pwm_mediatek_of_data mt8365_pwm_data = { 326 + static const struct pwm_mediatek_of_data mt7981_pwm_data = { 332 327 .num_pwms = 3, 333 328 .pwm45_fixup = false, 334 329 .has_ck_26m_sel = true, 330 + .reg_offset = mtk_pwm_reg_offset_v2, 335 331 }; 336 332 337 333 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 338 334 .num_pwms = 2, 339 335 .pwm45_fixup = false, 340 336 .has_ck_26m_sel = true, 337 + .reg_offset = mtk_pwm_reg_offset_v1, 338 + }; 339 + 340 + static const struct pwm_mediatek_of_data mt8183_pwm_data = { 341 + .num_pwms = 4, 342 + .pwm45_fixup = false, 343 + .has_ck_26m_sel = true, 344 + .reg_offset = mtk_pwm_reg_offset_v1, 345 + }; 346 + 347 + static const struct pwm_mediatek_of_data mt8365_pwm_data = { 348 + .num_pwms = 3, 349 + .pwm45_fixup = false, 350 + .has_ck_26m_sel = true, 351 + .reg_offset = mtk_pwm_reg_offset_v1, 341 352 }; 342 353 343 354 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 344 355 .num_pwms = 5, 345 356 .pwm45_fixup = false, 346 357 .has_ck_26m_sel = true, 358 + .reg_offset = mtk_pwm_reg_offset_v1, 347 359 }; 348 360 349 361 static const struct of_device_id pwm_mediatek_of_match[] = { ··· 370 348 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 371 349 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 372 350 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 351 + { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, 373 352 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, 374 353 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, 375 354 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },

+104 -108

drivers/pwm/pwm-meson.c

··· 49 49 #define PWM_HIGH_MASK GENMASK(31, 16) 50 50 51 51 #define REG_MISC_AB 0x8 52 - #define MISC_B_CLK_EN BIT(23) 53 - #define MISC_A_CLK_EN BIT(15) 54 - #define MISC_CLK_DIV_MASK 0x7f 52 + #define MISC_B_CLK_EN_SHIFT 23 53 + #define MISC_A_CLK_EN_SHIFT 15 54 + #define MISC_CLK_DIV_WIDTH 7 55 55 #define MISC_B_CLK_DIV_SHIFT 16 56 56 #define MISC_A_CLK_DIV_SHIFT 8 57 57 #define MISC_B_CLK_SEL_SHIFT 6 ··· 61 61 #define MISC_A_EN BIT(0) 62 62 63 63 #define MESON_NUM_PWMS 2 64 + #define MESON_MAX_MUX_PARENTS 4 64 65 65 66 static struct meson_pwm_channel_data { 66 67 u8 reg_offset; 67 68 u8 clk_sel_shift; 68 69 u8 clk_div_shift; 69 - u32 clk_en_mask; 70 + u8 clk_en_shift; 70 71 u32 pwm_en_mask; 71 72 } meson_pwm_per_channel_data[MESON_NUM_PWMS] = { 72 73 { 73 74 .reg_offset = REG_PWM_A, 74 75 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT, 75 76 .clk_div_shift = MISC_A_CLK_DIV_SHIFT, 76 - .clk_en_mask = MISC_A_CLK_EN, 77 + .clk_en_shift = MISC_A_CLK_EN_SHIFT, 77 78 .pwm_en_mask = MISC_A_EN, 78 79 }, 79 80 { 80 81 .reg_offset = REG_PWM_B, 81 82 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT, 82 83 .clk_div_shift = MISC_B_CLK_DIV_SHIFT, 83 - .clk_en_mask = MISC_B_CLK_EN, 84 + .clk_en_shift = MISC_B_CLK_EN_SHIFT, 84 85 .pwm_en_mask = MISC_B_EN, 85 86 } 86 87 }; 87 88 88 89 struct meson_pwm_channel { 90 + unsigned long rate; 89 91 unsigned int hi; 90 92 unsigned int lo; 91 - u8 pre_div; 92 93 93 - struct clk *clk_parent; 94 94 struct clk_mux mux; 95 + struct clk_divider div; 96 + struct clk_gate gate; 95 97 struct clk *clk; 96 98 }; 97 99 ··· 126 124 struct device *dev = chip->dev; 127 125 int err; 128 126 129 - if (channel->clk_parent) { 130 - err = clk_set_parent(channel->clk, channel->clk_parent); 131 - if (err < 0) { 132 - dev_err(dev, "failed to set parent %s for %s: %d\n", 133 - __clk_get_name(channel->clk_parent), 134 - __clk_get_name(channel->clk), err); 135 - return err; 136 - } 137 - } 138 - 139 127 err = clk_prepare_enable(channel->clk); 140 128 if (err < 0) { 141 129 dev_err(dev, "failed to enable clock %s: %d\n", ··· 148 156 const struct pwm_state *state) 149 157 { 150 158 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; 151 - unsigned int duty, period, pre_div, cnt, duty_cnt; 159 + unsigned int cnt, duty_cnt; 152 160 unsigned long fin_freq; 161 + u64 duty, period, freq; 153 162 154 163 duty = state->duty_cycle; 155 164 period = state->period; ··· 164 171 if (state->polarity == PWM_POLARITY_INVERSED) 165 172 duty = period - duty; 166 173 167 - fin_freq = clk_get_rate(channel->clk); 174 + freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period); 175 + if (freq > ULONG_MAX) 176 + freq = ULONG_MAX; 177 + 178 + fin_freq = clk_round_rate(channel->clk, freq); 168 179 if (fin_freq == 0) { 169 180 dev_err(meson->chip.dev, "invalid source clock frequency\n"); 170 181 return -EINVAL; ··· 176 179 177 180 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); 178 181 179 - pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL); 180 - if (pre_div > MISC_CLK_DIV_MASK) { 181 - dev_err(meson->chip.dev, "unable to get period pre_div\n"); 182 - return -EINVAL; 183 - } 184 - 185 - cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1)); 182 + cnt = div_u64(fin_freq * period, NSEC_PER_SEC); 186 183 if (cnt > 0xffff) { 187 184 dev_err(meson->chip.dev, "unable to get period cnt\n"); 188 185 return -EINVAL; 189 186 } 190 187 191 - dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, 192 - pre_div, cnt); 188 + dev_dbg(meson->chip.dev, "period=%llu cnt=%u\n", period, cnt); 193 189 194 190 if (duty == period) { 195 - channel->pre_div = pre_div; 196 191 channel->hi = cnt; 197 192 channel->lo = 0; 198 193 } else if (duty == 0) { 199 - channel->pre_div = pre_div; 200 194 channel->hi = 0; 201 195 channel->lo = cnt; 202 196 } else { 203 - /* Then check is we can have the duty with the same pre_div */ 204 - duty_cnt = div64_u64(fin_freq * (u64)duty, 205 - NSEC_PER_SEC * (pre_div + 1)); 206 - if (duty_cnt > 0xffff) { 207 - dev_err(meson->chip.dev, "unable to get duty cycle\n"); 208 - return -EINVAL; 209 - } 197 + duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC); 210 198 211 - dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n", 212 - duty, pre_div, duty_cnt); 199 + dev_dbg(meson->chip.dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt); 213 200 214 - channel->pre_div = pre_div; 215 201 channel->hi = duty_cnt; 216 202 channel->lo = cnt - duty_cnt; 217 203 } 204 + 205 + channel->rate = fin_freq; 218 206 219 207 return 0; 220 208 } ··· 210 228 struct meson_pwm_channel_data *channel_data; 211 229 unsigned long flags; 212 230 u32 value; 231 + int err; 213 232 214 233 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; 215 234 216 - spin_lock_irqsave(&meson->lock, flags); 235 + err = clk_set_rate(channel->clk, channel->rate); 236 + if (err) 237 + dev_err(meson->chip.dev, "setting clock rate failed\n"); 217 238 218 - value = readl(meson->base + REG_MISC_AB); 219 - value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift); 220 - value |= channel->pre_div << channel_data->clk_div_shift; 221 - value |= channel_data->clk_en_mask; 222 - writel(value, meson->base + REG_MISC_AB); 239 + spin_lock_irqsave(&meson->lock, flags); 223 240 224 241 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | 225 242 FIELD_PREP(PWM_LOW_MASK, channel->lo); ··· 257 276 /* 258 277 * This IP block revision doesn't have an "always high" 259 278 * setting which we can use for "inverted disabled". 260 - * Instead we achieve this using the same settings 261 - * that we use a pre_div of 0 (to get the shortest 262 - * possible duration for one "count") and 263 - * "period == duty_cycle". This results in a signal 279 + * Instead we achieve this by setting mux parent with 280 + * highest rate and minimum divider value, resulting 281 + * in the shortest possible duration for one "count" 282 + * and "period == duty_cycle". This results in a signal 264 283 * which is LOW for one "count", while being HIGH for 265 284 * the rest of the (so the signal is HIGH for slightly 266 285 * less than 100% of the period, but this is the best 267 286 * we can achieve). 268 287 */ 269 - channel->pre_div = 0; 288 + channel->rate = ULONG_MAX; 270 289 channel->hi = ~0; 271 290 channel->lo = 0; 272 291 ··· 285 304 return 0; 286 305 } 287 306 288 - static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip, 289 - struct pwm_device *pwm, u32 cnt) 307 + static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm, 308 + u32 cnt) 290 309 { 291 310 struct meson_pwm *meson = to_meson_pwm(chip); 292 311 struct meson_pwm_channel *channel; 293 312 unsigned long fin_freq; 294 - u32 fin_ns; 295 313 296 314 /* to_meson_pwm() can only be used after .get_state() is called */ 297 315 channel = &meson->channels[pwm->hwpwm]; ··· 299 319 if (fin_freq == 0) 300 320 return 0; 301 321 302 - fin_ns = div_u64(NSEC_PER_SEC, fin_freq); 303 - 304 - return cnt * fin_ns * (channel->pre_div + 1); 322 + return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq); 305 323 } 306 324 307 325 static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, ··· 308 330 struct meson_pwm *meson = to_meson_pwm(chip); 309 331 struct meson_pwm_channel_data *channel_data; 310 332 struct meson_pwm_channel *channel; 311 - u32 value, tmp; 333 + u32 value; 312 334 313 335 if (!state) 314 336 return 0; ··· 317 339 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; 318 340 319 341 value = readl(meson->base + REG_MISC_AB); 320 - 321 - tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask; 322 - state->enabled = (value & tmp) == tmp; 323 - 324 - tmp = value >> channel_data->clk_div_shift; 325 - channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp); 342 + state->enabled = value & channel_data->pwm_en_mask; 326 343 327 344 value = readl(meson->base + channel_data->reg_offset); 328 - 329 345 channel->lo = FIELD_GET(PWM_LOW_MASK, value); 330 346 channel->hi = FIELD_GET(PWM_HIGH_MASK, value); 331 347 332 - if (channel->lo == 0) { 333 - state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); 334 - state->duty_cycle = state->period; 335 - } else if (channel->lo >= channel->hi) { 336 - state->period = meson_pwm_cnt_to_ns(chip, pwm, 337 - channel->lo + channel->hi); 338 - state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, 339 - channel->hi); 340 - } else { 341 - state->period = 0; 342 - state->duty_cycle = 0; 343 - } 348 + state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi); 349 + state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); 344 350 345 351 state->polarity = PWM_POLARITY_NORMAL; 346 352 ··· 340 378 }; 341 379 342 380 static const char * const pwm_meson8b_parent_names[] = { 343 - "xtal", "vid_pll", "fclk_div4", "fclk_div3" 381 + "xtal", NULL, "fclk_div4", "fclk_div3" 344 382 }; 345 383 346 384 static const struct meson_pwm_data pwm_meson8b_data = { 347 385 .parent_names = pwm_meson8b_parent_names, 348 386 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names), 349 - }; 350 - 351 - static const char * const pwm_gxbb_parent_names[] = { 352 - "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" 353 - }; 354 - 355 - static const struct meson_pwm_data pwm_gxbb_data = { 356 - .parent_names = pwm_gxbb_parent_names, 357 - .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names), 358 387 }; 359 388 360 389 /* ··· 397 444 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), 398 445 }; 399 446 400 - static const char * const pwm_g12a_ee_parent_names[] = { 401 - "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" 402 - }; 403 - 404 - static const struct meson_pwm_data pwm_g12a_ee_data = { 405 - .parent_names = pwm_g12a_ee_parent_names, 406 - .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names), 407 - }; 408 - 409 447 static const struct of_device_id meson_pwm_matches[] = { 410 448 { 411 449 .compatible = "amlogic,meson8b-pwm", ··· 404 460 }, 405 461 { 406 462 .compatible = "amlogic,meson-gxbb-pwm", 407 - .data = &pwm_gxbb_data 463 + .data = &pwm_meson8b_data 408 464 }, 409 465 { 410 466 .compatible = "amlogic,meson-gxbb-ao-pwm", ··· 420 476 }, 421 477 { 422 478 .compatible = "amlogic,meson-g12a-ee-pwm", 423 - .data = &pwm_g12a_ee_data 479 + .data = &pwm_meson8b_data 424 480 }, 425 481 { 426 482 .compatible = "amlogic,meson-g12a-ao-pwm-ab", ··· 436 492 437 493 static int meson_pwm_init_channels(struct meson_pwm *meson) 438 494 { 495 + struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {}; 439 496 struct device *dev = meson->chip.dev; 440 - struct clk_init_data init; 441 497 unsigned int i; 442 498 char name[255]; 443 499 int err; 444 500 501 + for (i = 0; i < meson->data->num_parents; i++) { 502 + mux_parent_data[i].index = -1; 503 + mux_parent_data[i].name = meson->data->parent_names[i]; 504 + } 505 + 445 506 for (i = 0; i < meson->chip.npwm; i++) { 446 507 struct meson_pwm_channel *channel = &meson->channels[i]; 508 + struct clk_parent_data div_parent = {}, gate_parent = {}; 509 + struct clk_init_data init = {}; 447 510 448 511 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); 449 512 450 513 init.name = name; 451 514 init.ops = &clk_mux_ops; 452 515 init.flags = 0; 453 - init.parent_names = meson->data->parent_names; 516 + init.parent_data = mux_parent_data; 454 517 init.num_parents = meson->data->num_parents; 455 518 456 519 channel->mux.reg = meson->base + REG_MISC_AB; ··· 469 518 channel->mux.table = NULL; 470 519 channel->mux.hw.init = &init; 471 520 472 - channel->clk = devm_clk_register(dev, &channel->mux.hw); 521 + err = devm_clk_hw_register(dev, &channel->mux.hw); 522 + if (err) { 523 + dev_err(dev, "failed to register %s: %d\n", name, err); 524 + return err; 525 + } 526 + 527 + snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i); 528 + 529 + init.name = name; 530 + init.ops = &clk_divider_ops; 531 + init.flags = CLK_SET_RATE_PARENT; 532 + div_parent.index = -1; 533 + div_parent.hw = &channel->mux.hw; 534 + init.parent_data = &div_parent; 535 + init.num_parents = 1; 536 + 537 + channel->div.reg = meson->base + REG_MISC_AB; 538 + channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift; 539 + channel->div.width = MISC_CLK_DIV_WIDTH; 540 + channel->div.hw.init = &init; 541 + channel->div.flags = 0; 542 + channel->div.lock = &meson->lock; 543 + 544 + err = devm_clk_hw_register(dev, &channel->div.hw); 545 + if (err) { 546 + dev_err(dev, "failed to register %s: %d\n", name, err); 547 + return err; 548 + } 549 + 550 + snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); 551 + 552 + init.name = name; 553 + init.ops = &clk_gate_ops; 554 + init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; 555 + gate_parent.index = -1; 556 + gate_parent.hw = &channel->div.hw; 557 + init.parent_data = &gate_parent; 558 + init.num_parents = 1; 559 + 560 + channel->gate.reg = meson->base + REG_MISC_AB; 561 + channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift; 562 + channel->gate.hw.init = &init; 563 + channel->gate.flags = 0; 564 + channel->gate.lock = &meson->lock; 565 + 566 + err = devm_clk_hw_register(dev, &channel->gate.hw); 567 + if (err) { 568 + dev_err(dev, "failed to register %s: %d\n", name, err); 569 + return err; 570 + } 571 + 572 + channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL); 473 573 if (IS_ERR(channel->clk)) { 474 574 err = PTR_ERR(channel->clk); 475 575 dev_err(dev, "failed to register %s: %d\n", name, err); 476 576 return err; 477 577 } 478 - 479 - snprintf(name, sizeof(name), "clkin%u", i); 480 - 481 - channel->clk_parent = devm_clk_get_optional(dev, name); 482 - if (IS_ERR(channel->clk_parent)) 483 - return PTR_ERR(channel->clk_parent); 484 578 } 485 579 486 580 return 0;

+507

drivers/pwm/pwm-microchip-core.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * corePWM driver for Microchip "soft" FPGA IP cores. 4 + * 5 + * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved. 6 + * Author: Conor Dooley <conor.dooley@microchip.com> 7 + * Documentation: 8 + * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb 9 + * 10 + * Limitations: 11 + * - If the IP block is configured without "shadow registers", all register 12 + * writes will take effect immediately, causing glitches on the output. 13 + * If shadow registers *are* enabled, setting the "SYNC_UPDATE" register 14 + * notifies the core that it needs to update the registers defining the 15 + * waveform from the contents of the "shadow registers". Otherwise, changes 16 + * will take effective immediately, even for those channels. 17 + * As setting the period/duty cycle takes 4 register writes, there is a window 18 + * in which this races against the start of a new period. 19 + * - The IP block has no concept of a duty cycle, only rising/falling edges of 20 + * the waveform. Unfortunately, if the rising & falling edges registers have 21 + * the same value written to them the IP block will do whichever of a rising 22 + * or a falling edge is possible. I.E. a 50% waveform at twice the requested 23 + * period. Therefore to get a 0% waveform, the output is set the max high/low 24 + * time depending on polarity. 25 + * If the duty cycle is 0%, and the requested period is less than the 26 + * available period resolution, this will manifest as a ~100% waveform (with 27 + * some output glitches) rather than 50%. 28 + * - The PWM period is set for the whole IP block not per channel. The driver 29 + * will only change the period if no other PWM output is enabled. 30 + */ 31 + 32 + #include <linux/clk.h> 33 + #include <linux/delay.h> 34 + #include <linux/err.h> 35 + #include <linux/io.h> 36 + #include <linux/ktime.h> 37 + #include <linux/math.h> 38 + #include <linux/module.h> 39 + #include <linux/mutex.h> 40 + #include <linux/of_device.h> 41 + #include <linux/platform_device.h> 42 + #include <linux/pwm.h> 43 + 44 + #define MCHPCOREPWM_PRESCALE_MAX 0xff 45 + #define MCHPCOREPWM_PERIOD_STEPS_MAX 0xfe 46 + #define MCHPCOREPWM_PERIOD_MAX 0xff00 47 + 48 + #define MCHPCOREPWM_PRESCALE 0x00 49 + #define MCHPCOREPWM_PERIOD 0x04 50 + #define MCHPCOREPWM_EN(i) (0x08 + 0x04 * (i)) /* 0x08, 0x0c */ 51 + #define MCHPCOREPWM_POSEDGE(i) (0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */ 52 + #define MCHPCOREPWM_NEGEDGE(i) (0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */ 53 + #define MCHPCOREPWM_SYNC_UPD 0xe4 54 + #define MCHPCOREPWM_TIMEOUT_MS 100u 55 + 56 + struct mchp_core_pwm_chip { 57 + struct pwm_chip chip; 58 + struct clk *clk; 59 + void __iomem *base; 60 + struct mutex lock; /* protects the shared period */ 61 + ktime_t update_timestamp; 62 + u32 sync_update_mask; 63 + u16 channel_enabled; 64 + }; 65 + 66 + static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip) 67 + { 68 + return container_of(chip, struct mchp_core_pwm_chip, chip); 69 + } 70 + 71 + static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, 72 + bool enable, u64 period) 73 + { 74 + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); 75 + u8 channel_enable, reg_offset, shift; 76 + 77 + /* 78 + * There are two adjacent 8 bit control regs, the lower reg controls 79 + * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg 80 + * and if so, offset by the bus width. 81 + */ 82 + reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); 83 + shift = pwm->hwpwm & 7; 84 + 85 + channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset); 86 + channel_enable &= ~(1 << shift); 87 + channel_enable |= (enable << shift); 88 + 89 + writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); 90 + mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); 91 + mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; 92 + 93 + /* 94 + * The updated values will not appear on the bus until they have been 95 + * applied to the waveform at the beginning of the next period. 96 + * This is a NO-OP if the channel does not have shadow registers. 97 + */ 98 + if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) 99 + mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period); 100 + } 101 + 102 + static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm, 103 + unsigned int channel) 104 + { 105 + /* 106 + * If a shadow register is used for this PWM channel, and iff there is 107 + * a pending update to the waveform, we must wait for it to be applied 108 + * before attempting to read its state. Reading the registers yields 109 + * the currently implemented settings & the new ones are only readable 110 + * once the current period has ended. 111 + */ 112 + 113 + if (mchp_core_pwm->sync_update_mask & (1 << channel)) { 114 + ktime_t current_time = ktime_get(); 115 + s64 remaining_ns; 116 + u32 delay_us; 117 + 118 + remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp, 119 + current_time)); 120 + 121 + /* 122 + * If the update has gone through, don't bother waiting for 123 + * obvious reasons. Otherwise wait around for an appropriate 124 + * amount of time for the update to go through. 125 + */ 126 + if (remaining_ns <= 0) 127 + return; 128 + 129 + delay_us = DIV_ROUND_UP_ULL(remaining_ns, NSEC_PER_USEC); 130 + fsleep(delay_us); 131 + } 132 + } 133 + 134 + static u64 mchp_core_pwm_calc_duty(const struct pwm_state *state, u64 clk_rate, 135 + u8 prescale, u8 period_steps) 136 + { 137 + u64 duty_steps, tmp; 138 + 139 + /* 140 + * Calculate the duty cycle in multiples of the prescaled period: 141 + * duty_steps = duty_in_ns / step_in_ns 142 + * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate 143 + * The code below is rearranged slightly to only divide once. 144 + */ 145 + tmp = (((u64)prescale) + 1) * NSEC_PER_SEC; 146 + duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp); 147 + 148 + return duty_steps; 149 + } 150 + 151 + static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm, 152 + const struct pwm_state *state, u64 duty_steps, 153 + u16 period_steps) 154 + { 155 + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); 156 + u8 posedge, negedge; 157 + u8 first_edge = 0, second_edge = duty_steps; 158 + 159 + /* 160 + * Setting posedge == negedge doesn't yield a constant output, 161 + * so that's an unsuitable setting to model duty_steps = 0. 162 + * In that case set the unwanted edge to a value that never 163 + * triggers. 164 + */ 165 + if (duty_steps == 0) 166 + first_edge = period_steps + 1; 167 + 168 + if (state->polarity == PWM_POLARITY_INVERSED) { 169 + negedge = first_edge; 170 + posedge = second_edge; 171 + } else { 172 + posedge = first_edge; 173 + negedge = second_edge; 174 + } 175 + 176 + /* 177 + * Set the sync bit which ensures that periods that already started are 178 + * completed unaltered. At each counter reset event the values are 179 + * updated from the shadow registers. 180 + */ 181 + writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); 182 + writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); 183 + } 184 + 185 + static int mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate, 186 + u16 *prescale, u16 *period_steps) 187 + { 188 + u64 tmp; 189 + 190 + /* 191 + * Calculate the period cycles and prescale values. 192 + * The registers are each 8 bits wide & multiplied to compute the period 193 + * using the formula: 194 + * (prescale + 1) * (period_steps + 1) 195 + * period = ------------------------------------- 196 + * clk_rate 197 + * so the maximum period that can be generated is 0x10000 times the 198 + * period of the input clock. 199 + * However, due to the design of the "hardware", it is not possible to 200 + * attain a 100% duty cycle if the full range of period_steps is used. 201 + * Therefore period_steps is restricted to 0xfe and the maximum multiple 202 + * of the clock period attainable is (0xff + 1) * (0xfe + 1) = 0xff00 203 + * 204 + * The prescale and period_steps registers operate similarly to 205 + * CLK_DIVIDER_ONE_BASED, where the value used by the hardware is that 206 + * in the register plus one. 207 + * It's therefore not possible to set a period lower than 1/clk_rate, so 208 + * if tmp is 0, abort. Without aborting, we will set a period that is 209 + * greater than that requested and, more importantly, will trigger the 210 + * neg-/pos-edge issue described in the limitations. 211 + */ 212 + tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC); 213 + if (tmp >= MCHPCOREPWM_PERIOD_MAX) { 214 + *prescale = MCHPCOREPWM_PRESCALE_MAX; 215 + *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX; 216 + 217 + return 0; 218 + } 219 + 220 + /* 221 + * There are multiple strategies that could be used to choose the 222 + * prescale & period_steps values. 223 + * Here the idea is to pick values so that the selection of duty cycles 224 + * is as finegrain as possible, while also keeping the period less than 225 + * that requested. 226 + * 227 + * A simple way to satisfy the first condition is to always set 228 + * period_steps to its maximum value. This neatly also satisfies the 229 + * second condition too, since using the maximum value of period_steps 230 + * to calculate prescale actually calculates its upper bound. 231 + * Integer division will ensure a round down, so the period will thereby 232 + * always be less than that requested. 233 + * 234 + * The downside of this approach is a significant degree of inaccuracy, 235 + * especially as tmp approaches integer multiples of 236 + * MCHPCOREPWM_PERIOD_STEPS_MAX. 237 + * 238 + * As we must produce a period less than that requested, and for the 239 + * sake of creating a simple algorithm, disallow small values of tmp 240 + * that would need special handling. 241 + */ 242 + if (tmp < MCHPCOREPWM_PERIOD_STEPS_MAX + 1) 243 + return -EINVAL; 244 + 245 + /* 246 + * This "optimal" value for prescale is be calculated using the maximum 247 + * permitted value of period_steps, 0xfe. 248 + * 249 + * period * clk_rate 250 + * prescale = ------------------------- - 1 251 + * NSEC_PER_SEC * (0xfe + 1) 252 + * 253 + * 254 + * period * clk_rate 255 + * ------------------- was precomputed as `tmp` 256 + * NSEC_PER_SEC 257 + */ 258 + *prescale = ((u16)tmp) / (MCHPCOREPWM_PERIOD_STEPS_MAX + 1) - 1; 259 + 260 + /* 261 + * period_steps can be computed from prescale: 262 + * period * clk_rate 263 + * period_steps = ----------------------------- - 1 264 + * NSEC_PER_SEC * (prescale + 1) 265 + * 266 + * However, in this approximation, we simply use the maximum value that 267 + * was used to compute prescale. 268 + */ 269 + *period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX; 270 + 271 + return 0; 272 + } 273 + 274 + static int mchp_core_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, 275 + const struct pwm_state *state) 276 + { 277 + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); 278 + bool period_locked; 279 + unsigned long clk_rate; 280 + u64 duty_steps; 281 + u16 prescale, period_steps; 282 + int ret; 283 + 284 + if (!state->enabled) { 285 + mchp_core_pwm_enable(chip, pwm, false, pwm->state.period); 286 + return 0; 287 + } 288 + 289 + /* 290 + * If clk_rate is too big, the following multiplication might overflow. 291 + * However this is implausible, as the fabric of current FPGAs cannot 292 + * provide clocks at a rate high enough. 293 + */ 294 + clk_rate = clk_get_rate(mchp_core_pwm->clk); 295 + if (clk_rate >= NSEC_PER_SEC) 296 + return -EINVAL; 297 + 298 + ret = mchp_core_pwm_calc_period(state, clk_rate, &prescale, &period_steps); 299 + if (ret) 300 + return ret; 301 + 302 + /* 303 + * If the only thing that has changed is the duty cycle or the polarity, 304 + * we can shortcut the calculations and just compute/apply the new duty 305 + * cycle pos & neg edges 306 + * As all the channels share the same period, do not allow it to be 307 + * changed if any other channels are enabled. 308 + * If the period is locked, it may not be possible to use a period 309 + * less than that requested. In that case, we just abort. 310 + */ 311 + period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); 312 + 313 + if (period_locked) { 314 + u16 hw_prescale; 315 + u16 hw_period_steps; 316 + 317 + hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); 318 + hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); 319 + 320 + if ((period_steps + 1) * (prescale + 1) < 321 + (hw_period_steps + 1) * (hw_prescale + 1)) 322 + return -EINVAL; 323 + 324 + /* 325 + * It is possible that something could have set the period_steps 326 + * register to 0xff, which would prevent us from setting a 100% 327 + * or 0% relative duty cycle, as explained above in 328 + * mchp_core_pwm_calc_period(). 329 + * The period is locked and we cannot change this, so we abort. 330 + */ 331 + if (hw_period_steps == MCHPCOREPWM_PERIOD_STEPS_MAX) 332 + return -EINVAL; 333 + 334 + prescale = hw_prescale; 335 + period_steps = hw_period_steps; 336 + } 337 + 338 + duty_steps = mchp_core_pwm_calc_duty(state, clk_rate, prescale, period_steps); 339 + 340 + /* 341 + * Because the period is not per channel, it is possible that the 342 + * requested duty cycle is longer than the period, in which case cap it 343 + * to the period, IOW a 100% duty cycle. 344 + */ 345 + if (duty_steps > period_steps) 346 + duty_steps = period_steps + 1; 347 + 348 + if (!period_locked) { 349 + writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); 350 + writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); 351 + } 352 + 353 + mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps); 354 + 355 + mchp_core_pwm_enable(chip, pwm, true, pwm->state.period); 356 + 357 + return 0; 358 + } 359 + 360 + static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 361 + const struct pwm_state *state) 362 + { 363 + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); 364 + int ret; 365 + 366 + mutex_lock(&mchp_core_pwm->lock); 367 + 368 + mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); 369 + 370 + ret = mchp_core_pwm_apply_locked(chip, pwm, state); 371 + 372 + mutex_unlock(&mchp_core_pwm->lock); 373 + 374 + return ret; 375 + } 376 + 377 + static int mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 378 + struct pwm_state *state) 379 + { 380 + struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); 381 + u64 rate; 382 + u16 prescale, period_steps; 383 + u8 duty_steps, posedge, negedge; 384 + 385 + mutex_lock(&mchp_core_pwm->lock); 386 + 387 + mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); 388 + 389 + if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm)) 390 + state->enabled = true; 391 + else 392 + state->enabled = false; 393 + 394 + rate = clk_get_rate(mchp_core_pwm->clk); 395 + 396 + /* 397 + * Calculating the period: 398 + * The registers are each 8 bits wide & multiplied to compute the period 399 + * using the formula: 400 + * (prescale + 1) * (period_steps + 1) 401 + * period = ------------------------------------- 402 + * clk_rate 403 + * 404 + * Note: 405 + * The prescale and period_steps registers operate similarly to 406 + * CLK_DIVIDER_ONE_BASED, where the value used by the hardware is that 407 + * in the register plus one. 408 + */ 409 + prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); 410 + period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); 411 + 412 + state->period = (period_steps + 1) * (prescale + 1); 413 + state->period *= NSEC_PER_SEC; 414 + state->period = DIV64_U64_ROUND_UP(state->period, rate); 415 + 416 + posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); 417 + negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); 418 + 419 + mutex_unlock(&mchp_core_pwm->lock); 420 + 421 + if (negedge == posedge) { 422 + state->duty_cycle = state->period; 423 + state->period *= 2; 424 + } else { 425 + duty_steps = abs((s16)posedge - (s16)negedge); 426 + state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC; 427 + state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate); 428 + } 429 + 430 + state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; 431 + 432 + return 0; 433 + } 434 + 435 + static const struct pwm_ops mchp_core_pwm_ops = { 436 + .apply = mchp_core_pwm_apply, 437 + .get_state = mchp_core_pwm_get_state, 438 + .owner = THIS_MODULE, 439 + }; 440 + 441 + static const struct of_device_id mchp_core_of_match[] = { 442 + { 443 + .compatible = "microchip,corepwm-rtl-v4", 444 + }, 445 + { /* sentinel */ } 446 + }; 447 + MODULE_DEVICE_TABLE(of, mchp_core_of_match); 448 + 449 + static int mchp_core_pwm_probe(struct platform_device *pdev) 450 + { 451 + struct mchp_core_pwm_chip *mchp_core_pwm; 452 + struct resource *regs; 453 + int ret; 454 + 455 + mchp_core_pwm = devm_kzalloc(&pdev->dev, sizeof(*mchp_core_pwm), GFP_KERNEL); 456 + if (!mchp_core_pwm) 457 + return -ENOMEM; 458 + 459 + mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs); 460 + if (IS_ERR(mchp_core_pwm->base)) 461 + return PTR_ERR(mchp_core_pwm->base); 462 + 463 + mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL); 464 + if (IS_ERR(mchp_core_pwm->clk)) 465 + return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk), 466 + "failed to get PWM clock\n"); 467 + 468 + if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask", 469 + &mchp_core_pwm->sync_update_mask)) 470 + mchp_core_pwm->sync_update_mask = 0; 471 + 472 + mutex_init(&mchp_core_pwm->lock); 473 + 474 + mchp_core_pwm->chip.dev = &pdev->dev; 475 + mchp_core_pwm->chip.ops = &mchp_core_pwm_ops; 476 + mchp_core_pwm->chip.npwm = 16; 477 + 478 + mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0)); 479 + mchp_core_pwm->channel_enabled |= 480 + readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8; 481 + 482 + /* 483 + * Enable synchronous update mode for all channels for which shadow 484 + * registers have been synthesised. 485 + */ 486 + writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD); 487 + mchp_core_pwm->update_timestamp = ktime_get(); 488 + 489 + ret = devm_pwmchip_add(&pdev->dev, &mchp_core_pwm->chip); 490 + if (ret) 491 + return dev_err_probe(&pdev->dev, ret, "Failed to add pwmchip\n"); 492 + 493 + return 0; 494 + } 495 + 496 + static struct platform_driver mchp_core_pwm_driver = { 497 + .driver = { 498 + .name = "mchp-core-pwm", 499 + .of_match_table = mchp_core_of_match, 500 + }, 501 + .probe = mchp_core_pwm_probe, 502 + }; 503 + module_platform_driver(mchp_core_pwm_driver); 504 + 505 + MODULE_LICENSE("GPL"); 506 + MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); 507 + MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs");

+5 -8

drivers/pwm/pwm-mtk-disp.c

··· 79 79 if (state->polarity != PWM_POLARITY_NORMAL) 80 80 return -EINVAL; 81 81 82 - if (!state->enabled) { 83 - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, 84 - 0x0); 85 - 86 - if (mdp->enabled) { 87 - clk_disable_unprepare(mdp->clk_mm); 88 - clk_disable_unprepare(mdp->clk_main); 89 - } 82 + if (!state->enabled && mdp->enabled) { 83 + mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, 84 + mdp->data->enable_mask, 0x0); 85 + clk_disable_unprepare(mdp->clk_mm); 86 + clk_disable_unprepare(mdp->clk_main); 90 87 91 88 mdp->enabled = false; 92 89 return 0;

+1 -1

drivers/pwm/pwm-pca9685.c

··· 665 665 .of_match_table = of_match_ptr(pca9685_dt_ids), 666 666 .pm = &pca9685_pwm_pm, 667 667 }, 668 - .probe_new = pca9685_pwm_probe, 668 + .probe = pca9685_pwm_probe, 669 669 .remove = pca9685_pwm_remove, 670 670 .id_table = pca9685_id, 671 671 };

+551

drivers/pwm/pwm-rz-mtu3.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Renesas RZ/G2L MTU3a PWM Timer driver 4 + * 5 + * Copyright (C) 2023 Renesas Electronics Corporation 6 + * 7 + * Hardware manual for this IP can be found here 8 + * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en 9 + * 10 + * Limitations: 11 + * - When PWM is disabled, the output is driven to Hi-Z. 12 + * - While the hardware supports both polarities, the driver (for now) 13 + * only handles normal polarity. 14 + * - HW uses one counter and two match components to configure duty_cycle 15 + * and period. 16 + * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM 17 + * operations. (The channels are MTU{0..4, 6, 7}.) 18 + * - MTU{1, 2} channels have a single IO, whereas all other HW channels have 19 + * 2 IOs. 20 + * - Each IO is modelled as an independent PWM channel. 21 + * - rz_mtu3_channel_io_map table is used to map the PWM channel to the 22 + * corresponding HW channel as there are difference in number of IOs 23 + * between HW channels. 24 + */ 25 + 26 + #include <linux/bitfield.h> 27 + #include <linux/clk.h> 28 + #include <linux/limits.h> 29 + #include <linux/mfd/rz-mtu3.h> 30 + #include <linux/module.h> 31 + #include <linux/platform_device.h> 32 + #include <linux/pm_runtime.h> 33 + #include <linux/pwm.h> 34 + #include <linux/time.h> 35 + 36 + #define RZ_MTU3_MAX_PWM_CHANNELS 12 37 + #define RZ_MTU3_MAX_HW_CHANNELS 7 38 + 39 + /** 40 + * struct rz_mtu3_channel_io_map - MTU3 pwm channel map 41 + * 42 + * @base_pwm_number: First PWM of a channel 43 + * @num: number of IOs on the HW channel. 44 + */ 45 + struct rz_mtu3_channel_io_map { 46 + u8 base_pwm_number; 47 + u8 num_channel_ios; 48 + }; 49 + 50 + /** 51 + * struct rz_mtu3_pwm_channel - MTU3 pwm channel data 52 + * 53 + * @mtu: MTU3 channel data 54 + * @map: MTU3 pwm channel map 55 + */ 56 + struct rz_mtu3_pwm_channel { 57 + struct rz_mtu3_channel *mtu; 58 + const struct rz_mtu3_channel_io_map *map; 59 + }; 60 + 61 + /** 62 + * struct rz_mtu3_pwm_chip - MTU3 pwm private data 63 + * 64 + * @chip: MTU3 pwm chip data 65 + * @clk: MTU3 module clock 66 + * @lock: Lock to prevent concurrent access for usage count 67 + * @rate: MTU3 clock rate 68 + * @user_count: MTU3 usage count 69 + * @enable_count: MTU3 enable count 70 + * @prescale: MTU3 prescale 71 + * @channel_data: MTU3 pwm channel data 72 + */ 73 + 74 + struct rz_mtu3_pwm_chip { 75 + struct pwm_chip chip; 76 + struct clk *clk; 77 + struct mutex lock; 78 + unsigned long rate; 79 + u32 user_count[RZ_MTU3_MAX_HW_CHANNELS]; 80 + u32 enable_count[RZ_MTU3_MAX_HW_CHANNELS]; 81 + u8 prescale[RZ_MTU3_MAX_HW_CHANNELS]; 82 + struct rz_mtu3_pwm_channel channel_data[RZ_MTU3_MAX_HW_CHANNELS]; 83 + }; 84 + 85 + /* 86 + * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1 87 + * and MTU2 channel is 1 compared to 2 on others. 88 + */ 89 + static const struct rz_mtu3_channel_io_map channel_map[] = { 90 + { 0, 2 }, { 2, 1 }, { 3, 1 }, { 4, 2 }, { 6, 2 }, { 8, 2 }, { 10, 2 } 91 + }; 92 + 93 + static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip) 94 + { 95 + return container_of(chip, struct rz_mtu3_pwm_chip, chip); 96 + } 97 + 98 + static void rz_mtu3_pwm_read_tgr_registers(struct rz_mtu3_pwm_channel *priv, 99 + u16 reg_pv_offset, u16 *pv_val, 100 + u16 reg_dc_offset, u16 *dc_val) 101 + { 102 + *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset); 103 + *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset); 104 + } 105 + 106 + static void rz_mtu3_pwm_write_tgr_registers(struct rz_mtu3_pwm_channel *priv, 107 + u16 reg_pv_offset, u16 pv_val, 108 + u16 reg_dc_offset, u16 dc_val) 109 + { 110 + rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val); 111 + rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val); 112 + } 113 + 114 + static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rz_mtu3, 115 + u64 period_cycles) 116 + { 117 + u32 prescaled_period_cycles; 118 + u8 prescale; 119 + 120 + /* 121 + * Supported prescale values are 1, 4, 16 and 64. 122 + * TODO: Support prescale values 2, 8, 32, 256 and 1024. 123 + */ 124 + prescaled_period_cycles = period_cycles >> 16; 125 + if (prescaled_period_cycles >= 16) 126 + prescale = 3; 127 + else 128 + prescale = (fls(prescaled_period_cycles) + 1) / 2; 129 + 130 + return prescale; 131 + } 132 + 133 + static struct rz_mtu3_pwm_channel * 134 + rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) 135 + { 136 + struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data; 137 + unsigned int ch; 138 + 139 + for (ch = 0; ch < RZ_MTU3_MAX_HW_CHANNELS; ch++, priv++) { 140 + if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) 141 + break; 142 + } 143 + 144 + return priv; 145 + } 146 + 147 + static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, 148 + u32 hwpwm) 149 + { 150 + struct rz_mtu3_pwm_channel *priv; 151 + bool is_channel_en; 152 + u8 val; 153 + 154 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); 155 + is_channel_en = rz_mtu3_is_enabled(priv->mtu); 156 + if (!is_channel_en) 157 + return false; 158 + 159 + if (priv->map->base_pwm_number == hwpwm) 160 + val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH); 161 + else 162 + val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL); 163 + 164 + return val & RZ_MTU3_TIOR_IOA; 165 + } 166 + 167 + static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 168 + { 169 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 170 + struct rz_mtu3_pwm_channel *priv; 171 + bool is_mtu3_channel_available; 172 + u32 ch; 173 + 174 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 175 + ch = priv - rz_mtu3_pwm->channel_data; 176 + 177 + mutex_lock(&rz_mtu3_pwm->lock); 178 + /* 179 + * Each channel must be requested only once, so if the channel 180 + * serves two PWMs and the other is already requested, skip over 181 + * rz_mtu3_request_channel() 182 + */ 183 + if (!rz_mtu3_pwm->user_count[ch]) { 184 + is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu); 185 + if (!is_mtu3_channel_available) { 186 + mutex_unlock(&rz_mtu3_pwm->lock); 187 + return -EBUSY; 188 + } 189 + } 190 + 191 + rz_mtu3_pwm->user_count[ch]++; 192 + mutex_unlock(&rz_mtu3_pwm->lock); 193 + 194 + return 0; 195 + } 196 + 197 + static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 198 + { 199 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 200 + struct rz_mtu3_pwm_channel *priv; 201 + u32 ch; 202 + 203 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 204 + ch = priv - rz_mtu3_pwm->channel_data; 205 + 206 + mutex_lock(&rz_mtu3_pwm->lock); 207 + rz_mtu3_pwm->user_count[ch]--; 208 + if (!rz_mtu3_pwm->user_count[ch]) 209 + rz_mtu3_release_channel(priv->mtu); 210 + 211 + mutex_unlock(&rz_mtu3_pwm->lock); 212 + } 213 + 214 + static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, 215 + struct pwm_device *pwm) 216 + { 217 + struct rz_mtu3_pwm_channel *priv; 218 + u32 ch; 219 + u8 val; 220 + int rc; 221 + 222 + rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev); 223 + if (rc) 224 + return rc; 225 + 226 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 227 + ch = priv - rz_mtu3_pwm->channel_data; 228 + val = RZ_MTU3_TIOR_OC_IOB_TOGGLE | RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH; 229 + 230 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1); 231 + if (priv->map->base_pwm_number == pwm->hwpwm) 232 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val); 233 + else 234 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val); 235 + 236 + mutex_lock(&rz_mtu3_pwm->lock); 237 + if (!rz_mtu3_pwm->enable_count[ch]) 238 + rz_mtu3_enable(priv->mtu); 239 + 240 + rz_mtu3_pwm->enable_count[ch]++; 241 + mutex_unlock(&rz_mtu3_pwm->lock); 242 + 243 + return 0; 244 + } 245 + 246 + static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, 247 + struct pwm_device *pwm) 248 + { 249 + struct rz_mtu3_pwm_channel *priv; 250 + u32 ch; 251 + 252 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 253 + ch = priv - rz_mtu3_pwm->channel_data; 254 + 255 + /* Disable output pins of MTU3 channel */ 256 + if (priv->map->base_pwm_number == pwm->hwpwm) 257 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN); 258 + else 259 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN); 260 + 261 + mutex_lock(&rz_mtu3_pwm->lock); 262 + rz_mtu3_pwm->enable_count[ch]--; 263 + if (!rz_mtu3_pwm->enable_count[ch]) 264 + rz_mtu3_disable(priv->mtu); 265 + 266 + mutex_unlock(&rz_mtu3_pwm->lock); 267 + 268 + pm_runtime_put_sync(rz_mtu3_pwm->chip.dev); 269 + } 270 + 271 + static int rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 272 + struct pwm_state *state) 273 + { 274 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 275 + int rc; 276 + 277 + rc = pm_runtime_resume_and_get(chip->dev); 278 + if (rc) 279 + return rc; 280 + 281 + state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm); 282 + if (state->enabled) { 283 + struct rz_mtu3_pwm_channel *priv; 284 + u8 prescale, val; 285 + u16 dc, pv; 286 + u64 tmp; 287 + 288 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 289 + if (priv->map->base_pwm_number == pwm->hwpwm) 290 + rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRA, &pv, 291 + RZ_MTU3_TGRB, &dc); 292 + else 293 + rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRC, &pv, 294 + RZ_MTU3_TGRD, &dc); 295 + 296 + val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR); 297 + prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val); 298 + 299 + /* With prescale <= 7 and pv <= 0xffff this doesn't overflow. */ 300 + tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale); 301 + state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); 302 + tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale); 303 + state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); 304 + 305 + if (state->duty_cycle > state->period) 306 + state->duty_cycle = state->period; 307 + } 308 + 309 + state->polarity = PWM_POLARITY_NORMAL; 310 + pm_runtime_put(chip->dev); 311 + 312 + return 0; 313 + } 314 + 315 + static u16 rz_mtu3_pwm_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale) 316 + { 317 + return min(period_or_duty_cycle >> (2 * prescale), (u64)U16_MAX); 318 + } 319 + 320 + static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 321 + const struct pwm_state *state) 322 + { 323 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 324 + struct rz_mtu3_pwm_channel *priv; 325 + u64 period_cycles; 326 + u64 duty_cycles; 327 + u8 prescale; 328 + u16 pv, dc; 329 + u8 val; 330 + u32 ch; 331 + 332 + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); 333 + ch = priv - rz_mtu3_pwm->channel_data; 334 + 335 + period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate, 336 + NSEC_PER_SEC); 337 + prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles); 338 + 339 + /* 340 + * Prescalar is shared by multiple channels, so prescale can 341 + * NOT be modified when there are multiple channels in use with 342 + * different settings. Modify prescalar if other PWM is off or handle 343 + * it, if current prescale value is less than the one we want to set. 344 + */ 345 + if (rz_mtu3_pwm->enable_count[ch] > 1) { 346 + if (rz_mtu3_pwm->prescale[ch] > prescale) 347 + return -EBUSY; 348 + 349 + prescale = rz_mtu3_pwm->prescale[ch]; 350 + } 351 + 352 + pv = rz_mtu3_pwm_calculate_pv_or_dc(period_cycles, prescale); 353 + 354 + duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate, 355 + NSEC_PER_SEC); 356 + dc = rz_mtu3_pwm_calculate_pv_or_dc(duty_cycles, prescale); 357 + 358 + /* 359 + * If the PWM channel is disabled, make sure to turn on the clock 360 + * before writing the register. 361 + */ 362 + if (!pwm->state.enabled) { 363 + int rc; 364 + 365 + rc = pm_runtime_resume_and_get(chip->dev); 366 + if (rc) 367 + return rc; 368 + } 369 + 370 + val = RZ_MTU3_TCR_CKEG_RISING | prescale; 371 + 372 + /* Counter must be stopped while updating TCR register */ 373 + if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch]) 374 + rz_mtu3_disable(priv->mtu); 375 + 376 + if (priv->map->base_pwm_number == pwm->hwpwm) { 377 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, 378 + RZ_MTU3_TCR_CCLR_TGRA | val); 379 + rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRA, pv, 380 + RZ_MTU3_TGRB, dc); 381 + } else { 382 + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, 383 + RZ_MTU3_TCR_CCLR_TGRC | val); 384 + rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRC, pv, 385 + RZ_MTU3_TGRD, dc); 386 + } 387 + 388 + if (rz_mtu3_pwm->prescale[ch] != prescale) { 389 + /* 390 + * Prescalar is shared by multiple channels, we cache the 391 + * prescalar value from first enabled channel and use the same 392 + * value for both channels. 393 + */ 394 + rz_mtu3_pwm->prescale[ch] = prescale; 395 + 396 + if (rz_mtu3_pwm->enable_count[ch]) 397 + rz_mtu3_enable(priv->mtu); 398 + } 399 + 400 + /* If the PWM is not enabled, turn the clock off again to save power. */ 401 + if (!pwm->state.enabled) 402 + pm_runtime_put(chip->dev); 403 + 404 + return 0; 405 + } 406 + 407 + static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 408 + const struct pwm_state *state) 409 + { 410 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); 411 + bool enabled = pwm->state.enabled; 412 + int ret; 413 + 414 + if (state->polarity != PWM_POLARITY_NORMAL) 415 + return -EINVAL; 416 + 417 + if (!state->enabled) { 418 + if (enabled) 419 + rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm); 420 + 421 + return 0; 422 + } 423 + 424 + mutex_lock(&rz_mtu3_pwm->lock); 425 + ret = rz_mtu3_pwm_config(chip, pwm, state); 426 + mutex_unlock(&rz_mtu3_pwm->lock); 427 + if (ret) 428 + return ret; 429 + 430 + if (!enabled) 431 + ret = rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm); 432 + 433 + return ret; 434 + } 435 + 436 + static const struct pwm_ops rz_mtu3_pwm_ops = { 437 + .request = rz_mtu3_pwm_request, 438 + .free = rz_mtu3_pwm_free, 439 + .get_state = rz_mtu3_pwm_get_state, 440 + .apply = rz_mtu3_pwm_apply, 441 + .owner = THIS_MODULE, 442 + }; 443 + 444 + static int rz_mtu3_pwm_pm_runtime_suspend(struct device *dev) 445 + { 446 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev); 447 + 448 + clk_disable_unprepare(rz_mtu3_pwm->clk); 449 + 450 + return 0; 451 + } 452 + 453 + static int rz_mtu3_pwm_pm_runtime_resume(struct device *dev) 454 + { 455 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev); 456 + 457 + return clk_prepare_enable(rz_mtu3_pwm->clk); 458 + } 459 + 460 + static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_pwm_pm_ops, 461 + rz_mtu3_pwm_pm_runtime_suspend, 462 + rz_mtu3_pwm_pm_runtime_resume, NULL); 463 + 464 + static void rz_mtu3_pwm_pm_disable(void *data) 465 + { 466 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data; 467 + 468 + clk_rate_exclusive_put(rz_mtu3_pwm->clk); 469 + pm_runtime_disable(rz_mtu3_pwm->chip.dev); 470 + pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev); 471 + } 472 + 473 + static int rz_mtu3_pwm_probe(struct platform_device *pdev) 474 + { 475 + struct rz_mtu3 *parent_ddata = dev_get_drvdata(pdev->dev.parent); 476 + struct rz_mtu3_pwm_chip *rz_mtu3_pwm; 477 + struct device *dev = &pdev->dev; 478 + unsigned int i, j = 0; 479 + int ret; 480 + 481 + rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL); 482 + if (!rz_mtu3_pwm) 483 + return -ENOMEM; 484 + 485 + rz_mtu3_pwm->clk = parent_ddata->clk; 486 + 487 + for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) { 488 + if (i == RZ_MTU3_CHAN_5 || i == RZ_MTU3_CHAN_8) 489 + continue; 490 + 491 + rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i]; 492 + rz_mtu3_pwm->channel_data[j].mtu->dev = dev; 493 + rz_mtu3_pwm->channel_data[j].map = &channel_map[j]; 494 + j++; 495 + } 496 + 497 + mutex_init(&rz_mtu3_pwm->lock); 498 + platform_set_drvdata(pdev, rz_mtu3_pwm); 499 + ret = clk_prepare_enable(rz_mtu3_pwm->clk); 500 + if (ret) 501 + return dev_err_probe(dev, ret, "Clock enable failed\n"); 502 + 503 + clk_rate_exclusive_get(rz_mtu3_pwm->clk); 504 + 505 + rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk); 506 + /* 507 + * Refuse clk rates > 1 GHz to prevent overflow later for computing 508 + * period and duty cycle. 509 + */ 510 + if (rz_mtu3_pwm->rate > NSEC_PER_SEC) { 511 + ret = -EINVAL; 512 + clk_rate_exclusive_put(rz_mtu3_pwm->clk); 513 + goto disable_clock; 514 + } 515 + 516 + pm_runtime_set_active(&pdev->dev); 517 + pm_runtime_enable(&pdev->dev); 518 + rz_mtu3_pwm->chip.dev = &pdev->dev; 519 + ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_pwm_pm_disable, 520 + rz_mtu3_pwm); 521 + if (ret < 0) 522 + return ret; 523 + 524 + rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops; 525 + rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS; 526 + ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip); 527 + if (ret) 528 + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); 529 + 530 + pm_runtime_idle(&pdev->dev); 531 + 532 + return 0; 533 + 534 + disable_clock: 535 + clk_disable_unprepare(rz_mtu3_pwm->clk); 536 + return ret; 537 + } 538 + 539 + static struct platform_driver rz_mtu3_pwm_driver = { 540 + .driver = { 541 + .name = "pwm-rz-mtu3", 542 + .pm = pm_ptr(&rz_mtu3_pwm_pm_ops), 543 + }, 544 + .probe = rz_mtu3_pwm_probe, 545 + }; 546 + module_platform_driver(rz_mtu3_pwm_driver); 547 + 548 + MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 549 + MODULE_ALIAS("platform:pwm-rz-mtu3"); 550 + MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a PWM Timer Driver"); 551 + MODULE_LICENSE("GPL");

+2 -5

drivers/pwm/pwm-sifive.c

··· 244 244 if (IS_ERR(ddata->regs)) 245 245 return PTR_ERR(ddata->regs); 246 246 247 - ddata->clk = devm_clk_get(dev, NULL); 247 + ddata->clk = devm_clk_get_prepared(dev, NULL); 248 248 if (IS_ERR(ddata->clk)) 249 249 return dev_err_probe(dev, PTR_ERR(ddata->clk), 250 250 "Unable to find controller clock\n"); 251 251 252 - ret = clk_prepare_enable(ddata->clk); 252 + ret = clk_enable(ddata->clk); 253 253 if (ret) { 254 254 dev_err(dev, "failed to enable clock for pwm: %d\n", ret); 255 255 return ret; ··· 308 308 clk_disable(ddata->clk); 309 309 --enabled_clks; 310 310 } 311 - clk_unprepare(ddata->clk); 312 311 313 312 return ret; 314 313 } ··· 326 327 if (pwm->state.enabled) 327 328 clk_disable(ddata->clk); 328 329 } 329 - 330 - clk_unprepare(ddata->clk); 331 330 } 332 331 333 332 static const struct of_device_id pwm_sifive_of_match[] = {

+17

drivers/pwm/sysfs.c

··· 424 424 if (!export) 425 425 continue; 426 426 427 + /* If pwmchip was not enabled before suspend, do nothing. */ 428 + if (!export->suspend.enabled) { 429 + /* release lock taken in pwm_class_get_state */ 430 + mutex_unlock(&export->lock); 431 + continue; 432 + } 433 + 427 434 state.enabled = export->suspend.enabled; 428 435 ret = pwm_class_apply_state(export, pwm, &state); 429 436 if (ret < 0) ··· 455 448 if (!export) 456 449 continue; 457 450 451 + /* 452 + * If pwmchip was not enabled before suspend, save 453 + * state for resume time and do nothing else. 454 + */ 458 455 export->suspend = state; 456 + if (!state.enabled) { 457 + /* release lock taken in pwm_class_get_state */ 458 + mutex_unlock(&export->lock); 459 + continue; 460 + } 461 + 459 462 state.enabled = false; 460 463 ret = pwm_class_apply_state(export, pwm, &state); 461 464 if (ret < 0) {

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