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clk: qcom: dispcc-sm8250: Enable parents for pixel clocks

Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent
clocks are enabled during clock operations, preventing potential
stability issues during display configuration.

Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-9-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Val Packett and committed by
Bjorn Andersson acf7a91d 8c522da7

+2 -2
+2 -2
drivers/clk/qcom/dispcc-sm8250.c
··· 578 578 .name = "disp_cc_mdss_pclk0_clk_src", 579 579 .parent_data = disp_cc_parent_data_6, 580 580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 581 - .flags = CLK_SET_RATE_PARENT, 581 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 582 582 .ops = &clk_pixel_ops, 583 583 }, 584 584 }; ··· 592 592 .name = "disp_cc_mdss_pclk1_clk_src", 593 593 .parent_data = disp_cc_parent_data_6, 594 594 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 595 - .flags = CLK_SET_RATE_PARENT, 595 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 596 596 .ops = &clk_pixel_ops, 597 597 }, 598 598 };