Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6

+4 -1

drivers/gpu/drm/i915/i915_drv.h

··· 262 262 }; 263 263 264 264 #define QUIRK_PIPEA_FORCE (1<<0) 265 + #define QUIRK_LVDS_SSC_DISABLE (1<<1) 265 266 266 267 struct intel_fbdev; 267 268 ··· 1195 1194 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1196 1195 1197 1196 uint32_t 1198 - i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj); 1197 + i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1198 + uint32_t size, 1199 + int tiling_mode); 1199 1200 1200 1201 /* i915_gem_gtt.c */ 1201 1202 void i915_gem_restore_gtt_mappings(struct drm_device *dev);

+35 -36

drivers/gpu/drm/i915/i915_gem.c

··· 1374 1374 } 1375 1375 1376 1376 static uint32_t 1377 - i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) 1377 + i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) 1378 1378 { 1379 - struct drm_device *dev = obj->base.dev; 1380 - uint32_t size; 1379 + uint32_t gtt_size; 1381 1380 1382 1381 if (INTEL_INFO(dev)->gen >= 4 || 1383 - obj->tiling_mode == I915_TILING_NONE) 1384 - return obj->base.size; 1382 + tiling_mode == I915_TILING_NONE) 1383 + return size; 1385 1384 1386 1385 /* Previous chips need a power-of-two fence region when tiling */ 1387 1386 if (INTEL_INFO(dev)->gen == 3) 1388 - size = 1024*1024; 1387 + gtt_size = 1024*1024; 1389 1388 else 1390 - size = 512*1024; 1389 + gtt_size = 512*1024; 1391 1390 1392 - while (size < obj->base.size) 1393 - size <<= 1; 1391 + while (gtt_size < size) 1392 + gtt_size <<= 1; 1394 1393 1395 - return size; 1394 + return gtt_size; 1396 1395 } 1397 1396 1398 1397 /** ··· 1402 1403 * potential fence register mapping. 1403 1404 */ 1404 1405 static uint32_t 1405 - i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) 1406 + i915_gem_get_gtt_alignment(struct drm_device *dev, 1407 + uint32_t size, 1408 + int tiling_mode) 1406 1409 { 1407 - struct drm_device *dev = obj->base.dev; 1408 - 1409 1410 /* 1410 1411 * Minimum alignment is 4k (GTT page size), but might be greater 1411 1412 * if a fence register is needed for the object. 1412 1413 */ 1413 1414 if (INTEL_INFO(dev)->gen >= 4 || 1414 - obj->tiling_mode == I915_TILING_NONE) 1415 + tiling_mode == I915_TILING_NONE) 1415 1416 return 4096; 1416 1417 1417 1418 /* 1418 1419 * Previous chips need to be aligned to the size of the smallest 1419 1420 * fence register that can contain the object. 1420 1421 */ 1421 - return i915_gem_get_gtt_size(obj); 1422 + return i915_gem_get_gtt_size(dev, size, tiling_mode); 1422 1423 } 1423 1424 1424 1425 /** 1425 1426 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an 1426 1427 * unfenced object 1427 - * @obj: object to check 1428 + * @dev: the device 1429 + * @size: size of the object 1430 + * @tiling_mode: tiling mode of the object 1428 1431 * 1429 1432 * Return the required GTT alignment for an object, only taking into account 1430 1433 * unfenced tiled surface requirements. 1431 1434 */ 1432 1435 uint32_t 1433 - i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) 1436 + i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1437 + uint32_t size, 1438 + int tiling_mode) 1434 1439 { 1435 - struct drm_device *dev = obj->base.dev; 1436 - int tile_height; 1437 - 1438 1440 /* 1439 1441 * Minimum alignment is 4k (GTT page size) for sane hw. 1440 1442 */ 1441 1443 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || 1442 - obj->tiling_mode == I915_TILING_NONE) 1444 + tiling_mode == I915_TILING_NONE) 1443 1445 return 4096; 1444 1446 1445 - /* 1446 - * Older chips need unfenced tiled buffers to be aligned to the left 1447 - * edge of an even tile row (where tile rows are counted as if the bo is 1448 - * placed in a fenced gtt region). 1447 + /* Previous hardware however needs to be aligned to a power-of-two 1448 + * tile height. The simplest method for determining this is to reuse 1449 + * the power-of-tile object size. 1449 1450 */ 1450 - if (IS_GEN2(dev)) 1451 - tile_height = 16; 1452 - else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) 1453 - tile_height = 32; 1454 - else 1455 - tile_height = 8; 1456 - 1457 - return tile_height * obj->stride * 2; 1451 + return i915_gem_get_gtt_size(dev, size, tiling_mode); 1458 1452 } 1459 1453 1460 1454 int ··· 2736 2744 return -EINVAL; 2737 2745 } 2738 2746 2739 - fence_size = i915_gem_get_gtt_size(obj); 2740 - fence_alignment = i915_gem_get_gtt_alignment(obj); 2741 - unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); 2747 + fence_size = i915_gem_get_gtt_size(dev, 2748 + obj->base.size, 2749 + obj->tiling_mode); 2750 + fence_alignment = i915_gem_get_gtt_alignment(dev, 2751 + obj->base.size, 2752 + obj->tiling_mode); 2753 + unfenced_alignment = 2754 + i915_gem_get_unfenced_gtt_alignment(dev, 2755 + obj->base.size, 2756 + obj->tiling_mode); 2742 2757 2743 2758 if (alignment == 0) 2744 2759 alignment = map_and_fenceable ? fence_alignment :

+3 -1

drivers/gpu/drm/i915/i915_gem_tiling.c

··· 348 348 /* Rebind if we need a change of alignment */ 349 349 if (!obj->map_and_fenceable) { 350 350 u32 unfenced_alignment = 351 - i915_gem_get_unfenced_gtt_alignment(obj); 351 + i915_gem_get_unfenced_gtt_alignment(dev, 352 + obj->base.size, 353 + args->tiling_mode); 352 354 if (obj->gtt_offset & (unfenced_alignment - 1)) 353 355 ret = i915_gem_object_unbind(obj); 354 356 }

+14 -1

drivers/gpu/drm/i915/intel_display.c

··· 4305 4305 4306 4306 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 4307 4307 { 4308 - return dev_priv->lvds_use_ssc && i915_panel_use_ssc; 4308 + return dev_priv->lvds_use_ssc && i915_panel_use_ssc 4309 + && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 4309 4310 } 4310 4311 4311 4312 static int i9xx_crtc_mode_set(struct drm_crtc *crtc, ··· 7811 7810 DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); 7812 7811 } 7813 7812 7813 + /* 7814 + * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 7815 + */ 7816 + static void quirk_ssc_force_disable(struct drm_device *dev) 7817 + { 7818 + struct drm_i915_private *dev_priv = dev->dev_private; 7819 + dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 7820 + } 7821 + 7814 7822 struct intel_quirk { 7815 7823 int device; 7816 7824 int subsystem_vendor; ··· 7848 7838 /* 855 & before need to leave pipe A & dpll A up */ 7849 7839 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 7850 7840 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 7841 + 7842 + /* Lenovo U160 cannot use SSC on LVDS */ 7843 + { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 7851 7844 }; 7852 7845 7853 7846 static void intel_init_quirks(struct drm_device *dev)

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