Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Replace this driver's HIWORD_UPDATE with the FIELD_PREP_WM16 macro from
hw_bitfield.h. While at it, disambiguate the GRF write to SOC_CON7 by
splitting the definition into the individual bitflags. This is done
because FIELD_PREP_WM16 shifts the value for us according to the mask,
so writing the mask to itself to enable two bits is no longer something
that can be done. It should also not be done anyway because it hides the
true meaning of those two individual bit flags.
HDMI output with this patch has been tested on both RK3588 and RK3576.
On the former, with both present HDMI connectors.
Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
authored by
Nicolas Frattaroli
and committed by
Yury Norov
ad24f6e1
d6de45fd
+33
-35
+33
-35
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+33
-35
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
···
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/hw_bitfield.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
···
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#define RK3588_HDMI1_HPD_INT_MSK BIT(15)
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#define RK3588_HDMI1_HPD_INT_CLR BIT(14)
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#define RK3588_GRF_SOC_CON7 0x031c
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#define RK3588_SET_HPD_PATH_MASK GENMASK(13, 12)
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#define RK3588_HPD_HDMI0_IO_EN_MASK BIT(12)
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#define RK3588_HPD_HDMI1_IO_EN_MASK BIT(13)
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#define RK3588_GRF_SOC_STATUS1 0x0384
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#define RK3588_HDMI0_LEVEL_INT BIT(16)
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#define RK3588_HDMI1_LEVEL_INT BIT(24)
···
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#define RK3588_HDMI0_GRANT_SEL BIT(10)
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#define RK3588_HDMI1_GRANT_SEL BIT(12)
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-
#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
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#define HOTPLUG_DEBOUNCE_MS 150
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#define MAX_HDMI_PORT_NUM 2
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···
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u32 val;
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if (hdmi->port_id)
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-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR,
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RK3588_HDMI1_HPD_INT_CLR | RK3588_HDMI1_HPD_INT_MSK);
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val = (FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1) |
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FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0));
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else
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-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
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RK3588_HDMI0_HPD_INT_CLR | RK3588_HDMI0_HPD_INT_MSK);
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val = (FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1) |
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FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0));
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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}
···
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
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u32 val;
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val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_CLR,
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RK3576_HDMI_HPD_INT_CLR | RK3576_HDMI_HPD_INT_MSK);
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val = (FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1) |
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FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0));
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regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
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regmap_write(hdmi->regmap, 0xa404, 0xffff0102);
···
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regmap_read(hdmi->regmap, RK3576_IOC_HDMI_HPD_STATUS, &intr_stat);
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if (intr_stat) {
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val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_MSK, RK3576_HDMI_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1);
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regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
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return IRQ_WAKE_THREAD;
···
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if (!intr_stat)
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return IRQ_NONE;
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-
val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_CLR, RK3576_HDMI_HPD_INT_CLR);
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val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1);
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regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
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mod_delayed_work(system_wq, &hdmi->hpd_work,
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msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
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-
val = HIWORD_UPDATE(0, RK3576_HDMI_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);
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regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
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return IRQ_HANDLED;
···
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if (intr_stat) {
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if (hdmi->port_id)
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-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK,
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RK3588_HDMI1_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);
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else
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-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK,
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RK3588_HDMI0_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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return IRQ_WAKE_THREAD;
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}
···
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return IRQ_NONE;
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if (hdmi->port_id)
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-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR,
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RK3588_HDMI1_HPD_INT_CLR);
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val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1);
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else
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val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
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RK3588_HDMI0_HPD_INT_CLR);
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val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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mod_delayed_work(system_wq, &hdmi->hpd_work,
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msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
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if (hdmi->port_id)
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val |= HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK);
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val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0);
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else
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-
val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
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val |= FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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return IRQ_HANDLED;
···
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{
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u32 val;
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val = HIWORD_UPDATE(RK3576_SCLIN_MASK, RK3576_SCLIN_MASK) |
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HIWORD_UPDATE(RK3576_SDAIN_MASK, RK3576_SDAIN_MASK) |
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HIWORD_UPDATE(RK3576_HDMI_GRANT_SEL, RK3576_HDMI_GRANT_SEL) |
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HIWORD_UPDATE(RK3576_I2S_SEL_MASK, RK3576_I2S_SEL_MASK);
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val = FIELD_PREP_WM16(RK3576_SCLIN_MASK, 1) |
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FIELD_PREP_WM16(RK3576_SDAIN_MASK, 1) |
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FIELD_PREP_WM16(RK3576_HDMI_GRANT_SEL, 1) |
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FIELD_PREP_WM16(RK3576_I2S_SEL_MASK, 1);
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regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON14, val);
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val = HIWORD_UPDATE(0, RK3576_HDMI_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);
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regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
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}
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···
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{
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u32 val;
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val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
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HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
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HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
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HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
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val = FIELD_PREP_WM16(RK3588_SCLIN_MASK, 1) |
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FIELD_PREP_WM16(RK3588_SDAIN_MASK, 1) |
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FIELD_PREP_WM16(RK3588_MODE_MASK, 1) |
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FIELD_PREP_WM16(RK3588_I2S_SEL_MASK, 1);
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regmap_write(hdmi->vo_regmap,
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hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3,
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val);
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val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, RK3588_SET_HPD_PATH_MASK);
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val = FIELD_PREP_WM16(RK3588_HPD_HDMI0_IO_EN_MASK, 1) |
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FIELD_PREP_WM16(RK3588_HPD_HDMI1_IO_EN_MASK, 1);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
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if (hdmi->port_id)
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val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, RK3588_HDMI1_GRANT_SEL);
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val = FIELD_PREP_WM16(RK3588_HDMI1_GRANT_SEL, 1);
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else
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val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, RK3588_HDMI0_GRANT_SEL);
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val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1);
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regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
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if (hdmi->port_id)
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val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);
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else
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-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK);
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val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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}
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