Merge branch 'net-stmmac-improve-pcs-support'

-4

drivers/net/ethernet/stmicro/stmmac/common.h

··· 278 278 #define FLOW_TX 2 279 279 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 280 280 281 - /* PCS defines */ 282 - #define STMMAC_PCS_SGMII (1 << 1) 283 - 284 281 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 285 282 286 283 /* DMA HW feature register fields */ ··· 629 632 unsigned int unicast_filter_entries; 630 633 unsigned int mcast_bits_log2; 631 634 unsigned int rx_csum; 632 - unsigned int pcs; 633 635 unsigned int num_vlan; 634 636 u32 vlan_filter[32]; 635 637 bool vlan_fail_q_en;

+2 -2

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

··· 298 298 299 299 if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) { 300 300 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); 301 - priv->plat->mdio_bus_data->default_an_inband = false; 301 + priv->plat->default_an_inband = false; 302 302 interface = PHY_INTERFACE_MODE_2500BASEX; 303 303 } else { 304 304 interface = PHY_INTERFACE_MODE_SGMII; ··· 700 700 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || 701 701 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { 702 702 plat->mdio_bus_data->pcs_mask = BIT_U32(INTEL_MGBE_XPCS_ADDR); 703 - plat->mdio_bus_data->default_an_inband = true; 703 + plat->default_an_inband = true; 704 704 plat->select_pcs = intel_mgbe_select_pcs; 705 705 } 706 706

+1 -11

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

··· 70 70 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */ 71 71 72 72 /* SGMII/RGMII status register */ 73 - #define GMAC_RGSMIIIS_LNKMODE BIT(0) 74 - #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1) 75 - #define GMAC_RGSMIIIS_LNKSTS BIT(3) 76 - #define GMAC_RGSMIIIS_JABTO BIT(4) 77 - #define GMAC_RGSMIIIS_FALSECARDET BIT(5) 73 + #define GMAC_RSGMIIIS_MASK GENMASK(15, 0) 78 74 #define GMAC_RGSMIIIS_SMIDRXS BIT(16) 79 - /* LNKMOD */ 80 - #define GMAC_RGSMIIIS_LNKMOD_MASK 0x1 81 - /* LNKSPEED */ 82 - #define GMAC_RGSMIIIS_SPEED_125 0x2 83 - #define GMAC_RGSMIIIS_SPEED_25 0x1 84 - #define GMAC_RGSMIIIS_SPEED_2_5 0x0 85 75 86 76 /* GMAC Configuration defines */ 87 77 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */

+8 -3

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

··· 22 22 #include "stmmac_ptp.h" 23 23 #include "dwmac1000.h" 24 24 25 + static const struct stmmac_pcs_info dwmac1000_pcs_info = { 26 + .pcs_offset = GMAC_PCS_BASE, 27 + .rgsmii_offset = GMAC_RGSMIIIS, 28 + .rgsmii_status_mask = GMAC_RSGMIIIS_MASK, 29 + .int_mask = GMAC_INT_DISABLE_PCSLINK | GMAC_INT_DISABLE_PCSAN, 30 + }; 31 + 25 32 static int dwmac1000_pcs_init(struct stmmac_priv *priv) 26 33 { 27 34 if (!priv->dma_cap.pcs) 28 35 return 0; 29 36 30 - return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE, 31 - GMAC_INT_DISABLE_PCSLINK | 32 - GMAC_INT_DISABLE_PCSAN); 37 + return stmmac_integrated_pcs_init(priv, &dwmac1000_pcs_info); 33 38 } 34 39 35 40 static void dwmac1000_core_init(struct mac_device_info *hw,

+1 -9

drivers/net/ethernet/stmicro/stmmac/dwmac4.h

··· 470 470 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0) 471 471 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1) 472 472 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4) 473 - #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16) 474 - #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17) 475 - #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19) 476 - #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20) 477 - #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21) 478 - /* LNKSPEED */ 479 - #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2 480 - #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1 481 - #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0 473 + #define GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK GENMASK(31, 16) 482 474 483 475 extern const struct stmmac_dma_ops dwmac4_dma_ops; 484 476 extern const struct stmmac_dma_ops dwmac410_dma_ops;

+8 -2

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

··· 22 22 #include "dwmac4.h" 23 23 #include "dwmac5.h" 24 24 25 + static const struct stmmac_pcs_info dwmac4_pcs_info = { 26 + .pcs_offset = GMAC_PCS_BASE, 27 + .rgsmii_offset = GMAC_PHYIF_CONTROL_STATUS, 28 + .rgsmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK, 29 + .int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE, 30 + }; 31 + 25 32 static int dwmac4_pcs_init(struct stmmac_priv *priv) 26 33 { 27 34 if (!priv->dma_cap.pcs) 28 35 return 0; 29 36 30 - return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE, 31 - GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE); 37 + return stmmac_integrated_pcs_init(priv, &dwmac4_pcs_info); 32 38 } 33 39 34 40 static void dwmac4_core_init(struct mac_device_info *hw,

+3 -10

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

··· 1027 1027 return pcs; 1028 1028 } 1029 1029 1030 - /* The PCS control register is only relevant for SGMII, TBI and RTBI 1031 - * modes. We no longer support TBI or RTBI, so only configure this 1032 - * register when operating in SGMII mode with the integrated PCS. 1033 - */ 1034 - if (priv->hw->pcs & STMMAC_PCS_SGMII && priv->integrated_pcs) 1030 + if (priv->integrated_pcs && 1031 + test_bit(interface, priv->integrated_pcs->pcs.supported_interfaces)) 1035 1032 return &priv->integrated_pcs->pcs; 1036 1033 1037 1034 return NULL; ··· 1287 1290 1288 1291 if (priv->dma_cap.pcs && interface == PHY_INTERFACE_MODE_SGMII) { 1289 1292 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1290 - priv->hw->pcs = STMMAC_PCS_SGMII; 1291 1293 1292 1294 switch (speed) { 1293 1295 case SPEED_10: ··· 1386 1390 1387 1391 static int stmmac_phylink_setup(struct stmmac_priv *priv) 1388 1392 { 1389 - struct stmmac_mdio_bus_data *mdio_bus_data; 1390 1393 struct phylink_config *config; 1391 1394 struct phylink_pcs *pcs; 1392 1395 struct phylink *phylink; ··· 1410 1415 priv->tx_lpi_clk_stop = priv->plat->flags & 1411 1416 STMMAC_FLAG_EN_TX_LPI_CLOCKGATING; 1412 1417 1413 - mdio_bus_data = priv->plat->mdio_bus_data; 1414 - if (mdio_bus_data) 1415 - config->default_an_inband = mdio_bus_data->default_an_inband; 1418 + config->default_an_inband = priv->plat->default_an_inband; 1416 1419 1417 1420 /* Get the PHY interface modes (at the PHY end of the link) that 1418 1421 * are supported by the platform.

+149 -7

drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c

··· 16 16 #define GMAC_ANE_LPA 0x0c /* ANE link partener ability */ 17 17 #define GMAC_TBI 0x14 /* TBI extend status */ 18 18 19 + /* 20 + * RGSMII status bitfield definitions. 21 + */ 22 + #define GMAC_RGSMII_LNKMOD BIT(0) 23 + #define GMAC_RGSMII_SPEED_MASK GENMASK(2, 1) 24 + #define GMAC_RGSMII_SPEED_125 2 25 + #define GMAC_RGSMII_SPEED_25 1 26 + #define GMAC_RGSMII_SPEED_2_5 0 27 + #define GMAC_RGSMII_LNKSTS BIT(3) 28 + 29 + static unsigned int dwmac_integrated_pcs_inband_caps(struct phylink_pcs *pcs, 30 + phy_interface_t interface) 31 + { 32 + struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs); 33 + unsigned int ib_caps; 34 + 35 + if (phy_interface_mode_is_8023z(interface)) { 36 + ib_caps = LINK_INBAND_DISABLE; 37 + 38 + /* If the PCS supports TBI/RTBI, then BASE-X negotiation is 39 + * supported. 40 + */ 41 + if (spcs->support_tbi_rtbi) 42 + ib_caps |= LINK_INBAND_ENABLE; 43 + 44 + return ib_caps; 45 + } 46 + 47 + return 0; 48 + } 49 + 19 50 static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs) 20 51 { 21 52 struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs); ··· 67 36 unsigned int neg_mode, 68 37 struct phylink_link_state *state) 69 38 { 70 - state->link = false; 39 + struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs); 40 + u32 status, lpa, rgsmii; 41 + 42 + status = readl(spcs->base + GMAC_AN_STATUS); 43 + 44 + if (phy_interface_mode_is_8023z(state->interface)) { 45 + /* For BASE-X modes, the PCS block supports the advertisement 46 + * and link partner advertisement registers using standard 47 + * 802.3 format. The status register also has the link status 48 + * and AN complete bits in the same bit location. This will 49 + * only be used when AN is enabled. 50 + */ 51 + lpa = readl(spcs->base + GMAC_ANE_LPA); 52 + 53 + phylink_mii_c22_pcs_decode_state(state, neg_mode, status, lpa); 54 + } else { 55 + rgsmii = field_get(spcs->rgsmii_status_mask, 56 + readl(spcs->rgsmii)); 57 + 58 + state->link = status & BMSR_LSTATUS && 59 + rgsmii & GMAC_RGSMII_LNKSTS; 60 + 61 + if (state->link && neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 62 + state->duplex = rgsmii & GMAC_RGSMII_LNKMOD ? 63 + DUPLEX_FULL : DUPLEX_HALF; 64 + switch (FIELD_GET(GMAC_RGSMII_SPEED_MASK, rgsmii)) { 65 + case GMAC_RGSMII_SPEED_2_5: 66 + state->speed = SPEED_10; 67 + break; 68 + 69 + case GMAC_RGSMII_SPEED_25: 70 + state->speed = SPEED_100; 71 + break; 72 + 73 + case GMAC_RGSMII_SPEED_125: 74 + state->speed = SPEED_1000; 75 + break; 76 + 77 + default: 78 + state->link = false; 79 + break; 80 + } 81 + } 82 + } 83 + } 84 + 85 + static int dwmac_integrated_pcs_config_aneg(struct stmmac_pcs *spcs, 86 + phy_interface_t interface, 87 + const unsigned long *advertising) 88 + { 89 + bool changed = false; 90 + u32 adv; 91 + 92 + adv = phylink_mii_c22_pcs_encode_advertisement(interface, advertising); 93 + if (readl(spcs->base + GMAC_ANE_ADV) != adv) 94 + changed = true; 95 + writel(adv, spcs->base + GMAC_ANE_ADV); 96 + 97 + return changed; 71 98 } 72 99 73 100 static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs, ··· 135 46 bool permit_pause_to_mac) 136 47 { 137 48 struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs); 49 + bool changed = false, ane = true; 138 50 139 - dwmac_ctrl_ane(spcs->base, 0, 1, spcs->priv->hw->reverse_sgmii_enable); 51 + /* Only configure the advertisement and allow AN in BASE-X mode if 52 + * the core supports TBI/RTBI. AN will be filtered out by via phylink 53 + * and the .pcs_inband_caps() method above. 54 + */ 55 + if (phy_interface_mode_is_8023z(interface) && 56 + spcs->support_tbi_rtbi) { 57 + ane = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED; 140 58 141 - return 0; 59 + changed = dwmac_integrated_pcs_config_aneg(spcs, interface, 60 + advertising); 61 + } 62 + 63 + dwmac_ctrl_ane(spcs->base, 0, ane, 64 + spcs->priv->hw->reverse_sgmii_enable); 65 + 66 + return changed; 67 + } 68 + 69 + static void dwmac_integrated_pcs_an_restart(struct phylink_pcs *pcs) 70 + { 71 + struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs); 72 + void __iomem *an_control = spcs->base + GMAC_AN_CTRL(0); 73 + u32 ctrl; 74 + 75 + /* We can only do AN restart if using TBI/RTBI mode */ 76 + if (spcs->support_tbi_rtbi) { 77 + ctrl = readl(an_control) | GMAC_AN_CTRL_RAN; 78 + writel(ctrl, an_control); 79 + } 142 80 } 143 81 144 82 static const struct phylink_pcs_ops dwmac_integrated_pcs_ops = { 83 + .pcs_inband_caps = dwmac_integrated_pcs_inband_caps, 145 84 .pcs_enable = dwmac_integrated_pcs_enable, 146 85 .pcs_disable = dwmac_integrated_pcs_disable, 147 86 .pcs_get_state = dwmac_integrated_pcs_get_state, 148 87 .pcs_config = dwmac_integrated_pcs_config, 88 + .pcs_an_restart = dwmac_integrated_pcs_an_restart, 149 89 }; 150 90 151 91 void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status, ··· 202 84 int stmmac_integrated_pcs_get_phy_intf_sel(struct phylink_pcs *pcs, 203 85 phy_interface_t interface) 204 86 { 87 + struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs); 88 + 205 89 if (interface == PHY_INTERFACE_MODE_SGMII) 206 90 return PHY_INTF_SEL_SGMII; 91 + 92 + if (phy_interface_mode_is_8023z(interface)) { 93 + if (spcs->support_tbi_rtbi) 94 + return PHY_INTF_SEL_TBI; 95 + else 96 + return PHY_INTF_SEL_SGMII; 97 + } 207 98 208 99 return -EINVAL; 209 100 } 210 101 211 - int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset, 212 - u32 int_mask) 102 + int stmmac_integrated_pcs_init(struct stmmac_priv *priv, 103 + const struct stmmac_pcs_info *pcs_info) 213 104 { 214 105 struct stmmac_pcs *spcs; 215 106 ··· 227 100 return -ENOMEM; 228 101 229 102 spcs->priv = priv; 230 - spcs->base = priv->ioaddr + offset; 231 - spcs->int_mask = int_mask; 103 + spcs->base = priv->ioaddr + pcs_info->pcs_offset; 104 + spcs->rgsmii = priv->ioaddr + pcs_info->rgsmii_offset; 105 + spcs->rgsmii_status_mask = pcs_info->rgsmii_status_mask; 106 + spcs->int_mask = pcs_info->int_mask; 232 107 spcs->pcs.ops = &dwmac_integrated_pcs_ops; 233 108 109 + /* If the PCS supports extended status, then it supports BASE-X AN 110 + * with a TBI interface to the SerDes. Otherwise, we can support 111 + * BASE-X without AN using SGMII, which is required for qcom-ethqos. 112 + */ 113 + if (readl(spcs->base + GMAC_AN_STATUS) & BMSR_ESTATEN) 114 + spcs->support_tbi_rtbi = true; 115 + 234 116 __set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces); 117 + __set_bit(PHY_INTERFACE_MODE_1000BASEX, spcs->pcs.supported_interfaces); 118 + 119 + /* Only allow 2500BASE-X if the SerDes has support. */ 120 + if (priv->plat->flags & STMMAC_FLAG_SERDES_SUPPORTS_2500M) 121 + __set_bit(PHY_INTERFACE_MODE_2500BASEX, 122 + spcs->pcs.supported_interfaces); 235 123 236 124 priv->integrated_pcs = spcs; 237 125

+12 -2

drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h

··· 27 27 28 28 struct stmmac_priv; 29 29 30 + struct stmmac_pcs_info { 31 + unsigned int pcs_offset; 32 + unsigned int rgsmii_offset; 33 + u32 rgsmii_status_mask; 34 + u32 int_mask; 35 + }; 36 + 30 37 struct stmmac_pcs { 31 38 struct stmmac_priv *priv; 32 39 void __iomem *base; 40 + void __iomem *rgsmii; 41 + u32 rgsmii_status_mask; 33 42 u32 int_mask; 34 43 struct phylink_pcs pcs; 44 + bool support_tbi_rtbi; 35 45 }; 36 46 37 47 static inline struct stmmac_pcs * ··· 54 44 struct stmmac_extra_stats *x); 55 45 int stmmac_integrated_pcs_get_phy_intf_sel(struct phylink_pcs *pcs, 56 46 phy_interface_t interface); 57 - int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset, 58 - u32 int_mask); 47 + int stmmac_integrated_pcs_init(struct stmmac_priv *priv, 48 + const struct stmmac_pcs_info *pcs_info); 59 49 60 50 /** 61 51 * dwmac_ctrl_ane - To program the AN Control Register.

+2 -1

include/linux/stmmac.h

··· 89 89 int *irqs; 90 90 int probed_phy_irq; 91 91 bool needs_reset; 92 - bool default_an_inband; 93 92 }; 94 93 95 94 struct stmmac_dma_cfg { ··· 212 213 #define STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP BIT(12) 213 214 #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(13) 214 215 #define STMMAC_FLAG_KEEP_PREAMBLE_BEFORE_SFD BIT(14) 216 + #define STMMAC_FLAG_SERDES_SUPPORTS_2500M BIT(15) 215 217 216 218 struct mac_device_info; 217 219 ··· 250 250 struct stmmac_dma_cfg *dma_cfg; 251 251 struct stmmac_safety_feature_cfg *safety_feat_cfg; 252 252 int clk_csr; 253 + bool default_an_inband; 253 254 bool enh_desc; 254 255 bool tx_coe; 255 256 bool bugged_jumbo;

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