Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Modify the step that need to be skipped
Bspec has changed the non tbt pll enable sequence now we skip
steps 5-17 if no config change has occurred.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-26-suraj.kandpal@intel.com
+33
-30
+33
-30
drivers/gpu/drm/i915/display/intel_lt_phy.c
+33
-30
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1677
1677
XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
1678
1678
drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
1679
1679
phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
1680
+
1681
+
/*
1682
+
* 13. Ungate the forward clock by setting
1683
+
* PORT_CLOCK_CTL[Forward Clock Ungate] = 1.
1684
+
*/
1685
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
1686
+
XELPDP_FORWARD_CLOCK_UNGATE,
1687
+
XELPDP_FORWARD_CLOCK_UNGATE);
1688
+
1689
+
/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
1690
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
1691
+
lane_phy_pulse_status,
1692
+
lane_phy_pulse_status);
1693
+
/*
1694
+
* 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over
1695
+
* PHY message bus for Owned PHY Lanes.
1696
+
*/
1697
+
rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
1698
+
rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
1699
+
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
1700
+
rate_update, MB_WRITE_COMMITTED);
1701
+
1702
+
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
1703
+
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
1704
+
lane_phy_pulse_status, lane_phy_pulse_status,
1705
+
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
1706
+
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
1707
+
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
1708
+
1709
+
/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
1710
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
1711
+
lane_phy_pulse_status,
1712
+
lane_phy_pulse_status);
1680
1713
} else {
1681
1714
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
1682
1715
}
1683
-
1684
-
/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
1685
-
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
1686
-
XELPDP_FORWARD_CLOCK_UNGATE,
1687
-
XELPDP_FORWARD_CLOCK_UNGATE);
1688
-
1689
-
/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
1690
-
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
1691
-
lane_phy_pulse_status,
1692
-
lane_phy_pulse_status);
1693
-
/*
1694
-
* 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
1695
-
* Owned PHY Lanes.
1696
-
*/
1697
-
rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
1698
-
rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
1699
-
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
1700
-
rate_update, MB_WRITE_COMMITTED);
1701
-
1702
-
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
1703
-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
1704
-
lane_phy_pulse_status, lane_phy_pulse_status,
1705
-
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
1706
-
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
1707
-
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
1708
-
1709
-
/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
1710
-
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
1711
-
lane_phy_pulse_status,
1712
-
lane_phy_pulse_status);
1713
1716
1714
1717
/*
1715
1718
* 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.