Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '1662005846-4838-1-git-send-email-quic_c_skakit@quicinc.com' into clk-for-6.1
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-7
+2
-4
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
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-4
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
···
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items:
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- description: LPASS qdsp6ss register
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- description: LPASS top-cc register
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- description: LPASS cc register
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reg-names:
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items:
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- const: qdsp6ss
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- const: top_cc
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- const: cc
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required:
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- compatible
···
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#include <dt-bindings/clock/qcom,lpass-sc7280.h>
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clock-controller@3000000 {
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compatible = "qcom,sc7280-lpasscc";
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reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
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reg-names = "qdsp6ss", "top_cc", "cc";
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reg = <0x03000000 0x40>, <0x03c04000 0x4>;
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reg-names = "qdsp6ss", "top_cc";
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clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
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clock-names = "iface";
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#clock-cells = <1>;
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-3
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
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-3
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
···
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clock-names: true
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reg: true
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compatible:
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enum:
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- qcom,sc7280-lpassaoncc
···
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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'#reset-cells':
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const: 1
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qcom,adsp-pil-mode:
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description:
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Indicates if the LPASS would be brought out of reset using
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peripheral loader.
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type: boolean
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required:
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- compatible
···
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items:
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- const: bi_tcxo
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- const: lpass_aon_cc_main_rcg_clk_src
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reg:
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items:
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- description: lpass core cc register
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- description: lpass audio csr register
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- if:
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properties:
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compatible:
···
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- const: bi_tcxo_ao
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- const: iface
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
···
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items:
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- const: bi_tcxo
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reg:
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maxItems: 1
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
···
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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lpass_audiocc: clock-controller@3300000 {
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compatible = "qcom,sc7280-lpassaudiocc";
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reg = <0x3300000 0x30000>;
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reg = <0x3300000 0x30000>,
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<0x32a9000 0x1000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
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clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
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power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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- |
···
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
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<&lpasscore LPASS_CORE_CC_CORE_CLK>;
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clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
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qcom,adsp-pil-mode;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
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include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
···
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#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
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#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
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/* LPASS AUDIO CC CSR */
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#define LPASS_AUDIO_SWR_RX_CGCR 0
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#define LPASS_AUDIO_SWR_TX_CGCR 1
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#define LPASS_AUDIO_SWR_WSA_CGCR 2
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/* LPASS_AON_CC clocks */
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#define LPASS_AON_CC_PLL 0
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#define LPASS_AON_CC_PLL_OUT_EVEN 1
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include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
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include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
···
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#define LPASS_CORE_CC_LPM_CORE_CLK 9
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#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
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#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
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#define LPASS_CORE_CC_EXT_MCLK0_CLK 12
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#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13
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/* LPASS_CORE_CC power domains */
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#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0