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ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

The division calculation should be implemented using signed integer format.
This patch changes mc->shift from an unsigned type to a signed integer during the calculation.

Fixes: 501efdcb3b3a ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops")
Signed-off-by: Shuming Fan <shumingf@realtek.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20260327082331.2277498-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shuming Fan and committed by
Mark Brown ae00200a 7caae0ae

+1 -1
+1 -1
sound/soc/sdca/sdca_asoc.c
··· 850 850 851 851 reg_val = snd_soc_component_read(component, reg); 852 852 853 - val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min; 853 + val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min; 854 854 855 855 return val & GENMASK(mc->sign_bit, 0); 856 856 }