tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Just general fixes: radeon, i915, atmel, tegra, amdkfd and one core
fix"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (28 commits)
drm: atmel-hlcdc: remove clock polarity from crtc driver
drm/radeon: only enable DP audio if the monitor supports it
drm/radeon: fix atom aux payload size check for writes (v2)
drm/radeon: fix 1 RB harvest config setup for TN/RL
drm/radeon: enable SRBM timeout interrupt on EG/NI
drm/radeon: enable SRBM timeout interrupt on SI
drm/radeon: enable SRBM timeout interrupt on CIK v2
drm/radeon: dump full IB if we hit a packet error
drm/radeon: disable mclk switching with 120hz+ monitors
drm/radeon: use drm_mode_vrefresh() rather than mode->vrefresh
drm/radeon: enable native backlight control on old macs
drm/i915: Fix frontbuffer false positve.
drm/i915: Align initial plane backing objects correctly
drm/i915: avoid processing spurious/shared interrupts in low-power states
drm/i915: Check obj->vma_list under the struct_mutex
drm/i915: Fix a use after free, and unbalanced refcounting
drm: atmel-hlcdc: remove useless pm_runtime_put_sync in probe
drm: atmel-hlcdc: reset layer A2Q and UPDATE bits when disabling it
drm: Fix deadlock due to getconnector locking changes
drm/i915: Dell Chromebook 11 has PWM backlight
...

Linus Torvalds ae1aa797 a015d33c

+235 -98
+8 -2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
··· 62 62 return KFD_MQD_TYPE_CP; 63 63 } 64 64 65 - static inline unsigned int get_first_pipe(struct device_queue_manager *dqm) 65 + unsigned int get_first_pipe(struct device_queue_manager *dqm) 66 66 { 67 - BUG_ON(!dqm); 67 + BUG_ON(!dqm || !dqm->dev); 68 68 return dqm->dev->shared_resources.first_compute_pipe; 69 + } 70 + 71 + unsigned int get_pipes_num(struct device_queue_manager *dqm) 72 + { 73 + BUG_ON(!dqm || !dqm->dev); 74 + return dqm->dev->shared_resources.compute_pipe_count; 69 75 } 70 76 71 77 static inline unsigned int get_pipes_num_cpsch(void)
+2 -6
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
··· 163 163 struct qcm_process_device *qpd); 164 164 int init_pipelines(struct device_queue_manager *dqm, 165 165 unsigned int pipes_num, unsigned int first_pipe); 166 + unsigned int get_first_pipe(struct device_queue_manager *dqm); 167 + unsigned int get_pipes_num(struct device_queue_manager *dqm); 166 168 167 169 extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) 168 170 { ··· 175 173 get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd) 176 174 { 177 175 return (pdd->lds_base >> 60) & 0x0E; 178 - } 179 - 180 - extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm) 181 - { 182 - BUG_ON(!dqm || !dqm->dev); 183 - return dqm->dev->shared_resources.compute_pipe_count; 184 176 } 185 177 186 178 #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
··· 131 131 132 132 static int initialize_cpsch_cik(struct device_queue_manager *dqm) 133 133 { 134 - return init_pipelines(dqm, get_pipes_num(dqm), 0); 134 + return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm)); 135 135 }
+1 -1
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
··· 153 153 (adj->crtc_hdisplay - 1) | 154 154 ((adj->crtc_vdisplay - 1) << 16)); 155 155 156 - cfg = ATMEL_HLCDC_CLKPOL; 156 + cfg = 0; 157 157 158 158 prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); 159 159 mode_rate = mode->crtc_clock * 1000;
-2
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
··· 311 311 312 312 pm_runtime_enable(dev->dev); 313 313 314 - pm_runtime_put_sync(dev->dev); 315 - 316 314 ret = atmel_hlcdc_dc_modeset_init(dev); 317 315 if (ret < 0) { 318 316 dev_err(dev->dev, "failed to initialize mode setting\n");
+2 -1
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
··· 311 311 312 312 /* Disable the layer */ 313 313 regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR, 314 - ATMEL_HLCDC_LAYER_RST); 314 + ATMEL_HLCDC_LAYER_RST | ATMEL_HLCDC_LAYER_A2Q | 315 + ATMEL_HLCDC_LAYER_UPDATE); 315 316 316 317 /* Clear all pending interrupts */ 317 318 regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr);
+2 -1
drivers/gpu/drm/drm_crtc.c
··· 2127 2127 DRM_DEBUG_KMS("[CONNECTOR:%d:?]\n", out_resp->connector_id); 2128 2128 2129 2129 mutex_lock(&dev->mode_config.mutex); 2130 - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2131 2130 2132 2131 connector = drm_connector_find(dev, out_resp->connector_id); 2133 2132 if (!connector) { ··· 2156 2157 out_resp->mm_height = connector->display_info.height_mm; 2157 2158 out_resp->subpixel = connector->display_info.subpixel_order; 2158 2159 out_resp->connection = connector->status; 2160 + 2161 + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2159 2162 encoder = drm_connector_get_encoder(connector); 2160 2163 if (encoder) 2161 2164 out_resp->encoder_id = encoder->base.id;
+14 -1
drivers/gpu/drm/i915/i915_drv.h
··· 2114 2114 * number comparisons on buffer last_read|write_seqno. It also allows an 2115 2115 * emission time to be associated with the request for tracking how far ahead 2116 2116 * of the GPU the submission is. 2117 + * 2118 + * The requests are reference counted, so upon creation they should have an 2119 + * initial reference taken using kref_init 2117 2120 */ 2118 2121 struct drm_i915_gem_request { 2119 2122 struct kref ref; ··· 2140 2137 /** Position in the ringbuffer of the end of the whole request */ 2141 2138 u32 tail; 2142 2139 2143 - /** Context related to this request */ 2140 + /** 2141 + * Context related to this request 2142 + * Contexts are refcounted, so when this request is associated with a 2143 + * context, we must increment the context's refcount, to guarantee that 2144 + * it persists while any request is linked to it. Requests themselves 2145 + * are also refcounted, so the request will only be freed when the last 2146 + * reference to it is dismissed, and the code in 2147 + * i915_gem_request_free() will then decrement the refcount on the 2148 + * context. 2149 + */ 2144 2150 struct intel_context *ctx; 2145 2151 2146 2152 /** Batch buffer related to this request if any */ ··· 2386 2374 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2387 2375 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2388 2376 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2377 + (INTEL_DEVID(dev) & 0xf) == 0xb || \ 2389 2378 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2390 2379 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2391 2380 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
+1 -2
drivers/gpu/drm/i915/i915_gem.c
··· 2659 2659 if (submit_req->ctx != ring->default_context) 2660 2660 intel_lr_context_unpin(ring, submit_req->ctx); 2661 2661 2662 - i915_gem_context_unreference(submit_req->ctx); 2663 - kfree(submit_req); 2662 + i915_gem_request_unreference(submit_req); 2664 2663 } 2665 2664 2666 2665 /*
+2 -4
drivers/gpu/drm/i915/i915_gem_stolen.c
··· 485 485 stolen_offset, gtt_offset, size); 486 486 487 487 /* KISS and expect everything to be page-aligned */ 488 - BUG_ON(stolen_offset & 4095); 489 - BUG_ON(size & 4095); 490 - 491 - if (WARN_ON(size == 0)) 488 + if (WARN_ON(size == 0) || WARN_ON(size & 4095) || 489 + WARN_ON(stolen_offset & 4095)) 492 490 return NULL; 493 491 494 492 stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
+4 -3
drivers/gpu/drm/i915/i915_gem_tiling.c
··· 335 335 return -EINVAL; 336 336 } 337 337 338 + mutex_lock(&dev->struct_mutex); 338 339 if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) { 339 - drm_gem_object_unreference_unlocked(&obj->base); 340 - return -EBUSY; 340 + ret = -EBUSY; 341 + goto err; 341 342 } 342 343 343 344 if (args->tiling_mode == I915_TILING_NONE) { ··· 370 369 } 371 370 } 372 371 373 - mutex_lock(&dev->struct_mutex); 374 372 if (args->tiling_mode != obj->tiling_mode || 375 373 args->stride != obj->stride) { 376 374 /* We need to rebind the object if its current allocation ··· 424 424 obj->bit_17 = NULL; 425 425 } 426 426 427 + err: 427 428 drm_gem_object_unreference(&obj->base); 428 429 mutex_unlock(&dev->struct_mutex); 429 430
+22
drivers/gpu/drm/i915/i915_irq.c
··· 1892 1892 u32 iir, gt_iir, pm_iir; 1893 1893 irqreturn_t ret = IRQ_NONE; 1894 1894 1895 + if (!intel_irqs_enabled(dev_priv)) 1896 + return IRQ_NONE; 1897 + 1895 1898 while (true) { 1896 1899 /* Find, clear, then process each source of interrupt */ 1897 1900 ··· 1938 1935 struct drm_i915_private *dev_priv = dev->dev_private; 1939 1936 u32 master_ctl, iir; 1940 1937 irqreturn_t ret = IRQ_NONE; 1938 + 1939 + if (!intel_irqs_enabled(dev_priv)) 1940 + return IRQ_NONE; 1941 1941 1942 1942 for (;;) { 1943 1943 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; ··· 2214 2208 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 2215 2209 irqreturn_t ret = IRQ_NONE; 2216 2210 2211 + if (!intel_irqs_enabled(dev_priv)) 2212 + return IRQ_NONE; 2213 + 2217 2214 /* We get interrupts on unclaimed registers, so check for this before we 2218 2215 * do any I915_{READ,WRITE}. */ 2219 2216 intel_uncore_check_errors(dev); ··· 2287 2278 uint32_t tmp = 0; 2288 2279 enum pipe pipe; 2289 2280 u32 aux_mask = GEN8_AUX_CHANNEL_A; 2281 + 2282 + if (!intel_irqs_enabled(dev_priv)) 2283 + return IRQ_NONE; 2290 2284 2291 2285 if (IS_GEN9(dev)) 2292 2286 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | ··· 3783 3771 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3784 3772 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3785 3773 3774 + if (!intel_irqs_enabled(dev_priv)) 3775 + return IRQ_NONE; 3776 + 3786 3777 iir = I915_READ16(IIR); 3787 3778 if (iir == 0) 3788 3779 return IRQ_NONE; ··· 3965 3950 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3966 3951 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3967 3952 int pipe, ret = IRQ_NONE; 3953 + 3954 + if (!intel_irqs_enabled(dev_priv)) 3955 + return IRQ_NONE; 3968 3956 3969 3957 iir = I915_READ(IIR); 3970 3958 do { ··· 4188 4170 u32 flip_mask = 4189 4171 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 4190 4172 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 4173 + 4174 + if (!intel_irqs_enabled(dev_priv)) 4175 + return IRQ_NONE; 4191 4176 4192 4177 iir = I915_READ(IIR); 4193 4178 ··· 4541 4520 { 4542 4521 dev_priv->dev->driver->irq_uninstall(dev_priv->dev); 4543 4522 dev_priv->pm.irqs_enabled = false; 4523 + synchronize_irq(dev_priv->dev->irq); 4544 4524 } 4545 4525 4546 4526 /**
+24 -9
drivers/gpu/drm/i915/intel_display.c
··· 2371 2371 struct drm_device *dev = crtc->base.dev; 2372 2372 struct drm_i915_gem_object *obj = NULL; 2373 2373 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 2374 - u32 base = plane_config->base; 2374 + u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); 2375 + u32 size_aligned = round_up(plane_config->base + plane_config->size, 2376 + PAGE_SIZE); 2377 + 2378 + size_aligned -= base_aligned; 2375 2379 2376 2380 if (plane_config->size == 0) 2377 2381 return false; 2378 2382 2379 - obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, 2380 - plane_config->size); 2383 + obj = i915_gem_object_create_stolen_for_preallocated(dev, 2384 + base_aligned, 2385 + base_aligned, 2386 + size_aligned); 2381 2387 if (!obj) 2382 2388 return false; 2383 2389 ··· 2731 2725 case DRM_FORMAT_XRGB8888: 2732 2726 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; 2733 2727 break; 2728 + case DRM_FORMAT_ARGB8888: 2729 + plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; 2730 + plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; 2731 + break; 2734 2732 case DRM_FORMAT_XBGR8888: 2735 2733 plane_ctl |= PLANE_CTL_ORDER_RGBX; 2736 2734 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; 2735 + break; 2736 + case DRM_FORMAT_ABGR8888: 2737 + plane_ctl |= PLANE_CTL_ORDER_RGBX; 2738 + plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; 2739 + plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; 2737 2740 break; 2738 2741 case DRM_FORMAT_XRGB2101010: 2739 2742 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; ··· 6642 6627 aligned_height = intel_fb_align_height(dev, fb->height, 6643 6628 plane_config->tiling); 6644 6629 6645 - plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height); 6630 + plane_config->size = fb->pitches[0] * aligned_height; 6646 6631 6647 6632 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 6648 6633 pipe_name(pipe), plane, fb->width, fb->height, ··· 7679 7664 aligned_height = intel_fb_align_height(dev, fb->height, 7680 7665 plane_config->tiling); 7681 7666 7682 - plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE); 7667 + plane_config->size = fb->pitches[0] * aligned_height; 7683 7668 7684 7669 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 7685 7670 pipe_name(pipe), fb->width, fb->height, ··· 7770 7755 aligned_height = intel_fb_align_height(dev, fb->height, 7771 7756 plane_config->tiling); 7772 7757 7773 - plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height); 7758 + plane_config->size = fb->pitches[0] * aligned_height; 7774 7759 7775 7760 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 7776 7761 pipe_name(pipe), fb->width, fb->height, ··· 12197 12182 return -ENOMEM; 12198 12183 } 12199 12184 12200 - if (fb == crtc->cursor->fb) 12201 - return 0; 12202 - 12203 12185 /* we only need to pin inside GTT if cursor is non-phy */ 12204 12186 mutex_lock(&dev->struct_mutex); 12205 12187 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) { ··· 13108 13096 13109 13097 /* HP Chromebook 14 (Celeron 2955U) */ 13110 13098 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, 13099 + 13100 + /* Dell Chromebook 11 */ 13101 + { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, 13111 13102 }; 13112 13103 13113 13104 static void intel_init_quirks(struct drm_device *dev)
+4 -4
drivers/gpu/drm/i915/intel_lrc.c
··· 503 503 * If there isn't a request associated with this submission, 504 504 * create one as a temporary holder. 505 505 */ 506 - WARN(1, "execlist context submission without request"); 507 506 request = kzalloc(sizeof(*request), GFP_KERNEL); 508 507 if (request == NULL) 509 508 return -ENOMEM; 510 509 request->ring = ring; 511 510 request->ctx = to; 511 + kref_init(&request->ref); 512 + request->uniq = dev_priv->request_uniq++; 513 + i915_gem_context_reference(request->ctx); 512 514 } else { 515 + i915_gem_request_reference(request); 513 516 WARN_ON(to != request->ctx); 514 517 } 515 518 request->tail = tail; 516 - i915_gem_request_reference(request); 517 - i915_gem_context_reference(request->ctx); 518 519 519 520 intel_runtime_pm_get(dev_priv); 520 521 ··· 732 731 if (ctx_obj && (ctx != ring->default_context)) 733 732 intel_lr_context_unpin(ring, ctx); 734 733 intel_runtime_pm_put(dev_priv); 735 - i915_gem_context_unreference(ctx); 736 734 list_del(&req->execlist_link); 737 735 i915_gem_request_unreference(req); 738 736 }
+7
drivers/gpu/drm/radeon/atombios_dp.c
··· 178 178 switch (msg->request & ~DP_AUX_I2C_MOT) { 179 179 case DP_AUX_NATIVE_WRITE: 180 180 case DP_AUX_I2C_WRITE: 181 + /* The atom implementation only supports writes with a max payload of 182 + * 12 bytes since it uses 4 bits for the total count (header + payload) 183 + * in the parameter space. The atom interface supports 16 byte 184 + * payloads for reads. The hw itself supports up to 16 bytes of payload. 185 + */ 186 + if (WARN_ON_ONCE(msg->size > 12)) 187 + return -E2BIG; 181 188 /* tx_size needs to be 4 even for bare address packets since the atom 182 189 * table needs the info in tx_buf[3]. 183 190 */
+15 -6
drivers/gpu/drm/radeon/atombios_encoders.c
··· 731 731 dig_connector = radeon_connector->con_priv; 732 732 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 733 733 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 734 - if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 734 + if (radeon_audio != 0 && 735 + drm_detect_monitor_audio(radeon_connector_edid(connector)) && 736 + ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 735 737 return ATOM_ENCODER_MODE_DP_AUDIO; 736 738 return ATOM_ENCODER_MODE_DP; 737 739 } else if (radeon_audio != 0) { ··· 749 747 } 750 748 break; 751 749 case DRM_MODE_CONNECTOR_eDP: 752 - if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 750 + if (radeon_audio != 0 && 751 + drm_detect_monitor_audio(radeon_connector_edid(connector)) && 752 + ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 753 753 return ATOM_ENCODER_MODE_DP_AUDIO; 754 754 return ATOM_ENCODER_MODE_DP; 755 755 case DRM_MODE_CONNECTOR_DVIA: ··· 1724 1720 } 1725 1721 1726 1722 encoder_mode = atombios_get_encoder_mode(encoder); 1727 - if (radeon_audio != 0 && 1728 - (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode))) 1723 + if (connector && (radeon_audio != 0) && 1724 + ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1725 + (ENCODER_MODE_IS_DP(encoder_mode) && 1726 + drm_detect_monitor_audio(radeon_connector_edid(connector))))) 1729 1727 radeon_audio_dpms(encoder, mode); 1730 1728 } 1731 1729 ··· 2142 2136 struct drm_device *dev = encoder->dev; 2143 2137 struct radeon_device *rdev = dev->dev_private; 2144 2138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2139 + struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2145 2140 int encoder_mode; 2146 2141 2147 2142 radeon_encoder->pixel_clock = adjusted_mode->clock; ··· 2171 2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2172 2165 /* handled in dpms */ 2173 2166 encoder_mode = atombios_get_encoder_mode(encoder); 2174 - if (radeon_audio != 0 && 2175 - (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode))) 2167 + if (connector && (radeon_audio != 0) && 2168 + ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2169 + (ENCODER_MODE_IS_DP(encoder_mode) && 2170 + drm_detect_monitor_audio(radeon_connector_edid(connector))))) 2176 2171 radeon_audio_mode_set(encoder, adjusted_mode); 2177 2172 break; 2178 2173 case ENCODER_OBJECT_ID_INTERNAL_DDI:
+8
drivers/gpu/drm/radeon/cik.c
··· 3613 3613 } 3614 3614 3615 3615 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 3616 + WREG32(SRBM_INT_CNTL, 0x1); 3617 + WREG32(SRBM_INT_ACK, 0x1); 3616 3618 3617 3619 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 3618 3620 ··· 7232 7230 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); 7233 7231 /* grbm */ 7234 7232 WREG32(GRBM_INT_CNTL, 0); 7233 + /* SRBM */ 7234 + WREG32(SRBM_INT_CNTL, 0); 7235 7235 /* vline/vblank, etc. */ 7236 7236 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 7237 7237 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); ··· 8049 8045 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 8050 8046 break; 8051 8047 } 8048 + break; 8049 + case 96: 8050 + DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); 8051 + WREG32(SRBM_INT_ACK, 0x1); 8052 8052 break; 8053 8053 case 124: /* UVD */ 8054 8054 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
+4
drivers/gpu/drm/radeon/cikd.h
··· 482 482 #define SOFT_RESET_ORB (1 << 23) 483 483 #define SOFT_RESET_VCE (1 << 24) 484 484 485 + #define SRBM_READ_ERROR 0xE98 486 + #define SRBM_INT_CNTL 0xEA0 487 + #define SRBM_INT_ACK 0xEA8 488 + 485 489 #define VM_L2_CNTL 0x1400 486 490 #define ENABLE_L2_CACHE (1 << 0) 487 491 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
+7
drivers/gpu/drm/radeon/evergreen.c
··· 3253 3253 } 3254 3254 3255 3255 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 3256 + WREG32(SRBM_INT_CNTL, 0x1); 3257 + WREG32(SRBM_INT_ACK, 0x1); 3256 3258 3257 3259 evergreen_fix_pci_max_read_req_size(rdev); 3258 3260 ··· 4326 4324 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 4327 4325 WREG32(DMA_CNTL, tmp); 4328 4326 WREG32(GRBM_INT_CNTL, 0); 4327 + WREG32(SRBM_INT_CNTL, 0); 4329 4328 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 4330 4329 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 4331 4330 if (rdev->num_crtc >= 4) { ··· 5069 5066 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 5070 5067 break; 5071 5068 } 5069 + case 96: 5070 + DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); 5071 + WREG32(SRBM_INT_ACK, 0x1); 5072 + break; 5072 5073 case 124: /* UVD */ 5073 5074 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 5074 5075 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
+4
drivers/gpu/drm/radeon/evergreend.h
··· 1191 1191 #define SOFT_RESET_REGBB (1 << 22) 1192 1192 #define SOFT_RESET_ORB (1 << 23) 1193 1193 1194 + #define SRBM_READ_ERROR 0xE98 1195 + #define SRBM_INT_CNTL 0xEA0 1196 + #define SRBM_INT_ACK 0xEA8 1197 + 1194 1198 /* display watermarks */ 1195 1199 #define DC_LB_MEMORY_SPLIT 0x6b0c 1196 1200 #define PRIORITY_A_CNT 0x6b18
+6 -4
drivers/gpu/drm/radeon/ni.c
··· 962 962 } 963 963 964 964 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 965 + WREG32(SRBM_INT_CNTL, 0x1); 966 + WREG32(SRBM_INT_ACK, 0x1); 965 967 966 968 evergreen_fix_pci_max_read_req_size(rdev); 967 969 ··· 1088 1086 1089 1087 if ((rdev->config.cayman.max_backends_per_se == 1) && 1090 1088 (rdev->flags & RADEON_IS_IGP)) { 1091 - if ((disabled_rb_mask & 3) == 1) { 1092 - /* RB0 disabled, RB1 enabled */ 1093 - tmp = 0x11111111; 1094 - } else { 1089 + if ((disabled_rb_mask & 3) == 2) { 1095 1090 /* RB1 disabled, RB0 enabled */ 1096 1091 tmp = 0x00000000; 1092 + } else { 1093 + /* RB0 disabled, RB1 enabled */ 1094 + tmp = 0x11111111; 1097 1095 } 1098 1096 } else { 1099 1097 tmp = gb_addr_config & NUM_PIPES_MASK;
+4
drivers/gpu/drm/radeon/nid.h
··· 82 82 #define SOFT_RESET_REGBB (1 << 22) 83 83 #define SOFT_RESET_ORB (1 << 23) 84 84 85 + #define SRBM_READ_ERROR 0xE98 86 + #define SRBM_INT_CNTL 0xEA0 87 + #define SRBM_INT_ACK 0xEA8 88 + 85 89 #define SRBM_STATUS2 0x0EC4 86 90 #define DMA_BUSY (1 << 5) 87 91 #define DMA1_BUSY (1 << 6)
+1 -1
drivers/gpu/drm/radeon/r600_dpm.c
··· 188 188 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 189 189 radeon_crtc = to_radeon_crtc(crtc); 190 190 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 191 - vrefresh = radeon_crtc->hw_mode.vrefresh; 191 + vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode); 192 192 break; 193 193 } 194 194 }
+14 -2
drivers/gpu/drm/radeon/radeon_cs.c
··· 715 715 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; 716 716 struct radeon_device *rdev = p->rdev; 717 717 uint32_t header; 718 + int ret = 0, i; 718 719 719 720 if (idx >= ib_chunk->length_dw) { 720 721 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", ··· 744 743 break; 745 744 default: 746 745 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 747 - return -EINVAL; 746 + ret = -EINVAL; 747 + goto dump_ib; 748 748 } 749 749 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 750 750 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 751 751 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 752 - return -EINVAL; 752 + ret = -EINVAL; 753 + goto dump_ib; 753 754 } 754 755 return 0; 756 + 757 + dump_ib: 758 + for (i = 0; i < ib_chunk->length_dw; i++) { 759 + if (i == idx) 760 + printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); 761 + else 762 + printk("\t0x%08x\n", radeon_get_ib_value(p, i)); 763 + } 764 + return ret; 755 765 } 756 766 757 767 /**
+3
drivers/gpu/drm/radeon/radeon_encoders.c
··· 179 179 (rdev->pdev->subsystem_vendor == 0x1734) && 180 180 (rdev->pdev->subsystem_device == 0x1107)) 181 181 use_bl = false; 182 + /* Older PPC macs use on-GPU backlight controller */ 183 + #ifndef CONFIG_PPC_PMAC 182 184 /* disable native backlight control on older asics */ 183 185 else if (rdev->family < CHIP_R600) 184 186 use_bl = false; 187 + #endif 185 188 else 186 189 use_bl = true; 187 190 }
+6
drivers/gpu/drm/radeon/radeon_pm.c
··· 852 852 single_display = false; 853 853 } 854 854 855 + /* 120hz tends to be problematic even if they are under the 856 + * vblank limit. 857 + */ 858 + if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 859 + single_display = false; 860 + 855 861 /* certain older asics have a separare 3D performance state, 856 862 * so try that first if the user selected performance 857 863 */
+15 -7
drivers/gpu/drm/radeon/si.c
··· 3162 3162 } 3163 3163 3164 3164 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 3165 + WREG32(SRBM_INT_CNTL, 1); 3166 + WREG32(SRBM_INT_ACK, 1); 3165 3167 3166 3168 evergreen_fix_pci_max_read_req_size(rdev); 3167 3169 ··· 4701 4699 switch (pkt.type) { 4702 4700 case RADEON_PACKET_TYPE0: 4703 4701 dev_err(rdev->dev, "Packet0 not allowed!\n"); 4704 - for (i = 0; i < ib->length_dw; i++) { 4705 - if (i == idx) 4706 - printk("\t0x%08x <---\n", ib->ptr[i]); 4707 - else 4708 - printk("\t0x%08x\n", ib->ptr[i]); 4709 - } 4710 4702 ret = -EINVAL; 4711 4703 break; 4712 4704 case RADEON_PACKET_TYPE2: ··· 4732 4736 ret = -EINVAL; 4733 4737 break; 4734 4738 } 4735 - if (ret) 4739 + if (ret) { 4740 + for (i = 0; i < ib->length_dw; i++) { 4741 + if (i == idx) 4742 + printk("\t0x%08x <---\n", ib->ptr[i]); 4743 + else 4744 + printk("\t0x%08x\n", ib->ptr[i]); 4745 + } 4736 4746 break; 4747 + } 4737 4748 } while (idx < ib->length_dw); 4738 4749 4739 4750 return ret; ··· 5913 5910 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 5914 5911 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 5915 5912 WREG32(GRBM_INT_CNTL, 0); 5913 + WREG32(SRBM_INT_CNTL, 0); 5916 5914 if (rdev->num_crtc >= 2) { 5917 5915 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 5918 5916 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); ··· 6612 6608 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6613 6609 break; 6614 6610 } 6611 + break; 6612 + case 96: 6613 + DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); 6614 + WREG32(SRBM_INT_ACK, 0x1); 6615 6615 break; 6616 6616 case 124: /* UVD */ 6617 6617 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
+4
drivers/gpu/drm/radeon/sid.h
··· 358 358 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 359 359 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 360 360 361 + #define SRBM_READ_ERROR 0xE98 362 + #define SRBM_INT_CNTL 0xEA0 363 + #define SRBM_INT_ACK 0xEA8 364 + 361 365 #define SRBM_STATUS2 0x0EC4 362 366 #define DMA_BUSY (1 << 5) 363 367 #define DMA1_BUSY (1 << 6)
+40 -39
drivers/gpu/drm/tegra/dc.c
··· 997 997 crtc->state = NULL; 998 998 999 999 state = kzalloc(sizeof(*state), GFP_KERNEL); 1000 - if (state) 1000 + if (state) { 1001 1001 crtc->state = &state->base; 1002 + crtc->state->crtc = crtc; 1003 + } 1002 1004 } 1003 1005 1004 1006 static struct drm_crtc_state * ··· 1014 1012 return NULL; 1015 1013 1016 1014 copy->base.mode_changed = false; 1015 + copy->base.active_changed = false; 1017 1016 copy->base.planes_changed = false; 1018 1017 copy->base.event = NULL; 1019 1018 ··· 1230 1227 /* program display mode */ 1231 1228 tegra_dc_set_timings(dc, mode); 1232 1229 1233 - if (dc->soc->supports_border_color) 1234 - tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1235 - 1236 1230 /* interlacing isn't supported yet, so disable it */ 1237 1231 if (dc->soc->supports_interlacing) { 1238 1232 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); ··· 1252 1252 1253 1253 static void tegra_crtc_prepare(struct drm_crtc *crtc) 1254 1254 { 1255 - struct tegra_dc *dc = to_tegra_dc(crtc); 1256 - unsigned int syncpt; 1257 - unsigned long value; 1258 - 1259 1255 drm_crtc_vblank_off(crtc); 1260 - 1261 - if (dc->pipe) 1262 - syncpt = SYNCPT_VBLANK1; 1263 - else 1264 - syncpt = SYNCPT_VBLANK0; 1265 - 1266 - /* initialize display controller */ 1267 - tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1268 - tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); 1269 - 1270 - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; 1271 - tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1272 - 1273 - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1274 - WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1275 - tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1276 - 1277 - /* initialize timer */ 1278 - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1279 - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1280 - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1281 - 1282 - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1283 - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1284 - tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1285 - 1286 - value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1287 - tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1288 - 1289 - value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1290 - tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1291 1256 } 1292 1257 1293 1258 static void tegra_crtc_commit(struct drm_crtc *crtc) ··· 1629 1664 struct tegra_drm *tegra = drm->dev_private; 1630 1665 struct drm_plane *primary = NULL; 1631 1666 struct drm_plane *cursor = NULL; 1667 + unsigned int syncpt; 1668 + u32 value; 1632 1669 int err; 1633 1670 1634 1671 if (tegra->domain) { ··· 1696 1729 err); 1697 1730 goto cleanup; 1698 1731 } 1732 + 1733 + /* initialize display controller */ 1734 + if (dc->pipe) 1735 + syncpt = SYNCPT_VBLANK1; 1736 + else 1737 + syncpt = SYNCPT_VBLANK0; 1738 + 1739 + tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1740 + tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); 1741 + 1742 + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; 1743 + tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1744 + 1745 + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1746 + WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1747 + tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1748 + 1749 + /* initialize timer */ 1750 + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1751 + WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1752 + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1753 + 1754 + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1755 + WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1756 + tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1757 + 1758 + value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1759 + tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1760 + 1761 + value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 1762 + tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1763 + 1764 + if (dc->soc->supports_border_color) 1765 + tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1699 1766 1700 1767 return 0; 1701 1768
+8
drivers/gpu/drm/tegra/hdmi.c
··· 851 851 h_back_porch = mode->htotal - mode->hsync_end; 852 852 h_front_porch = mode->hsync_start - mode->hdisplay; 853 853 854 + err = clk_set_rate(hdmi->clk, pclk); 855 + if (err < 0) { 856 + dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", 857 + err); 858 + } 859 + 860 + DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); 861 + 854 862 /* power up sequence */ 855 863 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 856 864 value &= ~SOR_PLL_PDBG;
+2 -2
include/drm/i915_pciids.h
··· 214 214 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) 215 215 216 216 #define _INTEL_BDW_M_IDS(gt, info) \ 217 - _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \ 217 + _INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \ 218 218 _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \ 219 - _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \ 219 + _INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \ 220 220 _INTEL_BDW_M(gt, 0x160E, info) /* ULX */ 221 221 222 222 #define _INTEL_BDW_D_IDS(gt, info) \