Merge tag 'spi-fix-v5.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

+11

drivers/spi/atmel-quadspi.c

··· 149 149 struct clk *qspick; 150 150 struct platform_device *pdev; 151 151 const struct atmel_qspi_caps *caps; 152 + resource_size_t mmap_size; 152 153 u32 pending; 153 154 u32 mr; 154 155 u32 scr; ··· 330 329 u32 sr, offset; 331 330 int err; 332 331 332 + /* 333 + * Check if the address exceeds the MMIO window size. An improvement 334 + * would be to add support for regular SPI mode and fall back to it 335 + * when the flash memories overrun the controller's memory space. 336 + */ 337 + if (op->addr.val + op->data.nbytes > aq->mmap_size) 338 + return -ENOTSUPP; 339 + 333 340 err = atmel_qspi_set_cfg(aq, op, &offset); 334 341 if (err) 335 342 return err; ··· 488 479 err = PTR_ERR(aq->mem); 489 480 goto exit; 490 481 } 482 + 483 + aq->mmap_size = resource_size(res); 491 484 492 485 /* Get the peripheral clock */ 493 486 aq->pclk = devm_clk_get(&pdev->dev, "pclk");

-1

drivers/spi/spi-bcm63xx-hsspi.c

··· 366 366 goto out_disable_clk; 367 367 368 368 rate = clk_get_rate(pll_clk); 369 - clk_disable_unprepare(pll_clk); 370 369 if (!rate) { 371 370 ret = -EINVAL; 372 371 goto out_disable_pll_clk;

+64 -39

drivers/spi/spi-omap2-mcspi.c

··· 130 130 int fifo_depth; 131 131 bool slave_aborted; 132 132 unsigned int pin_dir:1; 133 + size_t max_xfer_len; 133 134 }; 134 135 135 136 struct omap2_mcspi_cs { ··· 975 974 * Note that we currently allow DMA only if we get a channel 976 975 * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 977 976 */ 978 - static int omap2_mcspi_request_dma(struct spi_device *spi) 977 + static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi, 978 + struct omap2_mcspi_dma *mcspi_dma) 979 979 { 980 - struct spi_master *master = spi->master; 981 - struct omap2_mcspi *mcspi; 982 - struct omap2_mcspi_dma *mcspi_dma; 983 980 int ret = 0; 984 981 985 - mcspi = spi_master_get_devdata(master); 986 - mcspi_dma = mcspi->dma_channels + spi->chip_select; 987 - 988 - init_completion(&mcspi_dma->dma_rx_completion); 989 - init_completion(&mcspi_dma->dma_tx_completion); 990 - 991 - mcspi_dma->dma_rx = dma_request_chan(&master->dev, 982 + mcspi_dma->dma_rx = dma_request_chan(mcspi->dev, 992 983 mcspi_dma->dma_rx_ch_name); 993 984 if (IS_ERR(mcspi_dma->dma_rx)) { 994 985 ret = PTR_ERR(mcspi_dma->dma_rx); ··· 988 995 goto no_dma; 989 996 } 990 997 991 - mcspi_dma->dma_tx = dma_request_chan(&master->dev, 998 + mcspi_dma->dma_tx = dma_request_chan(mcspi->dev, 992 999 mcspi_dma->dma_tx_ch_name); 993 1000 if (IS_ERR(mcspi_dma->dma_tx)) { 994 1001 ret = PTR_ERR(mcspi_dma->dma_tx); ··· 997 1004 mcspi_dma->dma_rx = NULL; 998 1005 } 999 1006 1007 + init_completion(&mcspi_dma->dma_rx_completion); 1008 + init_completion(&mcspi_dma->dma_tx_completion); 1009 + 1000 1010 no_dma: 1001 1011 return ret; 1012 + } 1013 + 1014 + static void omap2_mcspi_release_dma(struct spi_master *master) 1015 + { 1016 + struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1017 + struct omap2_mcspi_dma *mcspi_dma; 1018 + int i; 1019 + 1020 + for (i = 0; i < master->num_chipselect; i++) { 1021 + mcspi_dma = &mcspi->dma_channels[i]; 1022 + 1023 + if (mcspi_dma->dma_rx) { 1024 + dma_release_channel(mcspi_dma->dma_rx); 1025 + mcspi_dma->dma_rx = NULL; 1026 + } 1027 + if (mcspi_dma->dma_tx) { 1028 + dma_release_channel(mcspi_dma->dma_tx); 1029 + mcspi_dma->dma_tx = NULL; 1030 + } 1031 + } 1002 1032 } 1003 1033 1004 1034 static int omap2_mcspi_setup(struct spi_device *spi) ··· 1029 1013 int ret; 1030 1014 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 1031 1015 struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1032 - struct omap2_mcspi_dma *mcspi_dma; 1033 1016 struct omap2_mcspi_cs *cs = spi->controller_state; 1034 - 1035 - mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1036 1017 1037 1018 if (!cs) { 1038 1019 cs = kzalloc(sizeof *cs, GFP_KERNEL); ··· 1055 1042 } 1056 1043 } 1057 1044 1058 - if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 1059 - ret = omap2_mcspi_request_dma(spi); 1060 - if (ret) 1061 - dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n", 1062 - ret); 1063 - } 1064 - 1065 1045 ret = pm_runtime_get_sync(mcspi->dev); 1066 1046 if (ret < 0) { 1067 1047 pm_runtime_put_noidle(mcspi->dev); ··· 1071 1065 1072 1066 static void omap2_mcspi_cleanup(struct spi_device *spi) 1073 1067 { 1074 - struct omap2_mcspi *mcspi; 1075 - struct omap2_mcspi_dma *mcspi_dma; 1076 1068 struct omap2_mcspi_cs *cs; 1077 - 1078 - mcspi = spi_master_get_devdata(spi->master); 1079 1069 1080 1070 if (spi->controller_state) { 1081 1071 /* Unlink controller state from context save list */ ··· 1079 1077 list_del(&cs->node); 1080 1078 1081 1079 kfree(cs); 1082 - } 1083 - 1084 - if (spi->chip_select < spi->master->num_chipselect) { 1085 - mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1086 - 1087 - if (mcspi_dma->dma_rx) { 1088 - dma_release_channel(mcspi_dma->dma_rx); 1089 - mcspi_dma->dma_rx = NULL; 1090 - } 1091 - if (mcspi_dma->dma_tx) { 1092 - dma_release_channel(mcspi_dma->dma_tx); 1093 - mcspi_dma->dma_tx = NULL; 1094 - } 1095 1080 } 1096 1081 1097 1082 if (gpio_is_valid(spi->cs_gpio)) ··· 1291 1302 if (spi_controller_is_slave(master)) 1292 1303 return true; 1293 1304 1305 + master->dma_rx = mcspi_dma->dma_rx; 1306 + master->dma_tx = mcspi_dma->dma_tx; 1307 + 1294 1308 return (xfer->len >= DMA_MIN_BYTES); 1309 + } 1310 + 1311 + static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi) 1312 + { 1313 + struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 1314 + struct omap2_mcspi_dma *mcspi_dma = 1315 + &mcspi->dma_channels[spi->chip_select]; 1316 + 1317 + if (mcspi->max_xfer_len && mcspi_dma->dma_rx) 1318 + return mcspi->max_xfer_len; 1319 + 1320 + return SIZE_MAX; 1295 1321 } 1296 1322 1297 1323 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi) ··· 1377 1373 .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1378 1374 }; 1379 1375 1376 + static struct omap2_mcspi_platform_config am654_pdata = { 1377 + .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1378 + .max_xfer_len = SZ_4K - 1, 1379 + }; 1380 + 1380 1381 static const struct of_device_id omap_mcspi_of_match[] = { 1381 1382 { 1382 1383 .compatible = "ti,omap2-mcspi", ··· 1390 1381 { 1391 1382 .compatible = "ti,omap4-mcspi", 1392 1383 .data = &omap4_pdata, 1384 + }, 1385 + { 1386 + .compatible = "ti,am654-mcspi", 1387 + .data = &am654_pdata, 1393 1388 }, 1394 1389 { }, 1395 1390 }; ··· 1452 1439 mcspi->pin_dir = pdata->pin_dir; 1453 1440 } 1454 1441 regs_offset = pdata->regs_offset; 1442 + if (pdata->max_xfer_len) { 1443 + mcspi->max_xfer_len = pdata->max_xfer_len; 1444 + master->max_transfer_size = omap2_mcspi_max_xfer_size; 1445 + } 1455 1446 1456 1447 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1457 1448 mcspi->base = devm_ioremap_resource(&pdev->dev, r); ··· 1481 1464 for (i = 0; i < master->num_chipselect; i++) { 1482 1465 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); 1483 1466 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); 1467 + 1468 + status = omap2_mcspi_request_dma(mcspi, 1469 + &mcspi->dma_channels[i]); 1470 + if (status == -EPROBE_DEFER) 1471 + goto free_master; 1484 1472 } 1485 1473 1486 1474 status = platform_get_irq(pdev, 0); ··· 1523 1501 pm_runtime_put_sync(&pdev->dev); 1524 1502 pm_runtime_disable(&pdev->dev); 1525 1503 free_master: 1504 + omap2_mcspi_release_dma(master); 1526 1505 spi_master_put(master); 1527 1506 return status; 1528 1507 } ··· 1532 1509 { 1533 1510 struct spi_master *master = platform_get_drvdata(pdev); 1534 1511 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1512 + 1513 + omap2_mcspi_release_dma(master); 1535 1514 1536 1515 pm_runtime_dont_use_autosuspend(mcspi->dev); 1537 1516 pm_runtime_put_sync(mcspi->dev);

+23

drivers/spi/spi-pxa2xx.c

··· 70 70 #define LPSS_CAPS_CS_EN_SHIFT 9 71 71 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 72 72 73 + #define LPSS_PRIV_CLOCK_GATE 0x38 74 + #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 75 + #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 76 + 73 77 struct lpss_config { 74 78 /* LPSS offset from drv_data->ioaddr */ 75 79 unsigned offset; ··· 90 86 unsigned cs_sel_shift; 91 87 unsigned cs_sel_mask; 92 88 unsigned cs_num; 89 + /* Quirks */ 90 + unsigned cs_clk_stays_gated : 1; 93 91 }; 94 92 95 93 /* Keep these sorted with enum pxa_ssp_type */ ··· 162 156 .tx_threshold_hi = 56, 163 157 .cs_sel_shift = 8, 164 158 .cs_sel_mask = 3 << 8, 159 + .cs_clk_stays_gated = true, 165 160 }, 166 161 }; 167 162 ··· 390 383 else 391 384 value |= LPSS_CS_CONTROL_CS_HIGH; 392 385 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 386 + if (config->cs_clk_stays_gated) { 387 + u32 clkgate; 388 + 389 + /* 390 + * Changing CS alone when dynamic clock gating is on won't 391 + * actually flip CS at that time. This ruins SPI transfers 392 + * that specify delays, or have no data. Toggle the clock mode 393 + * to force on briefly to poke the CS pin to move. 394 + */ 395 + clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE); 396 + value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) | 397 + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON; 398 + 399 + __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value); 400 + __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate); 401 + } 393 402 } 394 403 395 404 static void cs_assert(struct spi_device *spi)

+7 -4

drivers/spi/spi-qup.c

··· 1217 1217 struct spi_qup *controller = spi_master_get_devdata(master); 1218 1218 int ret; 1219 1219 1220 + if (pm_runtime_suspended(device)) { 1221 + ret = spi_qup_pm_resume_runtime(device); 1222 + if (ret) 1223 + return ret; 1224 + } 1220 1225 ret = spi_master_suspend(master); 1221 1226 if (ret) 1222 1227 return ret; ··· 1230 1225 if (ret) 1231 1226 return ret; 1232 1227 1233 - if (!pm_runtime_suspended(device)) { 1234 - clk_disable_unprepare(controller->cclk); 1235 - clk_disable_unprepare(controller->iclk); 1236 - } 1228 + clk_disable_unprepare(controller->cclk); 1229 + clk_disable_unprepare(controller->iclk); 1237 1230 return 0; 1238 1231 } 1239 1232

-3

drivers/spi/spi-zynqmp-gqspi.c

··· 401 401 402 402 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 403 403 404 - /* Dummy generic FIFO entry */ 405 - zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 406 - 407 404 /* Manually start the generic FIFO command */ 408 405 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 409 406 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |

+15 -17

drivers/spi/spi.c

··· 2639 2639 if (ctlr->use_gpio_descriptors) { 2640 2640 status = spi_get_gpio_descs(ctlr); 2641 2641 if (status) 2642 - return status; 2642 + goto free_bus_id; 2643 2643 /* 2644 2644 * A controller using GPIO descriptors always 2645 2645 * supports SPI_CS_HIGH if need be. ··· 2649 2649 /* Legacy code path for GPIOs from DT */ 2650 2650 status = of_spi_get_gpio_numbers(ctlr); 2651 2651 if (status) 2652 - return status; 2652 + goto free_bus_id; 2653 2653 } 2654 2654 } 2655 2655 ··· 2657 2657 * Even if it's just one always-selected device, there must 2658 2658 * be at least one chipselect. 2659 2659 */ 2660 - if (!ctlr->num_chipselect) 2661 - return -EINVAL; 2660 + if (!ctlr->num_chipselect) { 2661 + status = -EINVAL; 2662 + goto free_bus_id; 2663 + } 2662 2664 2663 2665 status = device_add(&ctlr->dev); 2664 - if (status < 0) { 2665 - /* free bus id */ 2666 - mutex_lock(&board_lock); 2667 - idr_remove(&spi_master_idr, ctlr->bus_num); 2668 - mutex_unlock(&board_lock); 2669 - goto done; 2670 - } 2666 + if (status < 0) 2667 + goto free_bus_id; 2671 2668 dev_dbg(dev, "registered %s %s\n", 2672 2669 spi_controller_is_slave(ctlr) ? "slave" : "master", 2673 2670 dev_name(&ctlr->dev)); ··· 2680 2683 status = spi_controller_initialize_queue(ctlr); 2681 2684 if (status) { 2682 2685 device_del(&ctlr->dev); 2683 - /* free bus id */ 2684 - mutex_lock(&board_lock); 2685 - idr_remove(&spi_master_idr, ctlr->bus_num); 2686 - mutex_unlock(&board_lock); 2687 - goto done; 2686 + goto free_bus_id; 2688 2687 } 2689 2688 } 2690 2689 /* add statistics */ ··· 2695 2702 /* Register devices from the device tree and ACPI */ 2696 2703 of_register_spi_devices(ctlr); 2697 2704 acpi_register_spi_devices(ctlr); 2698 - done: 2705 + return status; 2706 + 2707 + free_bus_id: 2708 + mutex_lock(&board_lock); 2709 + idr_remove(&spi_master_idr, ctlr->bus_num); 2710 + mutex_unlock(&board_lock); 2699 2711 return status; 2700 2712 } 2701 2713 EXPORT_SYMBOL_GPL(spi_register_controller);

+5

drivers/spi/spidev.c

··· 396 396 else 397 397 retval = get_user(tmp, (u32 __user *)arg); 398 398 if (retval == 0) { 399 + struct spi_controller *ctlr = spi->controller; 399 400 u32 save = spi->mode; 400 401 401 402 if (tmp & ~SPI_MODE_MASK) { 402 403 retval = -EINVAL; 403 404 break; 404 405 } 406 + 407 + if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods && 408 + ctlr->cs_gpiods[spi->chip_select]) 409 + tmp |= SPI_CS_HIGH; 405 410 406 411 tmp |= spi->mode & ~SPI_MODE_MASK; 407 412 spi->mode = (u16)tmp;

+1

include/linux/platform_data/spi-omap2-mcspi.h

··· 11 11 unsigned short num_cs; 12 12 unsigned int regs_offset; 13 13 unsigned int pin_dir:1; 14 + size_t max_xfer_len; 14 15 }; 15 16 16 17 struct omap2_mcspi_device_config {

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