Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: ipq8074: convert to parent data
Convert the IPQ8074 GCC driver to use parent data instead of global
name matching.
Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
authored by
Robert Marko
and committed by
Bjorn Andersson
ae55ad32
05e5c125
+813
-968
+813
-968
drivers/clk/qcom/gcc-ipq8074.c
+813
-968
drivers/clk/qcom/gcc-ipq8074.c
···
49
49
P_UNIPHY2_TX,
50
50
};
51
51
52
-
static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
53
-
"xo",
54
-
"gpll0",
55
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"gpll0_out_main_div2",
56
-
};
57
-
58
-
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
59
-
{ P_XO, 0 },
60
-
{ P_GPLL0, 1 },
61
-
{ P_GPLL0_DIV2, 4 },
62
-
};
63
-
64
-
static const struct parent_map gcc_xo_gpll0_map[] = {
65
-
{ P_XO, 0 },
66
-
{ P_GPLL0, 1 },
67
-
};
68
-
69
-
static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
70
-
"xo",
71
-
"gpll0",
72
-
"gpll2",
73
-
"gpll0_out_main_div2",
74
-
};
75
-
76
-
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
77
-
{ P_XO, 0 },
78
-
{ P_GPLL0, 1 },
79
-
{ P_GPLL2, 2 },
80
-
{ P_GPLL0_DIV2, 4 },
81
-
};
82
-
83
-
static const char * const gcc_xo_gpll0_sleep_clk[] = {
84
-
"xo",
85
-
"gpll0",
86
-
"sleep_clk",
87
-
};
88
-
89
-
static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
90
-
{ P_XO, 0 },
91
-
{ P_GPLL0, 2 },
92
-
{ P_SLEEP_CLK, 6 },
93
-
};
94
-
95
-
static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
96
-
"xo",
97
-
"gpll6",
98
-
"gpll0",
99
-
"gpll0_out_main_div2",
100
-
};
101
-
102
-
static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
103
-
{ P_XO, 0 },
104
-
{ P_GPLL6, 1 },
105
-
{ P_GPLL0, 3 },
106
-
{ P_GPLL0_DIV2, 4 },
107
-
};
108
-
109
-
static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
110
-
"xo",
111
-
"gpll0_out_main_div2",
112
-
"gpll0",
113
-
};
114
-
115
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static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
116
-
{ P_XO, 0 },
117
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{ P_GPLL0_DIV2, 2 },
118
-
{ P_GPLL0, 1 },
119
-
};
120
-
121
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static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
122
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"usb3phy_0_cc_pipe_clk",
123
-
"xo",
124
-
};
125
-
126
-
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
127
-
{ P_USB3PHY_0_PIPE, 0 },
128
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{ P_XO, 2 },
129
-
};
130
-
131
-
static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
132
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"usb3phy_1_cc_pipe_clk",
133
-
"xo",
134
-
};
135
-
136
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static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
137
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{ P_USB3PHY_1_PIPE, 0 },
138
-
{ P_XO, 2 },
139
-
};
140
-
141
-
static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
142
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"pcie20_phy0_pipe_clk",
143
-
"xo",
144
-
};
145
-
146
-
static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
147
-
{ P_PCIE20_PHY0_PIPE, 0 },
148
-
{ P_XO, 2 },
149
-
};
150
-
151
-
static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
152
-
"pcie20_phy1_pipe_clk",
153
-
"xo",
154
-
};
155
-
156
-
static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
157
-
{ P_PCIE20_PHY1_PIPE, 0 },
158
-
{ P_XO, 2 },
159
-
};
160
-
161
-
static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
162
-
"xo",
163
-
"gpll0",
164
-
"gpll6",
165
-
"gpll0_out_main_div2",
166
-
};
167
-
168
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static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
169
-
{ P_XO, 0 },
170
-
{ P_GPLL0, 1 },
171
-
{ P_GPLL6, 2 },
172
-
{ P_GPLL0_DIV2, 4 },
173
-
};
174
-
175
-
static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
176
-
"xo",
177
-
"gpll0",
178
-
"gpll6",
179
-
"gpll0_out_main_div2",
180
-
};
181
-
182
-
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
183
-
{ P_XO, 0 },
184
-
{ P_GPLL0, 1 },
185
-
{ P_GPLL6, 2 },
186
-
{ P_GPLL0_DIV2, 3 },
187
-
};
188
-
189
-
static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
190
-
"xo",
191
-
"bias_pll_nss_noc_clk",
192
-
"gpll0",
193
-
"gpll2",
194
-
};
195
-
196
-
static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
197
-
{ P_XO, 0 },
198
-
{ P_BIAS_PLL_NSS_NOC, 1 },
199
-
{ P_GPLL0, 2 },
200
-
{ P_GPLL2, 3 },
201
-
};
202
-
203
-
static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
204
-
"xo",
205
-
"nss_crypto_pll",
206
-
"gpll0",
207
-
};
208
-
209
-
static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
210
-
{ P_XO, 0 },
211
-
{ P_NSS_CRYPTO_PLL, 1 },
212
-
{ P_GPLL0, 2 },
213
-
};
214
-
215
-
static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
216
-
"xo",
217
-
"ubi32_pll",
218
-
"gpll0",
219
-
"gpll2",
220
-
"gpll4",
221
-
"gpll6",
222
-
};
223
-
224
-
static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
225
-
{ P_XO, 0 },
226
-
{ P_UBI32_PLL, 1 },
227
-
{ P_GPLL0, 2 },
228
-
{ P_GPLL2, 3 },
229
-
{ P_GPLL4, 4 },
230
-
{ P_GPLL6, 5 },
231
-
};
232
-
233
-
static const char * const gcc_xo_gpll0_out_main_div2[] = {
234
-
"xo",
235
-
"gpll0_out_main_div2",
236
-
};
237
-
238
-
static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
239
-
{ P_XO, 0 },
240
-
{ P_GPLL0_DIV2, 1 },
241
-
};
242
-
243
-
static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
244
-
"xo",
245
-
"bias_pll_cc_clk",
246
-
"gpll0",
247
-
"gpll4",
248
-
"nss_crypto_pll",
249
-
"ubi32_pll",
250
-
};
251
-
252
-
static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
253
-
{ P_XO, 0 },
254
-
{ P_BIAS_PLL, 1 },
255
-
{ P_GPLL0, 2 },
256
-
{ P_GPLL4, 3 },
257
-
{ P_NSS_CRYPTO_PLL, 4 },
258
-
{ P_UBI32_PLL, 5 },
259
-
};
260
-
261
-
static const char * const gcc_xo_gpll0_gpll4[] = {
262
-
"xo",
263
-
"gpll0",
264
-
"gpll4",
265
-
};
266
-
267
-
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
268
-
{ P_XO, 0 },
269
-
{ P_GPLL0, 1 },
270
-
{ P_GPLL4, 2 },
271
-
};
272
-
273
-
static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
274
-
"xo",
275
-
"uniphy0_gcc_rx_clk",
276
-
"uniphy0_gcc_tx_clk",
277
-
"ubi32_pll",
278
-
"bias_pll_cc_clk",
279
-
};
280
-
281
-
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
282
-
{ P_XO, 0 },
283
-
{ P_UNIPHY0_RX, 1 },
284
-
{ P_UNIPHY0_TX, 2 },
285
-
{ P_UBI32_PLL, 5 },
286
-
{ P_BIAS_PLL, 6 },
287
-
};
288
-
289
-
static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
290
-
"xo",
291
-
"uniphy0_gcc_tx_clk",
292
-
"uniphy0_gcc_rx_clk",
293
-
"ubi32_pll",
294
-
"bias_pll_cc_clk",
295
-
};
296
-
297
-
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
298
-
{ P_XO, 0 },
299
-
{ P_UNIPHY0_TX, 1 },
300
-
{ P_UNIPHY0_RX, 2 },
301
-
{ P_UBI32_PLL, 5 },
302
-
{ P_BIAS_PLL, 6 },
303
-
};
304
-
305
-
static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
306
-
"xo",
307
-
"uniphy0_gcc_rx_clk",
308
-
"uniphy0_gcc_tx_clk",
309
-
"uniphy1_gcc_rx_clk",
310
-
"uniphy1_gcc_tx_clk",
311
-
"ubi32_pll",
312
-
"bias_pll_cc_clk",
313
-
};
314
-
315
-
static const struct parent_map
316
-
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
317
-
{ P_XO, 0 },
318
-
{ P_UNIPHY0_RX, 1 },
319
-
{ P_UNIPHY0_TX, 2 },
320
-
{ P_UNIPHY1_RX, 3 },
321
-
{ P_UNIPHY1_TX, 4 },
322
-
{ P_UBI32_PLL, 5 },
323
-
{ P_BIAS_PLL, 6 },
324
-
};
325
-
326
-
static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
327
-
"xo",
328
-
"uniphy0_gcc_tx_clk",
329
-
"uniphy0_gcc_rx_clk",
330
-
"uniphy1_gcc_tx_clk",
331
-
"uniphy1_gcc_rx_clk",
332
-
"ubi32_pll",
333
-
"bias_pll_cc_clk",
334
-
};
335
-
336
-
static const struct parent_map
337
-
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
338
-
{ P_XO, 0 },
339
-
{ P_UNIPHY0_TX, 1 },
340
-
{ P_UNIPHY0_RX, 2 },
341
-
{ P_UNIPHY1_TX, 3 },
342
-
{ P_UNIPHY1_RX, 4 },
343
-
{ P_UBI32_PLL, 5 },
344
-
{ P_BIAS_PLL, 6 },
345
-
};
346
-
347
-
static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
348
-
"xo",
349
-
"uniphy2_gcc_rx_clk",
350
-
"uniphy2_gcc_tx_clk",
351
-
"ubi32_pll",
352
-
"bias_pll_cc_clk",
353
-
};
354
-
355
-
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
356
-
{ P_XO, 0 },
357
-
{ P_UNIPHY2_RX, 1 },
358
-
{ P_UNIPHY2_TX, 2 },
359
-
{ P_UBI32_PLL, 5 },
360
-
{ P_BIAS_PLL, 6 },
361
-
};
362
-
363
-
static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
364
-
"xo",
365
-
"uniphy2_gcc_tx_clk",
366
-
"uniphy2_gcc_rx_clk",
367
-
"ubi32_pll",
368
-
"bias_pll_cc_clk",
369
-
};
370
-
371
-
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
372
-
{ P_XO, 0 },
373
-
{ P_UNIPHY2_TX, 1 },
374
-
{ P_UNIPHY2_RX, 2 },
375
-
{ P_UBI32_PLL, 5 },
376
-
{ P_BIAS_PLL, 6 },
377
-
};
378
-
379
-
static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
380
-
"xo",
381
-
"gpll0",
382
-
"gpll6",
383
-
"gpll0_out_main_div2",
384
-
"sleep_clk",
385
-
};
386
-
387
-
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
388
-
{ P_XO, 0 },
389
-
{ P_GPLL0, 1 },
390
-
{ P_GPLL6, 2 },
391
-
{ P_GPLL0_DIV2, 4 },
392
-
{ P_SLEEP_CLK, 6 },
393
-
};
394
-
395
52
static struct clk_alpha_pll gpll0_main = {
396
53
.offset = 0x21000,
397
54
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
···
57
400
.enable_mask = BIT(0),
58
401
.hw.init = &(struct clk_init_data){
59
402
.name = "gpll0_main",
60
-
.parent_names = (const char *[]){
61
-
"xo"
403
+
.parent_data = &(const struct clk_parent_data){
404
+
.fw_name = "xo",
405
+
.name = "xo",
62
406
},
63
407
.num_parents = 1,
64
408
.ops = &clk_alpha_pll_ops,
···
72
414
.div = 2,
73
415
.hw.init = &(struct clk_init_data){
74
416
.name = "gpll0_out_main_div2",
75
-
.parent_names = (const char *[]){
76
-
"gpll0_main"
77
-
},
417
+
.parent_hws = (const struct clk_hw *[]){
418
+
&gpll0_main.clkr.hw },
78
419
.num_parents = 1,
79
420
.ops = &clk_fixed_factor_ops,
80
421
.flags = CLK_SET_RATE_PARENT,
···
86
429
.width = 4,
87
430
.clkr.hw.init = &(struct clk_init_data){
88
431
.name = "gpll0",
89
-
.parent_names = (const char *[]){
90
-
"gpll0_main"
91
-
},
432
+
.parent_hws = (const struct clk_hw *[]){
433
+
&gpll0_main.clkr.hw },
92
434
.num_parents = 1,
93
435
.ops = &clk_alpha_pll_postdiv_ro_ops,
94
436
},
···
101
445
.enable_mask = BIT(2),
102
446
.hw.init = &(struct clk_init_data){
103
447
.name = "gpll2_main",
104
-
.parent_names = (const char *[]){
105
-
"xo"
448
+
.parent_data = &(const struct clk_parent_data){
449
+
.fw_name = "xo",
450
+
.name = "xo",
106
451
},
107
452
.num_parents = 1,
108
453
.ops = &clk_alpha_pll_ops,
···
118
461
.width = 4,
119
462
.clkr.hw.init = &(struct clk_init_data){
120
463
.name = "gpll2",
121
-
.parent_names = (const char *[]){
122
-
"gpll2_main"
123
-
},
464
+
.parent_hws = (const struct clk_hw *[]){
465
+
&gpll2_main.clkr.hw },
124
466
.num_parents = 1,
125
467
.ops = &clk_alpha_pll_postdiv_ro_ops,
126
468
.flags = CLK_SET_RATE_PARENT,
···
134
478
.enable_mask = BIT(5),
135
479
.hw.init = &(struct clk_init_data){
136
480
.name = "gpll4_main",
137
-
.parent_names = (const char *[]){
138
-
"xo"
481
+
.parent_data = &(const struct clk_parent_data){
482
+
.fw_name = "xo",
483
+
.name = "xo",
139
484
},
140
485
.num_parents = 1,
141
486
.ops = &clk_alpha_pll_ops,
···
151
494
.width = 4,
152
495
.clkr.hw.init = &(struct clk_init_data){
153
496
.name = "gpll4",
154
-
.parent_names = (const char *[]){
155
-
"gpll4_main"
156
-
},
497
+
.parent_hws = (const struct clk_hw *[]){
498
+
&gpll4_main.clkr.hw },
157
499
.num_parents = 1,
158
500
.ops = &clk_alpha_pll_postdiv_ro_ops,
159
501
.flags = CLK_SET_RATE_PARENT,
···
168
512
.enable_mask = BIT(7),
169
513
.hw.init = &(struct clk_init_data){
170
514
.name = "gpll6_main",
171
-
.parent_names = (const char *[]){
172
-
"xo"
515
+
.parent_data = &(const struct clk_parent_data){
516
+
.fw_name = "xo",
517
+
.name = "xo",
173
518
},
174
519
.num_parents = 1,
175
520
.ops = &clk_alpha_pll_ops,
···
185
528
.width = 2,
186
529
.clkr.hw.init = &(struct clk_init_data){
187
530
.name = "gpll6",
188
-
.parent_names = (const char *[]){
189
-
"gpll6_main"
190
-
},
531
+
.parent_hws = (const struct clk_hw *[]){
532
+
&gpll6_main.clkr.hw },
191
533
.num_parents = 1,
192
534
.ops = &clk_alpha_pll_postdiv_ro_ops,
193
535
.flags = CLK_SET_RATE_PARENT,
···
198
542
.div = 2,
199
543
.hw.init = &(struct clk_init_data){
200
544
.name = "gpll6_out_main_div2",
201
-
.parent_names = (const char *[]){
202
-
"gpll6_main"
203
-
},
545
+
.parent_hws = (const struct clk_hw *[]){
546
+
&gpll6_main.clkr.hw },
204
547
.num_parents = 1,
205
548
.ops = &clk_fixed_factor_ops,
206
549
.flags = CLK_SET_RATE_PARENT,
···
215
560
.enable_mask = BIT(6),
216
561
.hw.init = &(struct clk_init_data){
217
562
.name = "ubi32_pll_main",
218
-
.parent_names = (const char *[]){
219
-
"xo"
563
+
.parent_data = &(const struct clk_parent_data){
564
+
.fw_name = "xo",
565
+
.name = "xo",
220
566
},
221
567
.num_parents = 1,
222
568
.ops = &clk_alpha_pll_huayra_ops,
···
231
575
.width = 2,
232
576
.clkr.hw.init = &(struct clk_init_data){
233
577
.name = "ubi32_pll",
234
-
.parent_names = (const char *[]){
235
-
"ubi32_pll_main"
236
-
},
578
+
.parent_hws = (const struct clk_hw *[]){
579
+
&ubi32_pll_main.clkr.hw },
237
580
.num_parents = 1,
238
581
.ops = &clk_alpha_pll_postdiv_ro_ops,
239
582
.flags = CLK_SET_RATE_PARENT,
···
247
592
.enable_mask = BIT(4),
248
593
.hw.init = &(struct clk_init_data){
249
594
.name = "nss_crypto_pll_main",
250
-
.parent_names = (const char *[]){
251
-
"xo"
595
+
.parent_data = &(const struct clk_parent_data){
596
+
.fw_name = "xo",
597
+
.name = "xo",
252
598
},
253
599
.num_parents = 1,
254
600
.ops = &clk_alpha_pll_ops,
···
263
607
.width = 4,
264
608
.clkr.hw.init = &(struct clk_init_data){
265
609
.name = "nss_crypto_pll",
266
-
.parent_names = (const char *[]){
267
-
"nss_crypto_pll_main"
268
-
},
610
+
.parent_hws = (const struct clk_hw *[]){
611
+
&nss_crypto_pll_main.clkr.hw },
269
612
.num_parents = 1,
270
613
.ops = &clk_alpha_pll_postdiv_ro_ops,
271
614
.flags = CLK_SET_RATE_PARENT,
···
278
623
{ }
279
624
};
280
625
626
+
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
627
+
{ .fw_name = "xo", .name = "xo" },
628
+
{ .hw = &gpll0.clkr.hw},
629
+
{ .hw = &gpll0_out_main_div2.hw},
630
+
};
631
+
632
+
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
633
+
{ P_XO, 0 },
634
+
{ P_GPLL0, 1 },
635
+
{ P_GPLL0_DIV2, 4 },
636
+
};
637
+
281
638
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
282
639
.cmd_rcgr = 0x27000,
283
640
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
···
297
630
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
298
631
.clkr.hw.init = &(struct clk_init_data){
299
632
.name = "pcnoc_bfdcd_clk_src",
300
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
301
-
.num_parents = 3,
633
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
634
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
302
635
.ops = &clk_rcg2_ops,
303
636
.flags = CLK_IS_CRITICAL,
304
637
},
···
309
642
.div = 1,
310
643
.hw.init = &(struct clk_init_data){
311
644
.name = "pcnoc_clk_src",
312
-
.parent_names = (const char *[]){
313
-
"pcnoc_bfdcd_clk_src"
314
-
},
645
+
.parent_hws = (const struct clk_hw *[]){
646
+
&pcnoc_bfdcd_clk_src.clkr.hw },
315
647
.num_parents = 1,
316
648
.ops = &clk_fixed_factor_ops,
317
649
.flags = CLK_SET_RATE_PARENT,
···
324
658
.enable_mask = BIT(1),
325
659
.hw.init = &(struct clk_init_data){
326
660
.name = "gcc_sleep_clk_src",
327
-
.parent_names = (const char *[]){
328
-
"sleep_clk"
661
+
.parent_data = &(const struct clk_parent_data){
662
+
.fw_name = "sleep_clk",
663
+
.name = "sleep_clk",
329
664
},
330
665
.num_parents = 1,
331
666
.ops = &clk_branch2_ops,
···
349
682
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
350
683
.clkr.hw.init = &(struct clk_init_data){
351
684
.name = "blsp1_qup1_i2c_apps_clk_src",
352
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
353
-
.num_parents = 3,
685
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
686
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
354
687
.ops = &clk_rcg2_ops,
355
688
},
356
689
};
···
375
708
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
376
709
.clkr.hw.init = &(struct clk_init_data){
377
710
.name = "blsp1_qup1_spi_apps_clk_src",
378
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
379
-
.num_parents = 3,
711
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
712
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
380
713
.ops = &clk_rcg2_ops,
381
714
},
382
715
};
···
388
721
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
389
722
.clkr.hw.init = &(struct clk_init_data){
390
723
.name = "blsp1_qup2_i2c_apps_clk_src",
391
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
392
-
.num_parents = 3,
724
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
725
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
393
726
.ops = &clk_rcg2_ops,
394
727
},
395
728
};
···
402
735
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
403
736
.clkr.hw.init = &(struct clk_init_data){
404
737
.name = "blsp1_qup2_spi_apps_clk_src",
405
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
406
-
.num_parents = 3,
738
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
739
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
407
740
.ops = &clk_rcg2_ops,
408
741
},
409
742
};
···
415
748
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
416
749
.clkr.hw.init = &(struct clk_init_data){
417
750
.name = "blsp1_qup3_i2c_apps_clk_src",
418
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
419
-
.num_parents = 3,
751
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
752
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
420
753
.ops = &clk_rcg2_ops,
421
754
},
422
755
};
···
429
762
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
430
763
.clkr.hw.init = &(struct clk_init_data){
431
764
.name = "blsp1_qup3_spi_apps_clk_src",
432
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
433
-
.num_parents = 3,
765
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
766
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
434
767
.ops = &clk_rcg2_ops,
435
768
},
436
769
};
···
442
775
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
443
776
.clkr.hw.init = &(struct clk_init_data){
444
777
.name = "blsp1_qup4_i2c_apps_clk_src",
445
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
446
-
.num_parents = 3,
778
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
779
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
447
780
.ops = &clk_rcg2_ops,
448
781
},
449
782
};
···
456
789
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
457
790
.clkr.hw.init = &(struct clk_init_data){
458
791
.name = "blsp1_qup4_spi_apps_clk_src",
459
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
460
-
.num_parents = 3,
792
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
793
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
461
794
.ops = &clk_rcg2_ops,
462
795
},
463
796
};
···
469
802
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
470
803
.clkr.hw.init = &(struct clk_init_data){
471
804
.name = "blsp1_qup5_i2c_apps_clk_src",
472
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
473
-
.num_parents = 3,
805
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
806
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
474
807
.ops = &clk_rcg2_ops,
475
808
},
476
809
};
···
483
816
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
484
817
.clkr.hw.init = &(struct clk_init_data){
485
818
.name = "blsp1_qup5_spi_apps_clk_src",
486
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
487
-
.num_parents = 3,
819
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
820
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
488
821
.ops = &clk_rcg2_ops,
489
822
},
490
823
};
···
496
829
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
497
830
.clkr.hw.init = &(struct clk_init_data){
498
831
.name = "blsp1_qup6_i2c_apps_clk_src",
499
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
500
-
.num_parents = 3,
832
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
833
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
501
834
.ops = &clk_rcg2_ops,
502
835
},
503
836
};
···
510
843
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
511
844
.clkr.hw.init = &(struct clk_init_data){
512
845
.name = "blsp1_qup6_spi_apps_clk_src",
513
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
514
-
.num_parents = 3,
846
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
847
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
515
848
.ops = &clk_rcg2_ops,
516
849
},
517
850
};
···
544
877
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
545
878
.clkr.hw.init = &(struct clk_init_data){
546
879
.name = "blsp1_uart1_apps_clk_src",
547
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
548
-
.num_parents = 3,
880
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
881
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
549
882
.ops = &clk_rcg2_ops,
550
883
},
551
884
};
···
558
891
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
559
892
.clkr.hw.init = &(struct clk_init_data){
560
893
.name = "blsp1_uart2_apps_clk_src",
561
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
562
-
.num_parents = 3,
894
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
895
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
563
896
.ops = &clk_rcg2_ops,
564
897
},
565
898
};
···
572
905
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
573
906
.clkr.hw.init = &(struct clk_init_data){
574
907
.name = "blsp1_uart3_apps_clk_src",
575
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
576
-
.num_parents = 3,
908
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
909
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
577
910
.ops = &clk_rcg2_ops,
578
911
},
579
912
};
···
586
919
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
587
920
.clkr.hw.init = &(struct clk_init_data){
588
921
.name = "blsp1_uart4_apps_clk_src",
589
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
590
-
.num_parents = 3,
922
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
923
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
591
924
.ops = &clk_rcg2_ops,
592
925
},
593
926
};
···
600
933
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
601
934
.clkr.hw.init = &(struct clk_init_data){
602
935
.name = "blsp1_uart5_apps_clk_src",
603
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
604
-
.num_parents = 3,
936
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
937
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
605
938
.ops = &clk_rcg2_ops,
606
939
},
607
940
};
···
614
947
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
615
948
.clkr.hw.init = &(struct clk_init_data){
616
949
.name = "blsp1_uart6_apps_clk_src",
617
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
618
-
.num_parents = 3,
950
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
951
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
619
952
.ops = &clk_rcg2_ops,
620
953
},
621
954
};
···
623
956
static const struct clk_parent_data gcc_xo_gpll0[] = {
624
957
{ .fw_name = "xo" },
625
958
{ .hw = &gpll0.clkr.hw },
959
+
};
960
+
961
+
static const struct parent_map gcc_xo_gpll0_map[] = {
962
+
{ P_XO, 0 },
963
+
{ P_GPLL0, 1 },
626
964
};
627
965
628
966
static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
···
644
972
.clkr.hw.init = &(struct clk_init_data){
645
973
.name = "pcie0_axi_clk_src",
646
974
.parent_data = gcc_xo_gpll0,
647
-
.num_parents = 2,
975
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
648
976
.ops = &clk_rcg2_ops,
649
977
},
650
978
};
651
979
652
980
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
653
981
F(19200000, P_XO, 1, 0, 0),
982
+
};
983
+
984
+
static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
985
+
{ .fw_name = "xo", .name = "xo" },
986
+
{ .hw = &gpll0.clkr.hw },
987
+
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
988
+
};
989
+
990
+
static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
991
+
{ P_XO, 0 },
992
+
{ P_GPLL0, 2 },
993
+
{ P_SLEEP_CLK, 6 },
654
994
};
655
995
656
996
static struct clk_rcg2 pcie0_aux_clk_src = {
···
673
989
.parent_map = gcc_xo_gpll0_sleep_clk_map,
674
990
.clkr.hw.init = &(struct clk_init_data){
675
991
.name = "pcie0_aux_clk_src",
676
-
.parent_names = gcc_xo_gpll0_sleep_clk,
677
-
.num_parents = 3,
992
+
.parent_data = gcc_xo_gpll0_sleep_clk,
993
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
678
994
.ops = &clk_rcg2_ops,
679
995
},
996
+
};
997
+
998
+
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
999
+
{ .name = "pcie20_phy0_pipe_clk" },
1000
+
{ .fw_name = "xo", .name = "xo" },
1001
+
};
1002
+
1003
+
static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
1004
+
{ P_PCIE20_PHY0_PIPE, 0 },
1005
+
{ P_XO, 2 },
680
1006
};
681
1007
682
1008
static struct clk_regmap_mux pcie0_pipe_clk_src = {
···
697
1003
.clkr = {
698
1004
.hw.init = &(struct clk_init_data){
699
1005
.name = "pcie0_pipe_clk_src",
700
-
.parent_names = gcc_pcie20_phy0_pipe_clk_xo,
701
-
.num_parents = 2,
1006
+
.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
1007
+
.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
702
1008
.ops = &clk_regmap_mux_closest_ops,
703
1009
.flags = CLK_SET_RATE_PARENT,
704
1010
},
···
713
1019
.clkr.hw.init = &(struct clk_init_data){
714
1020
.name = "pcie1_axi_clk_src",
715
1021
.parent_data = gcc_xo_gpll0,
716
-
.num_parents = 2,
1022
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
717
1023
.ops = &clk_rcg2_ops,
718
1024
},
719
1025
};
···
726
1032
.parent_map = gcc_xo_gpll0_sleep_clk_map,
727
1033
.clkr.hw.init = &(struct clk_init_data){
728
1034
.name = "pcie1_aux_clk_src",
729
-
.parent_names = gcc_xo_gpll0_sleep_clk,
730
-
.num_parents = 3,
1035
+
.parent_data = gcc_xo_gpll0_sleep_clk,
1036
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
731
1037
.ops = &clk_rcg2_ops,
732
1038
},
1039
+
};
1040
+
1041
+
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
1042
+
{ .name = "pcie20_phy1_pipe_clk" },
1043
+
{ .fw_name = "xo", .name = "xo" },
1044
+
};
1045
+
1046
+
static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
1047
+
{ P_PCIE20_PHY1_PIPE, 0 },
1048
+
{ P_XO, 2 },
733
1049
};
734
1050
735
1051
static struct clk_regmap_mux pcie1_pipe_clk_src = {
···
750
1046
.clkr = {
751
1047
.hw.init = &(struct clk_init_data){
752
1048
.name = "pcie1_pipe_clk_src",
753
-
.parent_names = gcc_pcie20_phy1_pipe_clk_xo,
754
-
.num_parents = 2,
1049
+
.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
1050
+
.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
755
1051
.ops = &clk_regmap_mux_closest_ops,
756
1052
.flags = CLK_SET_RATE_PARENT,
757
1053
},
···
770
1066
{ }
771
1067
};
772
1068
1069
+
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
1070
+
{ .fw_name = "xo", .name = "xo" },
1071
+
{ .hw = &gpll0.clkr.hw },
1072
+
{ .hw = &gpll2.clkr.hw },
1073
+
{ .hw = &gpll0_out_main_div2.hw },
1074
+
};
1075
+
1076
+
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
1077
+
{ P_XO, 0 },
1078
+
{ P_GPLL0, 1 },
1079
+
{ P_GPLL2, 2 },
1080
+
{ P_GPLL0_DIV2, 4 },
1081
+
};
1082
+
773
1083
static struct clk_rcg2 sdcc1_apps_clk_src = {
774
1084
.cmd_rcgr = 0x42004,
775
1085
.freq_tbl = ftbl_sdcc_apps_clk_src,
···
792
1074
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
793
1075
.clkr.hw.init = &(struct clk_init_data){
794
1076
.name = "sdcc1_apps_clk_src",
795
-
.parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
796
-
.num_parents = 4,
1077
+
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1078
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
797
1079
.ops = &clk_rcg2_floor_ops,
798
1080
},
799
1081
};
···
804
1086
F(308570000, P_GPLL6, 3.5, 0, 0),
805
1087
};
806
1088
1089
+
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
1090
+
{ .fw_name = "xo", .name = "xo" },
1091
+
{ .hw = &gpll0.clkr.hw },
1092
+
{ .hw = &gpll6.clkr.hw },
1093
+
{ .hw = &gpll0_out_main_div2.hw },
1094
+
};
1095
+
1096
+
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
1097
+
{ P_XO, 0 },
1098
+
{ P_GPLL0, 1 },
1099
+
{ P_GPLL6, 2 },
1100
+
{ P_GPLL0_DIV2, 4 },
1101
+
};
1102
+
807
1103
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
808
1104
.cmd_rcgr = 0x5d000,
809
1105
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
···
826
1094
.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
827
1095
.clkr.hw.init = &(struct clk_init_data){
828
1096
.name = "sdcc1_ice_core_clk_src",
829
-
.parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
830
-
.num_parents = 4,
1097
+
.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
1098
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
831
1099
.ops = &clk_rcg2_ops,
832
1100
},
833
1101
};
···
840
1108
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
841
1109
.clkr.hw.init = &(struct clk_init_data){
842
1110
.name = "sdcc2_apps_clk_src",
843
-
.parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
844
-
.num_parents = 4,
1111
+
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1112
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
845
1113
.ops = &clk_rcg2_floor_ops,
846
1114
},
847
1115
};
···
853
1121
{ }
854
1122
};
855
1123
1124
+
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
1125
+
{ .fw_name = "xo", .name = "xo" },
1126
+
{ .hw = &gpll0_out_main_div2.hw },
1127
+
{ .hw = &gpll0.clkr.hw },
1128
+
};
1129
+
1130
+
static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
1131
+
{ P_XO, 0 },
1132
+
{ P_GPLL0_DIV2, 2 },
1133
+
{ P_GPLL0, 1 },
1134
+
};
1135
+
856
1136
static struct clk_rcg2 usb0_master_clk_src = {
857
1137
.cmd_rcgr = 0x3e00c,
858
1138
.freq_tbl = ftbl_usb_master_clk_src,
···
873
1129
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
874
1130
.clkr.hw.init = &(struct clk_init_data){
875
1131
.name = "usb0_master_clk_src",
876
-
.parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
877
-
.num_parents = 3,
1132
+
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1133
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
878
1134
.ops = &clk_rcg2_ops,
879
1135
},
880
1136
};
···
892
1148
.parent_map = gcc_xo_gpll0_sleep_clk_map,
893
1149
.clkr.hw.init = &(struct clk_init_data){
894
1150
.name = "usb0_aux_clk_src",
895
-
.parent_names = gcc_xo_gpll0_sleep_clk,
896
-
.num_parents = 3,
1151
+
.parent_data = gcc_xo_gpll0_sleep_clk,
1152
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
897
1153
.ops = &clk_rcg2_ops,
898
1154
},
899
1155
};
···
905
1161
{ }
906
1162
};
907
1163
1164
+
static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1165
+
{ .fw_name = "xo", .name = "xo" },
1166
+
{ .hw = &gpll6.clkr.hw },
1167
+
{ .hw = &gpll0.clkr.hw },
1168
+
{ .hw = &gpll0_out_main_div2.hw },
1169
+
};
1170
+
1171
+
static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1172
+
{ P_XO, 0 },
1173
+
{ P_GPLL6, 1 },
1174
+
{ P_GPLL0, 3 },
1175
+
{ P_GPLL0_DIV2, 4 },
1176
+
};
1177
+
908
1178
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
909
1179
.cmd_rcgr = 0x3e020,
910
1180
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
···
927
1169
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
928
1170
.clkr.hw.init = &(struct clk_init_data){
929
1171
.name = "usb0_mock_utmi_clk_src",
930
-
.parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
931
-
.num_parents = 4,
1172
+
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1173
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
932
1174
.ops = &clk_rcg2_ops,
933
1175
},
1176
+
};
1177
+
1178
+
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1179
+
{ .name = "usb3phy_0_cc_pipe_clk" },
1180
+
{ .fw_name = "xo", .name = "xo" },
1181
+
};
1182
+
1183
+
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1184
+
{ P_USB3PHY_0_PIPE, 0 },
1185
+
{ P_XO, 2 },
934
1186
};
935
1187
936
1188
static struct clk_regmap_mux usb0_pipe_clk_src = {
···
951
1183
.clkr = {
952
1184
.hw.init = &(struct clk_init_data){
953
1185
.name = "usb0_pipe_clk_src",
954
-
.parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
955
-
.num_parents = 2,
1186
+
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1187
+
.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
956
1188
.ops = &clk_regmap_mux_closest_ops,
957
1189
.flags = CLK_SET_RATE_PARENT,
958
1190
},
···
967
1199
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
968
1200
.clkr.hw.init = &(struct clk_init_data){
969
1201
.name = "usb1_master_clk_src",
970
-
.parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
971
-
.num_parents = 3,
1202
+
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1203
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
972
1204
.ops = &clk_rcg2_ops,
973
1205
},
974
1206
};
···
981
1213
.parent_map = gcc_xo_gpll0_sleep_clk_map,
982
1214
.clkr.hw.init = &(struct clk_init_data){
983
1215
.name = "usb1_aux_clk_src",
984
-
.parent_names = gcc_xo_gpll0_sleep_clk,
985
-
.num_parents = 3,
1216
+
.parent_data = gcc_xo_gpll0_sleep_clk,
1217
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
986
1218
.ops = &clk_rcg2_ops,
987
1219
},
988
1220
};
···
995
1227
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
996
1228
.clkr.hw.init = &(struct clk_init_data){
997
1229
.name = "usb1_mock_utmi_clk_src",
998
-
.parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
999
-
.num_parents = 4,
1230
+
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1231
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
1000
1232
.ops = &clk_rcg2_ops,
1001
1233
},
1234
+
};
1235
+
1236
+
static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
1237
+
{ .name = "usb3phy_1_cc_pipe_clk" },
1238
+
{ .fw_name = "xo", .name = "xo" },
1239
+
};
1240
+
1241
+
static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
1242
+
{ P_USB3PHY_1_PIPE, 0 },
1243
+
{ P_XO, 2 },
1002
1244
};
1003
1245
1004
1246
static struct clk_regmap_mux usb1_pipe_clk_src = {
···
1019
1241
.clkr = {
1020
1242
.hw.init = &(struct clk_init_data){
1021
1243
.name = "usb1_pipe_clk_src",
1022
-
.parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1023
-
.num_parents = 2,
1244
+
.parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
1245
+
.num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
1024
1246
.ops = &clk_regmap_mux_closest_ops,
1025
1247
.flags = CLK_SET_RATE_PARENT,
1026
1248
},
···
1034
1256
.enable_mask = BIT(1),
1035
1257
.hw.init = &(struct clk_init_data){
1036
1258
.name = "gcc_xo_clk_src",
1037
-
.parent_names = (const char *[]){
1038
-
"xo"
1259
+
.parent_data = &(const struct clk_parent_data){
1260
+
.fw_name = "xo",
1261
+
.name = "xo",
1039
1262
},
1040
1263
.num_parents = 1,
1041
1264
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
···
1050
1271
.div = 4,
1051
1272
.hw.init = &(struct clk_init_data){
1052
1273
.name = "gcc_xo_div4_clk_src",
1053
-
.parent_names = (const char *[]){
1054
-
"gcc_xo_clk_src"
1055
-
},
1274
+
.parent_hws = (const struct clk_hw *[]){
1275
+
&gcc_xo_clk_src.clkr.hw },
1056
1276
.num_parents = 1,
1057
1277
.ops = &clk_fixed_factor_ops,
1058
1278
.flags = CLK_SET_RATE_PARENT,
···
1069
1291
{ }
1070
1292
};
1071
1293
1294
+
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
1295
+
{ .fw_name = "xo", .name = "xo" },
1296
+
{ .hw = &gpll0.clkr.hw },
1297
+
{ .hw = &gpll6.clkr.hw },
1298
+
{ .hw = &gpll0_out_main_div2.hw },
1299
+
};
1300
+
1301
+
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
1302
+
{ P_XO, 0 },
1303
+
{ P_GPLL0, 1 },
1304
+
{ P_GPLL6, 2 },
1305
+
{ P_GPLL0_DIV2, 3 },
1306
+
};
1307
+
1072
1308
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1073
1309
.cmd_rcgr = 0x26004,
1074
1310
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
···
1090
1298
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1091
1299
.clkr.hw.init = &(struct clk_init_data){
1092
1300
.name = "system_noc_bfdcd_clk_src",
1093
-
.parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1094
-
.num_parents = 4,
1301
+
.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1302
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
1095
1303
.ops = &clk_rcg2_ops,
1096
1304
.flags = CLK_IS_CRITICAL,
1097
1305
},
···
1102
1310
.div = 1,
1103
1311
.hw.init = &(struct clk_init_data){
1104
1312
.name = "system_noc_clk_src",
1105
-
.parent_names = (const char *[]){
1106
-
"system_noc_bfdcd_clk_src"
1107
-
},
1313
+
.parent_hws = (const struct clk_hw *[]){
1314
+
&system_noc_bfdcd_clk_src.clkr.hw },
1108
1315
.num_parents = 1,
1109
1316
.ops = &clk_fixed_factor_ops,
1110
1317
.flags = CLK_SET_RATE_PARENT,
···
1124
1333
.clkr.hw.init = &(struct clk_init_data){
1125
1334
.name = "nss_ce_clk_src",
1126
1335
.parent_data = gcc_xo_gpll0,
1127
-
.num_parents = 2,
1336
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1128
1337
.ops = &clk_rcg2_ops,
1129
1338
},
1130
1339
};
···
1135
1344
{ }
1136
1345
};
1137
1346
1347
+
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
1348
+
{ .fw_name = "xo", .name = "xo" },
1349
+
{ .name = "bias_pll_nss_noc_clk" },
1350
+
{ .hw = &gpll0.clkr.hw },
1351
+
{ .hw = &gpll2.clkr.hw },
1352
+
};
1353
+
1354
+
static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
1355
+
{ P_XO, 0 },
1356
+
{ P_BIAS_PLL_NSS_NOC, 1 },
1357
+
{ P_GPLL0, 2 },
1358
+
{ P_GPLL2, 3 },
1359
+
};
1360
+
1138
1361
static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1139
1362
.cmd_rcgr = 0x68088,
1140
1363
.freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
···
1156
1351
.parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1157
1352
.clkr.hw.init = &(struct clk_init_data){
1158
1353
.name = "nss_noc_bfdcd_clk_src",
1159
-
.parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1160
-
.num_parents = 4,
1354
+
.parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1355
+
.num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
1161
1356
.ops = &clk_rcg2_ops,
1162
1357
},
1163
1358
};
···
1167
1362
.div = 1,
1168
1363
.hw.init = &(struct clk_init_data){
1169
1364
.name = "nss_noc_clk_src",
1170
-
.parent_names = (const char *[]){
1171
-
"nss_noc_bfdcd_clk_src"
1172
-
},
1365
+
.parent_hws = (const struct clk_hw *[]){
1366
+
&nss_noc_bfdcd_clk_src.clkr.hw },
1173
1367
.num_parents = 1,
1174
1368
.ops = &clk_fixed_factor_ops,
1175
1369
.flags = CLK_SET_RATE_PARENT,
···
1181
1377
{ }
1182
1378
};
1183
1379
1380
+
static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
1381
+
{ .fw_name = "xo", .name = "xo" },
1382
+
{ .hw = &nss_crypto_pll.clkr.hw },
1383
+
{ .hw = &gpll0.clkr.hw },
1384
+
};
1385
+
1386
+
static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
1387
+
{ P_XO, 0 },
1388
+
{ P_NSS_CRYPTO_PLL, 1 },
1389
+
{ P_GPLL0, 2 },
1390
+
};
1391
+
1184
1392
static struct clk_rcg2 nss_crypto_clk_src = {
1185
1393
.cmd_rcgr = 0x68144,
1186
1394
.freq_tbl = ftbl_nss_crypto_clk_src,
···
1201
1385
.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1202
1386
.clkr.hw.init = &(struct clk_init_data){
1203
1387
.name = "nss_crypto_clk_src",
1204
-
.parent_names = gcc_xo_nss_crypto_pll_gpll0,
1205
-
.num_parents = 3,
1388
+
.parent_data = gcc_xo_nss_crypto_pll_gpll0,
1389
+
.num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
1206
1390
.ops = &clk_rcg2_ops,
1207
1391
},
1208
1392
};
···
1216
1400
{ }
1217
1401
};
1218
1402
1403
+
static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1404
+
{ .fw_name = "xo", .name = "xo" },
1405
+
{ .hw = &ubi32_pll.clkr.hw },
1406
+
{ .hw = &gpll0.clkr.hw },
1407
+
{ .hw = &gpll2.clkr.hw },
1408
+
{ .hw = &gpll4.clkr.hw },
1409
+
{ .hw = &gpll6.clkr.hw },
1410
+
};
1411
+
1412
+
static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1413
+
{ P_XO, 0 },
1414
+
{ P_UBI32_PLL, 1 },
1415
+
{ P_GPLL0, 2 },
1416
+
{ P_GPLL2, 3 },
1417
+
{ P_GPLL4, 4 },
1418
+
{ P_GPLL6, 5 },
1419
+
};
1420
+
1219
1421
static struct clk_rcg2 nss_ubi0_clk_src = {
1220
1422
.cmd_rcgr = 0x68104,
1221
1423
.freq_tbl = ftbl_nss_ubi_clk_src,
···
1241
1407
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1242
1408
.clkr.hw.init = &(struct clk_init_data){
1243
1409
.name = "nss_ubi0_clk_src",
1244
-
.parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1245
-
.num_parents = 6,
1410
+
.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1411
+
.num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1246
1412
.ops = &clk_rcg2_ops,
1247
1413
.flags = CLK_SET_RATE_PARENT,
1248
1414
},
···
1255
1421
.clkr = {
1256
1422
.hw.init = &(struct clk_init_data){
1257
1423
.name = "nss_ubi0_div_clk_src",
1258
-
.parent_names = (const char *[]){
1259
-
"nss_ubi0_clk_src"
1260
-
},
1424
+
.parent_hws = (const struct clk_hw *[]){
1425
+
&nss_ubi0_clk_src.clkr.hw },
1261
1426
.num_parents = 1,
1262
1427
.ops = &clk_regmap_div_ro_ops,
1263
1428
.flags = CLK_SET_RATE_PARENT,
···
1271
1438
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1272
1439
.clkr.hw.init = &(struct clk_init_data){
1273
1440
.name = "nss_ubi1_clk_src",
1274
-
.parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1275
-
.num_parents = 6,
1441
+
.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1442
+
.num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
1276
1443
.ops = &clk_rcg2_ops,
1277
1444
.flags = CLK_SET_RATE_PARENT,
1278
1445
},
···
1285
1452
.clkr = {
1286
1453
.hw.init = &(struct clk_init_data){
1287
1454
.name = "nss_ubi1_div_clk_src",
1288
-
.parent_names = (const char *[]){
1289
-
"nss_ubi1_clk_src"
1290
-
},
1455
+
.parent_hws = (const struct clk_hw *[]){
1456
+
&nss_ubi1_clk_src.clkr.hw },
1291
1457
.num_parents = 1,
1292
1458
.ops = &clk_regmap_div_ro_ops,
1293
1459
.flags = CLK_SET_RATE_PARENT,
···
1300
1468
{ }
1301
1469
};
1302
1470
1471
+
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
1472
+
{ .fw_name = "xo", .name = "xo" },
1473
+
{ .hw = &gpll0_out_main_div2.hw },
1474
+
};
1475
+
1476
+
static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
1477
+
{ P_XO, 0 },
1478
+
{ P_GPLL0_DIV2, 1 },
1479
+
};
1480
+
1303
1481
static struct clk_rcg2 ubi_mpt_clk_src = {
1304
1482
.cmd_rcgr = 0x68090,
1305
1483
.freq_tbl = ftbl_ubi_mpt_clk_src,
···
1317
1475
.parent_map = gcc_xo_gpll0_out_main_div2_map,
1318
1476
.clkr.hw.init = &(struct clk_init_data){
1319
1477
.name = "ubi_mpt_clk_src",
1320
-
.parent_names = gcc_xo_gpll0_out_main_div2,
1321
-
.num_parents = 2,
1478
+
.parent_data = gcc_xo_gpll0_out_main_div2,
1479
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
1322
1480
.ops = &clk_rcg2_ops,
1323
1481
},
1324
1482
};
···
1329
1487
{ }
1330
1488
};
1331
1489
1490
+
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
1491
+
{ .fw_name = "xo", .name = "xo" },
1492
+
{ .hw = &gpll0.clkr.hw },
1493
+
{ .hw = &gpll4.clkr.hw },
1494
+
};
1495
+
1496
+
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
1497
+
{ P_XO, 0 },
1498
+
{ P_GPLL0, 1 },
1499
+
{ P_GPLL4, 2 },
1500
+
};
1501
+
1332
1502
static struct clk_rcg2 nss_imem_clk_src = {
1333
1503
.cmd_rcgr = 0x68158,
1334
1504
.freq_tbl = ftbl_nss_imem_clk_src,
···
1348
1494
.parent_map = gcc_xo_gpll0_gpll4_map,
1349
1495
.clkr.hw.init = &(struct clk_init_data){
1350
1496
.name = "nss_imem_clk_src",
1351
-
.parent_names = gcc_xo_gpll0_gpll4,
1352
-
.num_parents = 3,
1497
+
.parent_data = gcc_xo_gpll0_gpll4,
1498
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1353
1499
.ops = &clk_rcg2_ops,
1354
1500
},
1355
1501
};
···
1360
1506
{ }
1361
1507
};
1362
1508
1509
+
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
1510
+
{ .fw_name = "xo", .name = "xo" },
1511
+
{ .name = "bias_pll_cc_clk" },
1512
+
{ .hw = &gpll0.clkr.hw },
1513
+
{ .hw = &gpll4.clkr.hw },
1514
+
{ .hw = &nss_crypto_pll.clkr.hw },
1515
+
{ .hw = &ubi32_pll.clkr.hw },
1516
+
};
1517
+
1518
+
static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
1519
+
{ P_XO, 0 },
1520
+
{ P_BIAS_PLL, 1 },
1521
+
{ P_GPLL0, 2 },
1522
+
{ P_GPLL4, 3 },
1523
+
{ P_NSS_CRYPTO_PLL, 4 },
1524
+
{ P_UBI32_PLL, 5 },
1525
+
};
1526
+
1363
1527
static struct clk_rcg2 nss_ppe_clk_src = {
1364
1528
.cmd_rcgr = 0x68080,
1365
1529
.freq_tbl = ftbl_nss_ppe_clk_src,
···
1385
1513
.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1386
1514
.clkr.hw.init = &(struct clk_init_data){
1387
1515
.name = "nss_ppe_clk_src",
1388
-
.parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1389
-
.num_parents = 6,
1516
+
.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1517
+
.num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
1390
1518
.ops = &clk_rcg2_ops,
1391
1519
},
1392
1520
};
···
1396
1524
.div = 4,
1397
1525
.hw.init = &(struct clk_init_data){
1398
1526
.name = "nss_ppe_cdiv_clk_src",
1399
-
.parent_names = (const char *[]){
1400
-
"nss_ppe_clk_src"
1401
-
},
1527
+
.parent_hws = (const struct clk_hw *[]){
1528
+
&nss_ppe_clk_src.clkr.hw },
1402
1529
.num_parents = 1,
1403
1530
.ops = &clk_fixed_factor_ops,
1404
1531
.flags = CLK_SET_RATE_PARENT,
···
1411
1540
{ }
1412
1541
};
1413
1542
1543
+
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
1544
+
{ .fw_name = "xo", .name = "xo" },
1545
+
{ .name = "uniphy0_gcc_rx_clk" },
1546
+
{ .name = "uniphy0_gcc_tx_clk" },
1547
+
{ .hw = &ubi32_pll.clkr.hw },
1548
+
{ .name = "bias_pll_cc_clk" },
1549
+
};
1550
+
1551
+
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
1552
+
{ P_XO, 0 },
1553
+
{ P_UNIPHY0_RX, 1 },
1554
+
{ P_UNIPHY0_TX, 2 },
1555
+
{ P_UBI32_PLL, 5 },
1556
+
{ P_BIAS_PLL, 6 },
1557
+
};
1558
+
1414
1559
static struct clk_rcg2 nss_port1_rx_clk_src = {
1415
1560
.cmd_rcgr = 0x68020,
1416
1561
.freq_tbl = ftbl_nss_port1_rx_clk_src,
···
1434
1547
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1435
1548
.clkr.hw.init = &(struct clk_init_data){
1436
1549
.name = "nss_port1_rx_clk_src",
1437
-
.parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1438
-
.num_parents = 5,
1550
+
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1551
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1439
1552
.ops = &clk_rcg2_ops,
1440
1553
},
1441
1554
};
···
1447
1560
.clkr = {
1448
1561
.hw.init = &(struct clk_init_data){
1449
1562
.name = "nss_port1_rx_div_clk_src",
1450
-
.parent_names = (const char *[]){
1451
-
"nss_port1_rx_clk_src"
1452
-
},
1563
+
.parent_hws = (const struct clk_hw *[]){
1564
+
&nss_port1_rx_clk_src.clkr.hw },
1453
1565
.num_parents = 1,
1454
1566
.ops = &clk_regmap_div_ops,
1455
1567
.flags = CLK_SET_RATE_PARENT,
···
1463
1577
{ }
1464
1578
};
1465
1579
1580
+
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
1581
+
{ .fw_name = "xo", .name = "xo" },
1582
+
{ .name = "uniphy0_gcc_tx_clk" },
1583
+
{ .name = "uniphy0_gcc_rx_clk" },
1584
+
{ .hw = &ubi32_pll.clkr.hw },
1585
+
{ .name = "bias_pll_cc_clk" },
1586
+
};
1587
+
1588
+
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
1589
+
{ P_XO, 0 },
1590
+
{ P_UNIPHY0_TX, 1 },
1591
+
{ P_UNIPHY0_RX, 2 },
1592
+
{ P_UBI32_PLL, 5 },
1593
+
{ P_BIAS_PLL, 6 },
1594
+
};
1595
+
1466
1596
static struct clk_rcg2 nss_port1_tx_clk_src = {
1467
1597
.cmd_rcgr = 0x68028,
1468
1598
.freq_tbl = ftbl_nss_port1_tx_clk_src,
···
1486
1584
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1487
1585
.clkr.hw.init = &(struct clk_init_data){
1488
1586
.name = "nss_port1_tx_clk_src",
1489
-
.parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1490
-
.num_parents = 5,
1587
+
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1588
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1491
1589
.ops = &clk_rcg2_ops,
1492
1590
},
1493
1591
};
···
1499
1597
.clkr = {
1500
1598
.hw.init = &(struct clk_init_data){
1501
1599
.name = "nss_port1_tx_div_clk_src",
1502
-
.parent_names = (const char *[]){
1503
-
"nss_port1_tx_clk_src"
1504
-
},
1600
+
.parent_hws = (const struct clk_hw *[]){
1601
+
&nss_port1_tx_clk_src.clkr.hw },
1505
1602
.num_parents = 1,
1506
1603
.ops = &clk_regmap_div_ops,
1507
1604
.flags = CLK_SET_RATE_PARENT,
···
1515
1614
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1516
1615
.clkr.hw.init = &(struct clk_init_data){
1517
1616
.name = "nss_port2_rx_clk_src",
1518
-
.parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1519
-
.num_parents = 5,
1617
+
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1618
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1520
1619
.ops = &clk_rcg2_ops,
1521
1620
},
1522
1621
};
···
1528
1627
.clkr = {
1529
1628
.hw.init = &(struct clk_init_data){
1530
1629
.name = "nss_port2_rx_div_clk_src",
1531
-
.parent_names = (const char *[]){
1532
-
"nss_port2_rx_clk_src"
1533
-
},
1630
+
.parent_hws = (const struct clk_hw *[]){
1631
+
&nss_port2_rx_clk_src.clkr.hw },
1534
1632
.num_parents = 1,
1535
1633
.ops = &clk_regmap_div_ops,
1536
1634
.flags = CLK_SET_RATE_PARENT,
···
1544
1644
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1545
1645
.clkr.hw.init = &(struct clk_init_data){
1546
1646
.name = "nss_port2_tx_clk_src",
1547
-
.parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1548
-
.num_parents = 5,
1647
+
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1648
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1549
1649
.ops = &clk_rcg2_ops,
1550
1650
},
1551
1651
};
···
1557
1657
.clkr = {
1558
1658
.hw.init = &(struct clk_init_data){
1559
1659
.name = "nss_port2_tx_div_clk_src",
1560
-
.parent_names = (const char *[]){
1561
-
"nss_port2_tx_clk_src"
1562
-
},
1660
+
.parent_hws = (const struct clk_hw *[]){
1661
+
&nss_port2_tx_clk_src.clkr.hw },
1563
1662
.num_parents = 1,
1564
1663
.ops = &clk_regmap_div_ops,
1565
1664
.flags = CLK_SET_RATE_PARENT,
···
1573
1674
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1574
1675
.clkr.hw.init = &(struct clk_init_data){
1575
1676
.name = "nss_port3_rx_clk_src",
1576
-
.parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1577
-
.num_parents = 5,
1677
+
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1678
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1578
1679
.ops = &clk_rcg2_ops,
1579
1680
},
1580
1681
};
···
1586
1687
.clkr = {
1587
1688
.hw.init = &(struct clk_init_data){
1588
1689
.name = "nss_port3_rx_div_clk_src",
1589
-
.parent_names = (const char *[]){
1590
-
"nss_port3_rx_clk_src"
1591
-
},
1690
+
.parent_hws = (const struct clk_hw *[]){
1691
+
&nss_port3_rx_clk_src.clkr.hw },
1592
1692
.num_parents = 1,
1593
1693
.ops = &clk_regmap_div_ops,
1594
1694
.flags = CLK_SET_RATE_PARENT,
···
1602
1704
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1603
1705
.clkr.hw.init = &(struct clk_init_data){
1604
1706
.name = "nss_port3_tx_clk_src",
1605
-
.parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1606
-
.num_parents = 5,
1707
+
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1708
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1607
1709
.ops = &clk_rcg2_ops,
1608
1710
},
1609
1711
};
···
1615
1717
.clkr = {
1616
1718
.hw.init = &(struct clk_init_data){
1617
1719
.name = "nss_port3_tx_div_clk_src",
1618
-
.parent_names = (const char *[]){
1619
-
"nss_port3_tx_clk_src"
1620
-
},
1720
+
.parent_hws = (const struct clk_hw *[]){
1721
+
&nss_port3_tx_clk_src.clkr.hw },
1621
1722
.num_parents = 1,
1622
1723
.ops = &clk_regmap_div_ops,
1623
1724
.flags = CLK_SET_RATE_PARENT,
···
1631
1734
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1632
1735
.clkr.hw.init = &(struct clk_init_data){
1633
1736
.name = "nss_port4_rx_clk_src",
1634
-
.parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1635
-
.num_parents = 5,
1737
+
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1738
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
1636
1739
.ops = &clk_rcg2_ops,
1637
1740
},
1638
1741
};
···
1644
1747
.clkr = {
1645
1748
.hw.init = &(struct clk_init_data){
1646
1749
.name = "nss_port4_rx_div_clk_src",
1647
-
.parent_names = (const char *[]){
1648
-
"nss_port4_rx_clk_src"
1649
-
},
1750
+
.parent_hws = (const struct clk_hw *[]){
1751
+
&nss_port4_rx_clk_src.clkr.hw },
1650
1752
.num_parents = 1,
1651
1753
.ops = &clk_regmap_div_ops,
1652
1754
.flags = CLK_SET_RATE_PARENT,
···
1660
1764
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1661
1765
.clkr.hw.init = &(struct clk_init_data){
1662
1766
.name = "nss_port4_tx_clk_src",
1663
-
.parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1664
-
.num_parents = 5,
1767
+
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1768
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
1665
1769
.ops = &clk_rcg2_ops,
1666
1770
},
1667
1771
};
···
1673
1777
.clkr = {
1674
1778
.hw.init = &(struct clk_init_data){
1675
1779
.name = "nss_port4_tx_div_clk_src",
1676
-
.parent_names = (const char *[]){
1677
-
"nss_port4_tx_clk_src"
1678
-
},
1780
+
.parent_hws = (const struct clk_hw *[]){
1781
+
&nss_port4_tx_clk_src.clkr.hw },
1679
1782
.num_parents = 1,
1680
1783
.ops = &clk_regmap_div_ops,
1681
1784
.flags = CLK_SET_RATE_PARENT,
···
1694
1799
{ }
1695
1800
};
1696
1801
1802
+
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
1803
+
{ .fw_name = "xo", .name = "xo" },
1804
+
{ .name = "uniphy0_gcc_rx_clk" },
1805
+
{ .name = "uniphy0_gcc_tx_clk" },
1806
+
{ .name = "uniphy1_gcc_rx_clk" },
1807
+
{ .name = "uniphy1_gcc_tx_clk" },
1808
+
{ .hw = &ubi32_pll.clkr.hw },
1809
+
{ .name = "bias_pll_cc_clk" },
1810
+
};
1811
+
1812
+
static const struct parent_map
1813
+
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
1814
+
{ P_XO, 0 },
1815
+
{ P_UNIPHY0_RX, 1 },
1816
+
{ P_UNIPHY0_TX, 2 },
1817
+
{ P_UNIPHY1_RX, 3 },
1818
+
{ P_UNIPHY1_TX, 4 },
1819
+
{ P_UBI32_PLL, 5 },
1820
+
{ P_BIAS_PLL, 6 },
1821
+
};
1822
+
1697
1823
static struct clk_rcg2 nss_port5_rx_clk_src = {
1698
1824
.cmd_rcgr = 0x68060,
1699
1825
.freq_tbl = ftbl_nss_port5_rx_clk_src,
···
1722
1806
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1723
1807
.clkr.hw.init = &(struct clk_init_data){
1724
1808
.name = "nss_port5_rx_clk_src",
1725
-
.parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1726
-
.num_parents = 7,
1809
+
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1810
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1727
1811
.ops = &clk_rcg2_ops,
1728
1812
},
1729
1813
};
···
1735
1819
.clkr = {
1736
1820
.hw.init = &(struct clk_init_data){
1737
1821
.name = "nss_port5_rx_div_clk_src",
1738
-
.parent_names = (const char *[]){
1739
-
"nss_port5_rx_clk_src"
1740
-
},
1822
+
.parent_hws = (const struct clk_hw *[]){
1823
+
&nss_port5_rx_clk_src.clkr.hw },
1741
1824
.num_parents = 1,
1742
1825
.ops = &clk_regmap_div_ops,
1743
1826
.flags = CLK_SET_RATE_PARENT,
···
1756
1841
{ }
1757
1842
};
1758
1843
1844
+
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
1845
+
{ .fw_name = "xo", .name = "xo" },
1846
+
{ .name = "uniphy0_gcc_tx_clk" },
1847
+
{ .name = "uniphy0_gcc_rx_clk" },
1848
+
{ .name = "uniphy1_gcc_tx_clk" },
1849
+
{ .name = "uniphy1_gcc_rx_clk" },
1850
+
{ .hw = &ubi32_pll.clkr.hw },
1851
+
{ .name = "bias_pll_cc_clk" },
1852
+
};
1853
+
1854
+
static const struct parent_map
1855
+
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
1856
+
{ P_XO, 0 },
1857
+
{ P_UNIPHY0_TX, 1 },
1858
+
{ P_UNIPHY0_RX, 2 },
1859
+
{ P_UNIPHY1_TX, 3 },
1860
+
{ P_UNIPHY1_RX, 4 },
1861
+
{ P_UBI32_PLL, 5 },
1862
+
{ P_BIAS_PLL, 6 },
1863
+
};
1864
+
1759
1865
static struct clk_rcg2 nss_port5_tx_clk_src = {
1760
1866
.cmd_rcgr = 0x68068,
1761
1867
.freq_tbl = ftbl_nss_port5_tx_clk_src,
···
1784
1848
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1785
1849
.clkr.hw.init = &(struct clk_init_data){
1786
1850
.name = "nss_port5_tx_clk_src",
1787
-
.parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1788
-
.num_parents = 7,
1851
+
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1852
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1789
1853
.ops = &clk_rcg2_ops,
1790
1854
},
1791
1855
};
···
1797
1861
.clkr = {
1798
1862
.hw.init = &(struct clk_init_data){
1799
1863
.name = "nss_port5_tx_div_clk_src",
1800
-
.parent_names = (const char *[]){
1801
-
"nss_port5_tx_clk_src"
1802
-
},
1864
+
.parent_hws = (const struct clk_hw *[]){
1865
+
&nss_port5_tx_clk_src.clkr.hw },
1803
1866
.num_parents = 1,
1804
1867
.ops = &clk_regmap_div_ops,
1805
1868
.flags = CLK_SET_RATE_PARENT,
···
1818
1883
{ }
1819
1884
};
1820
1885
1886
+
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
1887
+
{ .fw_name = "xo", .name = "xo" },
1888
+
{ .name = "uniphy2_gcc_rx_clk" },
1889
+
{ .name = "uniphy2_gcc_tx_clk" },
1890
+
{ .hw = &ubi32_pll.clkr.hw },
1891
+
{ .name = "bias_pll_cc_clk" },
1892
+
};
1893
+
1894
+
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
1895
+
{ P_XO, 0 },
1896
+
{ P_UNIPHY2_RX, 1 },
1897
+
{ P_UNIPHY2_TX, 2 },
1898
+
{ P_UBI32_PLL, 5 },
1899
+
{ P_BIAS_PLL, 6 },
1900
+
};
1901
+
1821
1902
static struct clk_rcg2 nss_port6_rx_clk_src = {
1822
1903
.cmd_rcgr = 0x68070,
1823
1904
.freq_tbl = ftbl_nss_port6_rx_clk_src,
···
1841
1890
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1842
1891
.clkr.hw.init = &(struct clk_init_data){
1843
1892
.name = "nss_port6_rx_clk_src",
1844
-
.parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1845
-
.num_parents = 5,
1893
+
.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1894
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1846
1895
.ops = &clk_rcg2_ops,
1847
1896
},
1848
1897
};
···
1854
1903
.clkr = {
1855
1904
.hw.init = &(struct clk_init_data){
1856
1905
.name = "nss_port6_rx_div_clk_src",
1857
-
.parent_names = (const char *[]){
1858
-
"nss_port6_rx_clk_src"
1859
-
},
1906
+
.parent_hws = (const struct clk_hw *[]){
1907
+
&nss_port6_rx_clk_src.clkr.hw },
1860
1908
.num_parents = 1,
1861
1909
.ops = &clk_regmap_div_ops,
1862
1910
.flags = CLK_SET_RATE_PARENT,
···
1875
1925
{ }
1876
1926
};
1877
1927
1928
+
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
1929
+
{ .fw_name = "xo", .name = "xo" },
1930
+
{ .name = "uniphy2_gcc_tx_clk" },
1931
+
{ .name = "uniphy2_gcc_rx_clk" },
1932
+
{ .hw = &ubi32_pll.clkr.hw },
1933
+
{ .name = "bias_pll_cc_clk" },
1934
+
};
1935
+
1936
+
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
1937
+
{ P_XO, 0 },
1938
+
{ P_UNIPHY2_TX, 1 },
1939
+
{ P_UNIPHY2_RX, 2 },
1940
+
{ P_UBI32_PLL, 5 },
1941
+
{ P_BIAS_PLL, 6 },
1942
+
};
1943
+
1878
1944
static struct clk_rcg2 nss_port6_tx_clk_src = {
1879
1945
.cmd_rcgr = 0x68078,
1880
1946
.freq_tbl = ftbl_nss_port6_tx_clk_src,
···
1898
1932
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1899
1933
.clkr.hw.init = &(struct clk_init_data){
1900
1934
.name = "nss_port6_tx_clk_src",
1901
-
.parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1902
-
.num_parents = 5,
1935
+
.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1936
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1903
1937
.ops = &clk_rcg2_ops,
1904
1938
},
1905
1939
};
···
1911
1945
.clkr = {
1912
1946
.hw.init = &(struct clk_init_data){
1913
1947
.name = "nss_port6_tx_div_clk_src",
1914
-
.parent_names = (const char *[]){
1915
-
"nss_port6_tx_clk_src"
1916
-
},
1948
+
.parent_hws = (const struct clk_hw *[]){
1949
+
&nss_port6_tx_clk_src.clkr.hw },
1917
1950
.num_parents = 1,
1918
1951
.ops = &clk_regmap_div_ops,
1919
1952
.flags = CLK_SET_RATE_PARENT,
···
1935
1970
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1936
1971
.clkr.hw.init = &(struct clk_init_data){
1937
1972
.name = "crypto_clk_src",
1938
-
.parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1939
-
.num_parents = 3,
1973
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1974
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1940
1975
.ops = &clk_rcg2_ops,
1941
1976
},
1942
1977
};
···
1944
1979
static struct freq_tbl ftbl_gp_clk_src[] = {
1945
1980
F(19200000, P_XO, 1, 0, 0),
1946
1981
{ }
1982
+
};
1983
+
1984
+
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1985
+
{ .fw_name = "xo", .name = "xo" },
1986
+
{ .hw = &gpll0.clkr.hw },
1987
+
{ .hw = &gpll6.clkr.hw },
1988
+
{ .hw = &gpll0_out_main_div2.hw },
1989
+
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
1990
+
};
1991
+
1992
+
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1993
+
{ P_XO, 0 },
1994
+
{ P_GPLL0, 1 },
1995
+
{ P_GPLL6, 2 },
1996
+
{ P_GPLL0_DIV2, 4 },
1997
+
{ P_SLEEP_CLK, 6 },
1947
1998
};
1948
1999
1949
2000
static struct clk_rcg2 gp1_clk_src = {
···
1970
1989
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1971
1990
.clkr.hw.init = &(struct clk_init_data){
1972
1991
.name = "gp1_clk_src",
1973
-
.parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1974
-
.num_parents = 5,
1992
+
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1993
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1975
1994
.ops = &clk_rcg2_ops,
1976
1995
},
1977
1996
};
···
1984
2003
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1985
2004
.clkr.hw.init = &(struct clk_init_data){
1986
2005
.name = "gp2_clk_src",
1987
-
.parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1988
-
.num_parents = 5,
2006
+
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2007
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
1989
2008
.ops = &clk_rcg2_ops,
1990
2009
},
1991
2010
};
···
1998
2017
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1999
2018
.clkr.hw.init = &(struct clk_init_data){
2000
2019
.name = "gp3_clk_src",
2001
-
.parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2002
-
.num_parents = 5,
2020
+
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2021
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
2003
2022
.ops = &clk_rcg2_ops,
2004
2023
},
2005
2024
};
···
2011
2030
.enable_mask = BIT(0),
2012
2031
.hw.init = &(struct clk_init_data){
2013
2032
.name = "gcc_blsp1_ahb_clk",
2014
-
.parent_names = (const char *[]){
2015
-
"pcnoc_clk_src"
2016
-
},
2033
+
.parent_hws = (const struct clk_hw *[]){
2034
+
&pcnoc_clk_src.hw },
2017
2035
.num_parents = 1,
2018
2036
.flags = CLK_SET_RATE_PARENT,
2019
2037
.ops = &clk_branch2_ops,
···
2027
2047
.enable_mask = BIT(0),
2028
2048
.hw.init = &(struct clk_init_data){
2029
2049
.name = "gcc_blsp1_qup1_i2c_apps_clk",
2030
-
.parent_names = (const char *[]){
2031
-
"blsp1_qup1_i2c_apps_clk_src"
2032
-
},
2050
+
.parent_hws = (const struct clk_hw *[]){
2051
+
&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
2033
2052
.num_parents = 1,
2034
2053
.flags = CLK_SET_RATE_PARENT,
2035
2054
.ops = &clk_branch2_ops,
···
2043
2064
.enable_mask = BIT(0),
2044
2065
.hw.init = &(struct clk_init_data){
2045
2066
.name = "gcc_blsp1_qup1_spi_apps_clk",
2046
-
.parent_names = (const char *[]){
2047
-
"blsp1_qup1_spi_apps_clk_src"
2048
-
},
2067
+
.parent_hws = (const struct clk_hw *[]){
2068
+
&blsp1_qup1_spi_apps_clk_src.clkr.hw },
2049
2069
.num_parents = 1,
2050
2070
.flags = CLK_SET_RATE_PARENT,
2051
2071
.ops = &clk_branch2_ops,
···
2059
2081
.enable_mask = BIT(0),
2060
2082
.hw.init = &(struct clk_init_data){
2061
2083
.name = "gcc_blsp1_qup2_i2c_apps_clk",
2062
-
.parent_names = (const char *[]){
2063
-
"blsp1_qup2_i2c_apps_clk_src"
2064
-
},
2084
+
.parent_hws = (const struct clk_hw *[]){
2085
+
&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2065
2086
.num_parents = 1,
2066
2087
.flags = CLK_SET_RATE_PARENT,
2067
2088
.ops = &clk_branch2_ops,
···
2075
2098
.enable_mask = BIT(0),
2076
2099
.hw.init = &(struct clk_init_data){
2077
2100
.name = "gcc_blsp1_qup2_spi_apps_clk",
2078
-
.parent_names = (const char *[]){
2079
-
"blsp1_qup2_spi_apps_clk_src"
2080
-
},
2101
+
.parent_hws = (const struct clk_hw *[]){
2102
+
&blsp1_qup2_spi_apps_clk_src.clkr.hw },
2081
2103
.num_parents = 1,
2082
2104
.flags = CLK_SET_RATE_PARENT,
2083
2105
.ops = &clk_branch2_ops,
···
2091
2115
.enable_mask = BIT(0),
2092
2116
.hw.init = &(struct clk_init_data){
2093
2117
.name = "gcc_blsp1_qup3_i2c_apps_clk",
2094
-
.parent_names = (const char *[]){
2095
-
"blsp1_qup3_i2c_apps_clk_src"
2096
-
},
2118
+
.parent_hws = (const struct clk_hw *[]){
2119
+
&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2097
2120
.num_parents = 1,
2098
2121
.flags = CLK_SET_RATE_PARENT,
2099
2122
.ops = &clk_branch2_ops,
···
2107
2132
.enable_mask = BIT(0),
2108
2133
.hw.init = &(struct clk_init_data){
2109
2134
.name = "gcc_blsp1_qup3_spi_apps_clk",
2110
-
.parent_names = (const char *[]){
2111
-
"blsp1_qup3_spi_apps_clk_src"
2112
-
},
2135
+
.parent_hws = (const struct clk_hw *[]){
2136
+
&blsp1_qup3_spi_apps_clk_src.clkr.hw },
2113
2137
.num_parents = 1,
2114
2138
.flags = CLK_SET_RATE_PARENT,
2115
2139
.ops = &clk_branch2_ops,
···
2123
2149
.enable_mask = BIT(0),
2124
2150
.hw.init = &(struct clk_init_data){
2125
2151
.name = "gcc_blsp1_qup4_i2c_apps_clk",
2126
-
.parent_names = (const char *[]){
2127
-
"blsp1_qup4_i2c_apps_clk_src"
2128
-
},
2152
+
.parent_hws = (const struct clk_hw *[]){
2153
+
&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2129
2154
.num_parents = 1,
2130
2155
.flags = CLK_SET_RATE_PARENT,
2131
2156
.ops = &clk_branch2_ops,
···
2139
2166
.enable_mask = BIT(0),
2140
2167
.hw.init = &(struct clk_init_data){
2141
2168
.name = "gcc_blsp1_qup4_spi_apps_clk",
2142
-
.parent_names = (const char *[]){
2143
-
"blsp1_qup4_spi_apps_clk_src"
2144
-
},
2169
+
.parent_hws = (const struct clk_hw *[]){
2170
+
&blsp1_qup4_spi_apps_clk_src.clkr.hw },
2145
2171
.num_parents = 1,
2146
2172
.flags = CLK_SET_RATE_PARENT,
2147
2173
.ops = &clk_branch2_ops,
···
2155
2183
.enable_mask = BIT(0),
2156
2184
.hw.init = &(struct clk_init_data){
2157
2185
.name = "gcc_blsp1_qup5_i2c_apps_clk",
2158
-
.parent_names = (const char *[]){
2159
-
"blsp1_qup5_i2c_apps_clk_src"
2160
-
},
2186
+
.parent_hws = (const struct clk_hw *[]){
2187
+
&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2161
2188
.num_parents = 1,
2162
2189
.flags = CLK_SET_RATE_PARENT,
2163
2190
.ops = &clk_branch2_ops,
···
2171
2200
.enable_mask = BIT(0),
2172
2201
.hw.init = &(struct clk_init_data){
2173
2202
.name = "gcc_blsp1_qup5_spi_apps_clk",
2174
-
.parent_names = (const char *[]){
2175
-
"blsp1_qup5_spi_apps_clk_src"
2176
-
},
2203
+
.parent_hws = (const struct clk_hw *[]){
2204
+
&blsp1_qup5_spi_apps_clk_src.clkr.hw },
2177
2205
.num_parents = 1,
2178
2206
.flags = CLK_SET_RATE_PARENT,
2179
2207
.ops = &clk_branch2_ops,
···
2187
2217
.enable_mask = BIT(0),
2188
2218
.hw.init = &(struct clk_init_data){
2189
2219
.name = "gcc_blsp1_qup6_i2c_apps_clk",
2190
-
.parent_names = (const char *[]){
2191
-
"blsp1_qup6_i2c_apps_clk_src"
2192
-
},
2220
+
.parent_hws = (const struct clk_hw *[]){
2221
+
&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2193
2222
.num_parents = 1,
2194
2223
.flags = CLK_SET_RATE_PARENT,
2195
2224
.ops = &clk_branch2_ops,
···
2203
2234
.enable_mask = BIT(0),
2204
2235
.hw.init = &(struct clk_init_data){
2205
2236
.name = "gcc_blsp1_qup6_spi_apps_clk",
2206
-
.parent_names = (const char *[]){
2207
-
"blsp1_qup6_spi_apps_clk_src"
2208
-
},
2237
+
.parent_hws = (const struct clk_hw *[]){
2238
+
&blsp1_qup6_spi_apps_clk_src.clkr.hw },
2209
2239
.num_parents = 1,
2210
2240
.flags = CLK_SET_RATE_PARENT,
2211
2241
.ops = &clk_branch2_ops,
···
2219
2251
.enable_mask = BIT(0),
2220
2252
.hw.init = &(struct clk_init_data){
2221
2253
.name = "gcc_blsp1_uart1_apps_clk",
2222
-
.parent_names = (const char *[]){
2223
-
"blsp1_uart1_apps_clk_src"
2224
-
},
2254
+
.parent_hws = (const struct clk_hw *[]){
2255
+
&blsp1_uart1_apps_clk_src.clkr.hw },
2225
2256
.num_parents = 1,
2226
2257
.flags = CLK_SET_RATE_PARENT,
2227
2258
.ops = &clk_branch2_ops,
···
2235
2268
.enable_mask = BIT(0),
2236
2269
.hw.init = &(struct clk_init_data){
2237
2270
.name = "gcc_blsp1_uart2_apps_clk",
2238
-
.parent_names = (const char *[]){
2239
-
"blsp1_uart2_apps_clk_src"
2240
-
},
2271
+
.parent_hws = (const struct clk_hw *[]){
2272
+
&blsp1_uart2_apps_clk_src.clkr.hw },
2241
2273
.num_parents = 1,
2242
2274
.flags = CLK_SET_RATE_PARENT,
2243
2275
.ops = &clk_branch2_ops,
···
2251
2285
.enable_mask = BIT(0),
2252
2286
.hw.init = &(struct clk_init_data){
2253
2287
.name = "gcc_blsp1_uart3_apps_clk",
2254
-
.parent_names = (const char *[]){
2255
-
"blsp1_uart3_apps_clk_src"
2256
-
},
2288
+
.parent_hws = (const struct clk_hw *[]){
2289
+
&blsp1_uart3_apps_clk_src.clkr.hw },
2257
2290
.num_parents = 1,
2258
2291
.flags = CLK_SET_RATE_PARENT,
2259
2292
.ops = &clk_branch2_ops,
···
2267
2302
.enable_mask = BIT(0),
2268
2303
.hw.init = &(struct clk_init_data){
2269
2304
.name = "gcc_blsp1_uart4_apps_clk",
2270
-
.parent_names = (const char *[]){
2271
-
"blsp1_uart4_apps_clk_src"
2272
-
},
2305
+
.parent_hws = (const struct clk_hw *[]){
2306
+
&blsp1_uart4_apps_clk_src.clkr.hw },
2273
2307
.num_parents = 1,
2274
2308
.flags = CLK_SET_RATE_PARENT,
2275
2309
.ops = &clk_branch2_ops,
···
2283
2319
.enable_mask = BIT(0),
2284
2320
.hw.init = &(struct clk_init_data){
2285
2321
.name = "gcc_blsp1_uart5_apps_clk",
2286
-
.parent_names = (const char *[]){
2287
-
"blsp1_uart5_apps_clk_src"
2288
-
},
2322
+
.parent_hws = (const struct clk_hw *[]){
2323
+
&blsp1_uart5_apps_clk_src.clkr.hw },
2289
2324
.num_parents = 1,
2290
2325
.flags = CLK_SET_RATE_PARENT,
2291
2326
.ops = &clk_branch2_ops,
···
2299
2336
.enable_mask = BIT(0),
2300
2337
.hw.init = &(struct clk_init_data){
2301
2338
.name = "gcc_blsp1_uart6_apps_clk",
2302
-
.parent_names = (const char *[]){
2303
-
"blsp1_uart6_apps_clk_src"
2304
-
},
2339
+
.parent_hws = (const struct clk_hw *[]){
2340
+
&blsp1_uart6_apps_clk_src.clkr.hw },
2305
2341
.num_parents = 1,
2306
2342
.flags = CLK_SET_RATE_PARENT,
2307
2343
.ops = &clk_branch2_ops,
···
2316
2354
.enable_mask = BIT(8),
2317
2355
.hw.init = &(struct clk_init_data){
2318
2356
.name = "gcc_prng_ahb_clk",
2319
-
.parent_names = (const char *[]){
2320
-
"pcnoc_clk_src"
2321
-
},
2357
+
.parent_hws = (const struct clk_hw *[]){
2358
+
&pcnoc_clk_src.hw },
2322
2359
.num_parents = 1,
2323
2360
.flags = CLK_SET_RATE_PARENT,
2324
2361
.ops = &clk_branch2_ops,
···
2332
2371
.enable_mask = BIT(0),
2333
2372
.hw.init = &(struct clk_init_data){
2334
2373
.name = "gcc_qpic_ahb_clk",
2335
-
.parent_names = (const char *[]){
2336
-
"pcnoc_clk_src"
2337
-
},
2374
+
.parent_hws = (const struct clk_hw *[]){
2375
+
&pcnoc_clk_src.hw },
2338
2376
.num_parents = 1,
2339
2377
.flags = CLK_SET_RATE_PARENT,
2340
2378
.ops = &clk_branch2_ops,
···
2348
2388
.enable_mask = BIT(0),
2349
2389
.hw.init = &(struct clk_init_data){
2350
2390
.name = "gcc_qpic_clk",
2351
-
.parent_names = (const char *[]){
2352
-
"pcnoc_clk_src"
2353
-
},
2391
+
.parent_hws = (const struct clk_hw *[]){
2392
+
&pcnoc_clk_src.hw },
2354
2393
.num_parents = 1,
2355
2394
.flags = CLK_SET_RATE_PARENT,
2356
2395
.ops = &clk_branch2_ops,
···
2364
2405
.enable_mask = BIT(0),
2365
2406
.hw.init = &(struct clk_init_data){
2366
2407
.name = "gcc_pcie0_ahb_clk",
2367
-
.parent_names = (const char *[]){
2368
-
"pcnoc_clk_src"
2369
-
},
2408
+
.parent_hws = (const struct clk_hw *[]){
2409
+
&pcnoc_clk_src.hw },
2370
2410
.num_parents = 1,
2371
2411
.flags = CLK_SET_RATE_PARENT,
2372
2412
.ops = &clk_branch2_ops,
···
2380
2422
.enable_mask = BIT(0),
2381
2423
.hw.init = &(struct clk_init_data){
2382
2424
.name = "gcc_pcie0_aux_clk",
2383
-
.parent_names = (const char *[]){
2384
-
"pcie0_aux_clk_src"
2385
-
},
2425
+
.parent_hws = (const struct clk_hw *[]){
2426
+
&pcie0_aux_clk_src.clkr.hw },
2386
2427
.num_parents = 1,
2387
2428
.flags = CLK_SET_RATE_PARENT,
2388
2429
.ops = &clk_branch2_ops,
···
2396
2439
.enable_mask = BIT(0),
2397
2440
.hw.init = &(struct clk_init_data){
2398
2441
.name = "gcc_pcie0_axi_m_clk",
2399
-
.parent_names = (const char *[]){
2400
-
"pcie0_axi_clk_src"
2401
-
},
2442
+
.parent_hws = (const struct clk_hw *[]){
2443
+
&pcie0_axi_clk_src.clkr.hw },
2402
2444
.num_parents = 1,
2403
2445
.flags = CLK_SET_RATE_PARENT,
2404
2446
.ops = &clk_branch2_ops,
···
2412
2456
.enable_mask = BIT(0),
2413
2457
.hw.init = &(struct clk_init_data){
2414
2458
.name = "gcc_pcie0_axi_s_clk",
2415
-
.parent_names = (const char *[]){
2416
-
"pcie0_axi_clk_src"
2417
-
},
2459
+
.parent_hws = (const struct clk_hw *[]){
2460
+
&pcie0_axi_clk_src.clkr.hw },
2418
2461
.num_parents = 1,
2419
2462
.flags = CLK_SET_RATE_PARENT,
2420
2463
.ops = &clk_branch2_ops,
···
2429
2474
.enable_mask = BIT(0),
2430
2475
.hw.init = &(struct clk_init_data){
2431
2476
.name = "gcc_pcie0_pipe_clk",
2432
-
.parent_names = (const char *[]){
2433
-
"pcie0_pipe_clk_src"
2434
-
},
2477
+
.parent_hws = (const struct clk_hw *[]){
2478
+
&pcie0_pipe_clk_src.clkr.hw },
2435
2479
.num_parents = 1,
2436
2480
.flags = CLK_SET_RATE_PARENT,
2437
2481
.ops = &clk_branch2_ops,
···
2445
2491
.enable_mask = BIT(0),
2446
2492
.hw.init = &(struct clk_init_data){
2447
2493
.name = "gcc_sys_noc_pcie0_axi_clk",
2448
-
.parent_names = (const char *[]){
2449
-
"pcie0_axi_clk_src"
2450
-
},
2494
+
.parent_hws = (const struct clk_hw *[]){
2495
+
&pcie0_axi_clk_src.clkr.hw },
2451
2496
.num_parents = 1,
2452
2497
.flags = CLK_SET_RATE_PARENT,
2453
2498
.ops = &clk_branch2_ops,
···
2461
2508
.enable_mask = BIT(0),
2462
2509
.hw.init = &(struct clk_init_data){
2463
2510
.name = "gcc_pcie1_ahb_clk",
2464
-
.parent_names = (const char *[]){
2465
-
"pcnoc_clk_src"
2466
-
},
2511
+
.parent_hws = (const struct clk_hw *[]){
2512
+
&pcnoc_clk_src.hw },
2467
2513
.num_parents = 1,
2468
2514
.flags = CLK_SET_RATE_PARENT,
2469
2515
.ops = &clk_branch2_ops,
···
2477
2525
.enable_mask = BIT(0),
2478
2526
.hw.init = &(struct clk_init_data){
2479
2527
.name = "gcc_pcie1_aux_clk",
2480
-
.parent_names = (const char *[]){
2481
-
"pcie1_aux_clk_src"
2482
-
},
2528
+
.parent_hws = (const struct clk_hw *[]){
2529
+
&pcie1_aux_clk_src.clkr.hw },
2483
2530
.num_parents = 1,
2484
2531
.flags = CLK_SET_RATE_PARENT,
2485
2532
.ops = &clk_branch2_ops,
···
2493
2542
.enable_mask = BIT(0),
2494
2543
.hw.init = &(struct clk_init_data){
2495
2544
.name = "gcc_pcie1_axi_m_clk",
2496
-
.parent_names = (const char *[]){
2497
-
"pcie1_axi_clk_src"
2498
-
},
2545
+
.parent_hws = (const struct clk_hw *[]){
2546
+
&pcie1_axi_clk_src.clkr.hw },
2499
2547
.num_parents = 1,
2500
2548
.flags = CLK_SET_RATE_PARENT,
2501
2549
.ops = &clk_branch2_ops,
···
2509
2559
.enable_mask = BIT(0),
2510
2560
.hw.init = &(struct clk_init_data){
2511
2561
.name = "gcc_pcie1_axi_s_clk",
2512
-
.parent_names = (const char *[]){
2513
-
"pcie1_axi_clk_src"
2514
-
},
2562
+
.parent_hws = (const struct clk_hw *[]){
2563
+
&pcie1_axi_clk_src.clkr.hw },
2515
2564
.num_parents = 1,
2516
2565
.flags = CLK_SET_RATE_PARENT,
2517
2566
.ops = &clk_branch2_ops,
···
2526
2577
.enable_mask = BIT(0),
2527
2578
.hw.init = &(struct clk_init_data){
2528
2579
.name = "gcc_pcie1_pipe_clk",
2529
-
.parent_names = (const char *[]){
2530
-
"pcie1_pipe_clk_src"
2531
-
},
2580
+
.parent_hws = (const struct clk_hw *[]){
2581
+
&pcie1_pipe_clk_src.clkr.hw },
2532
2582
.num_parents = 1,
2533
2583
.flags = CLK_SET_RATE_PARENT,
2534
2584
.ops = &clk_branch2_ops,
···
2542
2594
.enable_mask = BIT(0),
2543
2595
.hw.init = &(struct clk_init_data){
2544
2596
.name = "gcc_sys_noc_pcie1_axi_clk",
2545
-
.parent_names = (const char *[]){
2546
-
"pcie1_axi_clk_src"
2547
-
},
2597
+
.parent_hws = (const struct clk_hw *[]){
2598
+
&pcie1_axi_clk_src.clkr.hw },
2548
2599
.num_parents = 1,
2549
2600
.flags = CLK_SET_RATE_PARENT,
2550
2601
.ops = &clk_branch2_ops,
···
2558
2611
.enable_mask = BIT(0),
2559
2612
.hw.init = &(struct clk_init_data){
2560
2613
.name = "gcc_usb0_aux_clk",
2561
-
.parent_names = (const char *[]){
2562
-
"usb0_aux_clk_src"
2563
-
},
2614
+
.parent_hws = (const struct clk_hw *[]){
2615
+
&usb0_aux_clk_src.clkr.hw },
2564
2616
.num_parents = 1,
2565
2617
.flags = CLK_SET_RATE_PARENT,
2566
2618
.ops = &clk_branch2_ops,
···
2574
2628
.enable_mask = BIT(0),
2575
2629
.hw.init = &(struct clk_init_data){
2576
2630
.name = "gcc_sys_noc_usb0_axi_clk",
2577
-
.parent_names = (const char *[]){
2578
-
"usb0_master_clk_src"
2579
-
},
2631
+
.parent_hws = (const struct clk_hw *[]){
2632
+
&usb0_master_clk_src.clkr.hw },
2580
2633
.num_parents = 1,
2581
2634
.flags = CLK_SET_RATE_PARENT,
2582
2635
.ops = &clk_branch2_ops,
···
2590
2645
.enable_mask = BIT(0),
2591
2646
.hw.init = &(struct clk_init_data){
2592
2647
.name = "gcc_usb0_master_clk",
2593
-
.parent_names = (const char *[]){
2594
-
"usb0_master_clk_src"
2595
-
},
2648
+
.parent_hws = (const struct clk_hw *[]){
2649
+
&usb0_master_clk_src.clkr.hw },
2596
2650
.num_parents = 1,
2597
2651
.flags = CLK_SET_RATE_PARENT,
2598
2652
.ops = &clk_branch2_ops,
···
2606
2662
.enable_mask = BIT(0),
2607
2663
.hw.init = &(struct clk_init_data){
2608
2664
.name = "gcc_usb0_mock_utmi_clk",
2609
-
.parent_names = (const char *[]){
2610
-
"usb0_mock_utmi_clk_src"
2611
-
},
2665
+
.parent_hws = (const struct clk_hw *[]){
2666
+
&usb0_mock_utmi_clk_src.clkr.hw },
2612
2667
.num_parents = 1,
2613
2668
.flags = CLK_SET_RATE_PARENT,
2614
2669
.ops = &clk_branch2_ops,
···
2622
2679
.enable_mask = BIT(0),
2623
2680
.hw.init = &(struct clk_init_data){
2624
2681
.name = "gcc_usb0_phy_cfg_ahb_clk",
2625
-
.parent_names = (const char *[]){
2626
-
"pcnoc_clk_src"
2627
-
},
2682
+
.parent_hws = (const struct clk_hw *[]){
2683
+
&pcnoc_clk_src.hw },
2628
2684
.num_parents = 1,
2629
2685
.flags = CLK_SET_RATE_PARENT,
2630
2686
.ops = &clk_branch2_ops,
···
2639
2697
.enable_mask = BIT(0),
2640
2698
.hw.init = &(struct clk_init_data){
2641
2699
.name = "gcc_usb0_pipe_clk",
2642
-
.parent_names = (const char *[]){
2643
-
"usb0_pipe_clk_src"
2644
-
},
2700
+
.parent_hws = (const struct clk_hw *[]){
2701
+
&usb0_pipe_clk_src.clkr.hw },
2645
2702
.num_parents = 1,
2646
2703
.flags = CLK_SET_RATE_PARENT,
2647
2704
.ops = &clk_branch2_ops,
···
2655
2714
.enable_mask = BIT(0),
2656
2715
.hw.init = &(struct clk_init_data){
2657
2716
.name = "gcc_usb0_sleep_clk",
2658
-
.parent_names = (const char *[]){
2659
-
"gcc_sleep_clk_src"
2660
-
},
2717
+
.parent_hws = (const struct clk_hw *[]){
2718
+
&gcc_sleep_clk_src.clkr.hw },
2661
2719
.num_parents = 1,
2662
2720
.flags = CLK_SET_RATE_PARENT,
2663
2721
.ops = &clk_branch2_ops,
···
2671
2731
.enable_mask = BIT(0),
2672
2732
.hw.init = &(struct clk_init_data){
2673
2733
.name = "gcc_usb1_aux_clk",
2674
-
.parent_names = (const char *[]){
2675
-
"usb1_aux_clk_src"
2676
-
},
2734
+
.parent_hws = (const struct clk_hw *[]){
2735
+
&usb1_aux_clk_src.clkr.hw },
2677
2736
.num_parents = 1,
2678
2737
.flags = CLK_SET_RATE_PARENT,
2679
2738
.ops = &clk_branch2_ops,
···
2687
2748
.enable_mask = BIT(0),
2688
2749
.hw.init = &(struct clk_init_data){
2689
2750
.name = "gcc_sys_noc_usb1_axi_clk",
2690
-
.parent_names = (const char *[]){
2691
-
"usb1_master_clk_src"
2692
-
},
2751
+
.parent_hws = (const struct clk_hw *[]){
2752
+
&usb1_master_clk_src.clkr.hw },
2693
2753
.num_parents = 1,
2694
2754
.flags = CLK_SET_RATE_PARENT,
2695
2755
.ops = &clk_branch2_ops,
···
2703
2765
.enable_mask = BIT(0),
2704
2766
.hw.init = &(struct clk_init_data){
2705
2767
.name = "gcc_usb1_master_clk",
2706
-
.parent_names = (const char *[]){
2707
-
"usb1_master_clk_src"
2708
-
},
2768
+
.parent_hws = (const struct clk_hw *[]){
2769
+
&usb1_master_clk_src.clkr.hw },
2709
2770
.num_parents = 1,
2710
2771
.flags = CLK_SET_RATE_PARENT,
2711
2772
.ops = &clk_branch2_ops,
···
2719
2782
.enable_mask = BIT(0),
2720
2783
.hw.init = &(struct clk_init_data){
2721
2784
.name = "gcc_usb1_mock_utmi_clk",
2722
-
.parent_names = (const char *[]){
2723
-
"usb1_mock_utmi_clk_src"
2724
-
},
2785
+
.parent_hws = (const struct clk_hw *[]){
2786
+
&usb1_mock_utmi_clk_src.clkr.hw },
2725
2787
.num_parents = 1,
2726
2788
.flags = CLK_SET_RATE_PARENT,
2727
2789
.ops = &clk_branch2_ops,
···
2735
2799
.enable_mask = BIT(0),
2736
2800
.hw.init = &(struct clk_init_data){
2737
2801
.name = "gcc_usb1_phy_cfg_ahb_clk",
2738
-
.parent_names = (const char *[]){
2739
-
"pcnoc_clk_src"
2740
-
},
2802
+
.parent_hws = (const struct clk_hw *[]){
2803
+
&pcnoc_clk_src.hw },
2741
2804
.num_parents = 1,
2742
2805
.flags = CLK_SET_RATE_PARENT,
2743
2806
.ops = &clk_branch2_ops,
···
2752
2817
.enable_mask = BIT(0),
2753
2818
.hw.init = &(struct clk_init_data){
2754
2819
.name = "gcc_usb1_pipe_clk",
2755
-
.parent_names = (const char *[]){
2756
-
"usb1_pipe_clk_src"
2757
-
},
2820
+
.parent_hws = (const struct clk_hw *[]){
2821
+
&usb1_pipe_clk_src.clkr.hw },
2758
2822
.num_parents = 1,
2759
2823
.flags = CLK_SET_RATE_PARENT,
2760
2824
.ops = &clk_branch2_ops,
···
2768
2834
.enable_mask = BIT(0),
2769
2835
.hw.init = &(struct clk_init_data){
2770
2836
.name = "gcc_usb1_sleep_clk",
2771
-
.parent_names = (const char *[]){
2772
-
"gcc_sleep_clk_src"
2773
-
},
2837
+
.parent_hws = (const struct clk_hw *[]){
2838
+
&gcc_sleep_clk_src.clkr.hw },
2774
2839
.num_parents = 1,
2775
2840
.flags = CLK_SET_RATE_PARENT,
2776
2841
.ops = &clk_branch2_ops,
···
2784
2851
.enable_mask = BIT(0),
2785
2852
.hw.init = &(struct clk_init_data){
2786
2853
.name = "gcc_sdcc1_ahb_clk",
2787
-
.parent_names = (const char *[]){
2788
-
"pcnoc_clk_src"
2789
-
},
2854
+
.parent_hws = (const struct clk_hw *[]){
2855
+
&pcnoc_clk_src.hw },
2790
2856
.num_parents = 1,
2791
2857
.flags = CLK_SET_RATE_PARENT,
2792
2858
.ops = &clk_branch2_ops,
···
2800
2868
.enable_mask = BIT(0),
2801
2869
.hw.init = &(struct clk_init_data){
2802
2870
.name = "gcc_sdcc1_apps_clk",
2803
-
.parent_names = (const char *[]){
2804
-
"sdcc1_apps_clk_src"
2805
-
},
2871
+
.parent_hws = (const struct clk_hw *[]){
2872
+
&sdcc1_apps_clk_src.clkr.hw },
2806
2873
.num_parents = 1,
2807
2874
.flags = CLK_SET_RATE_PARENT,
2808
2875
.ops = &clk_branch2_ops,
···
2816
2885
.enable_mask = BIT(0),
2817
2886
.hw.init = &(struct clk_init_data){
2818
2887
.name = "gcc_sdcc1_ice_core_clk",
2819
-
.parent_names = (const char *[]){
2820
-
"sdcc1_ice_core_clk_src"
2821
-
},
2888
+
.parent_hws = (const struct clk_hw *[]){
2889
+
&sdcc1_ice_core_clk_src.clkr.hw },
2822
2890
.num_parents = 1,
2823
2891
.flags = CLK_SET_RATE_PARENT,
2824
2892
.ops = &clk_branch2_ops,
···
2832
2902
.enable_mask = BIT(0),
2833
2903
.hw.init = &(struct clk_init_data){
2834
2904
.name = "gcc_sdcc2_ahb_clk",
2835
-
.parent_names = (const char *[]){
2836
-
"pcnoc_clk_src"
2837
-
},
2905
+
.parent_hws = (const struct clk_hw *[]){
2906
+
&pcnoc_clk_src.hw },
2838
2907
.num_parents = 1,
2839
2908
.flags = CLK_SET_RATE_PARENT,
2840
2909
.ops = &clk_branch2_ops,
···
2848
2919
.enable_mask = BIT(0),
2849
2920
.hw.init = &(struct clk_init_data){
2850
2921
.name = "gcc_sdcc2_apps_clk",
2851
-
.parent_names = (const char *[]){
2852
-
"sdcc2_apps_clk_src"
2853
-
},
2922
+
.parent_hws = (const struct clk_hw *[]){
2923
+
&sdcc2_apps_clk_src.clkr.hw },
2854
2924
.num_parents = 1,
2855
2925
.flags = CLK_SET_RATE_PARENT,
2856
2926
.ops = &clk_branch2_ops,
···
2864
2936
.enable_mask = BIT(0),
2865
2937
.hw.init = &(struct clk_init_data){
2866
2938
.name = "gcc_mem_noc_nss_axi_clk",
2867
-
.parent_names = (const char *[]){
2868
-
"nss_noc_clk_src"
2869
-
},
2939
+
.parent_hws = (const struct clk_hw *[]){
2940
+
&nss_noc_clk_src.hw },
2870
2941
.num_parents = 1,
2871
2942
.flags = CLK_SET_RATE_PARENT,
2872
2943
.ops = &clk_branch2_ops,
···
2880
2953
.enable_mask = BIT(0),
2881
2954
.hw.init = &(struct clk_init_data){
2882
2955
.name = "gcc_nss_ce_apb_clk",
2883
-
.parent_names = (const char *[]){
2884
-
"nss_ce_clk_src"
2885
-
},
2956
+
.parent_hws = (const struct clk_hw *[]){
2957
+
&nss_ce_clk_src.clkr.hw },
2886
2958
.num_parents = 1,
2887
2959
.flags = CLK_SET_RATE_PARENT,
2888
2960
.ops = &clk_branch2_ops,
···
2896
2970
.enable_mask = BIT(0),
2897
2971
.hw.init = &(struct clk_init_data){
2898
2972
.name = "gcc_nss_ce_axi_clk",
2899
-
.parent_names = (const char *[]){
2900
-
"nss_ce_clk_src"
2901
-
},
2973
+
.parent_hws = (const struct clk_hw *[]){
2974
+
&nss_ce_clk_src.clkr.hw },
2902
2975
.num_parents = 1,
2903
2976
.flags = CLK_SET_RATE_PARENT,
2904
2977
.ops = &clk_branch2_ops,
···
2912
2987
.enable_mask = BIT(0),
2913
2988
.hw.init = &(struct clk_init_data){
2914
2989
.name = "gcc_nss_cfg_clk",
2915
-
.parent_names = (const char *[]){
2916
-
"pcnoc_clk_src"
2917
-
},
2990
+
.parent_hws = (const struct clk_hw *[]){
2991
+
&pcnoc_clk_src.hw },
2918
2992
.num_parents = 1,
2919
2993
.flags = CLK_SET_RATE_PARENT,
2920
2994
.ops = &clk_branch2_ops,
···
2928
3004
.enable_mask = BIT(0),
2929
3005
.hw.init = &(struct clk_init_data){
2930
3006
.name = "gcc_nss_crypto_clk",
2931
-
.parent_names = (const char *[]){
2932
-
"nss_crypto_clk_src"
2933
-
},
3007
+
.parent_hws = (const struct clk_hw *[]){
3008
+
&nss_crypto_clk_src.clkr.hw },
2934
3009
.num_parents = 1,
2935
3010
.flags = CLK_SET_RATE_PARENT,
2936
3011
.ops = &clk_branch2_ops,
···
2944
3021
.enable_mask = BIT(0),
2945
3022
.hw.init = &(struct clk_init_data){
2946
3023
.name = "gcc_nss_csr_clk",
2947
-
.parent_names = (const char *[]){
2948
-
"nss_ce_clk_src"
2949
-
},
3024
+
.parent_hws = (const struct clk_hw *[]){
3025
+
&nss_ce_clk_src.clkr.hw },
2950
3026
.num_parents = 1,
2951
3027
.flags = CLK_SET_RATE_PARENT,
2952
3028
.ops = &clk_branch2_ops,
···
2960
3038
.enable_mask = BIT(0),
2961
3039
.hw.init = &(struct clk_init_data){
2962
3040
.name = "gcc_nss_edma_cfg_clk",
2963
-
.parent_names = (const char *[]){
2964
-
"nss_ppe_clk_src"
2965
-
},
3041
+
.parent_hws = (const struct clk_hw *[]){
3042
+
&nss_ppe_clk_src.clkr.hw },
2966
3043
.num_parents = 1,
2967
3044
.flags = CLK_SET_RATE_PARENT,
2968
3045
.ops = &clk_branch2_ops,
···
2976
3055
.enable_mask = BIT(0),
2977
3056
.hw.init = &(struct clk_init_data){
2978
3057
.name = "gcc_nss_edma_clk",
2979
-
.parent_names = (const char *[]){
2980
-
"nss_ppe_clk_src"
2981
-
},
3058
+
.parent_hws = (const struct clk_hw *[]){
3059
+
&nss_ppe_clk_src.clkr.hw },
2982
3060
.num_parents = 1,
2983
3061
.flags = CLK_SET_RATE_PARENT,
2984
3062
.ops = &clk_branch2_ops,
···
2992
3072
.enable_mask = BIT(0),
2993
3073
.hw.init = &(struct clk_init_data){
2994
3074
.name = "gcc_nss_imem_clk",
2995
-
.parent_names = (const char *[]){
2996
-
"nss_imem_clk_src"
2997
-
},
3075
+
.parent_hws = (const struct clk_hw *[]){
3076
+
&nss_imem_clk_src.clkr.hw },
2998
3077
.num_parents = 1,
2999
3078
.flags = CLK_SET_RATE_PARENT,
3000
3079
.ops = &clk_branch2_ops,
···
3008
3089
.enable_mask = BIT(0),
3009
3090
.hw.init = &(struct clk_init_data){
3010
3091
.name = "gcc_nss_noc_clk",
3011
-
.parent_names = (const char *[]){
3012
-
"nss_noc_clk_src"
3013
-
},
3092
+
.parent_hws = (const struct clk_hw *[]){
3093
+
&nss_noc_clk_src.hw },
3014
3094
.num_parents = 1,
3015
3095
.flags = CLK_SET_RATE_PARENT,
3016
3096
.ops = &clk_branch2_ops,
···
3024
3106
.enable_mask = BIT(0),
3025
3107
.hw.init = &(struct clk_init_data){
3026
3108
.name = "gcc_nss_ppe_btq_clk",
3027
-
.parent_names = (const char *[]){
3028
-
"nss_ppe_clk_src"
3029
-
},
3109
+
.parent_hws = (const struct clk_hw *[]){
3110
+
&nss_ppe_clk_src.clkr.hw },
3030
3111
.num_parents = 1,
3031
3112
.flags = CLK_SET_RATE_PARENT,
3032
3113
.ops = &clk_branch2_ops,
···
3040
3123
.enable_mask = BIT(0),
3041
3124
.hw.init = &(struct clk_init_data){
3042
3125
.name = "gcc_nss_ppe_cfg_clk",
3043
-
.parent_names = (const char *[]){
3044
-
"nss_ppe_clk_src"
3045
-
},
3126
+
.parent_hws = (const struct clk_hw *[]){
3127
+
&nss_ppe_clk_src.clkr.hw },
3046
3128
.num_parents = 1,
3047
3129
.flags = CLK_SET_RATE_PARENT,
3048
3130
.ops = &clk_branch2_ops,
···
3056
3140
.enable_mask = BIT(0),
3057
3141
.hw.init = &(struct clk_init_data){
3058
3142
.name = "gcc_nss_ppe_clk",
3059
-
.parent_names = (const char *[]){
3060
-
"nss_ppe_clk_src"
3061
-
},
3143
+
.parent_hws = (const struct clk_hw *[]){
3144
+
&nss_ppe_clk_src.clkr.hw },
3062
3145
.num_parents = 1,
3063
3146
.flags = CLK_SET_RATE_PARENT,
3064
3147
.ops = &clk_branch2_ops,
···
3072
3157
.enable_mask = BIT(0),
3073
3158
.hw.init = &(struct clk_init_data){
3074
3159
.name = "gcc_nss_ppe_ipe_clk",
3075
-
.parent_names = (const char *[]){
3076
-
"nss_ppe_clk_src"
3077
-
},
3160
+
.parent_hws = (const struct clk_hw *[]){
3161
+
&nss_ppe_clk_src.clkr.hw },
3078
3162
.num_parents = 1,
3079
3163
.flags = CLK_SET_RATE_PARENT,
3080
3164
.ops = &clk_branch2_ops,
···
3088
3174
.enable_mask = BIT(0),
3089
3175
.hw.init = &(struct clk_init_data){
3090
3176
.name = "gcc_nss_ptp_ref_clk",
3091
-
.parent_names = (const char *[]){
3092
-
"nss_ppe_cdiv_clk_src"
3093
-
},
3177
+
.parent_hws = (const struct clk_hw *[]){
3178
+
&nss_ppe_cdiv_clk_src.hw },
3094
3179
.num_parents = 1,
3095
3180
.flags = CLK_SET_RATE_PARENT,
3096
3181
.ops = &clk_branch2_ops,
···
3105
3192
.enable_mask = BIT(0),
3106
3193
.hw.init = &(struct clk_init_data){
3107
3194
.name = "gcc_crypto_ppe_clk",
3108
-
.parent_names = (const char *[]){
3109
-
"nss_ppe_clk_src"
3110
-
},
3195
+
.parent_hws = (const struct clk_hw *[]){
3196
+
&nss_ppe_clk_src.clkr.hw },
3111
3197
.num_parents = 1,
3112
3198
.flags = CLK_SET_RATE_PARENT,
3113
3199
.ops = &clk_branch2_ops,
···
3121
3209
.enable_mask = BIT(0),
3122
3210
.hw.init = &(struct clk_init_data){
3123
3211
.name = "gcc_nssnoc_ce_apb_clk",
3124
-
.parent_names = (const char *[]){
3125
-
"nss_ce_clk_src"
3126
-
},
3212
+
.parent_hws = (const struct clk_hw *[]){
3213
+
&nss_ce_clk_src.clkr.hw },
3127
3214
.num_parents = 1,
3128
3215
.flags = CLK_SET_RATE_PARENT,
3129
3216
.ops = &clk_branch2_ops,
···
3137
3226
.enable_mask = BIT(0),
3138
3227
.hw.init = &(struct clk_init_data){
3139
3228
.name = "gcc_nssnoc_ce_axi_clk",
3140
-
.parent_names = (const char *[]){
3141
-
"nss_ce_clk_src"
3142
-
},
3229
+
.parent_hws = (const struct clk_hw *[]){
3230
+
&nss_ce_clk_src.clkr.hw },
3143
3231
.num_parents = 1,
3144
3232
.flags = CLK_SET_RATE_PARENT,
3145
3233
.ops = &clk_branch2_ops,
···
3153
3243
.enable_mask = BIT(0),
3154
3244
.hw.init = &(struct clk_init_data){
3155
3245
.name = "gcc_nssnoc_crypto_clk",
3156
-
.parent_names = (const char *[]){
3157
-
"nss_crypto_clk_src"
3158
-
},
3246
+
.parent_hws = (const struct clk_hw *[]){
3247
+
&nss_crypto_clk_src.clkr.hw },
3159
3248
.num_parents = 1,
3160
3249
.flags = CLK_SET_RATE_PARENT,
3161
3250
.ops = &clk_branch2_ops,
···
3169
3260
.enable_mask = BIT(0),
3170
3261
.hw.init = &(struct clk_init_data){
3171
3262
.name = "gcc_nssnoc_ppe_cfg_clk",
3172
-
.parent_names = (const char *[]){
3173
-
"nss_ppe_clk_src"
3174
-
},
3263
+
.parent_hws = (const struct clk_hw *[]){
3264
+
&nss_ppe_clk_src.clkr.hw },
3175
3265
.num_parents = 1,
3176
3266
.flags = CLK_SET_RATE_PARENT,
3177
3267
.ops = &clk_branch2_ops,
···
3185
3277
.enable_mask = BIT(0),
3186
3278
.hw.init = &(struct clk_init_data){
3187
3279
.name = "gcc_nssnoc_ppe_clk",
3188
-
.parent_names = (const char *[]){
3189
-
"nss_ppe_clk_src"
3190
-
},
3280
+
.parent_hws = (const struct clk_hw *[]){
3281
+
&nss_ppe_clk_src.clkr.hw },
3191
3282
.num_parents = 1,
3192
3283
.flags = CLK_SET_RATE_PARENT,
3193
3284
.ops = &clk_branch2_ops,
···
3201
3294
.enable_mask = BIT(0),
3202
3295
.hw.init = &(struct clk_init_data){
3203
3296
.name = "gcc_nssnoc_qosgen_ref_clk",
3204
-
.parent_names = (const char *[]){
3205
-
"gcc_xo_clk_src"
3206
-
},
3297
+
.parent_hws = (const struct clk_hw *[]){
3298
+
&gcc_xo_clk_src.clkr.hw },
3207
3299
.num_parents = 1,
3208
3300
.flags = CLK_SET_RATE_PARENT,
3209
3301
.ops = &clk_branch2_ops,
···
3217
3311
.enable_mask = BIT(0),
3218
3312
.hw.init = &(struct clk_init_data){
3219
3313
.name = "gcc_nssnoc_snoc_clk",
3220
-
.parent_names = (const char *[]){
3221
-
"system_noc_clk_src"
3222
-
},
3314
+
.parent_hws = (const struct clk_hw *[]){
3315
+
&system_noc_clk_src.hw },
3223
3316
.num_parents = 1,
3224
3317
.flags = CLK_SET_RATE_PARENT,
3225
3318
.ops = &clk_branch2_ops,
···
3233
3328
.enable_mask = BIT(0),
3234
3329
.hw.init = &(struct clk_init_data){
3235
3330
.name = "gcc_nssnoc_timeout_ref_clk",
3236
-
.parent_names = (const char *[]){
3237
-
"gcc_xo_div4_clk_src"
3238
-
},
3331
+
.parent_hws = (const struct clk_hw *[]){
3332
+
&gcc_xo_div4_clk_src.hw },
3239
3333
.num_parents = 1,
3240
3334
.flags = CLK_SET_RATE_PARENT,
3241
3335
.ops = &clk_branch2_ops,
···
3249
3345
.enable_mask = BIT(0),
3250
3346
.hw.init = &(struct clk_init_data){
3251
3347
.name = "gcc_nssnoc_ubi0_ahb_clk",
3252
-
.parent_names = (const char *[]){
3253
-
"nss_ce_clk_src"
3254
-
},
3348
+
.parent_hws = (const struct clk_hw *[]){
3349
+
&nss_ce_clk_src.clkr.hw },
3255
3350
.num_parents = 1,
3256
3351
.flags = CLK_SET_RATE_PARENT,
3257
3352
.ops = &clk_branch2_ops,
···
3265
3362
.enable_mask = BIT(0),
3266
3363
.hw.init = &(struct clk_init_data){
3267
3364
.name = "gcc_nssnoc_ubi1_ahb_clk",
3268
-
.parent_names = (const char *[]){
3269
-
"nss_ce_clk_src"
3270
-
},
3365
+
.parent_hws = (const struct clk_hw *[]){
3366
+
&nss_ce_clk_src.clkr.hw },
3271
3367
.num_parents = 1,
3272
3368
.flags = CLK_SET_RATE_PARENT,
3273
3369
.ops = &clk_branch2_ops,
···
3282
3380
.enable_mask = BIT(0),
3283
3381
.hw.init = &(struct clk_init_data){
3284
3382
.name = "gcc_ubi0_ahb_clk",
3285
-
.parent_names = (const char *[]){
3286
-
"nss_ce_clk_src"
3287
-
},
3383
+
.parent_hws = (const struct clk_hw *[]){
3384
+
&nss_ce_clk_src.clkr.hw },
3288
3385
.num_parents = 1,
3289
3386
.flags = CLK_SET_RATE_PARENT,
3290
3387
.ops = &clk_branch2_ops,
···
3299
3398
.enable_mask = BIT(0),
3300
3399
.hw.init = &(struct clk_init_data){
3301
3400
.name = "gcc_ubi0_axi_clk",
3302
-
.parent_names = (const char *[]){
3303
-
"nss_noc_clk_src"
3304
-
},
3401
+
.parent_hws = (const struct clk_hw *[]){
3402
+
&nss_noc_clk_src.hw },
3305
3403
.num_parents = 1,
3306
3404
.flags = CLK_SET_RATE_PARENT,
3307
3405
.ops = &clk_branch2_ops,
···
3316
3416
.enable_mask = BIT(0),
3317
3417
.hw.init = &(struct clk_init_data){
3318
3418
.name = "gcc_ubi0_nc_axi_clk",
3319
-
.parent_names = (const char *[]){
3320
-
"nss_noc_clk_src"
3321
-
},
3419
+
.parent_hws = (const struct clk_hw *[]){
3420
+
&nss_noc_clk_src.hw },
3322
3421
.num_parents = 1,
3323
3422
.flags = CLK_SET_RATE_PARENT,
3324
3423
.ops = &clk_branch2_ops,
···
3333
3434
.enable_mask = BIT(0),
3334
3435
.hw.init = &(struct clk_init_data){
3335
3436
.name = "gcc_ubi0_core_clk",
3336
-
.parent_names = (const char *[]){
3337
-
"nss_ubi0_div_clk_src"
3338
-
},
3437
+
.parent_hws = (const struct clk_hw *[]){
3438
+
&nss_ubi0_div_clk_src.clkr.hw },
3339
3439
.num_parents = 1,
3340
3440
.flags = CLK_SET_RATE_PARENT,
3341
3441
.ops = &clk_branch2_ops,
···
3350
3452
.enable_mask = BIT(0),
3351
3453
.hw.init = &(struct clk_init_data){
3352
3454
.name = "gcc_ubi0_mpt_clk",
3353
-
.parent_names = (const char *[]){
3354
-
"ubi_mpt_clk_src"
3355
-
},
3455
+
.parent_hws = (const struct clk_hw *[]){
3456
+
&ubi_mpt_clk_src.clkr.hw },
3356
3457
.num_parents = 1,
3357
3458
.flags = CLK_SET_RATE_PARENT,
3358
3459
.ops = &clk_branch2_ops,
···
3367
3470
.enable_mask = BIT(0),
3368
3471
.hw.init = &(struct clk_init_data){
3369
3472
.name = "gcc_ubi1_ahb_clk",
3370
-
.parent_names = (const char *[]){
3371
-
"nss_ce_clk_src"
3372
-
},
3473
+
.parent_hws = (const struct clk_hw *[]){
3474
+
&nss_ce_clk_src.clkr.hw },
3373
3475
.num_parents = 1,
3374
3476
.flags = CLK_SET_RATE_PARENT,
3375
3477
.ops = &clk_branch2_ops,
···
3384
3488
.enable_mask = BIT(0),
3385
3489
.hw.init = &(struct clk_init_data){
3386
3490
.name = "gcc_ubi1_axi_clk",
3387
-
.parent_names = (const char *[]){
3388
-
"nss_noc_clk_src"
3389
-
},
3491
+
.parent_hws = (const struct clk_hw *[]){
3492
+
&nss_noc_clk_src.hw },
3390
3493
.num_parents = 1,
3391
3494
.flags = CLK_SET_RATE_PARENT,
3392
3495
.ops = &clk_branch2_ops,
···
3401
3506
.enable_mask = BIT(0),
3402
3507
.hw.init = &(struct clk_init_data){
3403
3508
.name = "gcc_ubi1_nc_axi_clk",
3404
-
.parent_names = (const char *[]){
3405
-
"nss_noc_clk_src"
3406
-
},
3509
+
.parent_hws = (const struct clk_hw *[]){
3510
+
&nss_noc_clk_src.hw },
3407
3511
.num_parents = 1,
3408
3512
.flags = CLK_SET_RATE_PARENT,
3409
3513
.ops = &clk_branch2_ops,
···
3418
3524
.enable_mask = BIT(0),
3419
3525
.hw.init = &(struct clk_init_data){
3420
3526
.name = "gcc_ubi1_core_clk",
3421
-
.parent_names = (const char *[]){
3422
-
"nss_ubi1_div_clk_src"
3423
-
},
3527
+
.parent_hws = (const struct clk_hw *[]){
3528
+
&nss_ubi1_div_clk_src.clkr.hw },
3424
3529
.num_parents = 1,
3425
3530
.flags = CLK_SET_RATE_PARENT,
3426
3531
.ops = &clk_branch2_ops,
···
3435
3542
.enable_mask = BIT(0),
3436
3543
.hw.init = &(struct clk_init_data){
3437
3544
.name = "gcc_ubi1_mpt_clk",
3438
-
.parent_names = (const char *[]){
3439
-
"ubi_mpt_clk_src"
3440
-
},
3545
+
.parent_hws = (const struct clk_hw *[]){
3546
+
&ubi_mpt_clk_src.clkr.hw },
3441
3547
.num_parents = 1,
3442
3548
.flags = CLK_SET_RATE_PARENT,
3443
3549
.ops = &clk_branch2_ops,
···
3451
3559
.enable_mask = BIT(0),
3452
3560
.hw.init = &(struct clk_init_data){
3453
3561
.name = "gcc_cmn_12gpll_ahb_clk",
3454
-
.parent_names = (const char *[]){
3455
-
"pcnoc_clk_src"
3456
-
},
3562
+
.parent_hws = (const struct clk_hw *[]){
3563
+
&pcnoc_clk_src.hw },
3457
3564
.num_parents = 1,
3458
3565
.flags = CLK_SET_RATE_PARENT,
3459
3566
.ops = &clk_branch2_ops,
···
3467
3576
.enable_mask = BIT(0),
3468
3577
.hw.init = &(struct clk_init_data){
3469
3578
.name = "gcc_cmn_12gpll_sys_clk",
3470
-
.parent_names = (const char *[]){
3471
-
"gcc_xo_clk_src"
3472
-
},
3579
+
.parent_hws = (const struct clk_hw *[]){
3580
+
&gcc_xo_clk_src.clkr.hw },
3473
3581
.num_parents = 1,
3474
3582
.flags = CLK_SET_RATE_PARENT,
3475
3583
.ops = &clk_branch2_ops,
···
3483
3593
.enable_mask = BIT(0),
3484
3594
.hw.init = &(struct clk_init_data){
3485
3595
.name = "gcc_mdio_ahb_clk",
3486
-
.parent_names = (const char *[]){
3487
-
"pcnoc_clk_src"
3488
-
},
3596
+
.parent_hws = (const struct clk_hw *[]){
3597
+
&pcnoc_clk_src.hw },
3489
3598
.num_parents = 1,
3490
3599
.flags = CLK_SET_RATE_PARENT,
3491
3600
.ops = &clk_branch2_ops,
···
3499
3610
.enable_mask = BIT(0),
3500
3611
.hw.init = &(struct clk_init_data){
3501
3612
.name = "gcc_uniphy0_ahb_clk",
3502
-
.parent_names = (const char *[]){
3503
-
"pcnoc_clk_src"
3504
-
},
3613
+
.parent_hws = (const struct clk_hw *[]){
3614
+
&pcnoc_clk_src.hw },
3505
3615
.num_parents = 1,
3506
3616
.flags = CLK_SET_RATE_PARENT,
3507
3617
.ops = &clk_branch2_ops,
···
3515
3627
.enable_mask = BIT(0),
3516
3628
.hw.init = &(struct clk_init_data){
3517
3629
.name = "gcc_uniphy0_sys_clk",
3518
-
.parent_names = (const char *[]){
3519
-
"gcc_xo_clk_src"
3520
-
},
3630
+
.parent_hws = (const struct clk_hw *[]){
3631
+
&gcc_xo_clk_src.clkr.hw },
3521
3632
.num_parents = 1,
3522
3633
.flags = CLK_SET_RATE_PARENT,
3523
3634
.ops = &clk_branch2_ops,
···
3531
3644
.enable_mask = BIT(0),
3532
3645
.hw.init = &(struct clk_init_data){
3533
3646
.name = "gcc_uniphy1_ahb_clk",
3534
-
.parent_names = (const char *[]){
3535
-
"pcnoc_clk_src"
3536
-
},
3647
+
.parent_hws = (const struct clk_hw *[]){
3648
+
&pcnoc_clk_src.hw },
3537
3649
.num_parents = 1,
3538
3650
.flags = CLK_SET_RATE_PARENT,
3539
3651
.ops = &clk_branch2_ops,
···
3547
3661
.enable_mask = BIT(0),
3548
3662
.hw.init = &(struct clk_init_data){
3549
3663
.name = "gcc_uniphy1_sys_clk",
3550
-
.parent_names = (const char *[]){
3551
-
"gcc_xo_clk_src"
3552
-
},
3664
+
.parent_hws = (const struct clk_hw *[]){
3665
+
&gcc_xo_clk_src.clkr.hw },
3553
3666
.num_parents = 1,
3554
3667
.flags = CLK_SET_RATE_PARENT,
3555
3668
.ops = &clk_branch2_ops,
···
3563
3678
.enable_mask = BIT(0),
3564
3679
.hw.init = &(struct clk_init_data){
3565
3680
.name = "gcc_uniphy2_ahb_clk",
3566
-
.parent_names = (const char *[]){
3567
-
"pcnoc_clk_src"
3568
-
},
3681
+
.parent_hws = (const struct clk_hw *[]){
3682
+
&pcnoc_clk_src.hw },
3569
3683
.num_parents = 1,
3570
3684
.flags = CLK_SET_RATE_PARENT,
3571
3685
.ops = &clk_branch2_ops,
···
3579
3695
.enable_mask = BIT(0),
3580
3696
.hw.init = &(struct clk_init_data){
3581
3697
.name = "gcc_uniphy2_sys_clk",
3582
-
.parent_names = (const char *[]){
3583
-
"gcc_xo_clk_src"
3584
-
},
3698
+
.parent_hws = (const struct clk_hw *[]){
3699
+
&gcc_xo_clk_src.clkr.hw },
3585
3700
.num_parents = 1,
3586
3701
.flags = CLK_SET_RATE_PARENT,
3587
3702
.ops = &clk_branch2_ops,
···
3595
3712
.enable_mask = BIT(0),
3596
3713
.hw.init = &(struct clk_init_data){
3597
3714
.name = "gcc_nss_port1_rx_clk",
3598
-
.parent_names = (const char *[]){
3599
-
"nss_port1_rx_div_clk_src"
3600
-
},
3715
+
.parent_hws = (const struct clk_hw *[]){
3716
+
&nss_port1_rx_div_clk_src.clkr.hw },
3601
3717
.num_parents = 1,
3602
3718
.flags = CLK_SET_RATE_PARENT,
3603
3719
.ops = &clk_branch2_ops,
···
3611
3729
.enable_mask = BIT(0),
3612
3730
.hw.init = &(struct clk_init_data){
3613
3731
.name = "gcc_nss_port1_tx_clk",
3614
-
.parent_names = (const char *[]){
3615
-
"nss_port1_tx_div_clk_src"
3616
-
},
3732
+
.parent_hws = (const struct clk_hw *[]){
3733
+
&nss_port1_tx_div_clk_src.clkr.hw },
3617
3734
.num_parents = 1,
3618
3735
.flags = CLK_SET_RATE_PARENT,
3619
3736
.ops = &clk_branch2_ops,
···
3627
3746
.enable_mask = BIT(0),
3628
3747
.hw.init = &(struct clk_init_data){
3629
3748
.name = "gcc_nss_port2_rx_clk",
3630
-
.parent_names = (const char *[]){
3631
-
"nss_port2_rx_div_clk_src"
3632
-
},
3749
+
.parent_hws = (const struct clk_hw *[]){
3750
+
&nss_port2_rx_div_clk_src.clkr.hw },
3633
3751
.num_parents = 1,
3634
3752
.flags = CLK_SET_RATE_PARENT,
3635
3753
.ops = &clk_branch2_ops,
···
3643
3763
.enable_mask = BIT(0),
3644
3764
.hw.init = &(struct clk_init_data){
3645
3765
.name = "gcc_nss_port2_tx_clk",
3646
-
.parent_names = (const char *[]){
3647
-
"nss_port2_tx_div_clk_src"
3648
-
},
3766
+
.parent_hws = (const struct clk_hw *[]){
3767
+
&nss_port2_tx_div_clk_src.clkr.hw },
3649
3768
.num_parents = 1,
3650
3769
.flags = CLK_SET_RATE_PARENT,
3651
3770
.ops = &clk_branch2_ops,
···
3659
3780
.enable_mask = BIT(0),
3660
3781
.hw.init = &(struct clk_init_data){
3661
3782
.name = "gcc_nss_port3_rx_clk",
3662
-
.parent_names = (const char *[]){
3663
-
"nss_port3_rx_div_clk_src"
3664
-
},
3783
+
.parent_hws = (const struct clk_hw *[]){
3784
+
&nss_port3_rx_div_clk_src.clkr.hw },
3665
3785
.num_parents = 1,
3666
3786
.flags = CLK_SET_RATE_PARENT,
3667
3787
.ops = &clk_branch2_ops,
···
3675
3797
.enable_mask = BIT(0),
3676
3798
.hw.init = &(struct clk_init_data){
3677
3799
.name = "gcc_nss_port3_tx_clk",
3678
-
.parent_names = (const char *[]){
3679
-
"nss_port3_tx_div_clk_src"
3680
-
},
3800
+
.parent_hws = (const struct clk_hw *[]){
3801
+
&nss_port3_tx_div_clk_src.clkr.hw },
3681
3802
.num_parents = 1,
3682
3803
.flags = CLK_SET_RATE_PARENT,
3683
3804
.ops = &clk_branch2_ops,
···
3691
3814
.enable_mask = BIT(0),
3692
3815
.hw.init = &(struct clk_init_data){
3693
3816
.name = "gcc_nss_port4_rx_clk",
3694
-
.parent_names = (const char *[]){
3695
-
"nss_port4_rx_div_clk_src"
3696
-
},
3817
+
.parent_hws = (const struct clk_hw *[]){
3818
+
&nss_port4_rx_div_clk_src.clkr.hw },
3697
3819
.num_parents = 1,
3698
3820
.flags = CLK_SET_RATE_PARENT,
3699
3821
.ops = &clk_branch2_ops,
···
3707
3831
.enable_mask = BIT(0),
3708
3832
.hw.init = &(struct clk_init_data){
3709
3833
.name = "gcc_nss_port4_tx_clk",
3710
-
.parent_names = (const char *[]){
3711
-
"nss_port4_tx_div_clk_src"
3712
-
},
3834
+
.parent_hws = (const struct clk_hw *[]){
3835
+
&nss_port4_tx_div_clk_src.clkr.hw },
3713
3836
.num_parents = 1,
3714
3837
.flags = CLK_SET_RATE_PARENT,
3715
3838
.ops = &clk_branch2_ops,
···
3723
3848
.enable_mask = BIT(0),
3724
3849
.hw.init = &(struct clk_init_data){
3725
3850
.name = "gcc_nss_port5_rx_clk",
3726
-
.parent_names = (const char *[]){
3727
-
"nss_port5_rx_div_clk_src"
3728
-
},
3851
+
.parent_hws = (const struct clk_hw *[]){
3852
+
&nss_port5_rx_div_clk_src.clkr.hw },
3729
3853
.num_parents = 1,
3730
3854
.flags = CLK_SET_RATE_PARENT,
3731
3855
.ops = &clk_branch2_ops,
···
3739
3865
.enable_mask = BIT(0),
3740
3866
.hw.init = &(struct clk_init_data){
3741
3867
.name = "gcc_nss_port5_tx_clk",
3742
-
.parent_names = (const char *[]){
3743
-
"nss_port5_tx_div_clk_src"
3744
-
},
3868
+
.parent_hws = (const struct clk_hw *[]){
3869
+
&nss_port5_tx_div_clk_src.clkr.hw },
3745
3870
.num_parents = 1,
3746
3871
.flags = CLK_SET_RATE_PARENT,
3747
3872
.ops = &clk_branch2_ops,
···
3755
3882
.enable_mask = BIT(0),
3756
3883
.hw.init = &(struct clk_init_data){
3757
3884
.name = "gcc_nss_port6_rx_clk",
3758
-
.parent_names = (const char *[]){
3759
-
"nss_port6_rx_div_clk_src"
3760
-
},
3885
+
.parent_hws = (const struct clk_hw *[]){
3886
+
&nss_port6_rx_div_clk_src.clkr.hw },
3761
3887
.num_parents = 1,
3762
3888
.flags = CLK_SET_RATE_PARENT,
3763
3889
.ops = &clk_branch2_ops,
···
3771
3899
.enable_mask = BIT(0),
3772
3900
.hw.init = &(struct clk_init_data){
3773
3901
.name = "gcc_nss_port6_tx_clk",
3774
-
.parent_names = (const char *[]){
3775
-
"nss_port6_tx_div_clk_src"
3776
-
},
3902
+
.parent_hws = (const struct clk_hw *[]){
3903
+
&nss_port6_tx_div_clk_src.clkr.hw },
3777
3904
.num_parents = 1,
3778
3905
.flags = CLK_SET_RATE_PARENT,
3779
3906
.ops = &clk_branch2_ops,
···
3787
3916
.enable_mask = BIT(0),
3788
3917
.hw.init = &(struct clk_init_data){
3789
3918
.name = "gcc_port1_mac_clk",
3790
-
.parent_names = (const char *[]){
3791
-
"nss_ppe_clk_src"
3792
-
},
3919
+
.parent_hws = (const struct clk_hw *[]){
3920
+
&nss_ppe_clk_src.clkr.hw },
3793
3921
.num_parents = 1,
3794
3922
.flags = CLK_SET_RATE_PARENT,
3795
3923
.ops = &clk_branch2_ops,
···
3803
3933
.enable_mask = BIT(0),
3804
3934
.hw.init = &(struct clk_init_data){
3805
3935
.name = "gcc_port2_mac_clk",
3806
-
.parent_names = (const char *[]){
3807
-
"nss_ppe_clk_src"
3808
-
},
3936
+
.parent_hws = (const struct clk_hw *[]){
3937
+
&nss_ppe_clk_src.clkr.hw },
3809
3938
.num_parents = 1,
3810
3939
.flags = CLK_SET_RATE_PARENT,
3811
3940
.ops = &clk_branch2_ops,
···
3819
3950
.enable_mask = BIT(0),
3820
3951
.hw.init = &(struct clk_init_data){
3821
3952
.name = "gcc_port3_mac_clk",
3822
-
.parent_names = (const char *[]){
3823
-
"nss_ppe_clk_src"
3824
-
},
3953
+
.parent_hws = (const struct clk_hw *[]){
3954
+
&nss_ppe_clk_src.clkr.hw },
3825
3955
.num_parents = 1,
3826
3956
.flags = CLK_SET_RATE_PARENT,
3827
3957
.ops = &clk_branch2_ops,
···
3835
3967
.enable_mask = BIT(0),
3836
3968
.hw.init = &(struct clk_init_data){
3837
3969
.name = "gcc_port4_mac_clk",
3838
-
.parent_names = (const char *[]){
3839
-
"nss_ppe_clk_src"
3840
-
},
3970
+
.parent_hws = (const struct clk_hw *[]){
3971
+
&nss_ppe_clk_src.clkr.hw },
3841
3972
.num_parents = 1,
3842
3973
.flags = CLK_SET_RATE_PARENT,
3843
3974
.ops = &clk_branch2_ops,
···
3851
3984
.enable_mask = BIT(0),
3852
3985
.hw.init = &(struct clk_init_data){
3853
3986
.name = "gcc_port5_mac_clk",
3854
-
.parent_names = (const char *[]){
3855
-
"nss_ppe_clk_src"
3856
-
},
3987
+
.parent_hws = (const struct clk_hw *[]){
3988
+
&nss_ppe_clk_src.clkr.hw },
3857
3989
.num_parents = 1,
3858
3990
.flags = CLK_SET_RATE_PARENT,
3859
3991
.ops = &clk_branch2_ops,
···
3867
4001
.enable_mask = BIT(0),
3868
4002
.hw.init = &(struct clk_init_data){
3869
4003
.name = "gcc_port6_mac_clk",
3870
-
.parent_names = (const char *[]){
3871
-
"nss_ppe_clk_src"
3872
-
},
4004
+
.parent_hws = (const struct clk_hw *[]){
4005
+
&nss_ppe_clk_src.clkr.hw },
3873
4006
.num_parents = 1,
3874
4007
.flags = CLK_SET_RATE_PARENT,
3875
4008
.ops = &clk_branch2_ops,
···
3883
4018
.enable_mask = BIT(0),
3884
4019
.hw.init = &(struct clk_init_data){
3885
4020
.name = "gcc_uniphy0_port1_rx_clk",
3886
-
.parent_names = (const char *[]){
3887
-
"nss_port1_rx_div_clk_src"
3888
-
},
4021
+
.parent_hws = (const struct clk_hw *[]){
4022
+
&nss_port1_rx_div_clk_src.clkr.hw },
3889
4023
.num_parents = 1,
3890
4024
.flags = CLK_SET_RATE_PARENT,
3891
4025
.ops = &clk_branch2_ops,
···
3899
4035
.enable_mask = BIT(0),
3900
4036
.hw.init = &(struct clk_init_data){
3901
4037
.name = "gcc_uniphy0_port1_tx_clk",
3902
-
.parent_names = (const char *[]){
3903
-
"nss_port1_tx_div_clk_src"
3904
-
},
4038
+
.parent_hws = (const struct clk_hw *[]){
4039
+
&nss_port1_tx_div_clk_src.clkr.hw },
3905
4040
.num_parents = 1,
3906
4041
.flags = CLK_SET_RATE_PARENT,
3907
4042
.ops = &clk_branch2_ops,
···
3915
4052
.enable_mask = BIT(0),
3916
4053
.hw.init = &(struct clk_init_data){
3917
4054
.name = "gcc_uniphy0_port2_rx_clk",
3918
-
.parent_names = (const char *[]){
3919
-
"nss_port2_rx_div_clk_src"
3920
-
},
4055
+
.parent_hws = (const struct clk_hw *[]){
4056
+
&nss_port2_rx_div_clk_src.clkr.hw },
3921
4057
.num_parents = 1,
3922
4058
.flags = CLK_SET_RATE_PARENT,
3923
4059
.ops = &clk_branch2_ops,
···
3931
4069
.enable_mask = BIT(0),
3932
4070
.hw.init = &(struct clk_init_data){
3933
4071
.name = "gcc_uniphy0_port2_tx_clk",
3934
-
.parent_names = (const char *[]){
3935
-
"nss_port2_tx_div_clk_src"
3936
-
},
4072
+
.parent_hws = (const struct clk_hw *[]){
4073
+
&nss_port2_tx_div_clk_src.clkr.hw },
3937
4074
.num_parents = 1,
3938
4075
.flags = CLK_SET_RATE_PARENT,
3939
4076
.ops = &clk_branch2_ops,
···
3947
4086
.enable_mask = BIT(0),
3948
4087
.hw.init = &(struct clk_init_data){
3949
4088
.name = "gcc_uniphy0_port3_rx_clk",
3950
-
.parent_names = (const char *[]){
3951
-
"nss_port3_rx_div_clk_src"
3952
-
},
4089
+
.parent_hws = (const struct clk_hw *[]){
4090
+
&nss_port3_rx_div_clk_src.clkr.hw },
3953
4091
.num_parents = 1,
3954
4092
.flags = CLK_SET_RATE_PARENT,
3955
4093
.ops = &clk_branch2_ops,
···
3963
4103
.enable_mask = BIT(0),
3964
4104
.hw.init = &(struct clk_init_data){
3965
4105
.name = "gcc_uniphy0_port3_tx_clk",
3966
-
.parent_names = (const char *[]){
3967
-
"nss_port3_tx_div_clk_src"
3968
-
},
4106
+
.parent_hws = (const struct clk_hw *[]){
4107
+
&nss_port3_tx_div_clk_src.clkr.hw },
3969
4108
.num_parents = 1,
3970
4109
.flags = CLK_SET_RATE_PARENT,
3971
4110
.ops = &clk_branch2_ops,
···
3979
4120
.enable_mask = BIT(0),
3980
4121
.hw.init = &(struct clk_init_data){
3981
4122
.name = "gcc_uniphy0_port4_rx_clk",
3982
-
.parent_names = (const char *[]){
3983
-
"nss_port4_rx_div_clk_src"
3984
-
},
4123
+
.parent_hws = (const struct clk_hw *[]){
4124
+
&nss_port4_rx_div_clk_src.clkr.hw },
3985
4125
.num_parents = 1,
3986
4126
.flags = CLK_SET_RATE_PARENT,
3987
4127
.ops = &clk_branch2_ops,
···
3995
4137
.enable_mask = BIT(0),
3996
4138
.hw.init = &(struct clk_init_data){
3997
4139
.name = "gcc_uniphy0_port4_tx_clk",
3998
-
.parent_names = (const char *[]){
3999
-
"nss_port4_tx_div_clk_src"
4000
-
},
4140
+
.parent_hws = (const struct clk_hw *[]){
4141
+
&nss_port4_tx_div_clk_src.clkr.hw },
4001
4142
.num_parents = 1,
4002
4143
.flags = CLK_SET_RATE_PARENT,
4003
4144
.ops = &clk_branch2_ops,
···
4011
4154
.enable_mask = BIT(0),
4012
4155
.hw.init = &(struct clk_init_data){
4013
4156
.name = "gcc_uniphy0_port5_rx_clk",
4014
-
.parent_names = (const char *[]){
4015
-
"nss_port5_rx_div_clk_src"
4016
-
},
4157
+
.parent_hws = (const struct clk_hw *[]){
4158
+
&nss_port5_rx_div_clk_src.clkr.hw },
4017
4159
.num_parents = 1,
4018
4160
.flags = CLK_SET_RATE_PARENT,
4019
4161
.ops = &clk_branch2_ops,
···
4027
4171
.enable_mask = BIT(0),
4028
4172
.hw.init = &(struct clk_init_data){
4029
4173
.name = "gcc_uniphy0_port5_tx_clk",
4030
-
.parent_names = (const char *[]){
4031
-
"nss_port5_tx_div_clk_src"
4032
-
},
4174
+
.parent_hws = (const struct clk_hw *[]){
4175
+
&nss_port5_tx_div_clk_src.clkr.hw },
4033
4176
.num_parents = 1,
4034
4177
.flags = CLK_SET_RATE_PARENT,
4035
4178
.ops = &clk_branch2_ops,
···
4043
4188
.enable_mask = BIT(0),
4044
4189
.hw.init = &(struct clk_init_data){
4045
4190
.name = "gcc_uniphy1_port5_rx_clk",
4046
-
.parent_names = (const char *[]){
4047
-
"nss_port5_rx_div_clk_src"
4048
-
},
4191
+
.parent_hws = (const struct clk_hw *[]){
4192
+
&nss_port5_rx_div_clk_src.clkr.hw },
4049
4193
.num_parents = 1,
4050
4194
.flags = CLK_SET_RATE_PARENT,
4051
4195
.ops = &clk_branch2_ops,
···
4059
4205
.enable_mask = BIT(0),
4060
4206
.hw.init = &(struct clk_init_data){
4061
4207
.name = "gcc_uniphy1_port5_tx_clk",
4062
-
.parent_names = (const char *[]){
4063
-
"nss_port5_tx_div_clk_src"
4064
-
},
4208
+
.parent_hws = (const struct clk_hw *[]){
4209
+
&nss_port5_tx_div_clk_src.clkr.hw },
4065
4210
.num_parents = 1,
4066
4211
.flags = CLK_SET_RATE_PARENT,
4067
4212
.ops = &clk_branch2_ops,
···
4075
4222
.enable_mask = BIT(0),
4076
4223
.hw.init = &(struct clk_init_data){
4077
4224
.name = "gcc_uniphy2_port6_rx_clk",
4078
-
.parent_names = (const char *[]){
4079
-
"nss_port6_rx_div_clk_src"
4080
-
},
4225
+
.parent_hws = (const struct clk_hw *[]){
4226
+
&nss_port6_rx_div_clk_src.clkr.hw },
4081
4227
.num_parents = 1,
4082
4228
.flags = CLK_SET_RATE_PARENT,
4083
4229
.ops = &clk_branch2_ops,
···
4091
4239
.enable_mask = BIT(0),
4092
4240
.hw.init = &(struct clk_init_data){
4093
4241
.name = "gcc_uniphy2_port6_tx_clk",
4094
-
.parent_names = (const char *[]){
4095
-
"nss_port6_tx_div_clk_src"
4096
-
},
4242
+
.parent_hws = (const struct clk_hw *[]){
4243
+
&nss_port6_tx_div_clk_src.clkr.hw },
4097
4244
.num_parents = 1,
4098
4245
.flags = CLK_SET_RATE_PARENT,
4099
4246
.ops = &clk_branch2_ops,
···
4108
4257
.enable_mask = BIT(0),
4109
4258
.hw.init = &(struct clk_init_data){
4110
4259
.name = "gcc_crypto_ahb_clk",
4111
-
.parent_names = (const char *[]){
4112
-
"pcnoc_clk_src"
4113
-
},
4260
+
.parent_hws = (const struct clk_hw *[]){
4261
+
&pcnoc_clk_src.hw },
4114
4262
.num_parents = 1,
4115
4263
.flags = CLK_SET_RATE_PARENT,
4116
4264
.ops = &clk_branch2_ops,
···
4125
4275
.enable_mask = BIT(1),
4126
4276
.hw.init = &(struct clk_init_data){
4127
4277
.name = "gcc_crypto_axi_clk",
4128
-
.parent_names = (const char *[]){
4129
-
"pcnoc_clk_src"
4130
-
},
4278
+
.parent_hws = (const struct clk_hw *[]){
4279
+
&pcnoc_clk_src.hw },
4131
4280
.num_parents = 1,
4132
4281
.flags = CLK_SET_RATE_PARENT,
4133
4282
.ops = &clk_branch2_ops,
···
4142
4293
.enable_mask = BIT(2),
4143
4294
.hw.init = &(struct clk_init_data){
4144
4295
.name = "gcc_crypto_clk",
4145
-
.parent_names = (const char *[]){
4146
-
"crypto_clk_src"
4147
-
},
4296
+
.parent_hws = (const struct clk_hw *[]){
4297
+
&crypto_clk_src.clkr.hw },
4148
4298
.num_parents = 1,
4149
4299
.flags = CLK_SET_RATE_PARENT,
4150
4300
.ops = &clk_branch2_ops,
···
4158
4310
.enable_mask = BIT(0),
4159
4311
.hw.init = &(struct clk_init_data){
4160
4312
.name = "gcc_gp1_clk",
4161
-
.parent_names = (const char *[]){
4162
-
"gp1_clk_src"
4163
-
},
4313
+
.parent_hws = (const struct clk_hw *[]){
4314
+
&gp1_clk_src.clkr.hw },
4164
4315
.num_parents = 1,
4165
4316
.flags = CLK_SET_RATE_PARENT,
4166
4317
.ops = &clk_branch2_ops,
···
4174
4327
.enable_mask = BIT(0),
4175
4328
.hw.init = &(struct clk_init_data){
4176
4329
.name = "gcc_gp2_clk",
4177
-
.parent_names = (const char *[]){
4178
-
"gp2_clk_src"
4179
-
},
4330
+
.parent_hws = (const struct clk_hw *[]){
4331
+
&gp2_clk_src.clkr.hw },
4180
4332
.num_parents = 1,
4181
4333
.flags = CLK_SET_RATE_PARENT,
4182
4334
.ops = &clk_branch2_ops,
···
4190
4344
.enable_mask = BIT(0),
4191
4345
.hw.init = &(struct clk_init_data){
4192
4346
.name = "gcc_gp3_clk",
4193
-
.parent_names = (const char *[]){
4194
-
"gp3_clk_src"
4195
-
},
4347
+
.parent_hws = (const struct clk_hw *[]){
4348
+
&gp3_clk_src.clkr.hw },
4196
4349
.num_parents = 1,
4197
4350
.flags = CLK_SET_RATE_PARENT,
4198
4351
.ops = &clk_branch2_ops,
···
4213
4368
.clkr.hw.init = &(struct clk_init_data){
4214
4369
.name = "pcie0_rchng_clk_src",
4215
4370
.parent_data = gcc_xo_gpll0,
4216
-
.num_parents = 2,
4371
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
4217
4372
.ops = &clk_rcg2_ops,
4218
4373
},
4219
4374
};