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spi: cadence-qspi: Add a flag for controllers without indirect access support

Renesas RZ/N1 QSPI controllers embed the Cadence IP with some
limitations/simplifications. One of the is that only direct access is
supported, none of the registers related to indirect writes are
populated, so create a flag to avoid these accesses and make sure only
direct accessors are called.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Tested-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://patch.msgid.link/20260122-schneider-6-19-rc1-qspi-v4-11-f9c21419a3e6@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Miquel Raynal (Schneider Electric) and committed by
Mark Brown ae62e7cf 612227b3

+16 -13
+16 -13
drivers/spi/spi-cadence-quadspi.c
··· 47 47 #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) 48 48 #define CQSPI_DISABLE_STIG_MODE BIT(9) 49 49 #define CQSPI_DISABLE_RUNTIME_PM BIT(10) 50 + #define CQSPI_NO_INDIRECT_MODE BIT(11) 50 51 51 52 /* Capabilities */ 52 53 #define CQSPI_SUPPORTS_OCTAL BIT(0) ··· 1426 1425 if (ret) 1427 1426 return ret; 1428 1427 1429 - if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 1428 + if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) || 1429 + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) 1430 1430 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1431 1431 1432 1432 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && ··· 1628 1626 /* Disable all interrupts. */ 1629 1627 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1630 1628 1631 - /* Configure the SRAM split to 1:1 . */ 1632 - writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1629 + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1630 + /* Configure the SRAM split to 1:1 . */ 1631 + writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1632 + /* Load indirect trigger address. */ 1633 + writel(cqspi->trigger_address, 1634 + cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1633 1635 1634 - /* Load indirect trigger address. */ 1635 - writel(cqspi->trigger_address, 1636 - cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1637 - 1638 - /* Program read watermark -- 1/2 of the FIFO. */ 1639 - writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1640 - cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1641 - /* Program write watermark -- 1/8 of the FIFO. */ 1642 - writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1643 - cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1636 + /* Program read watermark -- 1/2 of the FIFO. */ 1637 + writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1638 + cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1639 + /* Program write watermark -- 1/8 of the FIFO. */ 1640 + writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1641 + cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1642 + } 1644 1643 1645 1644 /* Disable direct access controller */ 1646 1645 if (!cqspi->use_direct_mode) {