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clk: qcom: gcc-sdm845: add sdm670 global clock data

The Snapdragon 670 adds and removes some clocks, adds new frequencies, and
adds a new GPLL (Global Phase-Locked Loop) in reference to SDM845, while
also removing some GDSCs. Despite these differences, there are many
similarities with SDM670. Add data for SDM670 in the driver for SDM845 to
reuse the most of the clock data.

Advantages and disadvantages of this approach:
+ maintenance applies to both sdm670 and sdm845 by default
+ less duplicate code (clocks) means smaller distro/pre-built kernels
with all drivers enabled
- clocks for both SoC's must be compiled if the user wants clocks for one
specific SoC (both or none)
- additional testing needed for sdm845 devices

Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F10
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220914013922.198778-4-mailingradian@gmail.com

authored by

Richard Acayan and committed by
Bjorn Andersson ae66b1fe 8e90216d

+396 -2
+2 -2
drivers/clk/qcom/Kconfig
··· 545 545 controller to reset the Q6SSTOP subsystem. 546 546 547 547 config SDM_GCC_845 548 - tristate "SDM845 Global Clock Controller" 548 + tristate "SDM845/SDM670 Global Clock Controller" 549 549 select QCOM_GDSC 550 550 help 551 - Support for the global clock controller on SDM845 devices. 551 + Support for the global clock controller on SDM845 and SDM670 devices. 552 552 Say Y if you want to use peripheral devices such as UART, SPI, 553 553 i2C, USB, UFS, SDDC, PCIe, etc. 554 554
+394
drivers/clk/qcom/gcc-sdm845.c
··· 31 31 P_GPLL0_OUT_EVEN, 32 32 P_GPLL0_OUT_MAIN, 33 33 P_GPLL4_OUT_MAIN, 34 + P_GPLL6_OUT_MAIN, 34 35 P_SLEEP_CLK, 35 36 }; 36 37 ··· 60 59 .enable_mask = BIT(4), 61 60 .hw.init = &(struct clk_init_data){ 62 61 .name = "gpll4", 62 + .parent_data = &(const struct clk_parent_data){ 63 + .fw_name = "bi_tcxo", .name = "bi_tcxo", 64 + }, 65 + .num_parents = 1, 66 + .ops = &clk_alpha_pll_fixed_fabia_ops, 67 + }, 68 + }, 69 + }; 70 + 71 + static struct clk_alpha_pll gpll6 = { 72 + .offset = 0x13000, 73 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 74 + .clkr = { 75 + .enable_reg = 0x52000, 76 + .enable_mask = BIT(6), 77 + .hw.init = &(struct clk_init_data){ 78 + .name = "gpll6", 63 79 .parent_data = &(const struct clk_parent_data){ 64 80 .fw_name = "bi_tcxo", .name = "bi_tcxo", 65 81 }, ··· 212 194 { .hw = &gpll0_out_even.clkr.hw }, 213 195 }; 214 196 197 + static const struct parent_map gcc_parent_map_11[] = { 198 + { P_BI_TCXO, 0 }, 199 + { P_GPLL0_OUT_MAIN, 1 }, 200 + { P_GPLL6_OUT_MAIN, 2 }, 201 + { P_GPLL0_OUT_EVEN, 6 }, 202 + }; 203 + 204 + static const struct clk_parent_data gcc_parent_data_11[] = { 205 + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 206 + { .hw = &gpll0.clkr.hw }, 207 + { .hw = &gpll6.clkr.hw }, 208 + { .hw = &gpll0_out_even.clkr.hw }, 209 + }; 215 210 216 211 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 217 212 F(19200000, P_BI_TCXO, 1, 0, 0), ··· 256 225 .hid_width = 5, 257 226 .parent_map = gcc_parent_map_3, 258 227 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, 228 + .clkr.hw.init = &(struct clk_init_data){ 229 + .name = "gcc_cpuss_rbcpr_clk_src", 230 + .parent_data = gcc_parent_data_8_ao, 231 + .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao), 232 + .ops = &clk_rcg2_ops, 233 + }, 234 + }; 235 + 236 + static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = { 237 + F(19200000, P_BI_TCXO, 1, 0, 0), 238 + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 239 + { } 240 + }; 241 + 242 + static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = { 243 + .cmd_rcgr = 0x4815c, 244 + .mnd_width = 0, 245 + .hid_width = 5, 246 + .parent_map = gcc_parent_map_3, 247 + .freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src, 259 248 .clkr.hw.init = &(struct clk_init_data){ 260 249 .name = "gcc_cpuss_rbcpr_clk_src", 261 250 .parent_data = gcc_parent_data_8_ao, ··· 707 656 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 708 657 }; 709 658 659 + static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 660 + F(144000, P_BI_TCXO, 16, 3, 25), 661 + F(400000, P_BI_TCXO, 12, 1, 4), 662 + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), 663 + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), 664 + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), 665 + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 666 + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), 667 + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), 668 + { } 669 + }; 670 + 671 + static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 672 + .cmd_rcgr = 0x26028, 673 + .mnd_width = 8, 674 + .hid_width = 5, 675 + .parent_map = gcc_parent_map_11, 676 + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, 677 + .clkr.hw.init = &(struct clk_init_data){ 678 + .name = "gcc_sdcc1_apps_clk_src", 679 + .parent_data = gcc_parent_data_11, 680 + .num_parents = ARRAY_SIZE(gcc_parent_data_11), 681 + .ops = &clk_rcg2_floor_ops, 682 + }, 683 + }; 684 + 685 + static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { 686 + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), 687 + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 688 + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 689 + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 690 + { } 691 + }; 692 + 693 + static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 694 + .cmd_rcgr = 0x26010, 695 + .mnd_width = 8, 696 + .hid_width = 5, 697 + .parent_map = gcc_parent_map_0, 698 + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, 699 + .clkr.hw.init = &(struct clk_init_data){ 700 + .name = "gcc_sdcc1_ice_core_clk_src", 701 + .parent_data = gcc_parent_data_0, 702 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 703 + .ops = &clk_rcg2_ops, 704 + }, 705 + }; 706 + 710 707 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 711 708 F(400000, P_BI_TCXO, 12, 1, 4), 712 709 F(9600000, P_BI_TCXO, 2, 0, 0), ··· 796 697 .hid_width = 5, 797 698 .parent_map = gcc_parent_map_0, 798 699 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 700 + .clkr.hw.init = &(struct clk_init_data){ 701 + .name = "gcc_sdcc4_apps_clk_src", 702 + .parent_data = gcc_parent_data_0, 703 + .num_parents = ARRAY_SIZE(gcc_parent_data_0), 704 + .ops = &clk_rcg2_floor_ops, 705 + }, 706 + }; 707 + 708 + static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = { 709 + F(400000, P_BI_TCXO, 12, 1, 4), 710 + F(9600000, P_BI_TCXO, 2, 0, 0), 711 + F(19200000, P_BI_TCXO, 1, 0, 0), 712 + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), 713 + F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), 714 + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 715 + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 716 + { } 717 + }; 718 + 719 + static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = { 720 + .cmd_rcgr = 0x1600c, 721 + .mnd_width = 8, 722 + .hid_width = 5, 723 + .parent_map = gcc_parent_map_0, 724 + .freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src, 799 725 .clkr.hw.init = &(struct clk_init_data){ 800 726 .name = "gcc_sdcc4_apps_clk_src", 801 727 .parent_data = gcc_parent_data_0, ··· 1399 1275 .name = "gcc_cpuss_rbcpr_clk", 1400 1276 .parent_hws = (const struct clk_hw*[]){ 1401 1277 &gcc_cpuss_rbcpr_clk_src.clkr.hw, 1278 + }, 1279 + .num_parents = 1, 1280 + .flags = CLK_SET_RATE_PARENT, 1281 + .ops = &clk_branch2_ops, 1282 + }, 1283 + }, 1284 + }; 1285 + 1286 + /* 1287 + * The source clock frequencies are different for SDM670; define a child clock 1288 + * pointing to the source clock that uses SDM670 frequencies. 1289 + */ 1290 + static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = { 1291 + .halt_reg = 0x48008, 1292 + .halt_check = BRANCH_HALT, 1293 + .clkr = { 1294 + .enable_reg = 0x48008, 1295 + .enable_mask = BIT(0), 1296 + .hw.init = &(struct clk_init_data){ 1297 + .name = "gcc_cpuss_rbcpr_clk", 1298 + .parent_hws = (const struct clk_hw*[]){ 1299 + &gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw, 1402 1300 }, 1403 1301 .num_parents = 1, 1404 1302 .flags = CLK_SET_RATE_PARENT, ··· 2499 2353 }, 2500 2354 }; 2501 2355 2356 + static struct clk_branch gcc_sdcc1_ahb_clk = { 2357 + .halt_reg = 0x26008, 2358 + .halt_check = BRANCH_HALT, 2359 + .clkr = { 2360 + .enable_reg = 0x26008, 2361 + .enable_mask = BIT(0), 2362 + .hw.init = &(struct clk_init_data){ 2363 + .name = "gcc_sdcc1_ahb_clk", 2364 + .ops = &clk_branch2_ops, 2365 + }, 2366 + }, 2367 + }; 2368 + 2369 + static struct clk_branch gcc_sdcc1_apps_clk = { 2370 + .halt_reg = 0x26004, 2371 + .halt_check = BRANCH_HALT, 2372 + .clkr = { 2373 + .enable_reg = 0x26004, 2374 + .enable_mask = BIT(0), 2375 + .hw.init = &(struct clk_init_data){ 2376 + .name = "gcc_sdcc1_apps_clk", 2377 + .parent_hws = (const struct clk_hw*[]){ 2378 + &gcc_sdcc1_apps_clk_src.clkr.hw, 2379 + }, 2380 + .num_parents = 1, 2381 + .flags = CLK_SET_RATE_PARENT, 2382 + .ops = &clk_branch2_ops, 2383 + }, 2384 + }, 2385 + }; 2386 + 2387 + static struct clk_branch gcc_sdcc1_ice_core_clk = { 2388 + .halt_reg = 0x2600c, 2389 + .halt_check = BRANCH_HALT, 2390 + .clkr = { 2391 + .enable_reg = 0x2600c, 2392 + .enable_mask = BIT(0), 2393 + .hw.init = &(struct clk_init_data){ 2394 + .name = "gcc_sdcc1_ice_core_clk", 2395 + .parent_hws = (const struct clk_hw*[]){ 2396 + &gcc_sdcc1_ice_core_clk_src.clkr.hw, 2397 + }, 2398 + .num_parents = 1, 2399 + .flags = CLK_SET_RATE_PARENT, 2400 + .ops = &clk_branch2_ops, 2401 + }, 2402 + }, 2403 + }; 2404 + 2502 2405 static struct clk_branch gcc_sdcc2_ahb_clk = { 2503 2406 .halt_reg = 0x14008, 2504 2407 .halt_check = BRANCH_HALT, ··· 2602 2407 .name = "gcc_sdcc4_apps_clk", 2603 2408 .parent_hws = (const struct clk_hw*[]){ 2604 2409 &gcc_sdcc4_apps_clk_src.clkr.hw, 2410 + }, 2411 + .num_parents = 1, 2412 + .flags = CLK_SET_RATE_PARENT, 2413 + .ops = &clk_branch2_ops, 2414 + }, 2415 + }, 2416 + }; 2417 + 2418 + /* 2419 + * The source clock frequencies are different for SDM670; define a child clock 2420 + * pointing to the source clock that uses SDM670 frequencies. 2421 + */ 2422 + static struct clk_branch gcc_sdm670_sdcc4_apps_clk = { 2423 + .halt_reg = 0x16004, 2424 + .halt_check = BRANCH_HALT, 2425 + .clkr = { 2426 + .enable_reg = 0x16004, 2427 + .enable_mask = BIT(0), 2428 + .hw.init = &(struct clk_init_data){ 2429 + .name = "gcc_sdcc4_apps_clk", 2430 + .parent_hws = (const struct clk_hw*[]){ 2431 + &gcc_sdm670_sdcc4_apps_clk_src.clkr.hw, 2605 2432 }, 2606 2433 .num_parents = 1, 2607 2434 .flags = CLK_SET_RATE_PARENT, ··· 3525 3308 .flags = VOTABLE, 3526 3309 }; 3527 3310 3311 + static struct clk_regmap *gcc_sdm670_clocks[] = { 3312 + [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3313 + [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3314 + [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, 3315 + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3316 + [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, 3317 + [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, 3318 + [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, 3319 + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 3320 + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 3321 + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 3322 + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3323 + [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 3324 + [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 3325 + [GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr, 3326 + [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr, 3327 + [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 3328 + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, 3329 + [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, 3330 + [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, 3331 + [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, 3332 + [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, 3333 + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3334 + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3335 + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3336 + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3337 + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3338 + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3339 + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 3340 + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3341 + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3342 + [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, 3343 + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, 3344 + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 3345 + [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, 3346 + [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, 3347 + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3348 + [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3349 + [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, 3350 + [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, 3351 + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3352 + [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, 3353 + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3354 + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3355 + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3356 + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3357 + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3358 + [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, 3359 + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, 3360 + [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, 3361 + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, 3362 + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, 3363 + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, 3364 + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, 3365 + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, 3366 + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, 3367 + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, 3368 + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, 3369 + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, 3370 + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, 3371 + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, 3372 + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, 3373 + [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, 3374 + [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, 3375 + [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, 3376 + [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, 3377 + [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3378 + [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3379 + [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3380 + [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3381 + [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3382 + [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3383 + [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3384 + [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3385 + [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3386 + [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3387 + [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3388 + [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3389 + [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3390 + [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3391 + [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3392 + [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3393 + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, 3394 + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, 3395 + [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, 3396 + [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3397 + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3398 + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3399 + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, 3400 + [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, 3401 + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 3402 + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3403 + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3404 + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3405 + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3406 + [GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr, 3407 + [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr, 3408 + [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 3409 + [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3410 + [GCC_TSIF_INACTIVITY_TIMERS_CLK] = 3411 + &gcc_tsif_inactivity_timers_clk.clkr, 3412 + [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3413 + [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, 3414 + [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, 3415 + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3416 + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3417 + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3418 + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3419 + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3420 + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3421 + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3422 + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3423 + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3424 + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3425 + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = 3426 + &gcc_ufs_phy_unipro_core_clk_src.clkr, 3427 + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3428 + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3429 + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3430 + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = 3431 + &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3432 + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3433 + [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, 3434 + [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3435 + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3436 + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3437 + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3438 + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3439 + [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, 3440 + [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, 3441 + [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, 3442 + [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, 3443 + [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, 3444 + [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, 3445 + [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, 3446 + [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, 3447 + [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, 3448 + [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, 3449 + [GPLL0] = &gpll0.clkr, 3450 + [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3451 + [GPLL4] = &gpll4.clkr, 3452 + [GPLL6] = &gpll6.clkr, 3453 + [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, 3454 + [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3455 + [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, 3456 + [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, 3457 + [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, 3458 + }; 3459 + 3528 3460 static struct clk_regmap *gcc_sdm845_clocks[] = { 3529 3461 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, 3530 3462 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, ··· 3899 3533 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3900 3534 }; 3901 3535 3536 + static struct gdsc *gcc_sdm670_gdscs[] = { 3537 + [UFS_PHY_GDSC] = &ufs_phy_gdsc, 3538 + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, 3539 + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = 3540 + &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 3541 + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = 3542 + &hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 3543 + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = 3544 + &hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 3545 + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = 3546 + &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 3547 + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = 3548 + &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 3549 + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 3550 + }; 3551 + 3902 3552 static struct gdsc *gcc_sdm845_gdscs[] = { 3903 3553 [PCIE_0_GDSC] = &pcie_0_gdsc, 3904 3554 [PCIE_1_GDSC] = &pcie_1_gdsc, ··· 3945 3563 .fast_io = true, 3946 3564 }; 3947 3565 3566 + static const struct qcom_cc_desc gcc_sdm670_desc = { 3567 + .config = &gcc_sdm845_regmap_config, 3568 + .clks = gcc_sdm670_clocks, 3569 + .num_clks = ARRAY_SIZE(gcc_sdm670_clocks), 3570 + /* Snapdragon 670 can function without its own exclusive resets. */ 3571 + .resets = gcc_sdm845_resets, 3572 + .num_resets = ARRAY_SIZE(gcc_sdm845_resets), 3573 + .gdscs = gcc_sdm670_gdscs, 3574 + .num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs), 3575 + }; 3576 + 3948 3577 static const struct qcom_cc_desc gcc_sdm845_desc = { 3949 3578 .config = &gcc_sdm845_regmap_config, 3950 3579 .clks = gcc_sdm845_clocks, ··· 3967 3574 }; 3968 3575 3969 3576 static const struct of_device_id gcc_sdm845_match_table[] = { 3577 + { .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc }, 3970 3578 { .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc }, 3971 3579 { } 3972 3580 };