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clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control

On MT8196, there are set/clr registers to control a shared PLL enable
register. These are intended to prevent different masters from
manipulating the PLLs independently. Add the corresponding en_set_reg
and en_clr_reg fields to the mtk_pll_data structure.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Laura Nao and committed by
Stephen Boyd aee9ffa0 5e121370

+8
+4
drivers/clk/mediatek/clk-pll.c
··· 308 308 pll->en_addr = base + data->en_reg; 309 309 else 310 310 pll->en_addr = pll->base_addr + REG_CON0; 311 + if (data->en_set_reg) 312 + pll->en_set_addr = base + data->en_set_reg; 313 + if (data->en_clr_reg) 314 + pll->en_clr_addr = base + data->en_clr_reg; 311 315 pll->hw.init = &init; 312 316 pll->data = data; 313 317
+4
drivers/clk/mediatek/clk-pll.h
··· 47 47 const struct mtk_pll_div_table *div_table; 48 48 const char *parent_name; 49 49 u32 en_reg; 50 + u32 en_set_reg; 51 + u32 en_clr_reg; 50 52 u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ 51 53 u8 pcw_chg_bit; 52 54 }; ··· 70 68 void __iomem *pcw_addr; 71 69 void __iomem *pcw_chg_addr; 72 70 void __iomem *en_addr; 71 + void __iomem *en_set_addr; 72 + void __iomem *en_clr_addr; 73 73 const struct mtk_pll_data *data; 74 74 }; 75 75