Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Misc radeon, nouveau, mgag200 and intel fixes.
The intel fixes should contain the fix for the touchpad on the
Chromebook - hey I'm an input maintainer now!"
Hate to pee on your parade, Dave, but I don't think being an input
maintainer is necessarily something to strive for..
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (25 commits)
drm/tegra: drop "select DRM_HDMI"
drm: Documentation typo fixes
drm/mgag200: Bug fix: Renesas board now selects native resolution.
drm/mgag200: Reject modes that are too big for VRAM
drm/mgag200: 'fbdev_list' in 'struct mga_fbdev' is not used
drm/radeon: don't check mipmap alignment if MIP_ADDRESS is FMASK
drm/radeon: skip MC reset as it's probably not hung
drm/radeon: add primary dac adj quirk for R200 board
drm/radeon: don't set hpd, afmt interrupts when interrupts are disabled
drm/i915: Turn off hsync and vsync on ADPA when disabling crt
drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits
drm/i915: also disable south interrupts when handling them
drm/i915: enable irqs earlier when resuming
drm/i915: Increase the RC6p threshold.
DRM/i915: On G45 enable cursor plane briefly after enabling the display plane.
drm/nv50-: prevent some races between modesetting and page flipping
drm/nouveau/i2c: drop parent refcount when creating ports
drm/nv84: fix regression in page flipping
drm/nouveau: Fix typo in init_idx_addr_latched().
drm/nouveau: Disable AGP on PowerPC again.
...
+275
-102
+18
-7
drivers/gpu/drm/i915/i915_drv.c
+18
-7
drivers/gpu/drm/i915/i915_drv.c
···
379
379
INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
380
380
INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
381
381
INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
382
-
INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
382
+
INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
383
+
INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
383
384
INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
384
-
INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
385
-
INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
385
+
INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
386
+
INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
386
387
INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
387
-
INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
388
-
INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
388
+
INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
389
+
INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
389
390
INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
390
-
INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
391
391
INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
392
392
INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
393
393
INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
···
495
495
intel_modeset_disable(dev);
496
496
497
497
drm_irq_uninstall(dev);
498
+
dev_priv->enable_hotplug_processing = false;
498
499
}
499
500
500
501
i915_save_state(dev);
···
569
568
error = i915_gem_init_hw(dev);
570
569
mutex_unlock(&dev->struct_mutex);
571
570
571
+
/* We need working interrupts for modeset enabling ... */
572
+
drm_irq_install(dev);
573
+
572
574
intel_modeset_init_hw(dev);
573
575
intel_modeset_setup_hw_state(dev, false);
574
-
drm_irq_install(dev);
576
+
577
+
/*
578
+
* ... but also need to make sure that hotplug processing
579
+
* doesn't cause havoc. Like in the driver load code we don't
580
+
* bother with the tiny race here where we might loose hotplug
581
+
* notifications.
582
+
* */
575
583
intel_hpd_init(dev);
584
+
dev_priv->enable_hotplug_processing = true;
576
585
}
577
586
578
587
intel_opregion_init(dev);
+24
-2
drivers/gpu/drm/i915/i915_irq.c
+24
-2
drivers/gpu/drm/i915/i915_irq.c
···
701
701
{
702
702
struct drm_device *dev = (struct drm_device *) arg;
703
703
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
704
-
u32 de_iir, gt_iir, de_ier, pm_iir;
704
+
u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
705
705
irqreturn_t ret = IRQ_NONE;
706
706
int i;
707
707
···
710
710
/* disable master interrupt before clearing iir */
711
711
de_ier = I915_READ(DEIER);
712
712
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
713
+
714
+
/* Disable south interrupts. We'll only write to SDEIIR once, so further
715
+
* interrupts will will be stored on its back queue, and then we'll be
716
+
* able to process them after we restore SDEIER (as soon as we restore
717
+
* it, we'll get an interrupt if SDEIIR still has something to process
718
+
* due to its back queue). */
719
+
sde_ier = I915_READ(SDEIER);
720
+
I915_WRITE(SDEIER, 0);
721
+
POSTING_READ(SDEIER);
713
722
714
723
gt_iir = I915_READ(GTIIR);
715
724
if (gt_iir) {
···
768
759
769
760
I915_WRITE(DEIER, de_ier);
770
761
POSTING_READ(DEIER);
762
+
I915_WRITE(SDEIER, sde_ier);
763
+
POSTING_READ(SDEIER);
771
764
772
765
return ret;
773
766
}
···
789
778
struct drm_device *dev = (struct drm_device *) arg;
790
779
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
791
780
int ret = IRQ_NONE;
792
-
u32 de_iir, gt_iir, de_ier, pm_iir;
781
+
u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
793
782
794
783
atomic_inc(&dev_priv->irq_received);
795
784
···
797
786
de_ier = I915_READ(DEIER);
798
787
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
799
788
POSTING_READ(DEIER);
789
+
790
+
/* Disable south interrupts. We'll only write to SDEIIR once, so further
791
+
* interrupts will will be stored on its back queue, and then we'll be
792
+
* able to process them after we restore SDEIER (as soon as we restore
793
+
* it, we'll get an interrupt if SDEIIR still has something to process
794
+
* due to its back queue). */
795
+
sde_ier = I915_READ(SDEIER);
796
+
I915_WRITE(SDEIER, 0);
797
+
POSTING_READ(SDEIER);
800
798
801
799
de_iir = I915_READ(DEIIR);
802
800
gt_iir = I915_READ(GTIIR);
···
869
849
done:
870
850
I915_WRITE(DEIER, de_ier);
871
851
POSTING_READ(DEIER);
852
+
I915_WRITE(SDEIER, sde_ier);
853
+
POSTING_READ(SDEIER);
872
854
873
855
return ret;
874
856
}
+2
-2
drivers/gpu/drm/i915/i915_reg.h
+2
-2
drivers/gpu/drm/i915/i915_reg.h
···
1613
1613
#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1614
1614
#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1615
1615
#define ADPA_SETS_HVPOLARITY 0
1616
-
#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1616
+
#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
1617
1617
#define ADPA_VSYNC_CNTL_ENABLE 0
1618
-
#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1618
+
#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
1619
1619
#define ADPA_HSYNC_CNTL_ENABLE 0
1620
1620
#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1621
1621
#define ADPA_VSYNC_ACTIVE_LOW 0
+1
-1
drivers/gpu/drm/i915/intel_crt.c
+1
-1
drivers/gpu/drm/i915/intel_crt.c
+1
-1
drivers/gpu/drm/i915/intel_ddi.c
+1
-1
drivers/gpu/drm/i915/intel_ddi.c
···
1391
1391
struct intel_dp *intel_dp = &intel_dig_port->dp;
1392
1392
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1393
1393
enum port port = intel_dig_port->port;
1394
-
bool wait;
1395
1394
uint32_t val;
1395
+
bool wait = false;
1396
1396
1397
1397
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1398
1398
val = I915_READ(DDI_BUF_CTL(port));
+30
-7
drivers/gpu/drm/i915/intel_display.c
+30
-7
drivers/gpu/drm/i915/intel_display.c
···
3604
3604
*/
3605
3605
}
3606
3606
3607
+
/**
3608
+
* i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3609
+
* cursor plane briefly if not already running after enabling the display
3610
+
* plane.
3611
+
* This workaround avoids occasional blank screens when self refresh is
3612
+
* enabled.
3613
+
*/
3614
+
static void
3615
+
g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3616
+
{
3617
+
u32 cntl = I915_READ(CURCNTR(pipe));
3618
+
3619
+
if ((cntl & CURSOR_MODE) == 0) {
3620
+
u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3621
+
3622
+
I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3623
+
I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3624
+
intel_wait_for_vblank(dev_priv->dev, pipe);
3625
+
I915_WRITE(CURCNTR(pipe), cntl);
3626
+
I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3627
+
I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3628
+
}
3629
+
}
3630
+
3607
3631
static void i9xx_crtc_enable(struct drm_crtc *crtc)
3608
3632
{
3609
3633
struct drm_device *dev = crtc->dev;
···
3653
3629
3654
3630
intel_enable_pipe(dev_priv, pipe, false);
3655
3631
intel_enable_plane(dev_priv, plane, pipe);
3632
+
if (IS_G4X(dev))
3633
+
g4x_fixup_plane(dev_priv, pipe);
3656
3634
3657
3635
intel_crtc_load_lut(crtc);
3658
3636
intel_update_fbc(dev);
···
7282
7256
{
7283
7257
struct drm_device *dev = crtc->dev;
7284
7258
struct drm_i915_private *dev_priv = dev->dev_private;
7285
-
struct intel_framebuffer *intel_fb;
7286
-
struct drm_i915_gem_object *obj;
7259
+
struct drm_framebuffer *old_fb = crtc->fb;
7260
+
struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7287
7261
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7288
7262
struct intel_unpin_work *work;
7289
7263
unsigned long flags;
···
7308
7282
7309
7283
work->event = event;
7310
7284
work->crtc = crtc;
7311
-
intel_fb = to_intel_framebuffer(crtc->fb);
7312
-
work->old_fb_obj = intel_fb->obj;
7285
+
work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7313
7286
INIT_WORK(&work->work, intel_unpin_work_fn);
7314
7287
7315
7288
ret = drm_vblank_get(dev, intel_crtc->pipe);
···
7327
7302
}
7328
7303
intel_crtc->unpin_work = work;
7329
7304
spin_unlock_irqrestore(&dev->event_lock, flags);
7330
-
7331
-
intel_fb = to_intel_framebuffer(fb);
7332
-
obj = intel_fb->obj;
7333
7305
7334
7306
if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7335
7307
flush_workqueue(dev_priv->wq);
···
7362
7340
7363
7341
cleanup_pending:
7364
7342
atomic_dec(&intel_crtc->unpin_work_count);
7343
+
crtc->fb = old_fb;
7365
7344
drm_gem_object_unreference(&work->old_fb_obj->base);
7366
7345
drm_gem_object_unreference(&obj->base);
7367
7346
mutex_unlock(&dev->struct_mutex);
+2
-1
drivers/gpu/drm/i915/intel_dp.c
+2
-1
drivers/gpu/drm/i915/intel_dp.c
···
353
353
354
354
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
355
355
if (has_aux_irq)
356
-
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
356
+
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
357
+
msecs_to_jiffies(10));
357
358
else
358
359
done = wait_for_atomic(C, 10) == 0;
359
360
if (!done)
+1
-1
drivers/gpu/drm/i915/intel_pm.c
+1
-1
drivers/gpu/drm/i915/intel_pm.c
···
2574
2574
I915_WRITE(GEN6_RC_SLEEP, 0);
2575
2575
I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2576
2576
I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2577
-
I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2577
+
I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2578
2578
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2579
2579
2580
2580
/* Check if we are enabling RC6 */
-1
drivers/gpu/drm/mgag200/mgag200_drv.h
-1
drivers/gpu/drm/mgag200/mgag200_drv.h
+1
drivers/gpu/drm/mgag200/mgag200_i2c.c
+1
drivers/gpu/drm/mgag200/mgag200_i2c.c
+27
drivers/gpu/drm/mgag200/mgag200_mode.c
+27
drivers/gpu/drm/mgag200/mgag200_mode.c
···
1406
1406
static int mga_vga_mode_valid(struct drm_connector *connector,
1407
1407
struct drm_display_mode *mode)
1408
1408
{
1409
+
struct drm_device *dev = connector->dev;
1410
+
struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1411
+
struct mga_fbdev *mfbdev = mdev->mfbdev;
1412
+
struct drm_fb_helper *fb_helper = &mfbdev->helper;
1413
+
struct drm_fb_helper_connector *fb_helper_conn = NULL;
1414
+
int bpp = 32;
1415
+
int i = 0;
1416
+
1409
1417
/* FIXME: Add bandwidth and g200se limitations */
1410
1418
1411
1419
if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1412
1420
mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1413
1421
mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1414
1422
mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1423
+
return MODE_BAD;
1424
+
}
1425
+
1426
+
/* Validate the mode input by the user */
1427
+
for (i = 0; i < fb_helper->connector_count; i++) {
1428
+
if (fb_helper->connector_info[i]->connector == connector) {
1429
+
/* Found the helper for this connector */
1430
+
fb_helper_conn = fb_helper->connector_info[i];
1431
+
if (fb_helper_conn->cmdline_mode.specified) {
1432
+
if (fb_helper_conn->cmdline_mode.bpp_specified) {
1433
+
bpp = fb_helper_conn->cmdline_mode.bpp;
1434
+
}
1435
+
}
1436
+
}
1437
+
}
1438
+
1439
+
if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1440
+
if (fb_helper_conn)
1441
+
fb_helper_conn->cmdline_mode.specified = false;
1415
1442
return MODE_BAD;
1416
1443
}
1417
1444
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+1
-1
drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+1
-1
drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+1
drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
+1
drivers/gpu/drm/nouveau/core/subdev/i2c/base.c
+12
drivers/gpu/drm/nouveau/nouveau_agp.c
+12
drivers/gpu/drm/nouveau/nouveau_agp.c
···
47
47
if (drm->agp.stat == UNKNOWN) {
48
48
if (!nouveau_agpmode)
49
49
return false;
50
+
#ifdef __powerpc__
51
+
/* Disable AGP by default on all PowerPC machines for
52
+
* now -- At least some UniNorth-2 AGP bridges are
53
+
* known to be broken: DMA from the host to the card
54
+
* works just fine, but writeback from the card to the
55
+
* host goes straight to memory untranslated bypassing
56
+
* the GATT somehow, making them quite painful to deal
57
+
* with...
58
+
*/
59
+
if (nouveau_agpmode == -1)
60
+
return false;
61
+
#endif
50
62
return true;
51
63
}
52
64
+102
-71
drivers/gpu/drm/nouveau/nv50_display.c
+102
-71
drivers/gpu/drm/nouveau/nv50_display.c
···
55
55
56
56
/* offsets in shared sync bo of various structures */
57
57
#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
58
-
#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59
-
#define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00)
60
-
#define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10)
58
+
#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59
+
#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
60
+
#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
61
61
62
62
#define EVO_CORE_HANDLE (0xd1500000)
63
63
#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
···
341
341
342
342
struct nv50_sync {
343
343
struct nv50_dmac base;
344
-
struct {
345
-
u32 offset;
346
-
u16 value;
347
-
} sem;
344
+
u32 addr;
345
+
u32 data;
348
346
};
349
347
350
348
struct nv50_ovly {
···
469
471
return nv50_disp(dev)->sync;
470
472
}
471
473
474
+
struct nv50_display_flip {
475
+
struct nv50_disp *disp;
476
+
struct nv50_sync *chan;
477
+
};
478
+
479
+
static bool
480
+
nv50_display_flip_wait(void *data)
481
+
{
482
+
struct nv50_display_flip *flip = data;
483
+
if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
484
+
flip->chan->data);
485
+
return true;
486
+
usleep_range(1, 2);
487
+
return false;
488
+
}
489
+
472
490
void
473
491
nv50_display_flip_stop(struct drm_crtc *crtc)
474
492
{
475
-
struct nv50_sync *sync = nv50_sync(crtc);
493
+
struct nouveau_device *device = nouveau_dev(crtc->dev);
494
+
struct nv50_display_flip flip = {
495
+
.disp = nv50_disp(crtc->dev),
496
+
.chan = nv50_sync(crtc),
497
+
};
476
498
u32 *push;
477
499
478
-
push = evo_wait(sync, 8);
500
+
push = evo_wait(flip.chan, 8);
479
501
if (push) {
480
502
evo_mthd(push, 0x0084, 1);
481
503
evo_data(push, 0x00000000);
···
505
487
evo_data(push, 0x00000000);
506
488
evo_mthd(push, 0x0080, 1);
507
489
evo_data(push, 0x00000000);
508
-
evo_kick(push, sync);
490
+
evo_kick(push, flip.chan);
509
491
}
492
+
493
+
nv_wait_cb(device, nv50_display_flip_wait, &flip);
510
494
}
511
495
512
496
int
···
516
496
struct nouveau_channel *chan, u32 swap_interval)
517
497
{
518
498
struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
519
-
struct nv50_disp *disp = nv50_disp(crtc->dev);
520
499
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
521
500
struct nv50_sync *sync = nv50_sync(crtc);
501
+
int head = nv_crtc->index, ret;
522
502
u32 *push;
523
-
int ret;
524
503
525
504
swap_interval <<= 4;
526
505
if (swap_interval == 0)
···
529
510
if (unlikely(push == NULL))
530
511
return -EBUSY;
531
512
532
-
/* synchronise with the rendering channel, if necessary */
533
-
if (likely(chan)) {
513
+
if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
514
+
ret = RING_SPACE(chan, 8);
515
+
if (ret)
516
+
return ret;
517
+
518
+
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
519
+
OUT_RING (chan, NvEvoSema0 + head);
520
+
OUT_RING (chan, sync->addr ^ 0x10);
521
+
BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
522
+
OUT_RING (chan, sync->data + 1);
523
+
BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
524
+
OUT_RING (chan, sync->addr);
525
+
OUT_RING (chan, sync->data);
526
+
} else
527
+
if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
528
+
u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
529
+
ret = RING_SPACE(chan, 12);
530
+
if (ret)
531
+
return ret;
532
+
533
+
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
534
+
OUT_RING (chan, chan->vram);
535
+
BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
536
+
OUT_RING (chan, upper_32_bits(addr ^ 0x10));
537
+
OUT_RING (chan, lower_32_bits(addr ^ 0x10));
538
+
OUT_RING (chan, sync->data + 1);
539
+
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
540
+
BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
541
+
OUT_RING (chan, upper_32_bits(addr));
542
+
OUT_RING (chan, lower_32_bits(addr));
543
+
OUT_RING (chan, sync->data);
544
+
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
545
+
} else
546
+
if (chan) {
547
+
u64 addr = nv84_fence_crtc(chan, head) + sync->addr;
534
548
ret = RING_SPACE(chan, 10);
535
549
if (ret)
536
550
return ret;
537
551
538
-
if (nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
539
-
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
540
-
OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
541
-
OUT_RING (chan, sync->sem.offset);
542
-
BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
543
-
OUT_RING (chan, 0xf00d0000 | sync->sem.value);
544
-
BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
545
-
OUT_RING (chan, sync->sem.offset ^ 0x10);
546
-
OUT_RING (chan, 0x74b1e000);
547
-
BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
548
-
OUT_RING (chan, NvSema);
549
-
} else
550
-
if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
551
-
u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
552
-
offset += sync->sem.offset;
552
+
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
553
+
OUT_RING (chan, upper_32_bits(addr ^ 0x10));
554
+
OUT_RING (chan, lower_32_bits(addr ^ 0x10));
555
+
OUT_RING (chan, sync->data + 1);
556
+
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
557
+
NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
558
+
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
559
+
OUT_RING (chan, upper_32_bits(addr));
560
+
OUT_RING (chan, lower_32_bits(addr));
561
+
OUT_RING (chan, sync->data);
562
+
OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
563
+
NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
564
+
}
553
565
554
-
BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
555
-
OUT_RING (chan, upper_32_bits(offset));
556
-
OUT_RING (chan, lower_32_bits(offset));
557
-
OUT_RING (chan, 0xf00d0000 | sync->sem.value);
558
-
OUT_RING (chan, 0x00000002);
559
-
BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
560
-
OUT_RING (chan, upper_32_bits(offset));
561
-
OUT_RING (chan, lower_32_bits(offset ^ 0x10));
562
-
OUT_RING (chan, 0x74b1e000);
563
-
OUT_RING (chan, 0x00000001);
564
-
} else {
565
-
u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
566
-
offset += sync->sem.offset;
567
-
568
-
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
569
-
OUT_RING (chan, upper_32_bits(offset));
570
-
OUT_RING (chan, lower_32_bits(offset));
571
-
OUT_RING (chan, 0xf00d0000 | sync->sem.value);
572
-
OUT_RING (chan, 0x00001002);
573
-
BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
574
-
OUT_RING (chan, upper_32_bits(offset));
575
-
OUT_RING (chan, lower_32_bits(offset ^ 0x10));
576
-
OUT_RING (chan, 0x74b1e000);
577
-
OUT_RING (chan, 0x00001001);
578
-
}
579
-
566
+
if (chan) {
567
+
sync->addr ^= 0x10;
568
+
sync->data++;
580
569
FIRE_RING (chan);
581
570
} else {
582
-
nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
583
-
0xf00d0000 | sync->sem.value);
584
571
evo_sync(crtc->dev);
585
572
}
586
573
···
600
575
evo_data(push, 0x40000000);
601
576
}
602
577
evo_mthd(push, 0x0088, 4);
603
-
evo_data(push, sync->sem.offset);
604
-
evo_data(push, 0xf00d0000 | sync->sem.value);
605
-
evo_data(push, 0x74b1e000);
578
+
evo_data(push, sync->addr);
579
+
evo_data(push, sync->data++);
580
+
evo_data(push, sync->data);
606
581
evo_data(push, NvEvoSync);
607
582
evo_mthd(push, 0x00a0, 2);
608
583
evo_data(push, 0x00000000);
···
630
605
evo_mthd(push, 0x0080, 1);
631
606
evo_data(push, 0x00000000);
632
607
evo_kick(push, sync);
633
-
634
-
sync->sem.offset ^= 0x10;
635
-
sync->sem.value++;
636
608
return 0;
637
609
}
638
610
···
1401
1379
if (ret)
1402
1380
goto out;
1403
1381
1404
-
head->sync.sem.offset = EVO_SYNC(1 + index, 0x00);
1382
+
head->sync.addr = EVO_FLIP_SEM0(index);
1383
+
head->sync.data = 0x00000000;
1405
1384
1406
1385
/* allocate overlay resources */
1407
1386
ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
···
2135
2112
int
2136
2113
nv50_display_init(struct drm_device *dev)
2137
2114
{
2138
-
u32 *push = evo_wait(nv50_mast(dev), 32);
2139
-
if (push) {
2140
-
evo_mthd(push, 0x0088, 1);
2141
-
evo_data(push, NvEvoSync);
2142
-
evo_kick(push, nv50_mast(dev));
2143
-
return 0;
2115
+
struct nv50_disp *disp = nv50_disp(dev);
2116
+
struct drm_crtc *crtc;
2117
+
u32 *push;
2118
+
2119
+
push = evo_wait(nv50_mast(dev), 32);
2120
+
if (!push)
2121
+
return -EBUSY;
2122
+
2123
+
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2124
+
struct nv50_sync *sync = nv50_sync(crtc);
2125
+
nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2144
2126
}
2145
2127
2146
-
return -EBUSY;
2128
+
evo_mthd(push, 0x0088, 1);
2129
+
evo_data(push, NvEvoSync);
2130
+
evo_kick(push, nv50_mast(dev));
2131
+
return 0;
2147
2132
}
2148
2133
2149
2134
void
+6
drivers/gpu/drm/radeon/evergreen.c
+6
drivers/gpu/drm/radeon/evergreen.c
···
2438
2438
if (tmp & L2_BUSY)
2439
2439
reset_mask |= RADEON_RESET_VMC;
2440
2440
2441
+
/* Skip MC reset as it's mostly likely not hung, just busy */
2442
+
if (reset_mask & RADEON_RESET_MC) {
2443
+
DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
2444
+
reset_mask &= ~RADEON_RESET_MC;
2445
+
}
2446
+
2441
2447
return reset_mask;
2442
2448
}
2443
2449
+1
-1
drivers/gpu/drm/radeon/evergreen_cs.c
+1
-1
drivers/gpu/drm/radeon/evergreen_cs.c
···
834
834
__func__, __LINE__, toffset, surf.base_align);
835
835
return -EINVAL;
836
836
}
837
-
if (moffset & (surf.base_align - 1)) {
837
+
if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) {
838
838
dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
839
839
__func__, __LINE__, moffset, surf.base_align);
840
840
return -EINVAL;
+6
drivers/gpu/drm/radeon/ni.c
+6
drivers/gpu/drm/radeon/ni.c
···
1381
1381
if (tmp & L2_BUSY)
1382
1382
reset_mask |= RADEON_RESET_VMC;
1383
1383
1384
+
/* Skip MC reset as it's mostly likely not hung, just busy */
1385
+
if (reset_mask & RADEON_RESET_MC) {
1386
+
DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1387
+
reset_mask &= ~RADEON_RESET_MC;
1388
+
}
1389
+
1384
1390
return reset_mask;
1385
1391
}
1386
1392
+6
drivers/gpu/drm/radeon/r600.c
+6
drivers/gpu/drm/radeon/r600.c
···
1394
1394
if (r600_is_display_hung(rdev))
1395
1395
reset_mask |= RADEON_RESET_DISPLAY;
1396
1396
1397
+
/* Skip MC reset as it's mostly likely not hung, just busy */
1398
+
if (reset_mask & RADEON_RESET_MC) {
1399
+
DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1400
+
reset_mask &= ~RADEON_RESET_MC;
1401
+
}
1402
+
1397
1403
return reset_mask;
1398
1404
}
1399
1405
+9
drivers/gpu/drm/radeon/radeon_combios.c
+9
drivers/gpu/drm/radeon/radeon_combios.c
···
970
970
found = 1;
971
971
}
972
972
973
+
/* quirks */
974
+
/* Radeon 9100 (R200) */
975
+
if ((dev->pdev->device == 0x514D) &&
976
+
(dev->pdev->subsystem_vendor == 0x174B) &&
977
+
(dev->pdev->subsystem_device == 0x7149)) {
978
+
/* vbios value is bad, use the default */
979
+
found = 0;
980
+
}
981
+
973
982
if (!found) /* fallback to defaults */
974
983
radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
975
984
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
70
70
* 2.27.0 - r600-SI: Add CS ioctl support for async DMA
71
71
* 2.28.0 - r600-eg: Add MEM_WRITE packet support
72
72
* 2.29.0 - R500 FP16 color clear registers
73
+
* 2.30.0 - fix for FMASK texturing
73
74
*/
74
75
#define KMS_DRIVER_MAJOR 2
75
-
#define KMS_DRIVER_MINOR 29
76
+
#define KMS_DRIVER_MINOR 30
76
77
#define KMS_DRIVER_PATCHLEVEL 0
77
78
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
78
79
int radeon_driver_unload_kms(struct drm_device *dev);
+12
drivers/gpu/drm/radeon/radeon_irq_kms.c
+12
drivers/gpu/drm/radeon/radeon_irq_kms.c
···
400
400
{
401
401
unsigned long irqflags;
402
402
403
+
if (!rdev->ddev->irq_enabled)
404
+
return;
405
+
403
406
spin_lock_irqsave(&rdev->irq.lock, irqflags);
404
407
rdev->irq.afmt[block] = true;
405
408
radeon_irq_set(rdev);
···
421
418
void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block)
422
419
{
423
420
unsigned long irqflags;
421
+
422
+
if (!rdev->ddev->irq_enabled)
423
+
return;
424
424
425
425
spin_lock_irqsave(&rdev->irq.lock, irqflags);
426
426
rdev->irq.afmt[block] = false;
···
444
438
unsigned long irqflags;
445
439
int i;
446
440
441
+
if (!rdev->ddev->irq_enabled)
442
+
return;
443
+
447
444
spin_lock_irqsave(&rdev->irq.lock, irqflags);
448
445
for (i = 0; i < RADEON_MAX_HPD_PINS; ++i)
449
446
rdev->irq.hpd[i] |= !!(hpd_mask & (1 << i));
···
466
457
{
467
458
unsigned long irqflags;
468
459
int i;
460
+
461
+
if (!rdev->ddev->irq_enabled)
462
+
return;
469
463
470
464
spin_lock_irqsave(&rdev->irq.lock, irqflags);
471
465
for (i = 0; i < RADEON_MAX_HPD_PINS; ++i)
+6
drivers/gpu/drm/radeon/si.c
+6
drivers/gpu/drm/radeon/si.c
···
2284
2284
if (tmp & L2_BUSY)
2285
2285
reset_mask |= RADEON_RESET_VMC;
2286
2286
2287
+
/* Skip MC reset as it's mostly likely not hung, just busy */
2288
+
if (reset_mask & RADEON_RESET_MC) {
2289
+
DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
2290
+
reset_mask &= ~RADEON_RESET_MC;
2291
+
}
2292
+
2287
2293
return reset_mask;
2288
2294
}
2289
2295
-1
drivers/gpu/drm/tegra/Kconfig
-1
drivers/gpu/drm/tegra/Kconfig
+3
-3
include/drm/drm_crtc.h
+3
-3
include/drm/drm_crtc.h
···
443
443
* @dpms: set power state (see drm_crtc_funcs above)
444
444
* @save: save connector state
445
445
* @restore: restore connector state
446
-
* @reset: reset connector after state has been invalidate (e.g. resume)
446
+
* @reset: reset connector after state has been invalidated (e.g. resume)
447
447
* @detect: is this connector active?
448
448
* @fill_modes: fill mode list for this connector
449
-
* @set_property: property for this connector may need update
449
+
* @set_property: property for this connector may need an update
450
450
* @destroy: make object go away
451
-
* @force: notify the driver the connector is forced on
451
+
* @force: notify the driver that the connector is forced on
452
452
*
453
453
* Each CRTC may have one or more connectors attached to it. The functions
454
454
* below allow the core DRM code to control connectors, enumerate available modes,