Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf_urgent_for_v5.19_rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fix from Borislav Petkov:
- Reorganize the perf LBR init code so that a TSX quirk is applied
early enough in order for the LBR MSR access to not #GP
* tag 'perf_urgent_for_v5.19_rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
+10
-9
+10
-9
arch/x86/events/intel/lbr.c
+10
-9
arch/x86/events/intel/lbr.c
···
278
278
};
279
279
280
280
/*
281
-
* For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
282
-
* MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
283
-
* TSX is not supported they have no consistent behavior:
281
+
* For format LBR_FORMAT_EIP_FLAGS2, bits 61:62 in MSR_LAST_BRANCH_FROM_x
282
+
* are the TSX flags when TSX is supported, but when TSX is not supported
283
+
* they have no consistent behavior:
284
284
*
285
285
* - For wrmsr(), bits 61:62 are considered part of the sign extension.
286
286
* - For HW updates (branch captures) bits 61:62 are always OFF and are not
···
288
288
*
289
289
* Therefore, if:
290
290
*
291
-
* 1) LBR has TSX format
291
+
* 1) LBR format LBR_FORMAT_EIP_FLAGS2
292
292
* 2) CPU has no TSX support enabled
293
293
*
294
294
* ... then any value passed to wrmsr() must be sign extended to 63 bits and any
···
300
300
bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
301
301
boot_cpu_has(X86_FEATURE_RTM);
302
302
303
-
return !tsx_support && x86_pmu.lbr_has_tsx;
303
+
return !tsx_support;
304
304
}
305
305
306
306
static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
···
1609
1609
x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1610
1610
1611
1611
x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0);
1612
-
1613
-
if (lbr_from_signext_quirk_needed())
1614
-
static_branch_enable(&lbr_from_quirk_key);
1615
1612
}
1616
1613
1617
1614
/* skylake */
···
1699
1702
switch (x86_pmu.intel_cap.lbr_format) {
1700
1703
case LBR_FORMAT_EIP_FLAGS2:
1701
1704
x86_pmu.lbr_has_tsx = 1;
1702
-
fallthrough;
1705
+
x86_pmu.lbr_from_flags = 1;
1706
+
if (lbr_from_signext_quirk_needed())
1707
+
static_branch_enable(&lbr_from_quirk_key);
1708
+
break;
1709
+
1703
1710
case LBR_FORMAT_EIP_FLAGS:
1704
1711
x86_pmu.lbr_from_flags = 1;
1705
1712
break;