tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (23 commits)
[POWERPC] Add arch/powerpc support for the Motorola PrPMC2800
[POWERPC] Add bootwrapper support for Motorola PrPMC2800 platform
[POWERPC] Add DTS file for the Motorola PrPMC2800 platform
[POWERPC] Check cache coherency of kernel vs firmware
[POWERPC] Add Marvell mv64x60 PCI bridge support
[POWERPC] Create Marvell mv64x60 I2C platform_data
[POWERPC] Create Marvell mv64x60 ethernet platform_data
[POWERPC] Create Marvell mv64x60 MPSC (serial) platform_data
[POWERPC] Add interrupt support for Marvell mv64x60 chips
[POWERPC] Add bootwrapper support for Marvell/mv64x60 I2C
[POWERPC] Add bootwrapper support for Marvell MPSC
[POWERPC] Add bootwrapper support for Marvell/mv64x60 hostbridge
[POWERPC] Add Makefile rules to wrap dts file in zImage
[POWERPC] Spelling fixes: arch/ppc/
[POWERPC] U-boot passes the initrd as start/end, not start/size.
[POWERPC] PS3: Update ps3_defconfig
[POWERPC] PS3: Fix request_irq warning
[POWERPC] Don't complain if size-cells == 0 in prom_parse()
[POWERPC] Simplify smp_space_timers
[POWERPC] Trivial ps3 warning fixes
...

Linus Torvalds af3b146d c5b7bede

+4682 -204
+4 -1
arch/powerpc/Kconfig
··· 389 389 bool 390 390 depends on 4xx || 8xx || E200 391 391 default y 392 + 393 + config CONFIG_CHECK_CACHE_COHERENCY 394 + bool 392 395 endmenu 393 396 394 397 source "init/Kconfig" ··· 454 451 455 452 config KEXEC 456 453 bool "kexec system call (EXPERIMENTAL)" 457 - depends on PPC_MULTIPLATFORM && EXPERIMENTAL 454 + depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL 458 455 help 459 456 kexec is a system call that implements the ability to shutdown your 460 457 current kernel, and to start another kernel. It is like a reboot
+1 -1
arch/powerpc/Makefile
··· 148 148 149 149 CPPFLAGS_vmlinux.lds := -Upowerpc 150 150 151 - BOOT_TARGETS = zImage zImage.initrd uImage 151 + BOOT_TARGETS = zImage zImage.initrd zImage.dts zImage.dts_initrd uImage 152 152 153 153 PHONY += $(BOOT_TARGETS) 154 154
+27 -3
arch/powerpc/boot/Makefile
··· 43 43 src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \ 44 44 ns16550.c serial.c simple_alloc.c div64.S util.S \ 45 45 gunzip_util.c elf_util.c $(zlib) devtree.c \ 46 - 44x.c ebony.c 46 + 44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c 47 47 src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \ 48 - cuboot-ebony.c treeboot-ebony.c 48 + cuboot-ebony.c treeboot-ebony.c prpmc2800.c 49 49 src-boot := $(src-wlib) $(src-plat) empty.c 50 50 51 51 src-boot := $(addprefix $(obj)/, $(src-boot)) ··· 132 132 image-$(CONFIG_PPC_EFIKA) += zImage.chrp 133 133 image-$(CONFIG_PPC_PMAC) += zImage.pmac 134 134 image-$(CONFIG_PPC_HOLLY) += zImage.holly-elf 135 + image-$(CONFIG_PPC_PRPMC2800) += zImage.prpmc2800 135 136 image-$(CONFIG_DEFAULT_UIMAGE) += uImage 136 137 137 138 ifneq ($(CONFIG_DEVICE_TREE),"") ··· 155 154 156 155 $(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz 157 156 157 + dts- := $(patsubst zImage%, zImage.dts%, $(image-n) $(image-)) 158 + dts-y := $(patsubst zImage%, zImage.dts%, $(image-y)) 159 + dts-y := $(filter-out $(image-y), $(dts-y)) 160 + targets += $(image-y) $(dts-y) 161 + 162 + dts_initrd- := $(patsubst zImage%, zImage.dts_initrd%, $(image-n) $(image-)) 163 + dts_initrd-y := $(patsubst zImage%, zImage.dts_initrd%, $(image-y)) 164 + dts_initrd-y := $(filter-out $(image-y), $(dts_initrd-y)) 165 + targets += $(image-y) $(dts_initrd-y) 166 + 167 + $(addprefix $(obj)/, $(dts_initrd-y)): $(obj)/ramdisk.image.gz 168 + 158 169 # Don't put the ramdisk on the pattern rule; when its missing make will try 159 170 # the pattern rule with less dependencies that also matches (even with the 160 171 # hard dependency listed). 172 + $(obj)/zImage.dts_initrd.%: vmlinux $(wrapperbits) $(dts) $(obj)/ramdisk.image.gz 173 + $(call if_changed,wrap,$*,$(dts),,$(obj)/ramdisk.image.gz) 174 + 175 + $(obj)/zImage.dts.%: vmlinux $(wrapperbits) $(dts) 176 + $(call if_changed,wrap,$*,$(dts)) 177 + 161 178 $(obj)/zImage.initrd.%: vmlinux $(wrapperbits) 162 179 $(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz) 163 180 ··· 214 195 @rm -f $@; ln $< $@ 215 196 $(obj)/zImage.initrd: $(addprefix $(obj)/, $(initrd-y)) 216 197 @rm -f $@; ln $< $@ 198 + $(obj)/zImage.dts: $(addprefix $(obj)/, $(dts-y)) 199 + @rm -f $@; ln $< $@ 200 + $(obj)/zImage.dts_initrd: $(addprefix $(obj)/, $(dts_initrd-y)) 201 + @rm -f $@; ln $< $@ 202 + 217 203 218 204 install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y)) 219 205 sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $< 220 206 221 207 # anything not in $(targets) 222 208 clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* \ 223 - treeImage.* 209 + treeImage.* zImage.dts zImage.dts_initrd 224 210 225 211 # clean up files cached by wrapper 226 212 clean-kernel := vmlinux.strip vmlinux.bin
+1 -1
arch/powerpc/boot/cuboot-83xx.c
··· 57 57 58 58 memcpy(&bd, (bd_t *)r3, sizeof(bd)); 59 59 loader_info.initrd_addr = r4; 60 - loader_info.initrd_size = r4 ? r5 : 0; 60 + loader_info.initrd_size = r4 ? r5 - r4 : 0; 61 61 loader_info.cmdline = (char *)r6; 62 62 loader_info.cmdline_len = r7 - r6; 63 63
+1 -1
arch/powerpc/boot/cuboot-85xx.c
··· 58 58 59 59 memcpy(&bd, (bd_t *)r3, sizeof(bd)); 60 60 loader_info.initrd_addr = r4; 61 - loader_info.initrd_size = r4 ? r5 : 0; 61 + loader_info.initrd_size = r4 ? r5 - r4 : 0; 62 62 loader_info.cmdline = (char *)r6; 63 63 loader_info.cmdline_len = r7 - r6; 64 64
+315
arch/powerpc/boot/dts/prpmc2800.dts
··· 1 + /* Device Tree Source for Motorola PrPMC2800 2 + * 3 + * Author: Mark A. Greer <mgreer@mvista.com> 4 + * 5 + * 2007 (c) MontaVista, Software, Inc. This file is licensed under 6 + * the terms of the GNU General Public License version 2. This program 7 + * is licensed "as is" without any warranty of any kind, whether express 8 + * or implied. 9 + * 10 + * Property values that are labeled as "Default" will be updated by bootwrapper 11 + * if it can determine the exact PrPMC type. 12 + * 13 + * To build: 14 + * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts 15 + * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts 16 + */ 17 + 18 + / { 19 + #address-cells = <1>; 20 + #size-cells = <1>; 21 + model = "PrPMC280/PrPMC2800"; /* Default */ 22 + compatible = "motorola,PrPMC2800"; 23 + coherency-off; 24 + 25 + cpus { 26 + #address-cells = <1>; 27 + #size-cells = <0>; 28 + 29 + PowerPC,7447 { 30 + device_type = "cpu"; 31 + reg = <0>; 32 + clock-frequency = <2bb0b140>; /* Default (733 MHz) */ 33 + bus-frequency = <7f28155>; /* 133.333333 MHz */ 34 + timebase-frequency = <1fca055>; /* 33.333333 MHz */ 35 + i-cache-line-size = <20>; 36 + d-cache-line-size = <20>; 37 + i-cache-size = <8000>; 38 + d-cache-size = <8000>; 39 + }; 40 + }; 41 + 42 + memory { 43 + device_type = "memory"; 44 + reg = <00000000 20000000>; /* Default (512MB) */ 45 + }; 46 + 47 + mv64x60@f1000000 { /* Marvell Discovery */ 48 + #address-cells = <1>; 49 + #size-cells = <1>; 50 + #interrupt-cells = <1>; 51 + model = "mv64360"; /* Default */ 52 + compatible = "marvell,mv64x60"; 53 + clock-frequency = <7f28155>; /* 133.333333 MHz */ 54 + reg = <f1000000 00010000>; 55 + virtual-reg = <f1000000>; 56 + ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */ 57 + 80000000 80000000 08000000 /* PCI 0 MEM Space */ 58 + a0000000 a0000000 04000000 /* User FLASH */ 59 + 00000000 f1000000 00010000 /* Bridge's regs */ 60 + f2000000 f2000000 00040000>; /* Integrated SRAM */ 61 + 62 + flash@a0000000 { 63 + device_type = "rom"; 64 + compatible = "direct-mapped"; 65 + reg = <a0000000 4000000>; /* Default (64MB) */ 66 + probe-type = "CFI"; 67 + bank-width = <4>; 68 + partitions = <00000000 00100000 /* RO */ 69 + 00100000 00040001 /* RW */ 70 + 00140000 00400000 /* RO */ 71 + 00540000 039c0000 /* RO */ 72 + 03f00000 00100000>; /* RO */ 73 + partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B"; 74 + }; 75 + 76 + mdio { 77 + #address-cells = <1>; 78 + #size-cells = <0>; 79 + device_type = "mdio"; 80 + compatible = "marvell,mv64x60-mdio"; 81 + ethernet-phy@1 { 82 + device_type = "ethernet-phy"; 83 + compatible = "broadcom,bcm5421"; 84 + interrupts = <4c>; /* GPP 12 */ 85 + interrupt-parent = <&/mv64x60/pic>; 86 + reg = <1>; 87 + }; 88 + ethernet-phy@3 { 89 + device_type = "ethernet-phy"; 90 + compatible = "broadcom,bcm5421"; 91 + interrupts = <4c>; /* GPP 12 */ 92 + interrupt-parent = <&/mv64x60/pic>; 93 + reg = <3>; 94 + }; 95 + }; 96 + 97 + ethernet@2000 { 98 + reg = <2000 2000>; 99 + eth0 { 100 + device_type = "network"; 101 + compatible = "marvell,mv64x60-eth"; 102 + block-index = <0>; 103 + interrupts = <20>; 104 + interrupt-parent = <&/mv64x60/pic>; 105 + phy = <&/mv64x60/mdio/ethernet-phy@1>; 106 + local-mac-address = [ 00 00 00 00 00 00 ]; 107 + }; 108 + eth1 { 109 + device_type = "network"; 110 + compatible = "marvell,mv64x60-eth"; 111 + block-index = <1>; 112 + interrupts = <21>; 113 + interrupt-parent = <&/mv64x60/pic>; 114 + phy = <&/mv64x60/mdio/ethernet-phy@3>; 115 + local-mac-address = [ 00 00 00 00 00 00 ]; 116 + }; 117 + }; 118 + 119 + sdma@4000 { 120 + device_type = "dma"; 121 + compatible = "marvell,mv64x60-sdma"; 122 + reg = <4000 c18>; 123 + virtual-reg = <f1004000>; 124 + interrupt-base = <0>; 125 + interrupts = <24>; 126 + interrupt-parent = <&/mv64x60/pic>; 127 + }; 128 + 129 + sdma@6000 { 130 + device_type = "dma"; 131 + compatible = "marvell,mv64x60-sdma"; 132 + reg = <6000 c18>; 133 + virtual-reg = <f1006000>; 134 + interrupt-base = <0>; 135 + interrupts = <26>; 136 + interrupt-parent = <&/mv64x60/pic>; 137 + }; 138 + 139 + brg@b200 { 140 + compatible = "marvell,mv64x60-brg"; 141 + reg = <b200 8>; 142 + clock-src = <8>; 143 + clock-frequency = <7ed6b40>; 144 + current-speed = <2580>; 145 + bcr = <0>; 146 + }; 147 + 148 + brg@b208 { 149 + compatible = "marvell,mv64x60-brg"; 150 + reg = <b208 8>; 151 + clock-src = <8>; 152 + clock-frequency = <7ed6b40>; 153 + current-speed = <2580>; 154 + bcr = <0>; 155 + }; 156 + 157 + cunit@f200 { 158 + reg = <f200 200>; 159 + }; 160 + 161 + mpscrouting@b400 { 162 + reg = <b400 c>; 163 + }; 164 + 165 + mpscintr@b800 { 166 + reg = <b800 100>; 167 + virtual-reg = <f100b800>; 168 + }; 169 + 170 + mpsc@8000 { 171 + device_type = "serial"; 172 + compatible = "marvell,mpsc"; 173 + reg = <8000 38>; 174 + virtual-reg = <f1008000>; 175 + sdma = <&/mv64x60/sdma@4000>; 176 + brg = <&/mv64x60/brg@b200>; 177 + cunit = <&/mv64x60/cunit@f200>; 178 + mpscrouting = <&/mv64x60/mpscrouting@b400>; 179 + mpscintr = <&/mv64x60/mpscintr@b800>; 180 + block-index = <0>; 181 + max_idle = <28>; 182 + chr_1 = <0>; 183 + chr_2 = <0>; 184 + chr_10 = <3>; 185 + mpcr = <0>; 186 + interrupts = <28>; 187 + interrupt-parent = <&/mv64x60/pic>; 188 + }; 189 + 190 + mpsc@9000 { 191 + device_type = "serial"; 192 + compatible = "marvell,mpsc"; 193 + reg = <9000 38>; 194 + virtual-reg = <f1009000>; 195 + sdma = <&/mv64x60/sdma@6000>; 196 + brg = <&/mv64x60/brg@b208>; 197 + cunit = <&/mv64x60/cunit@f200>; 198 + mpscrouting = <&/mv64x60/mpscrouting@b400>; 199 + mpscintr = <&/mv64x60/mpscintr@b800>; 200 + block-index = <1>; 201 + max_idle = <28>; 202 + chr_1 = <0>; 203 + chr_2 = <0>; 204 + chr_10 = <3>; 205 + mpcr = <0>; 206 + interrupts = <2a>; 207 + interrupt-parent = <&/mv64x60/pic>; 208 + }; 209 + 210 + i2c@c000 { 211 + device_type = "i2c"; 212 + compatible = "marvell,mv64x60-i2c"; 213 + reg = <c000 20>; 214 + virtual-reg = <f100c000>; 215 + freq_m = <8>; 216 + freq_n = <3>; 217 + timeout = <3e8>; /* 1000 = 1 second */ 218 + retries = <1>; 219 + interrupts = <25>; 220 + interrupt-parent = <&/mv64x60/pic>; 221 + }; 222 + 223 + pic { 224 + #interrupt-cells = <1>; 225 + #address-cells = <0>; 226 + compatible = "marvell,mv64x60-pic"; 227 + reg = <0000 88>; 228 + interrupt-controller; 229 + }; 230 + 231 + mpp@f000 { 232 + compatible = "marvell,mv64x60-mpp"; 233 + reg = <f000 10>; 234 + }; 235 + 236 + gpp@f100 { 237 + compatible = "marvell,mv64x60-gpp"; 238 + reg = <f100 20>; 239 + }; 240 + 241 + pci@80000000 { 242 + #address-cells = <3>; 243 + #size-cells = <2>; 244 + #interrupt-cells = <1>; 245 + device_type = "pci"; 246 + compatible = "marvell,mv64x60-pci"; 247 + reg = <0cf8 8>; 248 + ranges = <01000000 0 0 88000000 0 01000000 249 + 02000000 0 80000000 80000000 0 08000000>; 250 + bus-range = <0 ff>; 251 + clock-frequency = <3EF1480>; 252 + interrupt-pci-iack = <0c34>; 253 + interrupt-parent = <&/mv64x60/pic>; 254 + interrupt-map-mask = <f800 0 0 7>; 255 + interrupt-map = < 256 + /* IDSEL 0x0a */ 257 + 5000 0 0 1 &/mv64x60/pic 50 258 + 5000 0 0 2 &/mv64x60/pic 51 259 + 5000 0 0 3 &/mv64x60/pic 5b 260 + 5000 0 0 4 &/mv64x60/pic 5d 261 + 262 + /* IDSEL 0x0b */ 263 + 5800 0 0 1 &/mv64x60/pic 5b 264 + 5800 0 0 2 &/mv64x60/pic 5d 265 + 5800 0 0 3 &/mv64x60/pic 50 266 + 5800 0 0 4 &/mv64x60/pic 51 267 + 268 + /* IDSEL 0x0c */ 269 + 6000 0 0 1 &/mv64x60/pic 5b 270 + 6000 0 0 2 &/mv64x60/pic 5d 271 + 6000 0 0 3 &/mv64x60/pic 50 272 + 6000 0 0 4 &/mv64x60/pic 51 273 + 274 + /* IDSEL 0x0d */ 275 + 6800 0 0 1 &/mv64x60/pic 5d 276 + 6800 0 0 2 &/mv64x60/pic 50 277 + 6800 0 0 3 &/mv64x60/pic 51 278 + 6800 0 0 4 &/mv64x60/pic 5b 279 + >; 280 + }; 281 + 282 + cpu-error@0070 { 283 + compatible = "marvell,mv64x60-cpu-error"; 284 + reg = <0070 10 0128 28>; 285 + interrupts = <03>; 286 + interrupt-parent = <&/mv64x60/pic>; 287 + }; 288 + 289 + sram-ctrl@0380 { 290 + compatible = "marvell,mv64x60-sram-ctrl"; 291 + reg = <0380 80>; 292 + interrupts = <0d>; 293 + interrupt-parent = <&/mv64x60/pic>; 294 + }; 295 + 296 + pci-error@1d40 { 297 + compatible = "marvell,mv64x60-pci-error"; 298 + reg = <1d40 40 0c28 4>; 299 + interrupts = <0c>; 300 + interrupt-parent = <&/mv64x60/pic>; 301 + }; 302 + 303 + mem-ctrl@1400 { 304 + compatible = "marvell,mv64x60-mem-ctrl"; 305 + reg = <1400 60>; 306 + interrupts = <11>; 307 + interrupt-parent = <&/mv64x60/pic>; 308 + }; 309 + }; 310 + 311 + chosen { 312 + bootargs = "ip=on console=ttyMM0"; 313 + linux,stdout-path = "/mv64x60@f1000000/mpsc@8000"; 314 + }; 315 + };
+170
arch/powerpc/boot/mpsc.c
··· 1 + /* 2 + * MPSC/UART driver for the Marvell mv64360, mv64460, ... 3 + * 4 + * Author: Mark A. Greer <mgreer@mvista.com> 5 + * 6 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <stdarg.h> 13 + #include <stddef.h> 14 + #include "types.h" 15 + #include "string.h" 16 + #include "stdio.h" 17 + #include "io.h" 18 + #include "ops.h" 19 + 20 + extern void udelay(long delay); 21 + 22 + #define MPSC_CHR_1 0x000c 23 + 24 + #define MPSC_CHR_2 0x0010 25 + #define MPSC_CHR_2_TA (1<<7) 26 + #define MPSC_CHR_2_TCS (1<<9) 27 + #define MPSC_CHR_2_RA (1<<23) 28 + #define MPSC_CHR_2_CRD (1<<25) 29 + #define MPSC_CHR_2_EH (1<<31) 30 + 31 + #define MPSC_CHR_4 0x0018 32 + #define MPSC_CHR_4_Z (1<<29) 33 + 34 + #define MPSC_CHR_5 0x001c 35 + #define MPSC_CHR_5_CTL1_INTR (1<<12) 36 + #define MPSC_CHR_5_CTL1_VALID (1<<15) 37 + 38 + #define MPSC_CHR_10 0x0030 39 + 40 + #define MPSC_INTR_CAUSE 0x0000 41 + #define MPSC_INTR_CAUSE_RCC (1<<6) 42 + #define MPSC_INTR_MASK 0x0080 43 + 44 + #define SDMA_SDCM 0x0008 45 + #define SDMA_SDCM_AR (1<<15) 46 + #define SDMA_SDCM_AT (1<<31) 47 + 48 + static volatile char *mpsc_base; 49 + static volatile char *mpscintr_base; 50 + static u32 chr1, chr2; 51 + 52 + static int mpsc_open(void) 53 + { 54 + chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000; 55 + chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA 56 + | MPSC_CHR_2_TCS | MPSC_CHR_2_RA | MPSC_CHR_2_CRD 57 + | MPSC_CHR_2_EH); 58 + out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z); 59 + out_le32((u32 *)(mpsc_base + MPSC_CHR_5), 60 + MPSC_CHR_5_CTL1_INTR | MPSC_CHR_5_CTL1_VALID); 61 + out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH); 62 + return 0; 63 + } 64 + 65 + static void mpsc_putc(unsigned char c) 66 + { 67 + while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS); 68 + 69 + out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c); 70 + out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS); 71 + } 72 + 73 + static unsigned char mpsc_getc(void) 74 + { 75 + u32 cause = 0; 76 + unsigned char c; 77 + 78 + while (!(cause & MPSC_INTR_CAUSE_RCC)) 79 + cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE)); 80 + 81 + c = in_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2)); 82 + out_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2), c); 83 + out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 84 + cause & ~MPSC_INTR_CAUSE_RCC); 85 + 86 + return c; 87 + } 88 + 89 + static u8 mpsc_tstc(void) 90 + { 91 + return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE)) 92 + & MPSC_INTR_CAUSE_RCC) != 0); 93 + } 94 + 95 + static void mpsc_stop_dma(volatile char *sdma_base) 96 + { 97 + out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA); 98 + out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT); 99 + 100 + while ((in_le32((u32 *)(sdma_base + SDMA_SDCM)) 101 + & (SDMA_SDCM_AR | SDMA_SDCM_AT)) != 0) 102 + udelay(100); 103 + } 104 + 105 + static volatile char *mpsc_get_virtreg_of_phandle(void *devp, char *prop) 106 + { 107 + void *v; 108 + int n; 109 + 110 + n = getprop(devp, prop, &v, sizeof(v)); 111 + if (n != sizeof(v)) 112 + goto err_out; 113 + 114 + devp = find_node_by_linuxphandle((u32)v); 115 + if (devp == NULL) 116 + goto err_out; 117 + 118 + n = getprop(devp, "virtual-reg", &v, sizeof(v)); 119 + if (n == sizeof(v)) 120 + return v; 121 + 122 + err_out: 123 + return NULL; 124 + } 125 + 126 + int mpsc_console_init(void *devp, struct serial_console_data *scdp) 127 + { 128 + void *v; 129 + int n, reg_set; 130 + volatile char *sdma_base; 131 + 132 + n = getprop(devp, "virtual-reg", &v, sizeof(v)); 133 + if (n != sizeof(v)) 134 + goto err_out; 135 + mpsc_base = v; 136 + 137 + sdma_base = mpsc_get_virtreg_of_phandle(devp, "sdma"); 138 + if (sdma_base == NULL) 139 + goto err_out; 140 + 141 + mpscintr_base = mpsc_get_virtreg_of_phandle(devp, "mpscintr"); 142 + if (mpscintr_base == NULL) 143 + goto err_out; 144 + 145 + n = getprop(devp, "block-index", &v, sizeof(v)); 146 + if (n != sizeof(v)) 147 + goto err_out; 148 + reg_set = (int)v; 149 + 150 + mpscintr_base += (reg_set == 0) ? 0x4 : 0xc; 151 + 152 + /* Make sure the mpsc ctlrs are shutdown */ 153 + out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0); 154 + out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0); 155 + out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0); 156 + out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0); 157 + 158 + mpsc_stop_dma(sdma_base); 159 + 160 + scdp->open = mpsc_open; 161 + scdp->putc = mpsc_putc; 162 + scdp->getc = mpsc_getc; 163 + scdp->tstc = mpsc_tstc; 164 + scdp->close = NULL; 165 + 166 + return 0; 167 + 168 + err_out: 169 + return -1; 170 + }
+581
arch/powerpc/boot/mv64x60.c
··· 1 + /* 2 + * Marvell hostbridge routines 3 + * 4 + * Author: Mark A. Greer <source@mvista.com> 5 + * 6 + * 2004, 2005, 2007 (c) MontaVista Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <stdarg.h> 13 + #include <stddef.h> 14 + #include "types.h" 15 + #include "elf.h" 16 + #include "page.h" 17 + #include "string.h" 18 + #include "stdio.h" 19 + #include "io.h" 20 + #include "ops.h" 21 + #include "mv64x60.h" 22 + 23 + #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 24 + 25 + #define MV64x60_CPU2MEM_WINDOWS 4 26 + #define MV64x60_CPU2MEM_0_BASE 0x0008 27 + #define MV64x60_CPU2MEM_0_SIZE 0x0010 28 + #define MV64x60_CPU2MEM_1_BASE 0x0208 29 + #define MV64x60_CPU2MEM_1_SIZE 0x0210 30 + #define MV64x60_CPU2MEM_2_BASE 0x0018 31 + #define MV64x60_CPU2MEM_2_SIZE 0x0020 32 + #define MV64x60_CPU2MEM_3_BASE 0x0218 33 + #define MV64x60_CPU2MEM_3_SIZE 0x0220 34 + 35 + #define MV64x60_ENET2MEM_BAR_ENABLE 0x2290 36 + #define MV64x60_ENET2MEM_0_BASE 0x2200 37 + #define MV64x60_ENET2MEM_0_SIZE 0x2204 38 + #define MV64x60_ENET2MEM_1_BASE 0x2208 39 + #define MV64x60_ENET2MEM_1_SIZE 0x220c 40 + #define MV64x60_ENET2MEM_2_BASE 0x2210 41 + #define MV64x60_ENET2MEM_2_SIZE 0x2214 42 + #define MV64x60_ENET2MEM_3_BASE 0x2218 43 + #define MV64x60_ENET2MEM_3_SIZE 0x221c 44 + #define MV64x60_ENET2MEM_4_BASE 0x2220 45 + #define MV64x60_ENET2MEM_4_SIZE 0x2224 46 + #define MV64x60_ENET2MEM_5_BASE 0x2228 47 + #define MV64x60_ENET2MEM_5_SIZE 0x222c 48 + #define MV64x60_ENET2MEM_ACC_PROT_0 0x2294 49 + #define MV64x60_ENET2MEM_ACC_PROT_1 0x2298 50 + #define MV64x60_ENET2MEM_ACC_PROT_2 0x229c 51 + 52 + #define MV64x60_MPSC2MEM_BAR_ENABLE 0xf250 53 + #define MV64x60_MPSC2MEM_0_BASE 0xf200 54 + #define MV64x60_MPSC2MEM_0_SIZE 0xf204 55 + #define MV64x60_MPSC2MEM_1_BASE 0xf208 56 + #define MV64x60_MPSC2MEM_1_SIZE 0xf20c 57 + #define MV64x60_MPSC2MEM_2_BASE 0xf210 58 + #define MV64x60_MPSC2MEM_2_SIZE 0xf214 59 + #define MV64x60_MPSC2MEM_3_BASE 0xf218 60 + #define MV64x60_MPSC2MEM_3_SIZE 0xf21c 61 + #define MV64x60_MPSC_0_REMAP 0xf240 62 + #define MV64x60_MPSC_1_REMAP 0xf244 63 + #define MV64x60_MPSC2MEM_ACC_PROT_0 0xf254 64 + #define MV64x60_MPSC2MEM_ACC_PROT_1 0xf258 65 + #define MV64x60_MPSC2REGS_BASE 0xf25c 66 + 67 + #define MV64x60_IDMA2MEM_BAR_ENABLE 0x0a80 68 + #define MV64x60_IDMA2MEM_0_BASE 0x0a00 69 + #define MV64x60_IDMA2MEM_0_SIZE 0x0a04 70 + #define MV64x60_IDMA2MEM_1_BASE 0x0a08 71 + #define MV64x60_IDMA2MEM_1_SIZE 0x0a0c 72 + #define MV64x60_IDMA2MEM_2_BASE 0x0a10 73 + #define MV64x60_IDMA2MEM_2_SIZE 0x0a14 74 + #define MV64x60_IDMA2MEM_3_BASE 0x0a18 75 + #define MV64x60_IDMA2MEM_3_SIZE 0x0a1c 76 + #define MV64x60_IDMA2MEM_4_BASE 0x0a20 77 + #define MV64x60_IDMA2MEM_4_SIZE 0x0a24 78 + #define MV64x60_IDMA2MEM_5_BASE 0x0a28 79 + #define MV64x60_IDMA2MEM_5_SIZE 0x0a2c 80 + #define MV64x60_IDMA2MEM_6_BASE 0x0a30 81 + #define MV64x60_IDMA2MEM_6_SIZE 0x0a34 82 + #define MV64x60_IDMA2MEM_7_BASE 0x0a38 83 + #define MV64x60_IDMA2MEM_7_SIZE 0x0a3c 84 + #define MV64x60_IDMA2MEM_ACC_PROT_0 0x0a70 85 + #define MV64x60_IDMA2MEM_ACC_PROT_1 0x0a74 86 + #define MV64x60_IDMA2MEM_ACC_PROT_2 0x0a78 87 + #define MV64x60_IDMA2MEM_ACC_PROT_3 0x0a7c 88 + 89 + #define MV64x60_PCI_ACC_CNTL_WINDOWS 6 90 + #define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c 91 + #define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc 92 + 93 + #define MV64x60_PCI0_BAR_ENABLE 0x0c3c 94 + #define MV64x60_PCI02MEM_0_SIZE 0x0c08 95 + #define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00 96 + #define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04 97 + #define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08 98 + #define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10 99 + #define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14 100 + #define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18 101 + #define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20 102 + #define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24 103 + #define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28 104 + #define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30 105 + #define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34 106 + #define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38 107 + #define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40 108 + #define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44 109 + #define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48 110 + #define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50 111 + #define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54 112 + #define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58 113 + 114 + #define MV64x60_PCI1_BAR_ENABLE 0x0cbc 115 + #define MV64x60_PCI12MEM_0_SIZE 0x0c88 116 + #define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80 117 + #define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84 118 + #define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88 119 + #define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90 120 + #define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94 121 + #define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98 122 + #define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0 123 + #define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4 124 + #define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8 125 + #define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0 126 + #define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4 127 + #define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8 128 + #define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0 129 + #define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4 130 + #define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8 131 + #define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0 132 + #define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4 133 + #define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8 134 + 135 + #define MV64x60_CPU2PCI_SWAP_NONE 0x01000000 136 + 137 + #define MV64x60_CPU2PCI0_IO_BASE 0x0048 138 + #define MV64x60_CPU2PCI0_IO_SIZE 0x0050 139 + #define MV64x60_CPU2PCI0_IO_REMAP 0x00f0 140 + #define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058 141 + #define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060 142 + #define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8 143 + #define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320 144 + 145 + #define MV64x60_CPU2PCI1_IO_BASE 0x0090 146 + #define MV64x60_CPU2PCI1_IO_SIZE 0x0098 147 + #define MV64x60_CPU2PCI1_IO_REMAP 0x0108 148 + #define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0 149 + #define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8 150 + #define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110 151 + #define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340 152 + 153 + struct mv64x60_mem_win { 154 + u32 hi; 155 + u32 lo; 156 + u32 size; 157 + }; 158 + 159 + struct mv64x60_pci_win { 160 + u32 fcn; 161 + u32 hi; 162 + u32 lo; 163 + u32 size; 164 + }; 165 + 166 + /* PCI config access routines */ 167 + struct { 168 + u32 addr; 169 + u32 data; 170 + } static mv64x60_pci_cfgio[2] = { 171 + { /* hose 0 */ 172 + .addr = 0xcf8, 173 + .data = 0xcfc, 174 + }, 175 + { /* hose 1 */ 176 + .addr = 0xc78, 177 + .data = 0xc7c, 178 + } 179 + }; 180 + 181 + u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset) 182 + { 183 + out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), 184 + (1 << 31) | (bus << 16) | (devfn << 8) | offset); 185 + return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data)); 186 + } 187 + 188 + void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset, 189 + u32 val) 190 + { 191 + out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), 192 + (1 << 31) | (bus << 16) | (devfn << 8) | offset); 193 + out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val); 194 + } 195 + 196 + /* I/O ctlr -> system memory setup */ 197 + static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = { 198 + { 199 + .lo = MV64x60_CPU2MEM_0_BASE, 200 + .size = MV64x60_CPU2MEM_0_SIZE, 201 + }, 202 + { 203 + .lo = MV64x60_CPU2MEM_1_BASE, 204 + .size = MV64x60_CPU2MEM_1_SIZE, 205 + }, 206 + { 207 + .lo = MV64x60_CPU2MEM_2_BASE, 208 + .size = MV64x60_CPU2MEM_2_SIZE, 209 + }, 210 + { 211 + .lo = MV64x60_CPU2MEM_3_BASE, 212 + .size = MV64x60_CPU2MEM_3_SIZE, 213 + }, 214 + }; 215 + 216 + static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = { 217 + { 218 + .lo = MV64x60_ENET2MEM_0_BASE, 219 + .size = MV64x60_ENET2MEM_0_SIZE, 220 + }, 221 + { 222 + .lo = MV64x60_ENET2MEM_1_BASE, 223 + .size = MV64x60_ENET2MEM_1_SIZE, 224 + }, 225 + { 226 + .lo = MV64x60_ENET2MEM_2_BASE, 227 + .size = MV64x60_ENET2MEM_2_SIZE, 228 + }, 229 + { 230 + .lo = MV64x60_ENET2MEM_3_BASE, 231 + .size = MV64x60_ENET2MEM_3_SIZE, 232 + }, 233 + }; 234 + 235 + static struct mv64x60_mem_win mv64x60_mpsc2mem[MV64x60_CPU2MEM_WINDOWS] = { 236 + { 237 + .lo = MV64x60_MPSC2MEM_0_BASE, 238 + .size = MV64x60_MPSC2MEM_0_SIZE, 239 + }, 240 + { 241 + .lo = MV64x60_MPSC2MEM_1_BASE, 242 + .size = MV64x60_MPSC2MEM_1_SIZE, 243 + }, 244 + { 245 + .lo = MV64x60_MPSC2MEM_2_BASE, 246 + .size = MV64x60_MPSC2MEM_2_SIZE, 247 + }, 248 + { 249 + .lo = MV64x60_MPSC2MEM_3_BASE, 250 + .size = MV64x60_MPSC2MEM_3_SIZE, 251 + }, 252 + }; 253 + 254 + static struct mv64x60_mem_win mv64x60_idma2mem[MV64x60_CPU2MEM_WINDOWS] = { 255 + { 256 + .lo = MV64x60_IDMA2MEM_0_BASE, 257 + .size = MV64x60_IDMA2MEM_0_SIZE, 258 + }, 259 + { 260 + .lo = MV64x60_IDMA2MEM_1_BASE, 261 + .size = MV64x60_IDMA2MEM_1_SIZE, 262 + }, 263 + { 264 + .lo = MV64x60_IDMA2MEM_2_BASE, 265 + .size = MV64x60_IDMA2MEM_2_SIZE, 266 + }, 267 + { 268 + .lo = MV64x60_IDMA2MEM_3_BASE, 269 + .size = MV64x60_IDMA2MEM_3_SIZE, 270 + }, 271 + }; 272 + 273 + static u32 mv64x60_dram_selects[MV64x60_CPU2MEM_WINDOWS] = {0xe,0xd,0xb,0x7}; 274 + 275 + /* 276 + * ENET, MPSC, and IDMA ctlrs on the MV64x60 have separate windows that 277 + * must be set up so that the respective ctlr can access system memory. 278 + * Configure them to be same as cpu->memory windows. 279 + */ 280 + void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, 281 + u8 is_coherent) 282 + { 283 + u32 i, base, size, enables, prot = 0, snoop_bits = 0; 284 + 285 + /* Disable ctlr->mem windows */ 286 + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f); 287 + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf); 288 + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff); 289 + 290 + if (is_coherent) 291 + snoop_bits = 0x2 << 12; /* Writeback */ 292 + 293 + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf; 294 + 295 + for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) { 296 + if (enables & (1 << i)) /* Set means disabled */ 297 + continue; 298 + 299 + base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo)) 300 + << 16; 301 + base |= snoop_bits | (mv64x60_dram_selects[i] << 8); 302 + size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size)) 303 + << 16; 304 + prot |= (0x3 << (i << 1)); /* RW access */ 305 + 306 + out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base); 307 + out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size); 308 + out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base); 309 + out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size); 310 + out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base); 311 + out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size); 312 + } 313 + 314 + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot); 315 + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot); 316 + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot); 317 + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot); 318 + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot); 319 + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot); 320 + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot); 321 + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot); 322 + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot); 323 + 324 + /* Set mpsc->bridge's reg window to the bridge's internal registers. */ 325 + out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE), 326 + (u32)bridge_pbase); 327 + 328 + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables); 329 + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables); 330 + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables); 331 + } 332 + 333 + /* PCI MEM -> system memory, et. al. setup */ 334 + static struct mv64x60_pci_win mv64x60_pci2mem[2] = { 335 + { /* hose 0 */ 336 + .fcn = 0, 337 + .hi = 0x14, 338 + .lo = 0x10, 339 + .size = MV64x60_PCI02MEM_0_SIZE, 340 + }, 341 + { /* hose 1 */ 342 + .fcn = 0, 343 + .hi = 0x94, 344 + .lo = 0x90, 345 + .size = MV64x60_PCI12MEM_0_SIZE, 346 + }, 347 + }; 348 + 349 + static struct 350 + mv64x60_mem_win mv64x60_pci_acc[2][MV64x60_PCI_ACC_CNTL_WINDOWS] = { 351 + { /* hose 0 */ 352 + { 353 + .hi = MV64x60_PCI0_ACC_CNTL_0_BASE_HI, 354 + .lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO, 355 + .size = MV64x60_PCI0_ACC_CNTL_0_SIZE, 356 + }, 357 + { 358 + .hi = MV64x60_PCI0_ACC_CNTL_1_BASE_HI, 359 + .lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO, 360 + .size = MV64x60_PCI0_ACC_CNTL_1_SIZE, 361 + }, 362 + { 363 + .hi = MV64x60_PCI0_ACC_CNTL_2_BASE_HI, 364 + .lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO, 365 + .size = MV64x60_PCI0_ACC_CNTL_2_SIZE, 366 + }, 367 + { 368 + .hi = MV64x60_PCI0_ACC_CNTL_3_BASE_HI, 369 + .lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO, 370 + .size = MV64x60_PCI0_ACC_CNTL_3_SIZE, 371 + }, 372 + }, 373 + { /* hose 1 */ 374 + { 375 + .hi = MV64x60_PCI1_ACC_CNTL_0_BASE_HI, 376 + .lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO, 377 + .size = MV64x60_PCI1_ACC_CNTL_0_SIZE, 378 + }, 379 + { 380 + .hi = MV64x60_PCI1_ACC_CNTL_1_BASE_HI, 381 + .lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO, 382 + .size = MV64x60_PCI1_ACC_CNTL_1_SIZE, 383 + }, 384 + { 385 + .hi = MV64x60_PCI1_ACC_CNTL_2_BASE_HI, 386 + .lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO, 387 + .size = MV64x60_PCI1_ACC_CNTL_2_SIZE, 388 + }, 389 + { 390 + .hi = MV64x60_PCI1_ACC_CNTL_3_BASE_HI, 391 + .lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO, 392 + .size = MV64x60_PCI1_ACC_CNTL_3_SIZE, 393 + }, 394 + }, 395 + }; 396 + 397 + static struct mv64x60_mem_win mv64x60_pci2reg[2] = { 398 + { 399 + .hi = 0x24, 400 + .lo = 0x20, 401 + .size = 0, 402 + }, 403 + { 404 + .hi = 0xa4, 405 + .lo = 0xa0, 406 + .size = 0, 407 + }, 408 + }; 409 + 410 + /* Only need to use 1 window (per hose) to get access to all of system memory */ 411 + void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, 412 + u8 bus, u32 mem_size, u32 acc_bits) 413 + { 414 + u32 i, offset, bar_enable, enables; 415 + 416 + /* Disable all windows but PCI MEM -> Bridge's regs window */ 417 + enables = ~(1 << 9); 418 + bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE; 419 + out_le32((u32 *)(bridge_base + bar_enable), enables); 420 + 421 + for (i=0; i<MV64x60_PCI_ACC_CNTL_WINDOWS; i++) 422 + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0); 423 + 424 + /* If mem_size is 0, leave windows disabled */ 425 + if (mem_size == 0) 426 + return; 427 + 428 + /* Cause automatic updates of PCI remap regs */ 429 + offset = hose ? 430 + MV64x60_PCI1_PCI_DECODE_CNTL : MV64x60_PCI0_PCI_DECODE_CNTL; 431 + i = in_le32((u32 *)(bridge_base + offset)); 432 + out_le32((u32 *)(bridge_base + offset), i & ~0x1); 433 + 434 + mem_size = (mem_size - 1) & 0xfffff000; 435 + 436 + /* Map PCI MEM addr 0 -> System Mem addr 0 */ 437 + mv64x60_cfg_write(bridge_base, hose, bus, 438 + PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn), 439 + mv64x60_pci2mem[hose].hi, 0); 440 + mv64x60_cfg_write(bridge_base, hose, bus, 441 + PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn), 442 + mv64x60_pci2mem[hose].lo, 0); 443 + out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size); 444 + 445 + acc_bits |= MV64x60_PCI_ACC_CNTL_ENABLE; 446 + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0); 447 + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits); 448 + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size); 449 + 450 + /* Set PCI MEM->bridge's reg window to where they are in CPU mem map */ 451 + i = (u32)bridge_base; 452 + i &= 0xffff0000; 453 + i |= (0x2 << 1); 454 + mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0), 455 + mv64x60_pci2reg[hose].hi, 0); 456 + mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0), 457 + mv64x60_pci2reg[hose].lo, i); 458 + 459 + enables &= ~0x1; /* Enable PCI MEM -> System Mem window 0 */ 460 + out_le32((u32 *)(bridge_base + bar_enable), enables); 461 + } 462 + 463 + /* CPU -> PCI I/O & MEM setup */ 464 + struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2] = { 465 + { /* hose 0 */ 466 + .lo = MV64x60_CPU2PCI0_IO_BASE, 467 + .size = MV64x60_CPU2PCI0_IO_SIZE, 468 + .remap_hi = 0, 469 + .remap_lo = MV64x60_CPU2PCI0_IO_REMAP, 470 + }, 471 + { /* hose 1 */ 472 + .lo = MV64x60_CPU2PCI1_IO_BASE, 473 + .size = MV64x60_CPU2PCI1_IO_SIZE, 474 + .remap_hi = 0, 475 + .remap_lo = MV64x60_CPU2PCI1_IO_REMAP, 476 + }, 477 + }; 478 + 479 + struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2] = { 480 + { /* hose 0 */ 481 + .lo = MV64x60_CPU2PCI0_MEM_0_BASE, 482 + .size = MV64x60_CPU2PCI0_MEM_0_SIZE, 483 + .remap_hi = MV64x60_CPU2PCI0_MEM_0_REMAP_HI, 484 + .remap_lo = MV64x60_CPU2PCI0_MEM_0_REMAP_LO, 485 + }, 486 + { /* hose 1 */ 487 + .lo = MV64x60_CPU2PCI1_MEM_0_BASE, 488 + .size = MV64x60_CPU2PCI1_MEM_0_SIZE, 489 + .remap_hi = MV64x60_CPU2PCI1_MEM_0_REMAP_HI, 490 + .remap_lo = MV64x60_CPU2PCI1_MEM_0_REMAP_LO, 491 + }, 492 + }; 493 + 494 + /* Only need to set up 1 window to pci mem space */ 495 + void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, 496 + u32 pci_base_lo, u32 cpu_base, u32 size, 497 + struct mv64x60_cpu2pci_win *offset_tbl) 498 + { 499 + cpu_base >>= 16; 500 + cpu_base |= MV64x60_CPU2PCI_SWAP_NONE; 501 + out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base); 502 + 503 + if (offset_tbl[hose].remap_hi != 0) 504 + out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi), 505 + pci_base_hi); 506 + out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo), 507 + pci_base_lo >> 16); 508 + 509 + size = (size - 1) >> 16; 510 + out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size); 511 + } 512 + 513 + /* Read mem ctlr to get the amount of mem in system */ 514 + u32 mv64x60_get_mem_size(u8 *bridge_base) 515 + { 516 + u32 enables, i, v; 517 + u32 mem = 0; 518 + 519 + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf; 520 + 521 + for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) 522 + if (!(enables & (1<<i))) { 523 + v = in_le32((u32*)(bridge_base 524 + + mv64x60_cpu2mem[i].size)); 525 + v = ((v & 0xffff) + 1) << 16; 526 + mem += v; 527 + } 528 + 529 + return mem; 530 + } 531 + 532 + /* Get physical address of bridge's registers */ 533 + u8 *mv64x60_get_bridge_pbase(void) 534 + { 535 + u32 v[2]; 536 + void *devp; 537 + 538 + devp = finddevice("/mv64x60"); 539 + if (devp == NULL) 540 + goto err_out; 541 + if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v)) 542 + goto err_out; 543 + 544 + return (u8 *)v[0]; 545 + 546 + err_out: 547 + return 0; 548 + } 549 + 550 + /* Get virtual address of bridge's registers */ 551 + u8 *mv64x60_get_bridge_base(void) 552 + { 553 + u32 v; 554 + void *devp; 555 + 556 + devp = finddevice("/mv64x60"); 557 + if (devp == NULL) 558 + goto err_out; 559 + if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) 560 + goto err_out; 561 + 562 + return (u8 *)v; 563 + 564 + err_out: 565 + return 0; 566 + } 567 + 568 + u8 mv64x60_is_coherent(void) 569 + { 570 + u32 v; 571 + void *devp; 572 + 573 + devp = finddevice("/"); 574 + if (devp == NULL) 575 + return 1; /* Assume coherency on */ 576 + 577 + if (getprop(devp, "coherency-off", &v, sizeof(v)) < 0) 578 + return 1; /* Coherency on */ 579 + else 580 + return 0; 581 + }
+70
arch/powerpc/boot/mv64x60.h
··· 1 + /* 2 + * Author: Mark A. Greer <source@mvista.com> 3 + * 4 + * 2007 (c) MontaVista Software, Inc. This file is licensed under 5 + * the terms of the GNU General Public License version 2. This program 6 + * is licensed "as is" without any warranty of any kind, whether express 7 + * or implied. 8 + */ 9 + 10 + #ifndef _PPC_BOOT_MV64x60_H_ 11 + #define _PPC_BOOT_MV64x60_H_ 12 + 13 + #define MV64x60_CPU_BAR_ENABLE 0x0278 14 + 15 + #define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0) 16 + #define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1) 17 + #define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 18 + #define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004 19 + #define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008 20 + #define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c 21 + #define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4) 22 + #define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5) 23 + #define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 24 + #define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040 25 + #define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 26 + #define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 27 + #define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 28 + #define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 29 + #define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 30 + #define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 31 + #define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300 32 + #define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 33 + #define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 34 + #define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 35 + #define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 36 + #define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 37 + 38 + struct mv64x60_cpu2pci_win { 39 + u32 lo; 40 + u32 size; 41 + u32 remap_hi; 42 + u32 remap_lo; 43 + }; 44 + 45 + extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2]; 46 + extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2]; 47 + 48 + u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, 49 + u8 offset); 50 + void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, 51 + u8 offset, u32 val); 52 + 53 + void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, 54 + u8 is_coherent); 55 + void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, 56 + u8 bus, u32 mem_size, u32 acc_bits); 57 + void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, 58 + u32 pci_base_lo, u32 cpu_base, u32 size, 59 + struct mv64x60_cpu2pci_win *offset_tbl); 60 + u32 mv64x60_get_mem_size(u8 *bridge_base); 61 + u8 *mv64x60_get_bridge_pbase(void); 62 + u8 *mv64x60_get_bridge_base(void); 63 + u8 mv64x60_is_coherent(void); 64 + 65 + int mv64x60_i2c_open(void); 66 + int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size, 67 + u32 count); 68 + void mv64x60_i2c_close(void); 69 + 70 + #endif /* _PPC_BOOT_MV64x60_H_ */
+206
arch/powerpc/boot/mv64x60_i2c.c
··· 1 + /* 2 + * Bootloader version of the i2c driver for the MV64x60. 3 + * 4 + * Author: Dale Farnsworth <dfarnsworth@mvista.com> 5 + * Maintained by: Mark A. Greer <mgreer@mvista.com> 6 + * 7 + * 2003, 2007 (c) MontaVista, Software, Inc. This file is licensed under 8 + * the terms of the GNU General Public License version 2. This program is 9 + * licensed "as is" without any warranty of any kind, whether express or 10 + * implied. 11 + */ 12 + 13 + #include <stdarg.h> 14 + #include <stddef.h> 15 + #include "types.h" 16 + #include "elf.h" 17 + #include "page.h" 18 + #include "string.h" 19 + #include "stdio.h" 20 + #include "io.h" 21 + #include "ops.h" 22 + #include "mv64x60.h" 23 + 24 + extern void udelay(long); 25 + 26 + /* Register defines */ 27 + #define MV64x60_I2C_REG_SLAVE_ADDR 0x00 28 + #define MV64x60_I2C_REG_DATA 0x04 29 + #define MV64x60_I2C_REG_CONTROL 0x08 30 + #define MV64x60_I2C_REG_STATUS 0x0c 31 + #define MV64x60_I2C_REG_BAUD 0x0c 32 + #define MV64x60_I2C_REG_EXT_SLAVE_ADDR 0x10 33 + #define MV64x60_I2C_REG_SOFT_RESET 0x1c 34 + 35 + #define MV64x60_I2C_CONTROL_ACK 0x04 36 + #define MV64x60_I2C_CONTROL_IFLG 0x08 37 + #define MV64x60_I2C_CONTROL_STOP 0x10 38 + #define MV64x60_I2C_CONTROL_START 0x20 39 + #define MV64x60_I2C_CONTROL_TWSIEN 0x40 40 + #define MV64x60_I2C_CONTROL_INTEN 0x80 41 + 42 + #define MV64x60_I2C_STATUS_BUS_ERR 0x00 43 + #define MV64x60_I2C_STATUS_MAST_START 0x08 44 + #define MV64x60_I2C_STATUS_MAST_REPEAT_START 0x10 45 + #define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 46 + #define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 47 + #define MV64x60_I2C_STATUS_MAST_WR_ACK 0x28 48 + #define MV64x60_I2C_STATUS_MAST_WR_NO_ACK 0x30 49 + #define MV64x60_I2C_STATUS_MAST_LOST_ARB 0x38 50 + #define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 51 + #define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 52 + #define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK 0x50 53 + #define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 54 + #define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 55 + #define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 56 + #define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 57 + #define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 58 + #define MV64x60_I2C_STATUS_NO_STATUS 0xf8 59 + 60 + static u8 *ctlr_base; 61 + 62 + static int mv64x60_i2c_wait_for_status(int wanted) 63 + { 64 + int i; 65 + int status; 66 + 67 + for (i=0; i<1000; i++) { 68 + udelay(10); 69 + status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS)) 70 + & 0xff; 71 + if (status == wanted) 72 + return status; 73 + } 74 + return -status; 75 + } 76 + 77 + static int mv64x60_i2c_control(int control, int status) 78 + { 79 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 80 + return mv64x60_i2c_wait_for_status(status); 81 + } 82 + 83 + static int mv64x60_i2c_read_byte(int control, int status) 84 + { 85 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 86 + if (mv64x60_i2c_wait_for_status(status) < 0) 87 + return -1; 88 + return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff; 89 + } 90 + 91 + static int mv64x60_i2c_write_byte(int data, int control, int status) 92 + { 93 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff); 94 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); 95 + return mv64x60_i2c_wait_for_status(status); 96 + } 97 + 98 + int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size, 99 + u32 count) 100 + { 101 + int i; 102 + int data; 103 + int control; 104 + int status; 105 + 106 + if (ctlr_base == NULL) 107 + return -1; 108 + 109 + /* send reset */ 110 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0); 111 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0); 112 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0); 113 + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4); 114 + 115 + if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN, 116 + MV64x60_I2C_STATUS_NO_STATUS) < 0) 117 + return -1; 118 + 119 + /* send start */ 120 + control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; 121 + status = MV64x60_I2C_STATUS_MAST_START; 122 + if (mv64x60_i2c_control(control, status) < 0) 123 + return -1; 124 + 125 + /* select device for writing */ 126 + data = devaddr & ~0x1; 127 + control = MV64x60_I2C_CONTROL_TWSIEN; 128 + status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK; 129 + if (mv64x60_i2c_write_byte(data, control, status) < 0) 130 + return -1; 131 + 132 + /* send offset of data */ 133 + control = MV64x60_I2C_CONTROL_TWSIEN; 134 + status = MV64x60_I2C_STATUS_MAST_WR_ACK; 135 + if (offset_size > 1) { 136 + if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0) 137 + return -1; 138 + } 139 + if (mv64x60_i2c_write_byte(offset, control, status) < 0) 140 + return -1; 141 + 142 + /* resend start */ 143 + control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; 144 + status = MV64x60_I2C_STATUS_MAST_REPEAT_START; 145 + if (mv64x60_i2c_control(control, status) < 0) 146 + return -1; 147 + 148 + /* select device for reading */ 149 + data = devaddr | 0x1; 150 + control = MV64x60_I2C_CONTROL_TWSIEN; 151 + status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK; 152 + if (mv64x60_i2c_write_byte(data, control, status) < 0) 153 + return -1; 154 + 155 + /* read all but last byte of data */ 156 + control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN; 157 + status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK; 158 + 159 + for (i=1; i<count; i++) { 160 + data = mv64x60_i2c_read_byte(control, status); 161 + if (data < 0) { 162 + printf("errors on iteration %d\n", i); 163 + return -1; 164 + } 165 + *buf++ = data; 166 + } 167 + 168 + /* read last byte of data */ 169 + control = MV64x60_I2C_CONTROL_TWSIEN; 170 + status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK; 171 + data = mv64x60_i2c_read_byte(control, status); 172 + if (data < 0) 173 + return -1; 174 + *buf++ = data; 175 + 176 + /* send stop */ 177 + control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN; 178 + status = MV64x60_I2C_STATUS_NO_STATUS; 179 + if (mv64x60_i2c_control(control, status) < 0) 180 + return -1; 181 + 182 + return count; 183 + } 184 + 185 + int mv64x60_i2c_open(void) 186 + { 187 + u32 v; 188 + void *devp; 189 + 190 + devp = finddevice("/mv64x60/i2c"); 191 + if (devp == NULL) 192 + goto err_out; 193 + if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) 194 + goto err_out; 195 + 196 + ctlr_base = (u8 *)v; 197 + return 0; 198 + 199 + err_out: 200 + return -1; 201 + } 202 + 203 + void mv64x60_i2c_close(void) 204 + { 205 + ctlr_base = NULL; 206 + }
+1
arch/powerpc/boot/ops.h
··· 79 79 int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device); 80 80 int serial_console_init(void); 81 81 int ns16550_console_init(void *devp, struct serial_console_data *scdp); 82 + int mpsc_console_init(void *devp, struct serial_console_data *scdp); 82 83 void *simple_alloc_init(char *base, unsigned long heap_size, 83 84 unsigned long granularity, unsigned long max_allocs); 84 85 extern void flush_cache(void *, unsigned long);
+577
arch/powerpc/boot/prpmc2800.c
··· 1 + /* 2 + * Motorola ECC prpmc280/f101 & prpmc2800/f101e platform code. 3 + * 4 + * Author: Mark A. Greer <mgreer@mvista.com> 5 + * 6 + * 2007 (c) MontaVista, Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <stdarg.h> 13 + #include <stddef.h> 14 + #include "types.h" 15 + #include "elf.h" 16 + #include "page.h" 17 + #include "string.h" 18 + #include "stdio.h" 19 + #include "io.h" 20 + #include "ops.h" 21 + #include "gunzip_util.h" 22 + #include "mv64x60.h" 23 + 24 + extern char _end[]; 25 + extern char _vmlinux_start[], _vmlinux_end[]; 26 + extern char _dtb_start[], _dtb_end[]; 27 + 28 + extern void udelay(long delay); 29 + 30 + #define KB 1024U 31 + #define MB (KB*KB) 32 + #define GB (KB*MB) 33 + #define MHz (1000U*1000U) 34 + #define GHz (1000U*MHz) 35 + 36 + #define BOARD_MODEL "PrPMC2800" 37 + #define BOARD_MODEL_MAX 32 /* max strlen(BOARD_MODEL) + 1 */ 38 + 39 + #define EEPROM2_ADDR 0xa4 40 + #define EEPROM3_ADDR 0xa8 41 + 42 + BSS_STACK(16*KB); 43 + 44 + static u8 *bridge_base; 45 + 46 + typedef enum { 47 + BOARD_MODEL_PRPMC280, 48 + BOARD_MODEL_PRPMC2800, 49 + } prpmc2800_board_model; 50 + 51 + typedef enum { 52 + BRIDGE_TYPE_MV64360, 53 + BRIDGE_TYPE_MV64362, 54 + } prpmc2800_bridge_type; 55 + 56 + struct prpmc2800_board_info { 57 + prpmc2800_board_model model; 58 + char variant; 59 + prpmc2800_bridge_type bridge_type; 60 + u8 subsys0; 61 + u8 subsys1; 62 + u8 vpd4; 63 + u8 vpd4_mask; 64 + u32 core_speed; 65 + u32 mem_size; 66 + u32 boot_flash; 67 + u32 user_flash; 68 + }; 69 + 70 + static struct prpmc2800_board_info prpmc2800_board_info[] = { 71 + { 72 + .model = BOARD_MODEL_PRPMC280, 73 + .variant = 'a', 74 + .bridge_type = BRIDGE_TYPE_MV64360, 75 + .subsys0 = 0xff, 76 + .subsys1 = 0xff, 77 + .vpd4 = 0x00, 78 + .vpd4_mask = 0x0f, 79 + .core_speed = 1*GHz, 80 + .mem_size = 512*MB, 81 + .boot_flash = 1*MB, 82 + .user_flash = 64*MB, 83 + }, 84 + { 85 + .model = BOARD_MODEL_PRPMC280, 86 + .variant = 'b', 87 + .bridge_type = BRIDGE_TYPE_MV64362, 88 + .subsys0 = 0xff, 89 + .subsys1 = 0xff, 90 + .vpd4 = 0x01, 91 + .vpd4_mask = 0x0f, 92 + .core_speed = 1*GHz, 93 + .mem_size = 512*MB, 94 + .boot_flash = 0, 95 + .user_flash = 0, 96 + }, 97 + { 98 + .model = BOARD_MODEL_PRPMC280, 99 + .variant = 'c', 100 + .bridge_type = BRIDGE_TYPE_MV64360, 101 + .subsys0 = 0xff, 102 + .subsys1 = 0xff, 103 + .vpd4 = 0x02, 104 + .vpd4_mask = 0x0f, 105 + .core_speed = 733*MHz, 106 + .mem_size = 512*MB, 107 + .boot_flash = 1*MB, 108 + .user_flash = 64*MB, 109 + }, 110 + { 111 + .model = BOARD_MODEL_PRPMC280, 112 + .variant = 'd', 113 + .bridge_type = BRIDGE_TYPE_MV64360, 114 + .subsys0 = 0xff, 115 + .subsys1 = 0xff, 116 + .vpd4 = 0x03, 117 + .vpd4_mask = 0x0f, 118 + .core_speed = 1*GHz, 119 + .mem_size = 1*GB, 120 + .boot_flash = 1*MB, 121 + .user_flash = 64*MB, 122 + }, 123 + { 124 + .model = BOARD_MODEL_PRPMC280, 125 + .variant = 'e', 126 + .bridge_type = BRIDGE_TYPE_MV64360, 127 + .subsys0 = 0xff, 128 + .subsys1 = 0xff, 129 + .vpd4 = 0x04, 130 + .vpd4_mask = 0x0f, 131 + .core_speed = 1*GHz, 132 + .mem_size = 512*MB, 133 + .boot_flash = 1*MB, 134 + .user_flash = 64*MB, 135 + }, 136 + { 137 + .model = BOARD_MODEL_PRPMC280, 138 + .variant = 'f', 139 + .bridge_type = BRIDGE_TYPE_MV64362, 140 + .subsys0 = 0xff, 141 + .subsys1 = 0xff, 142 + .vpd4 = 0x05, 143 + .vpd4_mask = 0x0f, 144 + .core_speed = 733*MHz, 145 + .mem_size = 128*MB, 146 + .boot_flash = 1*MB, 147 + .user_flash = 0, 148 + }, 149 + { 150 + .model = BOARD_MODEL_PRPMC280, 151 + .variant = 'g', 152 + .bridge_type = BRIDGE_TYPE_MV64360, 153 + .subsys0 = 0xff, 154 + .subsys1 = 0xff, 155 + .vpd4 = 0x06, 156 + .vpd4_mask = 0x0f, 157 + .core_speed = 1*GHz, 158 + .mem_size = 256*MB, 159 + .boot_flash = 1*MB, 160 + .user_flash = 0, 161 + }, 162 + { 163 + .model = BOARD_MODEL_PRPMC280, 164 + .variant = 'h', 165 + .bridge_type = BRIDGE_TYPE_MV64360, 166 + .subsys0 = 0xff, 167 + .subsys1 = 0xff, 168 + .vpd4 = 0x07, 169 + .vpd4_mask = 0x0f, 170 + .core_speed = 1*GHz, 171 + .mem_size = 1*GB, 172 + .boot_flash = 1*MB, 173 + .user_flash = 64*MB, 174 + }, 175 + { 176 + .model = BOARD_MODEL_PRPMC2800, 177 + .variant = 'a', 178 + .bridge_type = BRIDGE_TYPE_MV64360, 179 + .subsys0 = 0xb2, 180 + .subsys1 = 0x8c, 181 + .vpd4 = 0x00, 182 + .vpd4_mask = 0x00, 183 + .core_speed = 1*GHz, 184 + .mem_size = 512*MB, 185 + .boot_flash = 2*MB, 186 + .user_flash = 64*MB, 187 + }, 188 + { 189 + .model = BOARD_MODEL_PRPMC2800, 190 + .variant = 'b', 191 + .bridge_type = BRIDGE_TYPE_MV64362, 192 + .subsys0 = 0xb2, 193 + .subsys1 = 0x8d, 194 + .vpd4 = 0x00, 195 + .vpd4_mask = 0x00, 196 + .core_speed = 1*GHz, 197 + .mem_size = 512*MB, 198 + .boot_flash = 0, 199 + .user_flash = 0, 200 + }, 201 + { 202 + .model = BOARD_MODEL_PRPMC2800, 203 + .variant = 'c', 204 + .bridge_type = BRIDGE_TYPE_MV64360, 205 + .subsys0 = 0xb2, 206 + .subsys1 = 0x8e, 207 + .vpd4 = 0x00, 208 + .vpd4_mask = 0x00, 209 + .core_speed = 733*MHz, 210 + .mem_size = 512*MB, 211 + .boot_flash = 2*MB, 212 + .user_flash = 64*MB, 213 + }, 214 + { 215 + .model = BOARD_MODEL_PRPMC2800, 216 + .variant = 'd', 217 + .bridge_type = BRIDGE_TYPE_MV64360, 218 + .subsys0 = 0xb2, 219 + .subsys1 = 0x8f, 220 + .vpd4 = 0x00, 221 + .vpd4_mask = 0x00, 222 + .core_speed = 1*GHz, 223 + .mem_size = 1*GB, 224 + .boot_flash = 2*MB, 225 + .user_flash = 64*MB, 226 + }, 227 + { 228 + .model = BOARD_MODEL_PRPMC2800, 229 + .variant = 'e', 230 + .bridge_type = BRIDGE_TYPE_MV64360, 231 + .subsys0 = 0xa2, 232 + .subsys1 = 0x8a, 233 + .vpd4 = 0x00, 234 + .vpd4_mask = 0x00, 235 + .core_speed = 1*GHz, 236 + .mem_size = 512*MB, 237 + .boot_flash = 2*MB, 238 + .user_flash = 64*MB, 239 + }, 240 + { 241 + .model = BOARD_MODEL_PRPMC2800, 242 + .variant = 'f', 243 + .bridge_type = BRIDGE_TYPE_MV64362, 244 + .subsys0 = 0xa2, 245 + .subsys1 = 0x8b, 246 + .vpd4 = 0x00, 247 + .vpd4_mask = 0x00, 248 + .core_speed = 733*MHz, 249 + .mem_size = 128*MB, 250 + .boot_flash = 2*MB, 251 + .user_flash = 0, 252 + }, 253 + { 254 + .model = BOARD_MODEL_PRPMC2800, 255 + .variant = 'g', 256 + .bridge_type = BRIDGE_TYPE_MV64360, 257 + .subsys0 = 0xa2, 258 + .subsys1 = 0x8c, 259 + .vpd4 = 0x00, 260 + .vpd4_mask = 0x00, 261 + .core_speed = 1*GHz, 262 + .mem_size = 2*GB, 263 + .boot_flash = 2*MB, 264 + .user_flash = 64*MB, 265 + }, 266 + { 267 + .model = BOARD_MODEL_PRPMC2800, 268 + .variant = 'h', 269 + .bridge_type = BRIDGE_TYPE_MV64360, 270 + .subsys0 = 0xa2, 271 + .subsys1 = 0x8d, 272 + .vpd4 = 0x00, 273 + .vpd4_mask = 0x00, 274 + .core_speed = 733*MHz, 275 + .mem_size = 1*GB, 276 + .boot_flash = 2*MB, 277 + .user_flash = 64*MB, 278 + }, 279 + }; 280 + 281 + static struct prpmc2800_board_info *prpmc2800_get_board_info(u8 *vpd) 282 + { 283 + struct prpmc2800_board_info *bip; 284 + int i; 285 + 286 + for (i=0,bip=prpmc2800_board_info; i<ARRAY_SIZE(prpmc2800_board_info); 287 + i++,bip++) 288 + if ((vpd[0] == bip->subsys0) && (vpd[1] == bip->subsys1) 289 + && ((vpd[4] & bip->vpd4_mask) == bip->vpd4)) 290 + return bip; 291 + 292 + return NULL; 293 + } 294 + 295 + /* Get VPD from i2c eeprom 2, then match it to a board info entry */ 296 + static struct prpmc2800_board_info *prpmc2800_get_bip(void) 297 + { 298 + struct prpmc2800_board_info *bip; 299 + u8 vpd[5]; 300 + int rc; 301 + 302 + if (mv64x60_i2c_open()) 303 + fatal("Error: Can't open i2c device\n\r"); 304 + 305 + /* Get VPD from i2c eeprom-2 */ 306 + memset(vpd, 0, sizeof(vpd)); 307 + rc = mv64x60_i2c_read(EEPROM2_ADDR, vpd, 0x1fde, 2, sizeof(vpd)); 308 + if (rc < 0) 309 + fatal("Error: Couldn't read eeprom2\n\r"); 310 + mv64x60_i2c_close(); 311 + 312 + /* Get board type & related info */ 313 + bip = prpmc2800_get_board_info(vpd); 314 + if (bip == NULL) { 315 + printf("Error: Unsupported board or corrupted VPD:\n\r"); 316 + printf(" 0x%x 0x%x 0x%x 0x%x 0x%x\n\r", 317 + vpd[0], vpd[1], vpd[2], vpd[3], vpd[4]); 318 + printf("Using device tree defaults...\n\r"); 319 + } 320 + 321 + return bip; 322 + } 323 + 324 + static void prpmc2800_bridge_setup(u32 mem_size) 325 + { 326 + u32 i, v[12], enables, acc_bits; 327 + u32 pci_base_hi, pci_base_lo, size, buf[2]; 328 + unsigned long cpu_base; 329 + int rc; 330 + void *devp; 331 + u8 *bridge_pbase, is_coherent; 332 + struct mv64x60_cpu2pci_win *tbl; 333 + 334 + bridge_pbase = mv64x60_get_bridge_pbase(); 335 + is_coherent = mv64x60_is_coherent(); 336 + 337 + if (is_coherent) 338 + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB 339 + | MV64x60_PCI_ACC_CNTL_SWAP_NONE 340 + | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 341 + | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES; 342 + else 343 + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE 344 + | MV64x60_PCI_ACC_CNTL_SWAP_NONE 345 + | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 346 + | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES; 347 + 348 + mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); 349 + mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size, 350 + acc_bits); 351 + 352 + /* Get the cpu -> pci i/o & mem mappings from the device tree */ 353 + devp = finddevice("/mv64x60/pci@80000000"); 354 + if (devp == NULL) 355 + fatal("Error: Missing /mv64x60/pci@80000000" 356 + " device tree node\n\r"); 357 + 358 + rc = getprop(devp, "ranges", v, sizeof(v)); 359 + if (rc != sizeof(v)) 360 + fatal("Error: Can't find /mv64x60/pci@80000000/ranges" 361 + " property\n\r"); 362 + 363 + /* Get the cpu -> pci i/o & mem mappings from the device tree */ 364 + devp = finddevice("/mv64x60"); 365 + if (devp == NULL) 366 + fatal("Error: Missing /mv64x60 device tree node\n\r"); 367 + 368 + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); 369 + enables |= 0x0007fe00; /* Disable all cpu->pci windows */ 370 + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 371 + 372 + for (i=0; i<12; i+=6) { 373 + switch (v[i] & 0xff000000) { 374 + case 0x01000000: /* PCI I/O Space */ 375 + tbl = mv64x60_cpu2pci_io; 376 + break; 377 + case 0x02000000: /* PCI MEM Space */ 378 + tbl = mv64x60_cpu2pci_mem; 379 + break; 380 + default: 381 + continue; 382 + } 383 + 384 + pci_base_hi = v[i+1]; 385 + pci_base_lo = v[i+2]; 386 + cpu_base = v[i+3]; 387 + size = v[i+5]; 388 + 389 + buf[0] = cpu_base; 390 + buf[1] = size; 391 + 392 + if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base)) 393 + fatal("Error: Can't translate PCI address 0x%x\n\r", 394 + (u32)cpu_base); 395 + 396 + mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi, 397 + pci_base_lo, cpu_base, size, tbl); 398 + } 399 + 400 + enables &= ~0x00000600; /* Enable cpu->pci0 i/o, cpu->pci0 mem0 */ 401 + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); 402 + } 403 + 404 + static void prpmc2800_fixups(void) 405 + { 406 + u32 v[2], l, mem_size; 407 + int rc; 408 + void *devp; 409 + char model[BOARD_MODEL_MAX]; 410 + struct prpmc2800_board_info *bip; 411 + 412 + bip = prpmc2800_get_bip(); /* Get board info based on VPD */ 413 + 414 + mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base); 415 + prpmc2800_bridge_setup(mem_size); /* Do necessary bridge setup */ 416 + 417 + /* If the VPD doesn't match what we know about, just use the 418 + * defaults already in the device tree. 419 + */ 420 + if (!bip) 421 + return; 422 + 423 + /* Know the board type so override device tree defaults */ 424 + /* Set /model appropriately */ 425 + devp = finddevice("/"); 426 + if (devp == NULL) 427 + fatal("Error: Missing '/' device tree node\n\r"); 428 + memset(model, 0, BOARD_MODEL_MAX); 429 + strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 2); 430 + l = strlen(model); 431 + if (bip->model == BOARD_MODEL_PRPMC280) 432 + l--; 433 + model[l++] = bip->variant; 434 + model[l++] = '\0'; 435 + setprop(devp, "model", model, l); 436 + 437 + /* Set /cpus/PowerPC,7447/clock-frequency */ 438 + devp = finddevice("/cpus/PowerPC,7447"); 439 + if (devp == NULL) 440 + fatal("Error: Missing proper /cpus device tree node\n\r"); 441 + v[0] = bip->core_speed; 442 + setprop(devp, "clock-frequency", &v[0], sizeof(v[0])); 443 + 444 + /* Set /memory/reg size */ 445 + devp = finddevice("/memory"); 446 + if (devp == NULL) 447 + fatal("Error: Missing /memory device tree node\n\r"); 448 + v[0] = 0; 449 + v[1] = bip->mem_size; 450 + setprop(devp, "reg", v, sizeof(v)); 451 + 452 + /* Update /mv64x60/model, if this is a mv64362 */ 453 + if (bip->bridge_type == BRIDGE_TYPE_MV64362) { 454 + devp = finddevice("/mv64x60"); 455 + if (devp == NULL) 456 + fatal("Error: Missing /mv64x60 device tree node\n\r"); 457 + setprop(devp, "model", "mv64362", strlen("mv64362") + 1); 458 + } 459 + 460 + /* Set User FLASH size */ 461 + devp = finddevice("/mv64x60/flash@a0000000"); 462 + if (devp == NULL) 463 + fatal("Error: Missing User FLASH device tree node\n\r"); 464 + rc = getprop(devp, "reg", v, sizeof(v)); 465 + if (rc != sizeof(v)) 466 + fatal("Error: Can't find User FLASH reg property\n\r"); 467 + v[1] = bip->user_flash; 468 + setprop(devp, "reg", v, sizeof(v)); 469 + } 470 + 471 + #define MV64x60_MPP_CNTL_0 0xf000 472 + #define MV64x60_MPP_CNTL_2 0xf008 473 + #define MV64x60_GPP_IO_CNTL 0xf100 474 + #define MV64x60_GPP_LEVEL_CNTL 0xf110 475 + #define MV64x60_GPP_VALUE_SET 0xf118 476 + 477 + static void prpmc2800_reset(void) 478 + { 479 + u32 temp; 480 + 481 + udelay(5000000); 482 + 483 + if (bridge_base != 0) { 484 + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0)); 485 + temp &= 0xFFFF0FFF; 486 + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp); 487 + 488 + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); 489 + temp |= 0x00000004; 490 + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); 491 + 492 + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); 493 + temp |= 0x00000004; 494 + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); 495 + 496 + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2)); 497 + temp &= 0xFFFF0FFF; 498 + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp); 499 + 500 + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); 501 + temp |= 0x00080000; 502 + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); 503 + 504 + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); 505 + temp |= 0x00080000; 506 + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); 507 + 508 + out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET), 509 + 0x00080004); 510 + } 511 + 512 + for (;;); 513 + } 514 + 515 + #define HEAP_SIZE (16*MB) 516 + static struct gunzip_state gzstate; 517 + 518 + void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 519 + unsigned long r6, unsigned long r7) 520 + { 521 + struct elf_info ei; 522 + char *heap_start, *dtb; 523 + int dt_size = _dtb_end - _dtb_start; 524 + void *vmlinuz_addr = _vmlinux_start; 525 + unsigned long vmlinuz_size = _vmlinux_end - _vmlinux_start; 526 + char elfheader[256]; 527 + 528 + if (dt_size <= 0) /* No fdt */ 529 + exit(); 530 + 531 + /* 532 + * Start heap after end of the kernel (after decompressed to 533 + * address 0) or the end of the zImage, whichever is higher. 534 + * That's so things allocated by simple_alloc won't overwrite 535 + * any part of the zImage and the kernel won't overwrite the dtb 536 + * when decompressed & relocated. 537 + */ 538 + gunzip_start(&gzstate, vmlinuz_addr, vmlinuz_size); 539 + gunzip_exactly(&gzstate, elfheader, sizeof(elfheader)); 540 + 541 + if (!parse_elf32(elfheader, &ei)) 542 + exit(); 543 + 544 + heap_start = (char *)(ei.memsize + ei.elfoffset); /* end of kernel*/ 545 + heap_start = max(heap_start, (char *)_end); /* end of zImage */ 546 + 547 + if ((unsigned)simple_alloc_init(heap_start, HEAP_SIZE, 2*KB, 16) 548 + > (128*MB)) 549 + exit(); 550 + 551 + /* Relocate dtb to safe area past end of zImage & kernel */ 552 + dtb = malloc(dt_size); 553 + if (!dtb) 554 + exit(); 555 + memmove(dtb, _dtb_start, dt_size); 556 + if (ft_init(dtb, dt_size, 16)) 557 + exit(); 558 + 559 + bridge_base = mv64x60_get_bridge_base(); 560 + 561 + platform_ops.fixups = prpmc2800_fixups; 562 + platform_ops.exit = prpmc2800_reset; 563 + 564 + if (serial_console_init() < 0) 565 + exit(); 566 + } 567 + 568 + /* _zimage_start called very early--need to turn off external interrupts */ 569 + asm (" .globl _zimage_start\n\ 570 + _zimage_start:\n\ 571 + mfmsr 10\n\ 572 + rlwinm 10,10,0,~(1<<15) /* Clear MSR_EE */\n\ 573 + sync\n\ 574 + mtmsr 10\n\ 575 + isync\n\ 576 + b _zimage_start_lib\n\ 577 + ");
+2
arch/powerpc/boot/serial.c
··· 125 125 126 126 if (!strcmp(compat, "ns16550")) 127 127 rc = ns16550_console_init(devp, &serial_cd); 128 + else if (!strcmp(compat, "marvell,mpsc")) 129 + rc = mpsc_console_init(devp, &serial_cd); 128 130 129 131 /* Add other serial console driver calls here */ 130 132
+1442
arch/powerpc/configs/prpmc2800_defconfig
··· 1 + # 2 + # Automatically generated make config: don't edit 3 + # Linux kernel version: 2.6.21 4 + # Wed May 9 09:42:46 2007 5 + # 6 + # CONFIG_PPC64 is not set 7 + CONFIG_PPC32=y 8 + CONFIG_PPC_MERGE=y 9 + CONFIG_MMU=y 10 + CONFIG_GENERIC_HARDIRQS=y 11 + CONFIG_IRQ_PER_CPU=y 12 + CONFIG_RWSEM_XCHGADD_ALGORITHM=y 13 + CONFIG_ARCH_HAS_ILOG2_U32=y 14 + CONFIG_GENERIC_HWEIGHT=y 15 + CONFIG_GENERIC_CALIBRATE_DELAY=y 16 + CONFIG_GENERIC_FIND_NEXT_BIT=y 17 + CONFIG_PPC=y 18 + CONFIG_EARLY_PRINTK=y 19 + CONFIG_GENERIC_NVRAM=y 20 + CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 21 + CONFIG_ARCH_MAY_HAVE_PC_FDC=y 22 + CONFIG_PPC_OF=y 23 + # CONFIG_PPC_UDBG_16550 is not set 24 + # CONFIG_GENERIC_TBSYNC is not set 25 + CONFIG_AUDIT_ARCH=y 26 + CONFIG_GENERIC_BUG=y 27 + # CONFIG_DEFAULT_UIMAGE is not set 28 + 29 + # 30 + # Processor support 31 + # 32 + CONFIG_CLASSIC32=y 33 + # CONFIG_PPC_82xx is not set 34 + # CONFIG_PPC_83xx is not set 35 + # CONFIG_PPC_85xx is not set 36 + # CONFIG_PPC_86xx is not set 37 + # CONFIG_PPC_8xx is not set 38 + # CONFIG_40x is not set 39 + # CONFIG_44x is not set 40 + # CONFIG_E200 is not set 41 + CONFIG_6xx=y 42 + CONFIG_PPC_FPU=y 43 + # CONFIG_PPC_DCR_NATIVE is not set 44 + # CONFIG_PPC_DCR_MMIO is not set 45 + CONFIG_ALTIVEC=y 46 + CONFIG_PPC_STD_MMU=y 47 + CONFIG_PPC_STD_MMU_32=y 48 + # CONFIG_PPC_MM_SLICES is not set 49 + # CONFIG_SMP is not set 50 + CONFIG_NOT_COHERENT_CACHE=y 51 + CONFIG_CONFIG_CHECK_CACHE_COHERENCY=y 52 + CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 53 + 54 + # 55 + # Code maturity level options 56 + # 57 + CONFIG_EXPERIMENTAL=y 58 + CONFIG_BROKEN_ON_SMP=y 59 + CONFIG_INIT_ENV_ARG_LIMIT=32 60 + 61 + # 62 + # General setup 63 + # 64 + CONFIG_LOCALVERSION="" 65 + CONFIG_LOCALVERSION_AUTO=y 66 + CONFIG_SWAP=y 67 + CONFIG_SYSVIPC=y 68 + # CONFIG_IPC_NS is not set 69 + CONFIG_SYSVIPC_SYSCTL=y 70 + CONFIG_POSIX_MQUEUE=y 71 + # CONFIG_BSD_PROCESS_ACCT is not set 72 + # CONFIG_TASKSTATS is not set 73 + # CONFIG_UTS_NS is not set 74 + # CONFIG_AUDIT is not set 75 + # CONFIG_IKCONFIG is not set 76 + CONFIG_LOG_BUF_SHIFT=14 77 + # CONFIG_SYSFS_DEPRECATED is not set 78 + # CONFIG_RELAY is not set 79 + CONFIG_BLK_DEV_INITRD=y 80 + CONFIG_INITRAMFS_SOURCE="" 81 + # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 82 + CONFIG_SYSCTL=y 83 + # CONFIG_EMBEDDED is not set 84 + CONFIG_SYSCTL_SYSCALL=y 85 + CONFIG_KALLSYMS=y 86 + # CONFIG_KALLSYMS_EXTRA_PASS is not set 87 + CONFIG_HOTPLUG=y 88 + CONFIG_PRINTK=y 89 + CONFIG_BUG=y 90 + CONFIG_ELF_CORE=y 91 + CONFIG_BASE_FULL=y 92 + CONFIG_FUTEX=y 93 + CONFIG_EPOLL=y 94 + CONFIG_SHMEM=y 95 + CONFIG_VM_EVENT_COUNTERS=y 96 + CONFIG_SLAB=y 97 + # CONFIG_SLUB is not set 98 + # CONFIG_SLOB is not set 99 + CONFIG_RT_MUTEXES=y 100 + # CONFIG_TINY_SHMEM is not set 101 + CONFIG_BASE_SMALL=0 102 + 103 + # 104 + # Loadable module support 105 + # 106 + # CONFIG_MODULES is not set 107 + 108 + # 109 + # Block layer 110 + # 111 + CONFIG_BLOCK=y 112 + CONFIG_LBD=y 113 + # CONFIG_BLK_DEV_IO_TRACE is not set 114 + # CONFIG_LSF is not set 115 + 116 + # 117 + # IO Schedulers 118 + # 119 + CONFIG_IOSCHED_NOOP=y 120 + CONFIG_IOSCHED_AS=y 121 + # CONFIG_IOSCHED_DEADLINE is not set 122 + # CONFIG_IOSCHED_CFQ is not set 123 + CONFIG_DEFAULT_AS=y 124 + # CONFIG_DEFAULT_DEADLINE is not set 125 + # CONFIG_DEFAULT_CFQ is not set 126 + # CONFIG_DEFAULT_NOOP is not set 127 + CONFIG_DEFAULT_IOSCHED="anticipatory" 128 + 129 + # 130 + # Platform support 131 + # 132 + # CONFIG_PPC_MULTIPLATFORM is not set 133 + CONFIG_EMBEDDED6xx=y 134 + # CONFIG_APUS is not set 135 + # CONFIG_PPC_MPC52xx is not set 136 + # CONFIG_PPC_MPC5200 is not set 137 + # CONFIG_PPC_CELL is not set 138 + # CONFIG_PPC_CELL_NATIVE is not set 139 + # CONFIG_PQ2ADS is not set 140 + # CONFIG_LINKSTATION is not set 141 + # CONFIG_MPC7448HPC2 is not set 142 + # CONFIG_PPC_HOLLY is not set 143 + CONFIG_PPC_PRPMC2800=y 144 + CONFIG_MV64X60=y 145 + # CONFIG_MPIC is not set 146 + # CONFIG_MPIC_WEIRD is not set 147 + # CONFIG_PPC_I8259 is not set 148 + # CONFIG_PPC_RTAS is not set 149 + # CONFIG_MMIO_NVRAM is not set 150 + # CONFIG_PPC_MPC106 is not set 151 + # CONFIG_PPC_970_NAP is not set 152 + # CONFIG_PPC_INDIRECT_IO is not set 153 + # CONFIG_GENERIC_IOMAP is not set 154 + # CONFIG_CPU_FREQ is not set 155 + # CONFIG_TAU is not set 156 + # CONFIG_CPM2 is not set 157 + 158 + # 159 + # Kernel options 160 + # 161 + CONFIG_HIGHMEM=y 162 + # CONFIG_HZ_100 is not set 163 + CONFIG_HZ_250=y 164 + # CONFIG_HZ_300 is not set 165 + # CONFIG_HZ_1000 is not set 166 + CONFIG_HZ=250 167 + CONFIG_PREEMPT_NONE=y 168 + # CONFIG_PREEMPT_VOLUNTARY is not set 169 + # CONFIG_PREEMPT is not set 170 + CONFIG_BINFMT_ELF=y 171 + CONFIG_BINFMT_MISC=y 172 + CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y 173 + # CONFIG_KEXEC is not set 174 + CONFIG_ARCH_FLATMEM_ENABLE=y 175 + CONFIG_ARCH_POPULATES_NODE_MAP=y 176 + CONFIG_SELECT_MEMORY_MODEL=y 177 + CONFIG_FLATMEM_MANUAL=y 178 + # CONFIG_DISCONTIGMEM_MANUAL is not set 179 + # CONFIG_SPARSEMEM_MANUAL is not set 180 + CONFIG_FLATMEM=y 181 + CONFIG_FLAT_NODE_MEM_MAP=y 182 + # CONFIG_SPARSEMEM_STATIC is not set 183 + CONFIG_SPLIT_PTLOCK_CPUS=4 184 + # CONFIG_RESOURCES_64BIT is not set 185 + CONFIG_ZONE_DMA_FLAG=1 186 + CONFIG_PROC_DEVICETREE=y 187 + # CONFIG_CMDLINE_BOOL is not set 188 + # CONFIG_PM is not set 189 + # CONFIG_SECCOMP is not set 190 + CONFIG_WANT_DEVICE_TREE=y 191 + CONFIG_DEVICE_TREE="prpmc2800.dts" 192 + CONFIG_ISA_DMA_API=y 193 + 194 + # 195 + # Bus options 196 + # 197 + CONFIG_ZONE_DMA=y 198 + CONFIG_GENERIC_ISA_DMA=y 199 + CONFIG_PPC_INDIRECT_PCI=y 200 + # CONFIG_PPC_INDIRECT_PCI_BE is not set 201 + CONFIG_PCI=y 202 + CONFIG_PCI_DOMAINS=y 203 + # CONFIG_PCIEPORTBUS is not set 204 + CONFIG_ARCH_SUPPORTS_MSI=y 205 + # CONFIG_PCI_MSI is not set 206 + 207 + # 208 + # PCCARD (PCMCIA/CardBus) support 209 + # 210 + # CONFIG_PCCARD is not set 211 + # CONFIG_HOTPLUG_PCI is not set 212 + 213 + # 214 + # Advanced setup 215 + # 216 + # CONFIG_ADVANCED_OPTIONS is not set 217 + 218 + # 219 + # Default settings for advanced configuration options are used 220 + # 221 + CONFIG_HIGHMEM_START=0xfe000000 222 + CONFIG_LOWMEM_SIZE=0x30000000 223 + CONFIG_KERNEL_START=0xc0000000 224 + CONFIG_TASK_SIZE=0x80000000 225 + CONFIG_CONSISTENT_START=0xff100000 226 + CONFIG_CONSISTENT_SIZE=0x00200000 227 + CONFIG_BOOT_LOAD=0x00800000 228 + 229 + # 230 + # Networking 231 + # 232 + CONFIG_NET=y 233 + 234 + # 235 + # Networking options 236 + # 237 + CONFIG_PACKET=y 238 + # CONFIG_PACKET_MMAP is not set 239 + CONFIG_UNIX=y 240 + CONFIG_XFRM=y 241 + CONFIG_XFRM_USER=y 242 + # CONFIG_XFRM_SUB_POLICY is not set 243 + # CONFIG_XFRM_MIGRATE is not set 244 + # CONFIG_NET_KEY is not set 245 + CONFIG_INET=y 246 + CONFIG_IP_MULTICAST=y 247 + # CONFIG_IP_ADVANCED_ROUTER is not set 248 + CONFIG_IP_FIB_HASH=y 249 + CONFIG_IP_PNP=y 250 + CONFIG_IP_PNP_DHCP=y 251 + CONFIG_IP_PNP_BOOTP=y 252 + # CONFIG_IP_PNP_RARP is not set 253 + # CONFIG_NET_IPIP is not set 254 + # CONFIG_NET_IPGRE is not set 255 + # CONFIG_IP_MROUTE is not set 256 + # CONFIG_ARPD is not set 257 + CONFIG_SYN_COOKIES=y 258 + # CONFIG_INET_AH is not set 259 + # CONFIG_INET_ESP is not set 260 + # CONFIG_INET_IPCOMP is not set 261 + # CONFIG_INET_XFRM_TUNNEL is not set 262 + # CONFIG_INET_TUNNEL is not set 263 + CONFIG_INET_XFRM_MODE_TRANSPORT=y 264 + CONFIG_INET_XFRM_MODE_TUNNEL=y 265 + CONFIG_INET_XFRM_MODE_BEET=y 266 + CONFIG_INET_DIAG=y 267 + CONFIG_INET_TCP_DIAG=y 268 + # CONFIG_TCP_CONG_ADVANCED is not set 269 + CONFIG_TCP_CONG_CUBIC=y 270 + CONFIG_DEFAULT_TCP_CONG="cubic" 271 + # CONFIG_TCP_MD5SIG is not set 272 + # CONFIG_IPV6 is not set 273 + # CONFIG_INET6_XFRM_TUNNEL is not set 274 + # CONFIG_INET6_TUNNEL is not set 275 + # CONFIG_NETWORK_SECMARK is not set 276 + # CONFIG_NETFILTER is not set 277 + 278 + # 279 + # DCCP Configuration (EXPERIMENTAL) 280 + # 281 + # CONFIG_IP_DCCP is not set 282 + 283 + # 284 + # SCTP Configuration (EXPERIMENTAL) 285 + # 286 + # CONFIG_IP_SCTP is not set 287 + 288 + # 289 + # TIPC Configuration (EXPERIMENTAL) 290 + # 291 + # CONFIG_TIPC is not set 292 + # CONFIG_ATM is not set 293 + # CONFIG_BRIDGE is not set 294 + # CONFIG_VLAN_8021Q is not set 295 + # CONFIG_DECNET is not set 296 + # CONFIG_LLC2 is not set 297 + # CONFIG_IPX is not set 298 + # CONFIG_ATALK is not set 299 + # CONFIG_X25 is not set 300 + # CONFIG_LAPB is not set 301 + # CONFIG_ECONET is not set 302 + # CONFIG_WAN_ROUTER is not set 303 + 304 + # 305 + # QoS and/or fair queueing 306 + # 307 + # CONFIG_NET_SCHED is not set 308 + 309 + # 310 + # Network testing 311 + # 312 + # CONFIG_NET_PKTGEN is not set 313 + # CONFIG_HAMRADIO is not set 314 + # CONFIG_IRDA is not set 315 + # CONFIG_BT is not set 316 + # CONFIG_AF_RXRPC is not set 317 + 318 + # 319 + # Wireless 320 + # 321 + # CONFIG_CFG80211 is not set 322 + # CONFIG_WIRELESS_EXT is not set 323 + # CONFIG_MAC80211 is not set 324 + # CONFIG_IEEE80211 is not set 325 + # CONFIG_RFKILL is not set 326 + 327 + # 328 + # Device Drivers 329 + # 330 + 331 + # 332 + # Generic Driver Options 333 + # 334 + CONFIG_STANDALONE=y 335 + CONFIG_PREVENT_FIRMWARE_BUILD=y 336 + # CONFIG_FW_LOADER is not set 337 + # CONFIG_SYS_HYPERVISOR is not set 338 + 339 + # 340 + # Connector - unified userspace <-> kernelspace linker 341 + # 342 + # CONFIG_CONNECTOR is not set 343 + CONFIG_MTD=y 344 + # CONFIG_MTD_DEBUG is not set 345 + CONFIG_MTD_CONCAT=y 346 + CONFIG_MTD_PARTITIONS=y 347 + # CONFIG_MTD_REDBOOT_PARTS is not set 348 + # CONFIG_MTD_CMDLINE_PARTS is not set 349 + 350 + # 351 + # User Modules And Translation Layers 352 + # 353 + CONFIG_MTD_CHAR=y 354 + CONFIG_MTD_BLKDEVS=y 355 + CONFIG_MTD_BLOCK=y 356 + # CONFIG_FTL is not set 357 + # CONFIG_NFTL is not set 358 + # CONFIG_INFTL is not set 359 + # CONFIG_RFD_FTL is not set 360 + # CONFIG_SSFDC is not set 361 + 362 + # 363 + # RAM/ROM/Flash chip drivers 364 + # 365 + CONFIG_MTD_CFI=y 366 + CONFIG_MTD_JEDECPROBE=y 367 + CONFIG_MTD_GEN_PROBE=y 368 + # CONFIG_MTD_CFI_ADV_OPTIONS is not set 369 + CONFIG_MTD_MAP_BANK_WIDTH_1=y 370 + CONFIG_MTD_MAP_BANK_WIDTH_2=y 371 + CONFIG_MTD_MAP_BANK_WIDTH_4=y 372 + # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set 373 + # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set 374 + # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set 375 + CONFIG_MTD_CFI_I1=y 376 + CONFIG_MTD_CFI_I2=y 377 + # CONFIG_MTD_CFI_I4 is not set 378 + # CONFIG_MTD_CFI_I8 is not set 379 + CONFIG_MTD_CFI_INTELEXT=y 380 + # CONFIG_MTD_CFI_AMDSTD is not set 381 + # CONFIG_MTD_CFI_STAA is not set 382 + CONFIG_MTD_CFI_UTIL=y 383 + # CONFIG_MTD_RAM is not set 384 + # CONFIG_MTD_ROM is not set 385 + # CONFIG_MTD_ABSENT is not set 386 + # CONFIG_MTD_OBSOLETE_CHIPS is not set 387 + 388 + # 389 + # Mapping drivers for chip access 390 + # 391 + # CONFIG_MTD_COMPLEX_MAPPINGS is not set 392 + # CONFIG_MTD_PHYSMAP is not set 393 + CONFIG_MTD_PHYSMAP_OF=y 394 + # CONFIG_MTD_PLATRAM is not set 395 + 396 + # 397 + # Self-contained MTD device drivers 398 + # 399 + # CONFIG_MTD_PMC551 is not set 400 + # CONFIG_MTD_SLRAM is not set 401 + # CONFIG_MTD_PHRAM is not set 402 + # CONFIG_MTD_MTDRAM is not set 403 + # CONFIG_MTD_BLOCK2MTD is not set 404 + 405 + # 406 + # Disk-On-Chip Device Drivers 407 + # 408 + # CONFIG_MTD_DOC2000 is not set 409 + # CONFIG_MTD_DOC2001 is not set 410 + # CONFIG_MTD_DOC2001PLUS is not set 411 + # CONFIG_MTD_NAND is not set 412 + # CONFIG_MTD_ONENAND is not set 413 + 414 + # 415 + # UBI - Unsorted block images 416 + # 417 + # CONFIG_MTD_UBI is not set 418 + 419 + # 420 + # Parallel port support 421 + # 422 + # CONFIG_PARPORT is not set 423 + 424 + # 425 + # Plug and Play support 426 + # 427 + # CONFIG_PNPACPI is not set 428 + 429 + # 430 + # Block devices 431 + # 432 + # CONFIG_BLK_DEV_FD is not set 433 + # CONFIG_BLK_CPQ_DA is not set 434 + # CONFIG_BLK_CPQ_CISS_DA is not set 435 + # CONFIG_BLK_DEV_DAC960 is not set 436 + # CONFIG_BLK_DEV_UMEM is not set 437 + # CONFIG_BLK_DEV_COW_COMMON is not set 438 + CONFIG_BLK_DEV_LOOP=y 439 + # CONFIG_BLK_DEV_CRYPTOLOOP is not set 440 + # CONFIG_BLK_DEV_NBD is not set 441 + # CONFIG_BLK_DEV_SX8 is not set 442 + # CONFIG_BLK_DEV_UB is not set 443 + CONFIG_BLK_DEV_RAM=y 444 + CONFIG_BLK_DEV_RAM_COUNT=16 445 + CONFIG_BLK_DEV_RAM_SIZE=131072 446 + CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 447 + # CONFIG_CDROM_PKTCDVD is not set 448 + # CONFIG_ATA_OVER_ETH is not set 449 + 450 + # 451 + # Misc devices 452 + # 453 + # CONFIG_PHANTOM is not set 454 + # CONFIG_SGI_IOC4 is not set 455 + # CONFIG_TIFM_CORE is not set 456 + # CONFIG_BLINK is not set 457 + 458 + # 459 + # ATA/ATAPI/MFM/RLL support 460 + # 461 + CONFIG_IDE=y 462 + CONFIG_BLK_DEV_IDE=y 463 + 464 + # 465 + # Please see Documentation/ide.txt for help/info on IDE drives 466 + # 467 + # CONFIG_BLK_DEV_IDE_SATA is not set 468 + CONFIG_BLK_DEV_IDEDISK=y 469 + # CONFIG_IDEDISK_MULTI_MODE is not set 470 + # CONFIG_BLK_DEV_IDECD is not set 471 + # CONFIG_BLK_DEV_IDETAPE is not set 472 + # CONFIG_BLK_DEV_IDEFLOPPY is not set 473 + # CONFIG_BLK_DEV_IDESCSI is not set 474 + # CONFIG_IDE_TASK_IOCTL is not set 475 + 476 + # 477 + # IDE chipset support/bugfixes 478 + # 479 + CONFIG_IDE_GENERIC=y 480 + CONFIG_BLK_DEV_IDEPCI=y 481 + # CONFIG_IDEPCI_SHARE_IRQ is not set 482 + # CONFIG_BLK_DEV_OFFBOARD is not set 483 + CONFIG_BLK_DEV_GENERIC=y 484 + # CONFIG_BLK_DEV_OPTI621 is not set 485 + CONFIG_BLK_DEV_IDEDMA_PCI=y 486 + # CONFIG_BLK_DEV_IDEDMA_FORCED is not set 487 + # CONFIG_IDEDMA_ONLYDISK is not set 488 + # CONFIG_BLK_DEV_AEC62XX is not set 489 + # CONFIG_BLK_DEV_ALI15X3 is not set 490 + # CONFIG_BLK_DEV_AMD74XX is not set 491 + # CONFIG_BLK_DEV_CMD64X is not set 492 + # CONFIG_BLK_DEV_TRIFLEX is not set 493 + # CONFIG_BLK_DEV_CY82C693 is not set 494 + # CONFIG_BLK_DEV_CS5520 is not set 495 + # CONFIG_BLK_DEV_CS5530 is not set 496 + # CONFIG_BLK_DEV_HPT34X is not set 497 + # CONFIG_BLK_DEV_HPT366 is not set 498 + # CONFIG_BLK_DEV_JMICRON is not set 499 + # CONFIG_BLK_DEV_SC1200 is not set 500 + # CONFIG_BLK_DEV_PIIX is not set 501 + # CONFIG_BLK_DEV_IT8213 is not set 502 + # CONFIG_BLK_DEV_IT821X is not set 503 + # CONFIG_BLK_DEV_NS87415 is not set 504 + # CONFIG_BLK_DEV_PDC202XX_OLD is not set 505 + CONFIG_BLK_DEV_PDC202XX_NEW=y 506 + # CONFIG_BLK_DEV_SVWKS is not set 507 + # CONFIG_BLK_DEV_SIIMAGE is not set 508 + # CONFIG_BLK_DEV_SL82C105 is not set 509 + # CONFIG_BLK_DEV_SLC90E66 is not set 510 + # CONFIG_BLK_DEV_TRM290 is not set 511 + # CONFIG_BLK_DEV_VIA82CXXX is not set 512 + # CONFIG_BLK_DEV_TC86C001 is not set 513 + # CONFIG_IDE_ARM is not set 514 + CONFIG_BLK_DEV_IDEDMA=y 515 + # CONFIG_IDEDMA_IVB is not set 516 + # CONFIG_BLK_DEV_HD is not set 517 + 518 + # 519 + # SCSI device support 520 + # 521 + # CONFIG_RAID_ATTRS is not set 522 + CONFIG_SCSI=y 523 + # CONFIG_SCSI_TGT is not set 524 + # CONFIG_SCSI_NETLINK is not set 525 + CONFIG_SCSI_PROC_FS=y 526 + 527 + # 528 + # SCSI support type (disk, tape, CD-ROM) 529 + # 530 + CONFIG_BLK_DEV_SD=y 531 + # CONFIG_CHR_DEV_ST is not set 532 + # CONFIG_CHR_DEV_OSST is not set 533 + # CONFIG_BLK_DEV_SR is not set 534 + # CONFIG_CHR_DEV_SG is not set 535 + # CONFIG_CHR_DEV_SCH is not set 536 + 537 + # 538 + # Some SCSI devices (e.g. CD jukebox) support multiple LUNs 539 + # 540 + # CONFIG_SCSI_MULTI_LUN is not set 541 + # CONFIG_SCSI_CONSTANTS is not set 542 + # CONFIG_SCSI_LOGGING is not set 543 + # CONFIG_SCSI_SCAN_ASYNC is not set 544 + 545 + # 546 + # SCSI Transports 547 + # 548 + # CONFIG_SCSI_SPI_ATTRS is not set 549 + # CONFIG_SCSI_FC_ATTRS is not set 550 + # CONFIG_SCSI_ISCSI_ATTRS is not set 551 + # CONFIG_SCSI_SAS_ATTRS is not set 552 + # CONFIG_SCSI_SAS_LIBSAS is not set 553 + 554 + # 555 + # SCSI low-level drivers 556 + # 557 + # CONFIG_ISCSI_TCP is not set 558 + # CONFIG_BLK_DEV_3W_XXXX_RAID is not set 559 + # CONFIG_SCSI_3W_9XXX is not set 560 + # CONFIG_SCSI_ACARD is not set 561 + # CONFIG_SCSI_AACRAID is not set 562 + # CONFIG_SCSI_AIC7XXX is not set 563 + # CONFIG_SCSI_AIC7XXX_OLD is not set 564 + # CONFIG_SCSI_AIC79XX is not set 565 + # CONFIG_SCSI_AIC94XX is not set 566 + # CONFIG_SCSI_DPT_I2O is not set 567 + # CONFIG_SCSI_ARCMSR is not set 568 + # CONFIG_MEGARAID_NEWGEN is not set 569 + # CONFIG_MEGARAID_LEGACY is not set 570 + # CONFIG_MEGARAID_SAS is not set 571 + # CONFIG_SCSI_HPTIOP is not set 572 + # CONFIG_SCSI_BUSLOGIC is not set 573 + # CONFIG_SCSI_DMX3191D is not set 574 + # CONFIG_SCSI_EATA is not set 575 + # CONFIG_SCSI_FUTURE_DOMAIN is not set 576 + # CONFIG_SCSI_GDTH is not set 577 + # CONFIG_SCSI_IPS is not set 578 + # CONFIG_SCSI_INITIO is not set 579 + # CONFIG_SCSI_INIA100 is not set 580 + # CONFIG_SCSI_STEX is not set 581 + # CONFIG_SCSI_SYM53C8XX_2 is not set 582 + # CONFIG_SCSI_IPR is not set 583 + # CONFIG_SCSI_QLOGIC_1280 is not set 584 + # CONFIG_SCSI_QLA_FC is not set 585 + # CONFIG_SCSI_QLA_ISCSI is not set 586 + # CONFIG_SCSI_LPFC is not set 587 + # CONFIG_SCSI_DC395x is not set 588 + # CONFIG_SCSI_DC390T is not set 589 + # CONFIG_SCSI_NSP32 is not set 590 + # CONFIG_SCSI_DEBUG is not set 591 + # CONFIG_SCSI_ESP_CORE is not set 592 + # CONFIG_SCSI_SRP is not set 593 + 594 + # 595 + # Serial ATA (prod) and Parallel ATA (experimental) drivers 596 + # 597 + CONFIG_ATA=y 598 + # CONFIG_ATA_NONSTANDARD is not set 599 + # CONFIG_SATA_AHCI is not set 600 + # CONFIG_SATA_SVW is not set 601 + # CONFIG_ATA_PIIX is not set 602 + CONFIG_SATA_MV=y 603 + # CONFIG_SATA_NV is not set 604 + # CONFIG_PDC_ADMA is not set 605 + # CONFIG_SATA_QSTOR is not set 606 + # CONFIG_SATA_PROMISE is not set 607 + # CONFIG_SATA_SX4 is not set 608 + # CONFIG_SATA_SIL is not set 609 + # CONFIG_SATA_SIL24 is not set 610 + # CONFIG_SATA_SIS is not set 611 + # CONFIG_SATA_ULI is not set 612 + # CONFIG_SATA_VIA is not set 613 + # CONFIG_SATA_VITESSE is not set 614 + # CONFIG_SATA_INIC162X is not set 615 + # CONFIG_PATA_ALI is not set 616 + # CONFIG_PATA_AMD is not set 617 + # CONFIG_PATA_ARTOP is not set 618 + # CONFIG_PATA_ATIIXP is not set 619 + # CONFIG_PATA_CMD640_PCI is not set 620 + # CONFIG_PATA_CMD64X is not set 621 + # CONFIG_PATA_CS5520 is not set 622 + # CONFIG_PATA_CS5530 is not set 623 + # CONFIG_PATA_CYPRESS is not set 624 + # CONFIG_PATA_EFAR is not set 625 + # CONFIG_ATA_GENERIC is not set 626 + # CONFIG_PATA_HPT366 is not set 627 + # CONFIG_PATA_HPT37X is not set 628 + # CONFIG_PATA_HPT3X2N is not set 629 + # CONFIG_PATA_HPT3X3 is not set 630 + # CONFIG_PATA_IT821X is not set 631 + # CONFIG_PATA_IT8213 is not set 632 + # CONFIG_PATA_JMICRON is not set 633 + # CONFIG_PATA_TRIFLEX is not set 634 + # CONFIG_PATA_MARVELL is not set 635 + # CONFIG_PATA_MPIIX is not set 636 + # CONFIG_PATA_OLDPIIX is not set 637 + # CONFIG_PATA_NETCELL is not set 638 + # CONFIG_PATA_NS87410 is not set 639 + # CONFIG_PATA_OPTI is not set 640 + # CONFIG_PATA_OPTIDMA is not set 641 + # CONFIG_PATA_PDC_OLD is not set 642 + # CONFIG_PATA_RADISYS is not set 643 + # CONFIG_PATA_RZ1000 is not set 644 + # CONFIG_PATA_SC1200 is not set 645 + # CONFIG_PATA_SERVERWORKS is not set 646 + # CONFIG_PATA_PDC2027X is not set 647 + # CONFIG_PATA_SIL680 is not set 648 + # CONFIG_PATA_SIS is not set 649 + # CONFIG_PATA_VIA is not set 650 + # CONFIG_PATA_WINBOND is not set 651 + 652 + # 653 + # Multi-device support (RAID and LVM) 654 + # 655 + # CONFIG_MD is not set 656 + 657 + # 658 + # Fusion MPT device support 659 + # 660 + # CONFIG_FUSION is not set 661 + # CONFIG_FUSION_SPI is not set 662 + # CONFIG_FUSION_FC is not set 663 + # CONFIG_FUSION_SAS is not set 664 + 665 + # 666 + # IEEE 1394 (FireWire) support 667 + # 668 + # CONFIG_IEEE1394 is not set 669 + 670 + # 671 + # I2O device support 672 + # 673 + # CONFIG_I2O is not set 674 + CONFIG_MACINTOSH_DRIVERS=y 675 + # CONFIG_MAC_EMUMOUSEBTN is not set 676 + # CONFIG_WINDFARM is not set 677 + 678 + # 679 + # Network device support 680 + # 681 + CONFIG_NETDEVICES=y 682 + # CONFIG_DUMMY is not set 683 + # CONFIG_BONDING is not set 684 + # CONFIG_EQUALIZER is not set 685 + # CONFIG_TUN is not set 686 + 687 + # 688 + # ARCnet devices 689 + # 690 + # CONFIG_ARCNET is not set 691 + 692 + # 693 + # PHY device support 694 + # 695 + CONFIG_PHYLIB=y 696 + 697 + # 698 + # MII PHY device drivers 699 + # 700 + # CONFIG_MARVELL_PHY is not set 701 + # CONFIG_DAVICOM_PHY is not set 702 + # CONFIG_QSEMI_PHY is not set 703 + # CONFIG_LXT_PHY is not set 704 + # CONFIG_CICADA_PHY is not set 705 + # CONFIG_VITESSE_PHY is not set 706 + # CONFIG_SMSC_PHY is not set 707 + # CONFIG_BROADCOM_PHY is not set 708 + # CONFIG_FIXED_PHY is not set 709 + 710 + # 711 + # Ethernet (10 or 100Mbit) 712 + # 713 + CONFIG_NET_ETHERNET=y 714 + CONFIG_MII=y 715 + # CONFIG_HAPPYMEAL is not set 716 + # CONFIG_SUNGEM is not set 717 + # CONFIG_CASSINI is not set 718 + # CONFIG_NET_VENDOR_3COM is not set 719 + 720 + # 721 + # Tulip family network device support 722 + # 723 + # CONFIG_NET_TULIP is not set 724 + # CONFIG_HP100 is not set 725 + CONFIG_NET_PCI=y 726 + # CONFIG_PCNET32 is not set 727 + # CONFIG_AMD8111_ETH is not set 728 + # CONFIG_ADAPTEC_STARFIRE is not set 729 + # CONFIG_B44 is not set 730 + # CONFIG_FORCEDETH is not set 731 + # CONFIG_DGRS is not set 732 + # CONFIG_EEPRO100 is not set 733 + CONFIG_E100=y 734 + # CONFIG_FEALNX is not set 735 + # CONFIG_NATSEMI is not set 736 + # CONFIG_NE2K_PCI is not set 737 + # CONFIG_8139CP is not set 738 + CONFIG_8139TOO=y 739 + # CONFIG_8139TOO_PIO is not set 740 + # CONFIG_8139TOO_TUNE_TWISTER is not set 741 + # CONFIG_8139TOO_8129 is not set 742 + # CONFIG_8139_OLD_RX_RESET is not set 743 + # CONFIG_SIS900 is not set 744 + # CONFIG_EPIC100 is not set 745 + # CONFIG_SUNDANCE is not set 746 + # CONFIG_TLAN is not set 747 + # CONFIG_VIA_RHINE is not set 748 + # CONFIG_SC92031 is not set 749 + 750 + # 751 + # Ethernet (1000 Mbit) 752 + # 753 + # CONFIG_ACENIC is not set 754 + # CONFIG_DL2K is not set 755 + CONFIG_E1000=y 756 + # CONFIG_E1000_NAPI is not set 757 + # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set 758 + # CONFIG_NS83820 is not set 759 + # CONFIG_HAMACHI is not set 760 + # CONFIG_YELLOWFIN is not set 761 + # CONFIG_R8169 is not set 762 + # CONFIG_SIS190 is not set 763 + # CONFIG_SKGE is not set 764 + # CONFIG_SKY2 is not set 765 + # CONFIG_SK98LIN is not set 766 + # CONFIG_VIA_VELOCITY is not set 767 + # CONFIG_TIGON3 is not set 768 + # CONFIG_BNX2 is not set 769 + CONFIG_MV643XX_ETH=y 770 + # CONFIG_QLA3XXX is not set 771 + # CONFIG_ATL1 is not set 772 + 773 + # 774 + # Ethernet (10000 Mbit) 775 + # 776 + # CONFIG_CHELSIO_T1 is not set 777 + # CONFIG_CHELSIO_T3 is not set 778 + # CONFIG_IXGB is not set 779 + # CONFIG_S2IO is not set 780 + # CONFIG_MYRI10GE is not set 781 + # CONFIG_NETXEN_NIC is not set 782 + 783 + # 784 + # Token Ring devices 785 + # 786 + # CONFIG_TR is not set 787 + 788 + # 789 + # Wireless LAN 790 + # 791 + # CONFIG_WLAN_PRE80211 is not set 792 + # CONFIG_WLAN_80211 is not set 793 + 794 + # 795 + # Wan interfaces 796 + # 797 + # CONFIG_WAN is not set 798 + # CONFIG_FDDI is not set 799 + # CONFIG_HIPPI is not set 800 + # CONFIG_PPP is not set 801 + # CONFIG_SLIP is not set 802 + # CONFIG_NET_FC is not set 803 + # CONFIG_SHAPER is not set 804 + # CONFIG_NETCONSOLE is not set 805 + # CONFIG_NETPOLL is not set 806 + # CONFIG_NET_POLL_CONTROLLER is not set 807 + 808 + # 809 + # ISDN subsystem 810 + # 811 + # CONFIG_ISDN is not set 812 + 813 + # 814 + # Telephony Support 815 + # 816 + # CONFIG_PHONE is not set 817 + 818 + # 819 + # Input device support 820 + # 821 + CONFIG_INPUT=y 822 + # CONFIG_INPUT_FF_MEMLESS is not set 823 + 824 + # 825 + # Userland interfaces 826 + # 827 + CONFIG_INPUT_MOUSEDEV=y 828 + CONFIG_INPUT_MOUSEDEV_PSAUX=y 829 + CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 830 + CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 831 + # CONFIG_INPUT_JOYDEV is not set 832 + # CONFIG_INPUT_TSDEV is not set 833 + # CONFIG_INPUT_EVDEV is not set 834 + # CONFIG_INPUT_EVBUG is not set 835 + 836 + # 837 + # Input Device Drivers 838 + # 839 + # CONFIG_INPUT_KEYBOARD is not set 840 + # CONFIG_INPUT_MOUSE is not set 841 + # CONFIG_INPUT_JOYSTICK is not set 842 + # CONFIG_INPUT_TABLET is not set 843 + # CONFIG_INPUT_TOUCHSCREEN is not set 844 + # CONFIG_INPUT_MISC is not set 845 + 846 + # 847 + # Hardware I/O ports 848 + # 849 + # CONFIG_SERIO is not set 850 + # CONFIG_GAMEPORT is not set 851 + 852 + # 853 + # Character devices 854 + # 855 + CONFIG_VT=y 856 + CONFIG_VT_CONSOLE=y 857 + CONFIG_HW_CONSOLE=y 858 + # CONFIG_VT_HW_CONSOLE_BINDING is not set 859 + # CONFIG_SERIAL_NONSTANDARD is not set 860 + 861 + # 862 + # Serial drivers 863 + # 864 + # CONFIG_SERIAL_8250 is not set 865 + 866 + # 867 + # Non-8250 serial port support 868 + # 869 + CONFIG_SERIAL_MPSC=y 870 + CONFIG_SERIAL_MPSC_CONSOLE=y 871 + # CONFIG_SERIAL_UARTLITE is not set 872 + CONFIG_SERIAL_CORE=y 873 + CONFIG_SERIAL_CORE_CONSOLE=y 874 + # CONFIG_SERIAL_JSM is not set 875 + CONFIG_UNIX98_PTYS=y 876 + CONFIG_LEGACY_PTYS=y 877 + CONFIG_LEGACY_PTY_COUNT=256 878 + 879 + # 880 + # IPMI 881 + # 882 + # CONFIG_IPMI_HANDLER is not set 883 + 884 + # 885 + # Watchdog Cards 886 + # 887 + # CONFIG_WATCHDOG is not set 888 + # CONFIG_HW_RANDOM is not set 889 + # CONFIG_NVRAM is not set 890 + CONFIG_GEN_RTC=y 891 + # CONFIG_GEN_RTC_X is not set 892 + # CONFIG_DTLK is not set 893 + # CONFIG_R3964 is not set 894 + # CONFIG_APPLICOM is not set 895 + # CONFIG_AGP is not set 896 + # CONFIG_DRM is not set 897 + # CONFIG_RAW_DRIVER is not set 898 + 899 + # 900 + # TPM devices 901 + # 902 + # CONFIG_TCG_TPM is not set 903 + CONFIG_DEVPORT=y 904 + CONFIG_I2C=y 905 + CONFIG_I2C_BOARDINFO=y 906 + CONFIG_I2C_CHARDEV=y 907 + 908 + # 909 + # I2C Algorithms 910 + # 911 + # CONFIG_I2C_ALGOBIT is not set 912 + # CONFIG_I2C_ALGOPCF is not set 913 + # CONFIG_I2C_ALGOPCA is not set 914 + 915 + # 916 + # I2C Hardware Bus support 917 + # 918 + # CONFIG_I2C_ALI1535 is not set 919 + # CONFIG_I2C_ALI1563 is not set 920 + # CONFIG_I2C_ALI15X3 is not set 921 + # CONFIG_I2C_AMD756 is not set 922 + # CONFIG_I2C_AMD8111 is not set 923 + # CONFIG_I2C_I801 is not set 924 + # CONFIG_I2C_I810 is not set 925 + # CONFIG_I2C_PIIX4 is not set 926 + # CONFIG_I2C_MPC is not set 927 + # CONFIG_I2C_NFORCE2 is not set 928 + # CONFIG_I2C_OCORES is not set 929 + # CONFIG_I2C_PARPORT_LIGHT is not set 930 + # CONFIG_I2C_PROSAVAGE is not set 931 + # CONFIG_I2C_SAVAGE4 is not set 932 + # CONFIG_I2C_SIMTEC is not set 933 + # CONFIG_I2C_SIS5595 is not set 934 + # CONFIG_I2C_SIS630 is not set 935 + # CONFIG_I2C_SIS96X is not set 936 + # CONFIG_I2C_TINY_USB is not set 937 + # CONFIG_I2C_VIA is not set 938 + # CONFIG_I2C_VIAPRO is not set 939 + # CONFIG_I2C_VOODOO3 is not set 940 + CONFIG_I2C_MV64XXX=y 941 + 942 + # 943 + # Miscellaneous I2C Chip support 944 + # 945 + # CONFIG_SENSORS_DS1337 is not set 946 + # CONFIG_SENSORS_DS1374 is not set 947 + # CONFIG_SENSORS_EEPROM is not set 948 + # CONFIG_SENSORS_PCF8574 is not set 949 + # CONFIG_SENSORS_PCA9539 is not set 950 + # CONFIG_SENSORS_PCF8591 is not set 951 + # CONFIG_SENSORS_M41T00 is not set 952 + # CONFIG_SENSORS_MAX6875 is not set 953 + # CONFIG_I2C_DEBUG_CORE is not set 954 + # CONFIG_I2C_DEBUG_ALGO is not set 955 + # CONFIG_I2C_DEBUG_BUS is not set 956 + # CONFIG_I2C_DEBUG_CHIP is not set 957 + 958 + # 959 + # SPI support 960 + # 961 + # CONFIG_SPI is not set 962 + # CONFIG_SPI_MASTER is not set 963 + 964 + # 965 + # Dallas's 1-wire bus 966 + # 967 + # CONFIG_W1 is not set 968 + CONFIG_HWMON=y 969 + # CONFIG_HWMON_VID is not set 970 + # CONFIG_SENSORS_ABITUGURU is not set 971 + # CONFIG_SENSORS_AD7418 is not set 972 + # CONFIG_SENSORS_ADM1021 is not set 973 + # CONFIG_SENSORS_ADM1025 is not set 974 + # CONFIG_SENSORS_ADM1026 is not set 975 + # CONFIG_SENSORS_ADM1029 is not set 976 + # CONFIG_SENSORS_ADM1031 is not set 977 + # CONFIG_SENSORS_ADM9240 is not set 978 + # CONFIG_SENSORS_ASB100 is not set 979 + # CONFIG_SENSORS_ATXP1 is not set 980 + # CONFIG_SENSORS_DS1621 is not set 981 + # CONFIG_SENSORS_F71805F is not set 982 + # CONFIG_SENSORS_FSCHER is not set 983 + # CONFIG_SENSORS_FSCPOS is not set 984 + # CONFIG_SENSORS_GL518SM is not set 985 + # CONFIG_SENSORS_GL520SM is not set 986 + # CONFIG_SENSORS_IT87 is not set 987 + # CONFIG_SENSORS_LM63 is not set 988 + # CONFIG_SENSORS_LM75 is not set 989 + # CONFIG_SENSORS_LM77 is not set 990 + # CONFIG_SENSORS_LM78 is not set 991 + # CONFIG_SENSORS_LM80 is not set 992 + # CONFIG_SENSORS_LM83 is not set 993 + # CONFIG_SENSORS_LM85 is not set 994 + # CONFIG_SENSORS_LM87 is not set 995 + # CONFIG_SENSORS_LM90 is not set 996 + # CONFIG_SENSORS_LM92 is not set 997 + # CONFIG_SENSORS_MAX1619 is not set 998 + # CONFIG_SENSORS_MAX6650 is not set 999 + # CONFIG_SENSORS_PC87360 is not set 1000 + # CONFIG_SENSORS_PC87427 is not set 1001 + # CONFIG_SENSORS_SIS5595 is not set 1002 + # CONFIG_SENSORS_SMSC47M1 is not set 1003 + # CONFIG_SENSORS_SMSC47M192 is not set 1004 + # CONFIG_SENSORS_SMSC47B397 is not set 1005 + # CONFIG_SENSORS_VIA686A is not set 1006 + # CONFIG_SENSORS_VT1211 is not set 1007 + # CONFIG_SENSORS_VT8231 is not set 1008 + # CONFIG_SENSORS_W83781D is not set 1009 + # CONFIG_SENSORS_W83791D is not set 1010 + # CONFIG_SENSORS_W83792D is not set 1011 + # CONFIG_SENSORS_W83793 is not set 1012 + # CONFIG_SENSORS_W83L785TS is not set 1013 + # CONFIG_SENSORS_W83627HF is not set 1014 + # CONFIG_SENSORS_W83627EHF is not set 1015 + # CONFIG_HWMON_DEBUG_CHIP is not set 1016 + 1017 + # 1018 + # Multifunction device drivers 1019 + # 1020 + # CONFIG_MFD_SM501 is not set 1021 + 1022 + # 1023 + # Multimedia devices 1024 + # 1025 + # CONFIG_VIDEO_DEV is not set 1026 + 1027 + # 1028 + # Digital Video Broadcasting Devices 1029 + # 1030 + # CONFIG_DVB is not set 1031 + # CONFIG_USB_DABUSB is not set 1032 + 1033 + # 1034 + # Graphics support 1035 + # 1036 + # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1037 + 1038 + # 1039 + # Display device support 1040 + # 1041 + # CONFIG_DISPLAY_SUPPORT is not set 1042 + # CONFIG_VGASTATE is not set 1043 + # CONFIG_FB is not set 1044 + # CONFIG_FB_IBM_GXT4500 is not set 1045 + 1046 + # 1047 + # Console display driver support 1048 + # 1049 + CONFIG_VGA_CONSOLE=y 1050 + # CONFIG_VGACON_SOFT_SCROLLBACK is not set 1051 + CONFIG_DUMMY_CONSOLE=y 1052 + 1053 + # 1054 + # Sound 1055 + # 1056 + # CONFIG_SOUND is not set 1057 + 1058 + # 1059 + # HID Devices 1060 + # 1061 + CONFIG_HID=y 1062 + # CONFIG_HID_DEBUG is not set 1063 + 1064 + # 1065 + # USB Input Devices 1066 + # 1067 + CONFIG_USB_HID=y 1068 + # CONFIG_USB_HIDINPUT_POWERBOOK is not set 1069 + # CONFIG_HID_FF is not set 1070 + # CONFIG_USB_HIDDEV is not set 1071 + 1072 + # 1073 + # USB support 1074 + # 1075 + CONFIG_USB_ARCH_HAS_HCD=y 1076 + CONFIG_USB_ARCH_HAS_OHCI=y 1077 + CONFIG_USB_ARCH_HAS_EHCI=y 1078 + CONFIG_USB=y 1079 + # CONFIG_USB_DEBUG is not set 1080 + 1081 + # 1082 + # Miscellaneous USB options 1083 + # 1084 + CONFIG_USB_DEVICEFS=y 1085 + # CONFIG_USB_DEVICE_CLASS is not set 1086 + # CONFIG_USB_DYNAMIC_MINORS is not set 1087 + # CONFIG_USB_OTG is not set 1088 + 1089 + # 1090 + # USB Host Controller Drivers 1091 + # 1092 + CONFIG_USB_EHCI_HCD=y 1093 + # CONFIG_USB_EHCI_SPLIT_ISO is not set 1094 + # CONFIG_USB_EHCI_ROOT_HUB_TT is not set 1095 + # CONFIG_USB_EHCI_TT_NEWSCHED is not set 1096 + # CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set 1097 + # CONFIG_USB_ISP116X_HCD is not set 1098 + CONFIG_USB_OHCI_HCD=y 1099 + # CONFIG_USB_OHCI_HCD_PPC_OF is not set 1100 + # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1101 + # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1102 + CONFIG_USB_OHCI_LITTLE_ENDIAN=y 1103 + # CONFIG_USB_UHCI_HCD is not set 1104 + # CONFIG_USB_SL811_HCD is not set 1105 + 1106 + # 1107 + # USB Device Class drivers 1108 + # 1109 + # CONFIG_USB_ACM is not set 1110 + # CONFIG_USB_PRINTER is not set 1111 + 1112 + # 1113 + # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1114 + # 1115 + 1116 + # 1117 + # may also be needed; see USB_STORAGE Help for more information 1118 + # 1119 + # CONFIG_USB_STORAGE is not set 1120 + # CONFIG_USB_LIBUSUAL is not set 1121 + 1122 + # 1123 + # USB Imaging devices 1124 + # 1125 + # CONFIG_USB_MDC800 is not set 1126 + # CONFIG_USB_MICROTEK is not set 1127 + 1128 + # 1129 + # USB Network Adapters 1130 + # 1131 + # CONFIG_USB_CATC is not set 1132 + # CONFIG_USB_KAWETH is not set 1133 + # CONFIG_USB_PEGASUS is not set 1134 + # CONFIG_USB_RTL8150 is not set 1135 + # CONFIG_USB_USBNET_MII is not set 1136 + # CONFIG_USB_USBNET is not set 1137 + CONFIG_USB_MON=y 1138 + 1139 + # 1140 + # USB port drivers 1141 + # 1142 + 1143 + # 1144 + # USB Serial Converter support 1145 + # 1146 + # CONFIG_USB_SERIAL is not set 1147 + 1148 + # 1149 + # USB Miscellaneous drivers 1150 + # 1151 + # CONFIG_USB_EMI62 is not set 1152 + # CONFIG_USB_EMI26 is not set 1153 + # CONFIG_USB_ADUTUX is not set 1154 + # CONFIG_USB_AUERSWALD is not set 1155 + # CONFIG_USB_RIO500 is not set 1156 + # CONFIG_USB_LEGOTOWER is not set 1157 + # CONFIG_USB_LCD is not set 1158 + # CONFIG_USB_BERRY_CHARGE is not set 1159 + # CONFIG_USB_LED is not set 1160 + # CONFIG_USB_CYPRESS_CY7C63 is not set 1161 + # CONFIG_USB_CYTHERM is not set 1162 + # CONFIG_USB_PHIDGET is not set 1163 + # CONFIG_USB_IDMOUSE is not set 1164 + # CONFIG_USB_FTDI_ELAN is not set 1165 + # CONFIG_USB_APPLEDISPLAY is not set 1166 + # CONFIG_USB_SISUSBVGA is not set 1167 + # CONFIG_USB_LD is not set 1168 + # CONFIG_USB_TRANCEVIBRATOR is not set 1169 + # CONFIG_USB_IOWARRIOR is not set 1170 + # CONFIG_USB_TEST is not set 1171 + 1172 + # 1173 + # USB DSL modem support 1174 + # 1175 + 1176 + # 1177 + # USB Gadget Support 1178 + # 1179 + # CONFIG_USB_GADGET is not set 1180 + # CONFIG_MMC is not set 1181 + 1182 + # 1183 + # LED devices 1184 + # 1185 + # CONFIG_NEW_LEDS is not set 1186 + 1187 + # 1188 + # LED drivers 1189 + # 1190 + 1191 + # 1192 + # LED Triggers 1193 + # 1194 + 1195 + # 1196 + # InfiniBand support 1197 + # 1198 + # CONFIG_INFINIBAND is not set 1199 + 1200 + # 1201 + # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) 1202 + # 1203 + 1204 + # 1205 + # Real Time Clock 1206 + # 1207 + CONFIG_RTC_LIB=y 1208 + CONFIG_RTC_CLASS=y 1209 + CONFIG_RTC_HCTOSYS=y 1210 + CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 1211 + # CONFIG_RTC_DEBUG is not set 1212 + 1213 + # 1214 + # RTC interfaces 1215 + # 1216 + CONFIG_RTC_INTF_SYSFS=y 1217 + CONFIG_RTC_INTF_PROC=y 1218 + CONFIG_RTC_INTF_DEV=y 1219 + # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 1220 + # CONFIG_RTC_DRV_TEST is not set 1221 + 1222 + # 1223 + # I2C RTC drivers 1224 + # 1225 + # CONFIG_RTC_DRV_DS1307 is not set 1226 + # CONFIG_RTC_DRV_DS1672 is not set 1227 + CONFIG_RTC_DRV_MAX6900=y 1228 + # CONFIG_RTC_DRV_RS5C372 is not set 1229 + # CONFIG_RTC_DRV_ISL1208 is not set 1230 + # CONFIG_RTC_DRV_X1205 is not set 1231 + # CONFIG_RTC_DRV_PCF8563 is not set 1232 + # CONFIG_RTC_DRV_PCF8583 is not set 1233 + 1234 + # 1235 + # SPI RTC drivers 1236 + # 1237 + 1238 + # 1239 + # Platform RTC drivers 1240 + # 1241 + # CONFIG_RTC_DRV_DS1553 is not set 1242 + # CONFIG_RTC_DRV_DS1742 is not set 1243 + # CONFIG_RTC_DRV_M48T86 is not set 1244 + # CONFIG_RTC_DRV_V3020 is not set 1245 + 1246 + # 1247 + # on-CPU RTC drivers 1248 + # 1249 + 1250 + # 1251 + # DMA Engine support 1252 + # 1253 + # CONFIG_DMA_ENGINE is not set 1254 + 1255 + # 1256 + # DMA Clients 1257 + # 1258 + 1259 + # 1260 + # DMA Devices 1261 + # 1262 + 1263 + # 1264 + # Auxiliary Display support 1265 + # 1266 + 1267 + # 1268 + # Virtualization 1269 + # 1270 + 1271 + # 1272 + # File systems 1273 + # 1274 + CONFIG_EXT2_FS=y 1275 + # CONFIG_EXT2_FS_XATTR is not set 1276 + # CONFIG_EXT2_FS_XIP is not set 1277 + CONFIG_EXT3_FS=y 1278 + CONFIG_EXT3_FS_XATTR=y 1279 + # CONFIG_EXT3_FS_POSIX_ACL is not set 1280 + # CONFIG_EXT3_FS_SECURITY is not set 1281 + # CONFIG_EXT4DEV_FS is not set 1282 + CONFIG_JBD=y 1283 + # CONFIG_JBD_DEBUG is not set 1284 + CONFIG_FS_MBCACHE=y 1285 + # CONFIG_REISERFS_FS is not set 1286 + # CONFIG_JFS_FS is not set 1287 + # CONFIG_FS_POSIX_ACL is not set 1288 + # CONFIG_XFS_FS is not set 1289 + # CONFIG_GFS2_FS is not set 1290 + # CONFIG_OCFS2_FS is not set 1291 + # CONFIG_MINIX_FS is not set 1292 + # CONFIG_ROMFS_FS is not set 1293 + CONFIG_INOTIFY=y 1294 + CONFIG_INOTIFY_USER=y 1295 + # CONFIG_QUOTA is not set 1296 + CONFIG_DNOTIFY=y 1297 + # CONFIG_AUTOFS_FS is not set 1298 + # CONFIG_AUTOFS4_FS is not set 1299 + # CONFIG_FUSE_FS is not set 1300 + 1301 + # 1302 + # CD-ROM/DVD Filesystems 1303 + # 1304 + # CONFIG_ISO9660_FS is not set 1305 + # CONFIG_UDF_FS is not set 1306 + 1307 + # 1308 + # DOS/FAT/NT Filesystems 1309 + # 1310 + # CONFIG_MSDOS_FS is not set 1311 + # CONFIG_VFAT_FS is not set 1312 + # CONFIG_NTFS_FS is not set 1313 + 1314 + # 1315 + # Pseudo filesystems 1316 + # 1317 + CONFIG_PROC_FS=y 1318 + CONFIG_PROC_KCORE=y 1319 + CONFIG_PROC_SYSCTL=y 1320 + CONFIG_SYSFS=y 1321 + CONFIG_TMPFS=y 1322 + # CONFIG_TMPFS_POSIX_ACL is not set 1323 + # CONFIG_HUGETLB_PAGE is not set 1324 + CONFIG_RAMFS=y 1325 + # CONFIG_CONFIGFS_FS is not set 1326 + 1327 + # 1328 + # Miscellaneous filesystems 1329 + # 1330 + # CONFIG_ADFS_FS is not set 1331 + # CONFIG_AFFS_FS is not set 1332 + # CONFIG_HFS_FS is not set 1333 + # CONFIG_HFSPLUS_FS is not set 1334 + # CONFIG_BEFS_FS is not set 1335 + # CONFIG_BFS_FS is not set 1336 + # CONFIG_EFS_FS is not set 1337 + # CONFIG_JFFS2_FS is not set 1338 + # CONFIG_CRAMFS is not set 1339 + # CONFIG_VXFS_FS is not set 1340 + # CONFIG_HPFS_FS is not set 1341 + # CONFIG_QNX4FS_FS is not set 1342 + # CONFIG_SYSV_FS is not set 1343 + # CONFIG_UFS_FS is not set 1344 + 1345 + # 1346 + # Network File Systems 1347 + # 1348 + CONFIG_NFS_FS=y 1349 + # CONFIG_NFS_V3 is not set 1350 + # CONFIG_NFS_V4 is not set 1351 + # CONFIG_NFS_DIRECTIO is not set 1352 + # CONFIG_NFSD is not set 1353 + CONFIG_ROOT_NFS=y 1354 + CONFIG_LOCKD=y 1355 + CONFIG_NFS_COMMON=y 1356 + CONFIG_SUNRPC=y 1357 + # CONFIG_SUNRPC_BIND34 is not set 1358 + # CONFIG_RPCSEC_GSS_KRB5 is not set 1359 + # CONFIG_RPCSEC_GSS_SPKM3 is not set 1360 + # CONFIG_SMB_FS is not set 1361 + # CONFIG_CIFS is not set 1362 + # CONFIG_NCP_FS is not set 1363 + # CONFIG_CODA_FS is not set 1364 + # CONFIG_AFS_FS is not set 1365 + # CONFIG_9P_FS is not set 1366 + 1367 + # 1368 + # Partition Types 1369 + # 1370 + CONFIG_PARTITION_ADVANCED=y 1371 + # CONFIG_ACORN_PARTITION is not set 1372 + # CONFIG_OSF_PARTITION is not set 1373 + # CONFIG_AMIGA_PARTITION is not set 1374 + # CONFIG_ATARI_PARTITION is not set 1375 + # CONFIG_MAC_PARTITION is not set 1376 + CONFIG_MSDOS_PARTITION=y 1377 + # CONFIG_BSD_DISKLABEL is not set 1378 + # CONFIG_MINIX_SUBPARTITION is not set 1379 + # CONFIG_SOLARIS_X86_PARTITION is not set 1380 + # CONFIG_UNIXWARE_DISKLABEL is not set 1381 + # CONFIG_LDM_PARTITION is not set 1382 + # CONFIG_SGI_PARTITION is not set 1383 + # CONFIG_ULTRIX_PARTITION is not set 1384 + # CONFIG_SUN_PARTITION is not set 1385 + # CONFIG_KARMA_PARTITION is not set 1386 + # CONFIG_EFI_PARTITION is not set 1387 + # CONFIG_SYSV68_PARTITION is not set 1388 + 1389 + # 1390 + # Native Language Support 1391 + # 1392 + # CONFIG_NLS is not set 1393 + 1394 + # 1395 + # Distributed Lock Manager 1396 + # 1397 + # CONFIG_DLM is not set 1398 + # CONFIG_UCC_SLOW is not set 1399 + # CONFIG_UCC_FAST is not set 1400 + 1401 + # 1402 + # Library routines 1403 + # 1404 + CONFIG_BITREVERSE=y 1405 + # CONFIG_CRC_CCITT is not set 1406 + # CONFIG_CRC16 is not set 1407 + CONFIG_CRC32=y 1408 + # CONFIG_LIBCRC32C is not set 1409 + CONFIG_PLIST=y 1410 + CONFIG_HAS_IOMEM=y 1411 + CONFIG_HAS_IOPORT=y 1412 + CONFIG_HAS_DMA=y 1413 + 1414 + # 1415 + # Instrumentation Support 1416 + # 1417 + # CONFIG_PROFILING is not set 1418 + 1419 + # 1420 + # Kernel hacking 1421 + # 1422 + # CONFIG_PRINTK_TIME is not set 1423 + CONFIG_ENABLE_MUST_CHECK=y 1424 + # CONFIG_MAGIC_SYSRQ is not set 1425 + # CONFIG_UNUSED_SYMBOLS is not set 1426 + # CONFIG_DEBUG_FS is not set 1427 + # CONFIG_HEADERS_CHECK is not set 1428 + # CONFIG_DEBUG_KERNEL is not set 1429 + CONFIG_DEBUG_BUGVERBOSE=y 1430 + # CONFIG_BOOTX_TEXT is not set 1431 + # CONFIG_PPC_EARLY_DEBUG is not set 1432 + 1433 + # 1434 + # Security options 1435 + # 1436 + # CONFIG_KEYS is not set 1437 + # CONFIG_SECURITY is not set 1438 + 1439 + # 1440 + # Cryptographic options 1441 + # 1442 + # CONFIG_CRYPTO is not set
+64 -103
arch/powerpc/configs/ps3_defconfig
··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 3 # Linux kernel version: 2.6.21 4 - # Mon Apr 30 12:03:35 2007 4 + # Fri May 11 10:16:27 2007 5 5 # 6 6 CONFIG_PPC64=y 7 7 CONFIG_64BIT=y ··· 40 40 # CONFIG_PPC_OF_PLATFORM_PCI is not set 41 41 CONFIG_ALTIVEC=y 42 42 CONFIG_PPC_STD_MMU=y 43 + # CONFIG_PPC_MM_SLICES is not set 43 44 CONFIG_VIRT_CPU_ACCOUNTING=y 44 45 CONFIG_SMP=y 45 46 CONFIG_NR_CPUS=2 ··· 68 67 # CONFIG_UTS_NS is not set 69 68 # CONFIG_AUDIT is not set 70 69 # CONFIG_IKCONFIG is not set 70 + CONFIG_LOG_BUF_SHIFT=17 71 71 # CONFIG_CPUSETS is not set 72 72 CONFIG_SYSFS_DEPRECATED=y 73 73 # CONFIG_RELAY is not set ··· 89 87 CONFIG_FUTEX=y 90 88 CONFIG_EPOLL=y 91 89 CONFIG_SHMEM=y 92 - CONFIG_SLAB=y 93 90 CONFIG_VM_EVENT_COUNTERS=y 91 + CONFIG_SLAB=y 92 + # CONFIG_SLUB is not set 93 + # CONFIG_SLOB is not set 94 94 CONFIG_RT_MUTEXES=y 95 95 # CONFIG_TINY_SHMEM is not set 96 96 CONFIG_BASE_SMALL=0 97 - # CONFIG_SLOB is not set 98 97 99 98 # 100 99 # Loadable module support ··· 216 213 CONFIG_RESOURCES_64BIT=y 217 214 CONFIG_ZONE_DMA_FLAG=1 218 215 CONFIG_ARCH_MEMORY_PROBE=y 216 + # CONFIG_PPC_HAS_HASH_64K is not set 219 217 # CONFIG_PPC_64K_PAGES is not set 220 218 # CONFIG_SCHED_SMT is not set 221 219 CONFIG_PROC_DEVICETREE=y ··· 233 229 CONFIG_GENERIC_ISA_DMA=y 234 230 # CONFIG_PCI is not set 235 231 # CONFIG_PCI_DOMAINS is not set 232 + # CONFIG_ARCH_SUPPORTS_MSI is not set 236 233 237 234 # 238 235 # PCCARD (PCMCIA/CardBus) support 239 236 # 240 237 # CONFIG_PCCARD is not set 241 - 242 - # 243 - # PCI Hotplug Support 244 - # 245 238 CONFIG_KERNEL_START=0xc000000000000000 246 239 247 240 # ··· 364 363 # 365 364 # CONFIG_CFG80211 is not set 366 365 CONFIG_WIRELESS_EXT=y 366 + # CONFIG_MAC80211 is not set 367 367 # CONFIG_IEEE80211 is not set 368 + # CONFIG_RFKILL is not set 368 369 369 370 # 370 371 # Device Drivers ··· 417 414 # 418 415 # Misc devices 419 416 # 417 + # CONFIG_BLINK is not set 420 418 421 419 # 422 420 # ATA/ATAPI/MFM/RLL support ··· 451 447 # CONFIG_SCSI_CONSTANTS is not set 452 448 # CONFIG_SCSI_LOGGING is not set 453 449 # CONFIG_SCSI_SCAN_ASYNC is not set 450 + CONFIG_SCSI_WAIT_SCAN=m 454 451 455 452 # 456 453 # SCSI Transports ··· 478 473 # Multi-device support (RAID and LVM) 479 474 # 480 475 # CONFIG_MD is not set 481 - 482 - # 483 - # Fusion MPT device support 484 - # 485 - # CONFIG_FUSION is not set 486 - 487 - # 488 - # IEEE 1394 (FireWire) support 489 - # 490 - 491 - # 492 - # I2O device support 493 - # 494 - 495 - # 496 - # Macintosh device drivers 497 - # 498 - # CONFIG_MAC_EMUMOUSEBTN is not set 499 - # CONFIG_WINDFARM is not set 476 + # CONFIG_MACINTOSH_DRIVERS is not set 500 477 501 478 # 502 479 # Network device support ··· 506 519 # 507 520 # Ethernet (10000 Mbit) 508 521 # 522 + CONFIG_MLX4_DEBUG=y 509 523 510 524 # 511 525 # Token Ring devices ··· 517 529 # 518 530 # CONFIG_WLAN_PRE80211 is not set 519 531 # CONFIG_WLAN_80211 is not set 532 + 533 + # 534 + # USB Network Adapters 535 + # 536 + # CONFIG_USB_CATC is not set 537 + # CONFIG_USB_KAWETH is not set 538 + CONFIG_USB_PEGASUS=m 539 + # CONFIG_USB_RTL8150 is not set 540 + CONFIG_USB_USBNET_MII=m 541 + CONFIG_USB_USBNET=m 542 + # CONFIG_USB_NET_CDCETHER is not set 543 + # CONFIG_USB_NET_DM9601 is not set 544 + # CONFIG_USB_NET_GL620A is not set 545 + # CONFIG_USB_NET_NET1080 is not set 546 + # CONFIG_USB_NET_PLUSB is not set 547 + CONFIG_USB_NET_MCS7830=m 548 + # CONFIG_USB_NET_RNDIS_HOST is not set 549 + # CONFIG_USB_NET_CDC_SUBSET is not set 550 + # CONFIG_USB_NET_ZAURUS is not set 520 551 521 552 # 522 553 # Wan interfaces ··· 582 575 # CONFIG_INPUT_KEYBOARD is not set 583 576 # CONFIG_INPUT_MOUSE is not set 584 577 # CONFIG_INPUT_JOYSTICK is not set 578 + # CONFIG_INPUT_TABLET is not set 585 579 # CONFIG_INPUT_TOUCHSCREEN is not set 586 580 # CONFIG_INPUT_MISC is not set 587 581 ··· 617 609 # IPMI 618 610 # 619 611 # CONFIG_IPMI_HANDLER is not set 620 - 621 - # 622 - # Watchdog Cards 623 - # 624 612 # CONFIG_WATCHDOG is not set 625 613 # CONFIG_HW_RANDOM is not set 626 614 CONFIG_GEN_RTC=y 627 615 # CONFIG_GEN_RTC_X is not set 628 - # CONFIG_DTLK is not set 629 616 # CONFIG_R3964 is not set 630 617 # CONFIG_RAW_DRIVER is not set 631 618 # CONFIG_HANGCHECK_TIMER is not set ··· 629 626 # TPM devices 630 627 # 631 628 # CONFIG_TCG_TPM is not set 632 - 633 - # 634 - # I2C support 635 - # 636 629 # CONFIG_I2C is not set 637 630 638 631 # ··· 641 642 # Dallas's 1-wire bus 642 643 # 643 644 # CONFIG_W1 is not set 644 - 645 - # 646 - # Hardware Monitoring support 647 - # 648 645 # CONFIG_HWMON is not set 649 - # CONFIG_HWMON_VID is not set 650 646 651 647 # 652 648 # Multifunction device drivers ··· 663 669 # Graphics support 664 670 # 665 671 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set 672 + 673 + # 674 + # Display device support 675 + # 676 + # CONFIG_DISPLAY_SUPPORT is not set 677 + # CONFIG_VGASTATE is not set 666 678 CONFIG_FB=y 667 679 # CONFIG_FIRMWARE_EDID is not set 668 680 # CONFIG_FB_DDC is not set 669 681 CONFIG_FB_CFB_FILLRECT=y 670 682 CONFIG_FB_CFB_COPYAREA=y 671 683 CONFIG_FB_CFB_IMAGEBLIT=y 684 + # CONFIG_FB_SYS_FILLRECT is not set 685 + # CONFIG_FB_SYS_COPYAREA is not set 686 + # CONFIG_FB_SYS_IMAGEBLIT is not set 687 + # CONFIG_FB_SYS_FOPS is not set 688 + CONFIG_FB_DEFERRED_IO=y 672 689 # CONFIG_FB_SVGALIB is not set 673 690 # CONFIG_FB_MACMODES is not set 674 691 # CONFIG_FB_BACKLIGHT is not set ··· 707 702 # CONFIG_FONTS is not set 708 703 CONFIG_FONT_8x8=y 709 704 CONFIG_FONT_8x16=y 710 - 711 - # 712 - # Logo configuration 713 - # 714 705 CONFIG_LOGO=y 715 706 # CONFIG_LOGO_LINUX_MONO is not set 716 707 # CONFIG_LOGO_LINUX_VGA16 is not set ··· 769 768 # CONFIG_HID_DEBUG is not set 770 769 771 770 # 771 + # USB Input Devices 772 + # 773 + CONFIG_USB_HID=m 774 + # CONFIG_USB_HIDINPUT_POWERBOOK is not set 775 + # CONFIG_HID_FF is not set 776 + # CONFIG_USB_HIDDEV is not set 777 + 778 + # 779 + # USB HID Boot Protocol drivers 780 + # 781 + # CONFIG_USB_KBD is not set 782 + # CONFIG_USB_MOUSE is not set 783 + 784 + # 772 785 # USB support 773 786 # 774 787 CONFIG_USB_ARCH_HAS_HCD=y ··· 842 827 # CONFIG_USB_LIBUSUAL is not set 843 828 844 829 # 845 - # USB Input Devices 846 - # 847 - CONFIG_USB_HID=m 848 - # CONFIG_USB_HIDINPUT_POWERBOOK is not set 849 - # CONFIG_HID_FF is not set 850 - # CONFIG_USB_HIDDEV is not set 851 - 852 - # 853 - # USB HID Boot Protocol drivers 854 - # 855 - # CONFIG_USB_KBD is not set 856 - # CONFIG_USB_MOUSE is not set 857 - # CONFIG_USB_AIPTEK is not set 858 - # CONFIG_USB_WACOM is not set 859 - # CONFIG_USB_ACECAD is not set 860 - # CONFIG_USB_KBTAB is not set 861 - # CONFIG_USB_POWERMATE is not set 862 - # CONFIG_USB_TOUCHSCREEN is not set 863 - # CONFIG_USB_YEALINK is not set 864 - # CONFIG_USB_XPAD is not set 865 - # CONFIG_USB_ATI_REMOTE is not set 866 - # CONFIG_USB_ATI_REMOTE2 is not set 867 - # CONFIG_USB_KEYSPAN_REMOTE is not set 868 - # CONFIG_USB_APPLETOUCH is not set 869 - # CONFIG_USB_GTCO is not set 870 - 871 - # 872 830 # USB Imaging devices 873 831 # 874 832 # CONFIG_USB_MDC800 is not set 875 833 # CONFIG_USB_MICROTEK is not set 876 - 877 - # 878 - # USB Network Adapters 879 - # 880 - # CONFIG_USB_CATC is not set 881 - # CONFIG_USB_KAWETH is not set 882 - CONFIG_USB_PEGASUS=m 883 - # CONFIG_USB_RTL8150 is not set 884 - CONFIG_USB_USBNET_MII=m 885 - CONFIG_USB_USBNET=m 886 - # CONFIG_USB_NET_CDCETHER is not set 887 - # CONFIG_USB_NET_DM9601 is not set 888 - # CONFIG_USB_NET_GL620A is not set 889 - # CONFIG_USB_NET_NET1080 is not set 890 - # CONFIG_USB_NET_PLUSB is not set 891 - CONFIG_USB_NET_MCS7830=m 892 - # CONFIG_USB_NET_RNDIS_HOST is not set 893 - # CONFIG_USB_NET_CDC_SUBSET is not set 894 - # CONFIG_USB_NET_ZAURUS is not set 895 834 CONFIG_USB_MON=y 896 835 897 836 # ··· 889 920 # USB Gadget Support 890 921 # 891 922 # CONFIG_USB_GADGET is not set 892 - 893 - # 894 - # MMC/SD Card support 895 - # 896 923 # CONFIG_MMC is not set 897 924 898 925 # ··· 928 963 929 964 # 930 965 # DMA Devices 931 - # 932 - 933 - # 934 - # Auxiliary Display support 935 - # 936 - 937 - # 938 - # Virtualization 939 966 # 940 967 941 968 # ··· 1028 1071 CONFIG_NFS_COMMON=y 1029 1072 CONFIG_SUNRPC=y 1030 1073 CONFIG_SUNRPC_GSS=y 1074 + # CONFIG_SUNRPC_BIND34 is not set 1031 1075 CONFIG_RPCSEC_GSS_KRB5=y 1032 1076 # CONFIG_RPCSEC_GSS_SPKM3 is not set 1033 1077 # CONFIG_SMB_FS is not set ··· 1106 1148 CONFIG_BITREVERSE=y 1107 1149 # CONFIG_CRC_CCITT is not set 1108 1150 # CONFIG_CRC16 is not set 1151 + # CONFIG_CRC_ITU_T is not set 1109 1152 CONFIG_CRC32=y 1110 1153 # CONFIG_LIBCRC32C is not set 1111 1154 CONFIG_PLIST=y 1112 1155 CONFIG_HAS_IOMEM=y 1113 1156 CONFIG_HAS_IOPORT=y 1157 + CONFIG_HAS_DMA=y 1114 1158 1115 1159 # 1116 1160 # Instrumentation Support ··· 1131 1171 # CONFIG_HEADERS_CHECK is not set 1132 1172 CONFIG_DEBUG_KERNEL=y 1133 1173 # CONFIG_DEBUG_SHIRQ is not set 1134 - CONFIG_LOG_BUF_SHIFT=17 1135 1174 CONFIG_DETECT_SOFTLOCKUP=y 1136 1175 # CONFIG_SCHEDSTATS is not set 1137 1176 # CONFIG_TIMER_STATS is not set ··· 1164 1205 # CONFIG_PPC_EARLY_DEBUG_ISERIES is not set 1165 1206 # CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set 1166 1207 # CONFIG_PPC_EARLY_DEBUG_BEAT is not set 1208 + # CONFIG_PPC_EARLY_DEBUG_44x is not set 1167 1209 1168 1210 # 1169 1211 # Security options ··· 1194 1234 CONFIG_CRYPTO_CBC=y 1195 1235 CONFIG_CRYPTO_PCBC=m 1196 1236 # CONFIG_CRYPTO_LRW is not set 1237 + # CONFIG_CRYPTO_CRYPTD is not set 1197 1238 CONFIG_CRYPTO_DES=y 1198 1239 # CONFIG_CRYPTO_FCRYPT is not set 1199 1240 # CONFIG_CRYPTO_BLOWFISH is not set
+1 -1
arch/powerpc/kernel/prom_parse.c
··· 24 24 /* Max address size we deal with */ 25 25 #define OF_MAX_ADDR_CELLS 4 26 26 #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ 27 - (ns) > 0) 27 + (ns) >= 0) 28 28 29 29 static struct of_bus *of_match_bus(struct device_node *np); 30 30 static int __of_address_to_resource(struct device_node *dev,
+41
arch/powerpc/kernel/setup-common.c
··· 530 530 { 531 531 atomic_notifier_chain_register(&panic_notifier_list, &ppc_panic_block); 532 532 } 533 + 534 + #ifdef CONFIG_CHECK_CACHE_COHERENCY 535 + /* 536 + * For platforms that have configurable cache-coherency. This function 537 + * checks that the cache coherency setting of the kernel matches the setting 538 + * left by the firmware, as indicated in the device tree. Since a mismatch 539 + * will eventually result in DMA failures, we print * and error and call 540 + * BUG() in that case. 541 + */ 542 + 543 + #ifdef CONFIG_NOT_COHERENT_CACHE 544 + #define KERNEL_COHERENCY 0 545 + #else 546 + #define KERNEL_COHERENCY 1 547 + #endif 548 + 549 + static int __init check_cache_coherency(void) 550 + { 551 + struct device_node *np; 552 + const void *prop; 553 + int devtree_coherency; 554 + 555 + np = of_find_node_by_path("/"); 556 + prop = of_get_property(np, "coherency-off", NULL); 557 + of_node_put(np); 558 + 559 + devtree_coherency = prop ? 0 : 1; 560 + 561 + if (devtree_coherency != KERNEL_COHERENCY) { 562 + printk(KERN_ERR 563 + "kernel coherency:%s != device tree_coherency:%s\n", 564 + KERNEL_COHERENCY ? "on" : "off", 565 + devtree_coherency ? "on" : "off"); 566 + BUG(); 567 + } 568 + 569 + return 0; 570 + } 571 + 572 + late_initcall(check_cache_coherency); 573 + #endif /* CONFIG_CHECK_CACHE_COHERENCY */
+2 -17
arch/powerpc/kernel/time.c
··· 711 711 void __init smp_space_timers(unsigned int max_cpus) 712 712 { 713 713 int i; 714 - unsigned long half = tb_ticks_per_jiffy / 2; 715 - unsigned long offset = tb_ticks_per_jiffy / max_cpus; 716 714 u64 previous_tb = per_cpu(last_jiffy, boot_cpuid); 717 715 718 716 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */ 719 717 previous_tb -= tb_ticks_per_jiffy; 720 - /* 721 - * The stolen time calculation for POWER5 shared-processor LPAR 722 - * systems works better if the two threads' timebase interrupts 723 - * are staggered by half a jiffy with respect to each other. 724 - */ 718 + 725 719 for_each_possible_cpu(i) { 726 720 if (i == boot_cpuid) 727 721 continue; 728 - if (i == (boot_cpuid ^ 1)) 729 - per_cpu(last_jiffy, i) = 730 - per_cpu(last_jiffy, boot_cpuid) - half; 731 - else if (i & 1) 732 - per_cpu(last_jiffy, i) = 733 - per_cpu(last_jiffy, i ^ 1) + half; 734 - else { 735 - previous_tb += offset; 736 - per_cpu(last_jiffy, i) = previous_tb; 737 - } 722 + per_cpu(last_jiffy, i) = previous_tb; 738 723 } 739 724 } 740 725 #endif
+2 -2
arch/powerpc/mm/hash_native_64.c
··· 351 351 unsigned long hpte_r = hpte->r; 352 352 unsigned long hpte_v = hpte->v; 353 353 unsigned long avpn; 354 - int i, size, shift, penc, avpnm_bits; 354 + int i, size, shift, penc; 355 355 356 356 if (!(hpte_v & HPTE_V_LARGE)) 357 357 size = MMU_PAGE_4K; ··· 395 395 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask; 396 396 break; 397 397 default: 398 - avpn = vpi = psize = 0; 398 + avpn = vpi = size = 0; 399 399 } 400 400 avpn |= (vpi << mmu_psize_defs[size].shift); 401 401 }
+13
arch/powerpc/platforms/embedded6xx/Kconfig
··· 31 31 help 32 32 Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval 33 33 Board with TSI108/9 bridge (Hickory/Holly) 34 + 35 + config PPC_PRPMC2800 36 + bool "Motorola-PrPMC2800" 37 + select MV64X60 38 + select NOT_COHERENT_CACHE 39 + select WANT_DEVICE_TREE 40 + help 41 + This option enables support for the Motorola PrPMC2800 board 34 42 endchoice 35 43 36 44 config TSI108_BRIDGE ··· 53 45 depends on LINKSTATION 54 46 select PPC_INDIRECT_PCI 55 47 default y 48 + 49 + config MV64X60 50 + bool 51 + select PPC_INDIRECT_PCI 52 + select CONFIG_CHECK_CACHE_COHERENCY 56 53 57 54 config MPC10X_OPENPIC 58 55 bool
+1
arch/powerpc/platforms/embedded6xx/Makefile
··· 4 4 obj-$(CONFIG_MPC7448HPC2) += mpc7448_hpc2.o 5 5 obj-$(CONFIG_LINKSTATION) += linkstation.o ls_uart.o 6 6 obj-$(CONFIG_PPC_HOLLY) += holly.o 7 + obj-$(CONFIG_PPC_PRPMC2800) += prpmc2800.o
+171
arch/powerpc/platforms/embedded6xx/prpmc2800.c
··· 1 + /* 2 + * Board setup routines for the Motorola PrPMC2800 3 + * 4 + * Author: Dale Farnsworth <dale@farnsworth.org> 5 + * 6 + * 2007 (c) MontaVista, Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <linux/stddef.h> 13 + #include <linux/kernel.h> 14 + #include <linux/delay.h> 15 + #include <linux/interrupt.h> 16 + #include <linux/seq_file.h> 17 + 18 + #include <asm/machdep.h> 19 + #include <asm/prom.h> 20 + #include <asm/system.h> 21 + #include <asm/time.h> 22 + #include <asm/kexec.h> 23 + 24 + #include <mm/mmu_decl.h> 25 + 26 + #include <sysdev/mv64x60.h> 27 + 28 + #define MV64x60_MPP_CNTL_0 0x0000 29 + #define MV64x60_MPP_CNTL_2 0x0008 30 + 31 + #define MV64x60_GPP_IO_CNTL 0x0000 32 + #define MV64x60_GPP_LEVEL_CNTL 0x0010 33 + #define MV64x60_GPP_VALUE_SET 0x0018 34 + 35 + #define PLATFORM_NAME_MAX 32 36 + 37 + static char prpmc2800_platform_name[PLATFORM_NAME_MAX]; 38 + 39 + static void __iomem *mv64x60_mpp_reg_base; 40 + static void __iomem *mv64x60_gpp_reg_base; 41 + 42 + static void __init prpmc2800_setup_arch(void) 43 + { 44 + struct device_node *np; 45 + phys_addr_t paddr; 46 + const unsigned int *reg; 47 + const unsigned int *prop; 48 + 49 + /* 50 + * ioremap mpp and gpp registers in case they are later 51 + * needed by prpmc2800_reset_board(). 52 + */ 53 + np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-mpp"); 54 + reg = of_get_property(np, "reg", NULL); 55 + paddr = of_translate_address(np, reg); 56 + of_node_put(np); 57 + mv64x60_mpp_reg_base = ioremap(paddr, reg[1]); 58 + 59 + np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp"); 60 + reg = of_get_property(np, "reg", NULL); 61 + paddr = of_translate_address(np, reg); 62 + of_node_put(np); 63 + mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); 64 + 65 + np = of_find_node_by_type(NULL, "cpu"); 66 + prop = of_get_property(np, "clock-frequency", NULL); 67 + if (prop) 68 + loops_per_jiffy = *prop / HZ; 69 + of_node_put(np); 70 + 71 + #ifdef CONFIG_PCI 72 + mv64x60_pci_init(); 73 + #endif 74 + 75 + printk("Motorola %s\n", prpmc2800_platform_name); 76 + } 77 + 78 + static void prpmc2800_reset_board(void) 79 + { 80 + u32 temp; 81 + 82 + local_irq_disable(); 83 + 84 + temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0); 85 + temp &= 0xFFFF0FFF; 86 + out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp); 87 + 88 + temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL); 89 + temp |= 0x00000004; 90 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp); 91 + 92 + temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL); 93 + temp |= 0x00000004; 94 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp); 95 + 96 + temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2); 97 + temp &= 0xFFFF0FFF; 98 + out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp); 99 + 100 + temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL); 101 + temp |= 0x00080000; 102 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp); 103 + 104 + temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL); 105 + temp |= 0x00080000; 106 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp); 107 + 108 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004); 109 + } 110 + 111 + static void prpmc2800_restart(char *cmd) 112 + { 113 + volatile ulong i = 10000000; 114 + 115 + prpmc2800_reset_board(); 116 + 117 + while (i-- > 0); 118 + panic("restart failed\n"); 119 + } 120 + 121 + #ifdef CONFIG_NOT_COHERENT_CACHE 122 + #define PPRPM2800_COHERENCY_SETTING "off" 123 + #else 124 + #define PPRPM2800_COHERENCY_SETTING "on" 125 + #endif 126 + 127 + void prpmc2800_show_cpuinfo(struct seq_file *m) 128 + { 129 + uint memsize = total_memory; 130 + 131 + seq_printf(m, "Vendor\t\t: Motorola\n"); 132 + seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); 133 + seq_printf(m, "coherency\t: %s\n", PPRPM2800_COHERENCY_SETTING); 134 + } 135 + 136 + /* 137 + * Called very early, device-tree isn't unflattened 138 + */ 139 + static int __init prpmc2800_probe(void) 140 + { 141 + unsigned long root = of_get_flat_dt_root(); 142 + unsigned long len = PLATFORM_NAME_MAX; 143 + void *m; 144 + 145 + if (!of_flat_dt_is_compatible(root, "motorola,PrPMC2800")) 146 + return 0; 147 + 148 + /* Update ppc_md.name with name from dt */ 149 + m = of_get_flat_dt_prop(root, "model", &len); 150 + if (m) 151 + strncpy(prpmc2800_platform_name, m, 152 + min((int)len, PLATFORM_NAME_MAX - 1)); 153 + 154 + return 1; 155 + } 156 + 157 + define_machine(prpmc2800){ 158 + .name = prpmc2800_platform_name, 159 + .probe = prpmc2800_probe, 160 + .setup_arch = prpmc2800_setup_arch, 161 + .show_cpuinfo = prpmc2800_show_cpuinfo, 162 + .init_IRQ = mv64x60_init_irq, 163 + .get_irq = mv64x60_get_irq, 164 + .restart = prpmc2800_restart, 165 + .calibrate_decr = generic_calibrate_decr, 166 + #ifdef CONFIG_KEXEC 167 + .machine_kexec = default_machine_kexec, 168 + .machine_kexec_prepare = default_machine_kexec_prepare, 169 + .machine_crash_shutdown = default_machine_crash_shutdown, 170 + #endif 171 + };
+1
arch/powerpc/platforms/pasemi/idle.c
··· 22 22 23 23 #include <linux/kernel.h> 24 24 #include <linux/string.h> 25 + #include <linux/irq.h> 25 26 26 27 #include <asm/machdep.h> 27 28 #include <asm/reg.h>
+1 -1
arch/powerpc/platforms/ps3/setup.c
··· 99 99 while(1); 100 100 } 101 101 102 + #ifdef CONFIG_FB_PS3 102 103 static void prealloc(struct ps3_prealloc *p) 103 104 { 104 105 if (!p->size) ··· 116 115 p->address); 117 116 } 118 117 119 - #ifdef CONFIG_FB_PS3 120 118 struct ps3_prealloc ps3fb_videomemory = { 121 119 .name = "ps3fb videomemory", 122 120 .size = CONFIG_FB_PS3_DEFAULT_SIZE_M*1024*1024,
+4 -2
arch/powerpc/platforms/ps3/smp.c
··· 118 118 DBG("%s:%d: (%d, %d) => virq %u\n", 119 119 __func__, __LINE__, cpu, i, virqs[i]); 120 120 121 + result = request_irq(virqs[i], ipi_function_handler, 122 + IRQF_DISABLED, names[i], (void*)(long)i); 121 123 122 - request_irq(virqs[i], ipi_function_handler, IRQF_DISABLED, 123 - names[i], (void*)(long)i); 124 + if (result) 125 + virqs[i] = NO_IRQ; 124 126 } 125 127 126 128 ps3_register_ipi_debug_brk(cpu, virqs[PPC_MSG_DEBUGGER_BREAK]);
+3 -3
arch/powerpc/platforms/ps3/system-bus.c
··· 274 274 static int ps3_map_sg(struct device *_dev, struct scatterlist *sg, int nents, 275 275 enum dma_data_direction direction) 276 276 { 277 - struct ps3_system_bus_device *dev = to_ps3_system_bus_device(_dev); 278 - int i; 279 - 280 277 #if defined(CONFIG_PS3_DYNAMIC_DMA) 281 278 BUG_ON("do"); 282 279 return -EPERM; 283 280 #else 281 + struct ps3_system_bus_device *dev = to_ps3_system_bus_device(_dev); 282 + int i; 283 + 284 284 for (i = 0; i < nents; i++, sg++) { 285 285 int result = ps3_dma_map(dev->d_region, 286 286 page_to_phys(sg->page) + sg->offset, sg->length,
+2
arch/powerpc/sysdev/Makefile
··· 16 16 obj-$(CONFIG_FSL_PCIE) += fsl_pcie.o 17 17 obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 18 18 obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 19 + mv64x60-$(CONFIG_PCI) += mv64x60_pci.o 20 + obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o 19 21 20 22 # contains only the suspend handler for time 21 23 obj-$(CONFIG_PM) += timer.o
+11
arch/powerpc/sysdev/mv64x60.h
··· 1 + #ifndef __MV64X60_H__ 2 + #define __MV64X60_H__ 3 + 4 + #include <linux/init.h> 5 + 6 + extern void __init mv64x60_init_irq(void); 7 + extern unsigned int mv64x60_get_irq(void); 8 + 9 + extern void __init mv64x60_pci_init(void); 10 + 11 + #endif /* __MV64X60_H__ */
+422
arch/powerpc/sysdev/mv64x60_dev.c
··· 1 + /* 2 + * Platform device setup for Marvell mv64360/mv64460 host bridges (Discovery) 3 + * 4 + * Author: Dale Farnsworth <dale@farnsworth.org> 5 + * 6 + * 2007 (c) MontaVista, Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <linux/stddef.h> 13 + #include <linux/kernel.h> 14 + #include <linux/init.h> 15 + #include <linux/mv643xx.h> 16 + #include <linux/platform_device.h> 17 + 18 + #include <asm/prom.h> 19 + 20 + /* 21 + * These functions provide the necessary setup for the mv64x60 drivers. 22 + * These drivers are unusual in that they work on both the MIPS and PowerPC 23 + * architectures. Because of that, the drivers do not support the normal 24 + * PowerPC of_platform_bus_type. They support platform_bus_type instead. 25 + */ 26 + 27 + /* 28 + * Create MPSC platform devices 29 + */ 30 + static int __init mv64x60_mpsc_register_shared_pdev(struct device_node *np) 31 + { 32 + struct platform_device *pdev; 33 + struct resource r[2]; 34 + struct mpsc_shared_pdata pdata; 35 + const phandle *ph; 36 + struct device_node *mpscrouting, *mpscintr; 37 + int err; 38 + 39 + ph = of_get_property(np, "mpscrouting", NULL); 40 + mpscrouting = of_find_node_by_phandle(*ph); 41 + if (!mpscrouting) 42 + return -ENODEV; 43 + 44 + err = of_address_to_resource(mpscrouting, 0, &r[0]); 45 + of_node_put(mpscrouting); 46 + if (err) 47 + return err; 48 + 49 + ph = of_get_property(np, "mpscintr", NULL); 50 + mpscintr = of_find_node_by_phandle(*ph); 51 + if (!mpscintr) 52 + return -ENODEV; 53 + 54 + err = of_address_to_resource(mpscintr, 0, &r[1]); 55 + of_node_put(mpscintr); 56 + if (err) 57 + return err; 58 + 59 + memset(&pdata, 0, sizeof(pdata)); 60 + 61 + pdev = platform_device_alloc(MPSC_SHARED_NAME, 0); 62 + if (!pdev) 63 + return -ENOMEM; 64 + 65 + err = platform_device_add_resources(pdev, r, 2); 66 + if (err) 67 + goto error; 68 + 69 + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); 70 + if (err) 71 + goto error; 72 + 73 + err = platform_device_add(pdev); 74 + if (err) 75 + goto error; 76 + 77 + return 0; 78 + 79 + error: 80 + platform_device_put(pdev); 81 + return err; 82 + } 83 + 84 + 85 + static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id) 86 + { 87 + struct resource r[5]; 88 + struct mpsc_pdata pdata; 89 + struct platform_device *pdev; 90 + const unsigned int *prop; 91 + const phandle *ph; 92 + struct device_node *sdma, *brg; 93 + int err; 94 + int port_number; 95 + 96 + /* only register the shared platform device the first time through */ 97 + if (id == 0 && (err = mv64x60_mpsc_register_shared_pdev(np))) 98 + return err; 99 + 100 + memset(r, 0, sizeof(r)); 101 + 102 + err = of_address_to_resource(np, 0, &r[0]); 103 + if (err) 104 + return err; 105 + 106 + of_irq_to_resource(np, 0, &r[4]); 107 + 108 + ph = of_get_property(np, "sdma", NULL); 109 + sdma = of_find_node_by_phandle(*ph); 110 + if (!sdma) 111 + return -ENODEV; 112 + 113 + of_irq_to_resource(sdma, 0, &r[3]); 114 + err = of_address_to_resource(sdma, 0, &r[1]); 115 + of_node_put(sdma); 116 + if (err) 117 + return err; 118 + 119 + ph = of_get_property(np, "brg", NULL); 120 + brg = of_find_node_by_phandle(*ph); 121 + if (!brg) 122 + return -ENODEV; 123 + 124 + err = of_address_to_resource(brg, 0, &r[2]); 125 + of_node_put(brg); 126 + if (err) 127 + return err; 128 + 129 + prop = of_get_property(np, "block-index", NULL); 130 + if (!prop) 131 + return -ENODEV; 132 + port_number = *(int *)prop; 133 + 134 + memset(&pdata, 0, sizeof(pdata)); 135 + 136 + pdata.cache_mgmt = 1; /* All current revs need this set */ 137 + 138 + prop = of_get_property(np, "max_idle", NULL); 139 + if (prop) 140 + pdata.max_idle = *prop; 141 + 142 + prop = of_get_property(brg, "current-speed", NULL); 143 + if (prop) 144 + pdata.default_baud = *prop; 145 + 146 + /* Default is 8 bits, no parity, no flow control */ 147 + pdata.default_bits = 8; 148 + pdata.default_parity = 'n'; 149 + pdata.default_flow = 'n'; 150 + 151 + prop = of_get_property(np, "chr_1", NULL); 152 + if (prop) 153 + pdata.chr_1_val = *prop; 154 + 155 + prop = of_get_property(np, "chr_2", NULL); 156 + if (prop) 157 + pdata.chr_2_val = *prop; 158 + 159 + prop = of_get_property(np, "chr_10", NULL); 160 + if (prop) 161 + pdata.chr_10_val = *prop; 162 + 163 + prop = of_get_property(np, "mpcr", NULL); 164 + if (prop) 165 + pdata.mpcr_val = *prop; 166 + 167 + prop = of_get_property(brg, "bcr", NULL); 168 + if (prop) 169 + pdata.bcr_val = *prop; 170 + 171 + pdata.brg_can_tune = 1; /* All current revs need this set */ 172 + 173 + prop = of_get_property(brg, "clock-src", NULL); 174 + if (prop) 175 + pdata.brg_clk_src = *prop; 176 + 177 + prop = of_get_property(brg, "clock-frequency", NULL); 178 + if (prop) 179 + pdata.brg_clk_freq = *prop; 180 + 181 + pdev = platform_device_alloc(MPSC_CTLR_NAME, port_number); 182 + if (!pdev) 183 + return -ENOMEM; 184 + 185 + err = platform_device_add_resources(pdev, r, 5); 186 + if (err) 187 + goto error; 188 + 189 + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); 190 + if (err) 191 + goto error; 192 + 193 + err = platform_device_add(pdev); 194 + if (err) 195 + goto error; 196 + 197 + return 0; 198 + 199 + error: 200 + platform_device_put(pdev); 201 + return err; 202 + } 203 + 204 + /* 205 + * Create mv64x60_eth platform devices 206 + */ 207 + static int __init eth_register_shared_pdev(struct device_node *np) 208 + { 209 + struct platform_device *pdev; 210 + struct resource r[1]; 211 + int err; 212 + 213 + np = of_get_parent(np); 214 + if (!np) 215 + return -ENODEV; 216 + 217 + err = of_address_to_resource(np, 0, &r[0]); 218 + of_node_put(np); 219 + if (err) 220 + return err; 221 + 222 + pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, 0, 223 + r, 1); 224 + if (IS_ERR(pdev)) 225 + return PTR_ERR(pdev); 226 + 227 + return 0; 228 + } 229 + 230 + static int __init mv64x60_eth_device_setup(struct device_node *np, int id) 231 + { 232 + struct resource r[1]; 233 + struct mv643xx_eth_platform_data pdata; 234 + struct platform_device *pdev; 235 + struct device_node *phy; 236 + const u8 *mac_addr; 237 + const int *prop; 238 + const phandle *ph; 239 + int err; 240 + 241 + /* only register the shared platform device the first time through */ 242 + if (id == 0 && (err = eth_register_shared_pdev(np))) 243 + return err;; 244 + 245 + memset(r, 0, sizeof(r)); 246 + of_irq_to_resource(np, 0, &r[0]); 247 + 248 + memset(&pdata, 0, sizeof(pdata)); 249 + 250 + prop = of_get_property(np, "block-index", NULL); 251 + if (!prop) 252 + return -ENODEV; 253 + pdata.port_number = *prop; 254 + 255 + mac_addr = of_get_mac_address(np); 256 + if (mac_addr) 257 + memcpy(pdata.mac_addr, mac_addr, 6); 258 + 259 + prop = of_get_property(np, "speed", NULL); 260 + if (prop) 261 + pdata.speed = *prop; 262 + 263 + prop = of_get_property(np, "tx_queue_size", NULL); 264 + if (prop) 265 + pdata.tx_queue_size = *prop; 266 + 267 + prop = of_get_property(np, "rx_queue_size", NULL); 268 + if (prop) 269 + pdata.rx_queue_size = *prop; 270 + 271 + prop = of_get_property(np, "tx_sram_addr", NULL); 272 + if (prop) 273 + pdata.tx_sram_addr = *prop; 274 + 275 + prop = of_get_property(np, "tx_sram_size", NULL); 276 + if (prop) 277 + pdata.tx_sram_size = *prop; 278 + 279 + prop = of_get_property(np, "rx_sram_addr", NULL); 280 + if (prop) 281 + pdata.rx_sram_addr = *prop; 282 + 283 + prop = of_get_property(np, "rx_sram_size", NULL); 284 + if (prop) 285 + pdata.rx_sram_size = *prop; 286 + 287 + ph = of_get_property(np, "phy", NULL); 288 + if (!ph) 289 + return -ENODEV; 290 + 291 + phy = of_find_node_by_phandle(*ph); 292 + if (phy == NULL) 293 + return -ENODEV; 294 + 295 + prop = of_get_property(phy, "reg", NULL); 296 + if (prop) { 297 + pdata.force_phy_addr = 1; 298 + pdata.phy_addr = *prop; 299 + } 300 + 301 + of_node_put(phy); 302 + 303 + pdev = platform_device_alloc(MV643XX_ETH_NAME, pdata.port_number); 304 + if (!pdev) 305 + return -ENOMEM; 306 + 307 + err = platform_device_add_resources(pdev, r, 1); 308 + if (err) 309 + goto error; 310 + 311 + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); 312 + if (err) 313 + goto error; 314 + 315 + err = platform_device_add(pdev); 316 + if (err) 317 + goto error; 318 + 319 + return 0; 320 + 321 + error: 322 + platform_device_put(pdev); 323 + return err; 324 + } 325 + 326 + /* 327 + * Create mv64x60_i2c platform devices 328 + */ 329 + static int __init mv64x60_i2c_device_setup(struct device_node *np, int id) 330 + { 331 + struct resource r[2]; 332 + struct platform_device *pdev; 333 + struct mv64xxx_i2c_pdata pdata; 334 + const unsigned int *prop; 335 + int err; 336 + 337 + memset(r, 0, sizeof(r)); 338 + 339 + err = of_address_to_resource(np, 0, &r[0]); 340 + if (err) 341 + return err; 342 + 343 + of_irq_to_resource(np, 0, &r[1]); 344 + 345 + memset(&pdata, 0, sizeof(pdata)); 346 + 347 + prop = of_get_property(np, "freq_m", NULL); 348 + if (!prop) 349 + return -ENODEV; 350 + pdata.freq_m = *prop; 351 + 352 + prop = of_get_property(np, "freq_n", NULL); 353 + if (!prop) 354 + return -ENODEV; 355 + pdata.freq_n = *prop; 356 + 357 + prop = of_get_property(np, "timeout", NULL); 358 + if (prop) 359 + pdata.timeout = *prop; 360 + else 361 + pdata.timeout = 1000; /* 1 second */ 362 + 363 + prop = of_get_property(np, "retries", NULL); 364 + if (prop) 365 + pdata.retries = *prop; 366 + else 367 + pdata.retries = 1; 368 + 369 + pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id); 370 + if (!pdev) 371 + return -ENOMEM; 372 + 373 + err = platform_device_add_resources(pdev, r, 2); 374 + if (err) 375 + goto error; 376 + 377 + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); 378 + if (err) 379 + goto error; 380 + 381 + err = platform_device_add(pdev); 382 + if (err) 383 + goto error; 384 + 385 + return 0; 386 + 387 + error: 388 + platform_device_put(pdev); 389 + return err; 390 + } 391 + 392 + static int __init mv64x60_device_setup(void) 393 + { 394 + struct device_node *np = NULL; 395 + int id; 396 + int err; 397 + 398 + for (id = 0; 399 + (np = of_find_compatible_node(np, "serial", "marvell,mpsc")); id++) 400 + if ((err = mv64x60_mpsc_device_setup(np, id))) 401 + goto error; 402 + 403 + for (id = 0; 404 + (np = of_find_compatible_node(np, "network", 405 + "marvell,mv64x60-eth")); 406 + id++) 407 + if ((err = mv64x60_eth_device_setup(np, id))) 408 + goto error; 409 + 410 + for (id = 0; 411 + (np = of_find_compatible_node(np, "i2c", "marvell,mv64x60-i2c")); 412 + id++) 413 + if ((err = mv64x60_i2c_device_setup(np, id))) 414 + goto error; 415 + 416 + return 0; 417 + 418 + error: 419 + of_node_put(np); 420 + return err; 421 + } 422 + arch_initcall(mv64x60_device_setup);
+172
arch/powerpc/sysdev/mv64x60_pci.c
··· 1 + /* 2 + * PCI bus setup for Marvell mv64360/mv64460 host bridges (Discovery) 3 + * 4 + * Author: Dale Farnsworth <dale@farnsworth.org> 5 + * 6 + * 2007 (c) MontaVista, Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <linux/stddef.h> 13 + #include <linux/kernel.h> 14 + #include <linux/init.h> 15 + #include <linux/pci.h> 16 + 17 + #include <asm/prom.h> 18 + #include <asm/pci-bridge.h> 19 + 20 + #define PCI_HEADER_TYPE_INVALID 0x7f /* Invalid PCI header type */ 21 + 22 + #ifdef CONFIG_SYSFS 23 + /* 32-bit hex or dec stringified number + '\n' */ 24 + #define MV64X60_VAL_LEN_MAX 11 25 + #define MV64X60_PCICFG_CPCI_HOTSWAP 0x68 26 + 27 + static ssize_t mv64x60_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, 28 + size_t count) 29 + { 30 + struct pci_dev *phb; 31 + u32 v; 32 + 33 + if (off > 0) 34 + return 0; 35 + if (count < MV64X60_VAL_LEN_MAX) 36 + return -EINVAL; 37 + 38 + phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 39 + if (!phb) 40 + return -ENODEV; 41 + pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v); 42 + pci_dev_put(phb); 43 + 44 + return sprintf(buf, "0x%08x\n", v); 45 + } 46 + 47 + static ssize_t mv64x60_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, 48 + size_t count) 49 + { 50 + struct pci_dev *phb; 51 + u32 v; 52 + 53 + if (off > 0) 54 + return 0; 55 + if (count <= 0) 56 + return -EINVAL; 57 + 58 + if (sscanf(buf, "%i", &v) != 1) 59 + return -EINVAL; 60 + 61 + phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); 62 + if (!phb) 63 + return -ENODEV; 64 + pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v); 65 + pci_dev_put(phb); 66 + 67 + return count; 68 + } 69 + 70 + static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */ 71 + .attr = { 72 + .name = "hs_reg", 73 + .mode = S_IRUGO | S_IWUSR, 74 + .owner = THIS_MODULE, 75 + }, 76 + .size = MV64X60_VAL_LEN_MAX, 77 + .read = mv64x60_hs_reg_read, 78 + .write = mv64x60_hs_reg_write, 79 + }; 80 + 81 + static int __init mv64x60_sysfs_init(void) 82 + { 83 + struct device_node *np; 84 + struct platform_device *pdev; 85 + const unsigned int *prop; 86 + 87 + np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60"); 88 + if (!np) 89 + return 0; 90 + 91 + prop = of_get_property(np, "hs_reg_valid", NULL); 92 + of_node_put(np); 93 + 94 + pdev = platform_device_register_simple("marvell,mv64x60", 0, NULL, 0); 95 + if (IS_ERR(pdev)) 96 + return PTR_ERR(pdev); 97 + 98 + return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr); 99 + } 100 + 101 + subsys_initcall(mv64x60_sysfs_init); 102 + 103 + #endif /* CONFIG_SYSFS */ 104 + 105 + static void __init mv64x60_pci_fixup_early(struct pci_dev *dev) 106 + { 107 + /* 108 + * Set the host bridge hdr_type to an invalid value so that 109 + * pci_setup_device() will ignore the host bridge. 110 + */ 111 + dev->hdr_type = PCI_HEADER_TYPE_INVALID; 112 + } 113 + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360, 114 + mv64x60_pci_fixup_early); 115 + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64460, 116 + mv64x60_pci_fixup_early); 117 + 118 + static int __init mv64x60_add_bridge(struct device_node *dev) 119 + { 120 + int len; 121 + struct pci_controller *hose; 122 + struct resource rsrc; 123 + const int *bus_range; 124 + int primary; 125 + 126 + memset(&rsrc, 0, sizeof(rsrc)); 127 + 128 + /* Fetch host bridge registers address */ 129 + if (of_address_to_resource(dev, 0, &rsrc)) { 130 + printk(KERN_ERR "No PCI reg property in device tree\n"); 131 + return -ENODEV; 132 + } 133 + 134 + /* Get bus range if any */ 135 + bus_range = of_get_property(dev, "bus-range", &len); 136 + if (bus_range == NULL || len < 2 * sizeof(int)) 137 + printk(KERN_WARNING "Can't get bus-range for %s, assume" 138 + " bus 0\n", dev->full_name); 139 + 140 + hose = pcibios_alloc_controller(); 141 + if (!hose) 142 + return -ENOMEM; 143 + 144 + hose->arch_data = dev; 145 + hose->set_cfg_type = 1; 146 + 147 + hose->first_busno = bus_range ? bus_range[0] : 0; 148 + hose->last_busno = bus_range ? bus_range[1] : 0xff; 149 + 150 + setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); 151 + hose->bus_offset = hose->first_busno; 152 + 153 + printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " 154 + "Firmware bus number: %d->%d\n", 155 + (unsigned long long)rsrc.start, hose->first_busno, 156 + hose->last_busno); 157 + 158 + /* Interpret the "ranges" property */ 159 + /* This also maps the I/O region and sets isa_io/mem_base */ 160 + primary = (hose->first_busno == 0); 161 + pci_process_bridge_OF_ranges(hose, dev, primary); 162 + 163 + return 0; 164 + } 165 + 166 + void __init mv64x60_pci_init(void) 167 + { 168 + struct device_node *np = NULL; 169 + 170 + while ((np = of_find_compatible_node(np, "pci", "marvell,mv64x60-pci"))) 171 + mv64x60_add_bridge(np); 172 + }
+305
arch/powerpc/sysdev/mv64x60_pic.c
··· 1 + /* 2 + * Interrupt handling for Marvell mv64360/mv64460 host bridges (Discovery) 3 + * 4 + * Author: Dale Farnsworth <dale@farnsworth.org> 5 + * 6 + * 2007 (c) MontaVista, Software, Inc. This file is licensed under 7 + * the terms of the GNU General Public License version 2. This program 8 + * is licensed "as is" without any warranty of any kind, whether express 9 + * or implied. 10 + */ 11 + 12 + #include <linux/stddef.h> 13 + #include <linux/kernel.h> 14 + #include <linux/init.h> 15 + #include <linux/irq.h> 16 + #include <linux/interrupt.h> 17 + #include <linux/spinlock.h> 18 + 19 + #include <asm/byteorder.h> 20 + #include <asm/io.h> 21 + #include <asm/prom.h> 22 + #include <asm/irq.h> 23 + 24 + #include "mv64x60.h" 25 + 26 + /* Interrupt Controller Interface Registers */ 27 + #define MV64X60_IC_MAIN_CAUSE_LO 0x0004 28 + #define MV64X60_IC_MAIN_CAUSE_HI 0x000c 29 + #define MV64X60_IC_CPU0_INTR_MASK_LO 0x0014 30 + #define MV64X60_IC_CPU0_INTR_MASK_HI 0x001c 31 + #define MV64X60_IC_CPU0_SELECT_CAUSE 0x0024 32 + 33 + #define MV64X60_HIGH_GPP_GROUPS 0x0f000000 34 + #define MV64X60_SELECT_CAUSE_HIGH 0x40000000 35 + 36 + /* General Purpose Pins Controller Interface Registers */ 37 + #define MV64x60_GPP_INTR_CAUSE 0x0008 38 + #define MV64x60_GPP_INTR_MASK 0x000c 39 + 40 + #define MV64x60_LEVEL1_LOW 0 41 + #define MV64x60_LEVEL1_HIGH 1 42 + #define MV64x60_LEVEL1_GPP 2 43 + 44 + #define MV64x60_LEVEL1_MASK 0x00000060 45 + #define MV64x60_LEVEL1_OFFSET 5 46 + 47 + #define MV64x60_LEVEL2_MASK 0x0000001f 48 + 49 + #define MV64x60_NUM_IRQS 96 50 + 51 + static DEFINE_SPINLOCK(mv64x60_lock); 52 + 53 + static void __iomem *mv64x60_irq_reg_base; 54 + static void __iomem *mv64x60_gpp_reg_base; 55 + 56 + /* 57 + * Interrupt Controller Handling 58 + * 59 + * The interrupt controller handles three groups of interrupts: 60 + * main low: IRQ0-IRQ31 61 + * main high: IRQ32-IRQ63 62 + * gpp: IRQ64-IRQ95 63 + * 64 + * This code handles interrupts in two levels. Level 1 selects the 65 + * interrupt group, and level 2 selects an IRQ within that group. 66 + * Each group has its own irq_chip structure. 67 + */ 68 + 69 + static u32 mv64x60_cached_low_mask; 70 + static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS; 71 + static u32 mv64x60_cached_gpp_mask; 72 + 73 + static struct irq_host *mv64x60_irq_host; 74 + 75 + /* 76 + * mv64x60_chip_low functions 77 + */ 78 + 79 + static void mv64x60_mask_low(unsigned int virq) 80 + { 81 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 82 + unsigned long flags; 83 + 84 + spin_lock_irqsave(&mv64x60_lock, flags); 85 + mv64x60_cached_low_mask &= ~(1 << level2); 86 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, 87 + mv64x60_cached_low_mask); 88 + spin_unlock_irqrestore(&mv64x60_lock, flags); 89 + (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); 90 + } 91 + 92 + static void mv64x60_unmask_low(unsigned int virq) 93 + { 94 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 95 + unsigned long flags; 96 + 97 + spin_lock_irqsave(&mv64x60_lock, flags); 98 + mv64x60_cached_low_mask |= 1 << level2; 99 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, 100 + mv64x60_cached_low_mask); 101 + spin_unlock_irqrestore(&mv64x60_lock, flags); 102 + (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); 103 + } 104 + 105 + static struct irq_chip mv64x60_chip_low = { 106 + .name = "mv64x60_low", 107 + .mask = mv64x60_mask_low, 108 + .mask_ack = mv64x60_mask_low, 109 + .unmask = mv64x60_unmask_low, 110 + }; 111 + 112 + /* 113 + * mv64x60_chip_high functions 114 + */ 115 + 116 + static void mv64x60_mask_high(unsigned int virq) 117 + { 118 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 119 + unsigned long flags; 120 + 121 + spin_lock_irqsave(&mv64x60_lock, flags); 122 + mv64x60_cached_high_mask &= ~(1 << level2); 123 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI, 124 + mv64x60_cached_high_mask); 125 + spin_unlock_irqrestore(&mv64x60_lock, flags); 126 + (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); 127 + } 128 + 129 + static void mv64x60_unmask_high(unsigned int virq) 130 + { 131 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 132 + unsigned long flags; 133 + 134 + spin_lock_irqsave(&mv64x60_lock, flags); 135 + mv64x60_cached_high_mask |= 1 << level2; 136 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI, 137 + mv64x60_cached_high_mask); 138 + spin_unlock_irqrestore(&mv64x60_lock, flags); 139 + (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); 140 + } 141 + 142 + static struct irq_chip mv64x60_chip_high = { 143 + .name = "mv64x60_high", 144 + .mask = mv64x60_mask_high, 145 + .mask_ack = mv64x60_mask_high, 146 + .unmask = mv64x60_unmask_high, 147 + }; 148 + 149 + /* 150 + * mv64x60_chip_gpp functions 151 + */ 152 + 153 + static void mv64x60_mask_gpp(unsigned int virq) 154 + { 155 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 156 + unsigned long flags; 157 + 158 + spin_lock_irqsave(&mv64x60_lock, flags); 159 + mv64x60_cached_gpp_mask &= ~(1 << level2); 160 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, 161 + mv64x60_cached_gpp_mask); 162 + spin_unlock_irqrestore(&mv64x60_lock, flags); 163 + (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); 164 + } 165 + 166 + static void mv64x60_mask_ack_gpp(unsigned int virq) 167 + { 168 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 169 + unsigned long flags; 170 + 171 + spin_lock_irqsave(&mv64x60_lock, flags); 172 + mv64x60_cached_gpp_mask &= ~(1 << level2); 173 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, 174 + mv64x60_cached_gpp_mask); 175 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 176 + ~(1 << level2)); 177 + spin_unlock_irqrestore(&mv64x60_lock, flags); 178 + (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE); 179 + } 180 + 181 + static void mv64x60_unmask_gpp(unsigned int virq) 182 + { 183 + int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 184 + unsigned long flags; 185 + 186 + spin_lock_irqsave(&mv64x60_lock, flags); 187 + mv64x60_cached_gpp_mask |= 1 << level2; 188 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, 189 + mv64x60_cached_gpp_mask); 190 + spin_unlock_irqrestore(&mv64x60_lock, flags); 191 + (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); 192 + } 193 + 194 + static struct irq_chip mv64x60_chip_gpp = { 195 + .name = "mv64x60_gpp", 196 + .mask = mv64x60_mask_gpp, 197 + .mask_ack = mv64x60_mask_ack_gpp, 198 + .unmask = mv64x60_unmask_gpp, 199 + }; 200 + 201 + /* 202 + * mv64x60_host_ops functions 203 + */ 204 + 205 + static int mv64x60_host_match(struct irq_host *h, struct device_node *np) 206 + { 207 + return mv64x60_irq_host->host_data == np; 208 + } 209 + 210 + static struct irq_chip *mv64x60_chips[] = { 211 + [MV64x60_LEVEL1_LOW] = &mv64x60_chip_low, 212 + [MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high, 213 + [MV64x60_LEVEL1_GPP] = &mv64x60_chip_gpp, 214 + }; 215 + 216 + static int mv64x60_host_map(struct irq_host *h, unsigned int virq, 217 + irq_hw_number_t hwirq) 218 + { 219 + int level1; 220 + 221 + get_irq_desc(virq)->status |= IRQ_LEVEL; 222 + 223 + level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; 224 + BUG_ON(level1 > MV64x60_LEVEL1_GPP); 225 + set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq); 226 + 227 + return 0; 228 + } 229 + 230 + static struct irq_host_ops mv64x60_host_ops = { 231 + .match = mv64x60_host_match, 232 + .map = mv64x60_host_map, 233 + }; 234 + 235 + /* 236 + * Global functions 237 + */ 238 + 239 + void __init mv64x60_init_irq(void) 240 + { 241 + struct device_node *np; 242 + phys_addr_t paddr; 243 + unsigned int size; 244 + const unsigned int *reg; 245 + unsigned long flags; 246 + 247 + np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp"); 248 + reg = of_get_property(np, "reg", &size); 249 + paddr = of_translate_address(np, reg); 250 + mv64x60_gpp_reg_base = ioremap(paddr, reg[1]); 251 + of_node_put(np); 252 + 253 + np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic"); 254 + reg = of_get_property(np, "reg", &size); 255 + paddr = of_translate_address(np, reg); 256 + of_node_put(np); 257 + mv64x60_irq_reg_base = ioremap(paddr, reg[1]); 258 + 259 + mv64x60_irq_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, MV64x60_NUM_IRQS, 260 + &mv64x60_host_ops, MV64x60_NUM_IRQS); 261 + 262 + mv64x60_irq_host->host_data = np; 263 + 264 + spin_lock_irqsave(&mv64x60_lock, flags); 265 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, 266 + mv64x60_cached_gpp_mask); 267 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, 268 + mv64x60_cached_low_mask); 269 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI, 270 + mv64x60_cached_high_mask); 271 + 272 + out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0); 273 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0); 274 + out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0); 275 + spin_unlock_irqrestore(&mv64x60_lock, flags); 276 + } 277 + 278 + unsigned int mv64x60_get_irq(void) 279 + { 280 + u32 cause; 281 + int level1; 282 + irq_hw_number_t hwirq; 283 + int virq = NO_IRQ; 284 + 285 + cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE); 286 + if (cause & MV64X60_SELECT_CAUSE_HIGH) { 287 + cause &= mv64x60_cached_high_mask; 288 + level1 = MV64x60_LEVEL1_HIGH; 289 + if (cause & MV64X60_HIGH_GPP_GROUPS) { 290 + cause = in_le32(mv64x60_gpp_reg_base + 291 + MV64x60_GPP_INTR_CAUSE); 292 + cause &= mv64x60_cached_gpp_mask; 293 + level1 = MV64x60_LEVEL1_GPP; 294 + } 295 + } else { 296 + cause &= mv64x60_cached_low_mask; 297 + level1 = MV64x60_LEVEL1_LOW; 298 + } 299 + if (cause) { 300 + hwirq = (level1 << MV64x60_LEVEL1_OFFSET) | __ilog2(cause); 301 + virq = irq_linear_revmap(mv64x60_irq_host, hwirq); 302 + } 303 + 304 + return virq; 305 + }
+5 -5
arch/ppc/4xx_io/serial_sicc.c
··· 3 3 * 4 4 * Based on drivers/char/serial_amba.c, by ARM Ltd. 5 5 * 6 - * Copyright 2001 IBM Crop. 6 + * Copyright 2001 IBM Corp. 7 7 * Author: IBM China Research Lab 8 8 * Yudong Yang <yangyud@cn.ibm.com> 9 9 * Yi Ge <geyi@cn.ibm.com> ··· 155 155 156 156 /* serial port transmit command register */ 157 157 158 - #define _TxCR_ET_MASK 0x80 /* transmiter enable mask */ 158 + #define _TxCR_ET_MASK 0x80 /* transmitter enable mask */ 159 159 #define _TxCR_DME_MASK 0x60 /* dma mode mask */ 160 160 #define _TxCR_TIE_MASK 0x10 /* empty interrupt enable mask */ 161 161 #define _TxCR_EIE_MASK 0x08 /* error interrupt enable mask */ 162 162 #define _TxCR_SPE_MASK 0x04 /* stop/pause mask */ 163 163 #define _TxCR_TB_MASK 0x02 /* transmit break mask */ 164 164 165 - #define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmiter enabled */ 166 - #define _TxCR_DME_DISABLE 0x00 /* transmiter disabled, TBR intr disabled */ 167 - #define _TxCR_DME_TBR 0x20 /* transmiter disabled, TBR intr enabled */ 165 + #define _TxCR_ET_ENABLE _TxCR_ET_MASK /* transmitter enabled */ 166 + #define _TxCR_DME_DISABLE 0x00 /* transmitter disabled, TBR intr disabled */ 167 + #define _TxCR_DME_TBR 0x20 /* transmitter disabled, TBR intr enabled */ 168 168 #define _TxCR_DME_CHAN_2 0x40 /* dma enabled, destination chann 2 */ 169 169 #define _TxCR_DME_CHAN_3 0x60 /* dma enabled, destination chann 3 */ 170 170
+1 -1
arch/ppc/8xx_io/commproc.c
··· 144 144 145 145 /* Set SDMA Bus Request priority 5. 146 146 * On 860T, this also enables FEC priority 6. I am not sure 147 - * this is what we realy want for some applications, but the 147 + * this is what we really want for some applications, but the 148 148 * manual recommends it. 149 149 * Bit 25, FAM can also be set to use FEC aggressive mode (860T). 150 150 */
+1 -1
arch/ppc/8xx_io/fec.c
··· 1878 1878 bdp--; 1879 1879 bdp->cbd_sc |= BD_SC_WRAP; 1880 1880 1881 - /* ...and the same for transmmit. 1881 + /* ...and the same for transmit. 1882 1882 */ 1883 1883 bdp = fep->tx_bd_base; 1884 1884 for (i=0; i<TX_RING_SIZE; i++) {
+1 -1
arch/ppc/boot/lib/vreset.c
··· 518 518 outb(0x3c6, 0xff); /* MASK */ 519 519 520 520 for ( i = 0; i < 0x10; i++) 521 - writeAttr(i, AC[i], 0); /* pallete */ 521 + writeAttr(i, AC[i], 0); /* palette */ 522 522 writeAttr(0x10, 0x0c, 0); /* text mode */ 523 523 writeAttr(0x11, 0x00, 0); /* overscan color (border) */ 524 524 writeAttr(0x12, 0x0f, 0); /* plane enable */
+1 -1
arch/ppc/boot/simple/m8xx_tty.c
··· 1 1 /* Minimal serial functions needed to send messages out the serial 2 2 * port on the MBX console. 3 3 * 4 - * The MBX uxes SMC1 for the serial port. We reset the port and use 4 + * The MBX uses SMC1 for the serial port. We reset the port and use 5 5 * only the first BD that EPPC-Bug set up as a character FIFO. 6 6 * 7 7 * Later versions (at least 1.4, maybe earlier) of the MBX EPPC-Bug
+1 -1
arch/ppc/boot/simple/misc-embedded.c
··· 136 136 137 137 /* 138 138 * We link ourself to an arbitrary low address. When we run, we 139 - * relocate outself to that address. __image_being points to 139 + * relocate ourself to that address. __image_being points to 140 140 * the part of the image where the zImage is. -- Tom 141 141 */ 142 142 zimage_start = (char *)(unsigned long)(&__image_begin);
+1 -1
arch/ppc/boot/simple/mpc52xx_tty.c
··· 33 33 * rtc. We read the decrementer change during one rtc tick 34 34 * and multiply by 4 to get the system bus clock frequency. Since a 35 35 * rtc tick is one seconds, and that's pretty long, we change the rtc 36 - * dividers temporarly to set them 64x faster ;) 36 + * dividers temporarily to set them 64x faster ;) 37 37 */ 38 38 static int 39 39 mpc52xx_ipbfreq(void)
+1 -1
arch/ppc/boot/simple/mv64x60_tty.c
··· 338 338 339 339 rdp = &rd[com_port][cur_rd[com_port]]; 340 340 341 - /* Go thru rcv desc's until empty looking for one with data (no error)*/ 341 + /* Go through rcv descs until empty looking for one with data (no error)*/ 342 342 while (((rdp->cmd_stat & SDMA_DESC_CMDSTAT_O) == 0) && 343 343 (loop_count++ < RX_NUM_DESC)) { 344 344
+1 -1
arch/ppc/boot/simple/rw4/stb.h
··· 88 88 /*----------------------------------------------------------------------------+ 89 89 | STB tasks, task stack sizes, and task priorities. The actual task priority 90 90 | is 1 more than the specified number since priority 0 is reserved (system 91 - | internaly adds 1 to supplied priority number). 91 + | internally adds 1 to supplied priority number). 92 92 +----------------------------------------------------------------------------*/ 93 93 #define STB_IDLE_TASK_SS (5* 1024) 94 94 #define STB_IDLE_TASK_PRIO 0
+2 -2
arch/ppc/kernel/traps.c
··· 577 577 * ESR_DST (!?) or 0. In the process of chasing this with the 578 578 * hardware people - not sure if it can happen on any illegal 579 579 * instruction or only on FP instructions, whether there is a 580 - * pattern to occurences etc. -dgibson 31/Mar/2003 */ 580 + * pattern to occurrences etc. -dgibson 31/Mar/2003 */ 581 581 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { 582 582 emulate_single_step(regs); 583 583 return; ··· 860 860 spefscr = current->thread.spefscr; 861 861 fpexc_mode = current->thread.fpexc_mode; 862 862 863 - /* Hardware does not neccessarily set sticky 863 + /* Hardware does not necessarily set sticky 864 864 * underflow/overflow/invalid flags */ 865 865 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 866 866 code = FPE_FLTOVF;
+1 -1
arch/ppc/mm/init.c
··· 48 48 #include "mmu_decl.h" 49 49 50 50 #if defined(CONFIG_KERNEL_START_BOOL) || defined(CONFIG_LOWMEM_SIZE_BOOL) 51 - /* The ammount of lowmem must be within 0xF0000000 - KERNELBASE. */ 51 + /* The amount of lowmem must be within 0xF0000000 - KERNELBASE. */ 52 52 #if (CONFIG_LOWMEM_SIZE > (0xF0000000 - KERNELBASE)) 53 53 #error "You must adjust CONFIG_LOWMEM_SIZE or CONFIG_START_KERNEL" 54 54 #endif
+1 -1
arch/ppc/platforms/4xx/bubinga.c
··· 197 197 hose->first_busno, PCI_SLOT(hose->first_busno), 198 198 PCI_FUNC(hose->first_busno), bar, bar_response); 199 199 } 200 - /* end work arround */ 200 + /* end workaround */ 201 201 202 202 #ifdef DEBUG 203 203 printk("PCI bridge regs after fixup \n");
+1 -1
arch/ppc/platforms/4xx/ep405.c
··· 130 130 hose->first_busno, PCI_SLOT(hose->first_busno), 131 131 PCI_FUNC(hose->first_busno), bar, bar_response); 132 132 } 133 - /* end work arround */ 133 + /* end workaround */ 134 134 #endif 135 135 } 136 136
+1 -1
arch/ppc/platforms/4xx/ibmnp405h.h
··· 80 80 #define DCRN_CPMFR_BASE 0x0B9 81 81 #define DCRN_CPMER_BASE 0x0B8 82 82 83 - /* CPM Clocking & Power Mangement defines */ 83 + /* CPM Clocking & Power Management defines */ 84 84 #define IBM_CPM_PCI 0x40000000 /* PCI */ 85 85 #define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */ 86 86 #define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
+1 -1
arch/ppc/platforms/4xx/sycamore.c
··· 225 225 hose->first_busno, PCI_SLOT(hose->first_busno), 226 226 PCI_FUNC(hose->first_busno), bar, bar_response); 227 227 } 228 - /* end work arround */ 228 + /* end workaround */ 229 229 230 230 #ifdef DEBUG 231 231 printk("PCI bridge regs after fixup \n");
+1 -1
arch/ppc/platforms/4xx/walnut.c
··· 200 200 hose->first_busno, PCI_SLOT(hose->first_busno), 201 201 PCI_FUNC(hose->first_busno), bar, bar_response); 202 202 } 203 - /* end work arround */ 203 + /* end work around */ 204 204 205 205 #ifdef DEBUG 206 206 printk("PCI bridge regs after fixup \n");
+1 -1
arch/ppc/platforms/ev64360.c
··· 473 473 * are non-zero, then we should use the board info from the bd_t 474 474 * structure and the cmdline pointed to by r6 instead of the 475 475 * information from birecs, if any. Otherwise, use the information 476 - * from birecs as discovered by the preceeding call to 476 + * from birecs as discovered by the preceding call to 477 477 * parse_bootinfo(). This rule should work with both PPCBoot, which 478 478 * uses a bd_t board info structure, and the kernel boot wrapper, 479 479 * which uses birecs.
+1 -1
arch/ppc/platforms/hdpu.c
··· 144 144 145 145 /* Enable pipelining */ 146 146 mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13)); 147 - /* Enable Snoop Pipelineing */ 147 + /* Enable Snoop Pipelining */ 148 148 mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24)); 149 149 150 150 /*
+1 -1
arch/ppc/platforms/katana.c
··· 880 880 * are non-zero, then we should use the board info from the bd_t 881 881 * structure and the cmdline pointed to by r6 instead of the 882 882 * information from birecs, if any. Otherwise, use the information 883 - * from birecs as discovered by the preceeding call to 883 + * from birecs as discovered by the preceding call to 884 884 * parse_bootinfo(). This rule should work with both PPCBoot, which 885 885 * uses a bd_t board info structure, and the kernel boot wrapper, 886 886 * which uses birecs.
+1 -1
arch/ppc/platforms/mbx.h
··· 37 37 38 38 /* Memory map for the MBX as configured by EPPC-Bug. We could reprogram 39 39 * The SIU and PCI bridge, and try to use larger MMU pages, but the 40 - * performance gain is not measureable and it certainly complicates the 40 + * performance gain is not measurable and it certainly complicates the 41 41 * generic MMU model. 42 42 * 43 43 * In a effort to minimize memory usage for embedded applications, any
+1 -1
arch/ppc/platforms/mvme5100.h
··· 69 69 70 70 #define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF 71 71 72 - /* All UART IRQ's are wire-OR'd to one MPIC IRQ */ 72 + /* All UART IRQs are wire-OR'd to one MPIC IRQ */ 73 73 #define STD_SERIAL_PORT_DFNS \ 74 74 { 0, BASE_BAUD, MVME5100_SERIAL_1, \ 75 75 MVME5100_SERIAL_IRQ, \
+1 -1
arch/ppc/platforms/pplus.h
··· 18 18 #include <asm/io.h> 19 19 20 20 /* 21 - * Due to limiations imposed by legacy hardware (primaryily IDE controllers), 21 + * Due to limitations imposed by legacy hardware (primarily IDE controllers), 22 22 * the PPLUS boards operate using a PReP address map. 23 23 * 24 24 * From Processor (physical) -> PCI:
+11 -11
arch/ppc/platforms/prep_pci.c
··· 589 589 { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */ 590 590 }; 591 591 592 - /* We have to turn on LEVEL mode for changed IRQ's */ 593 - /* All PCI IRQ's need to be level mode, so this should be something 594 - * other than hard-coded as well... IRQ's are individually mappable 592 + /* We have to turn on LEVEL mode for changed IRQs */ 593 + /* All PCI IRQs need to be level mode, so this should be something 594 + * other than hard-coded as well... IRQs are individually mappable 595 595 * to either edge or level. 596 596 */ 597 597 ··· 923 923 Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)"; 924 924 Motherboard_map = ibm6015_pci_IRQ_map; 925 925 Motherboard_routes = ibm6015_pci_IRQ_routes; 926 - *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */ 927 - *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */ 926 + *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 927 + *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ 928 928 } 929 929 930 930 void __init ··· 933 933 Motherboard_map_name = "IBM Thinkpad 850/860"; 934 934 Motherboard_map = Nobis_pci_IRQ_map; 935 935 Motherboard_routes = Nobis_pci_IRQ_routes; 936 - *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */ 937 - *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */ 936 + *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 937 + *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ 938 938 } 939 939 940 940 void __init ··· 943 943 Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)"; 944 944 Motherboard_map = ibm8xx_pci_IRQ_map; 945 945 Motherboard_routes = ibm8xx_pci_IRQ_routes; 946 - *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */ 947 - *irq_edge_mask_hi = 0xA4; /* irq's 10, 13, 15 level-triggered */ 946 + *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 947 + *irq_edge_mask_hi = 0xA4; /* IRQs 10, 13, 15 level-triggered */ 948 948 } 949 949 950 950 void __init ··· 954 954 Motherboard_map = ibm43p_pci_IRQ_map; 955 955 Motherboard_routes = ibm43p_pci_IRQ_routes; 956 956 Motherboard_non0 = ibm43p_pci_map_non0; 957 - *irq_edge_mask_lo = 0x00; /* irq's 0-7 all edge-triggered */ 958 - *irq_edge_mask_hi = 0xA0; /* irq's 13, 15 level-triggered */ 957 + *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 958 + *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ 959 959 } 960 960 961 961 void __init
+3 -3
arch/ppc/platforms/prep_setup.c
··· 593 593 PPC_DEVICE *audiodevice = NULL; 594 594 595 595 /* 596 - * Get the needed resource informations from residual data. 596 + * Get the needed resource information from residual data. 597 597 * 598 598 */ 599 599 if (have_residual_data) ··· 632 632 } 633 633 634 634 /* 635 - * Find a way to push these informations to the cs4232 driver 635 + * Find a way to push this information to the cs4232 driver 636 636 * Give it out with printk, when not in cmd_line? 637 - * Append it to cmd_line and boot_command_line? 637 + * Append it to cmd_line and boot_command_line? 638 638 * Format is cs4232=io,irq,dma,dma2 639 639 */ 640 640 }
+1 -1
arch/ppc/platforms/prpmc750.h
··· 16 16 #define __ASM_PRPMC750_H__ 17 17 18 18 /* 19 - * Due to limiations imposed by legacy hardware (primaryily IDE controllers), 19 + * Due to limitations imposed by legacy hardware (primarily IDE controllers), 20 20 * the PrPMC750 carrier board operates using a PReP address map. 21 21 * 22 22 * From Processor (physical) -> PCI:
+1 -1
arch/ppc/platforms/radstone_ppc7d.c
··· 1371 1371 * are non-zero, then we should use the board info from the bd_t 1372 1372 * structure and the cmdline pointed to by r6 instead of the 1373 1373 * information from birecs, if any. Otherwise, use the information 1374 - * from birecs as discovered by the preceeding call to 1374 + * from birecs as discovered by the preceding call to 1375 1375 * parse_bootinfo(). This rule should work with both PPCBoot, which 1376 1376 * uses a bd_t board info structure, and the kernel boot wrapper, 1377 1377 * which uses birecs.
+4 -4
arch/ppc/platforms/sandpoint.c
··· 54 54 * 55 55 * 56 56 * Motorola has finally released a version of DINK32 that correctly 57 - * (seemingly) initalizes the memory controller correctly, regardless 57 + * (seemingly) initializes the memory controller correctly, regardless 58 58 * of the amount of memory in the system. Once a method of determining 59 59 * what version of DINK initializes the system for us, if applicable, is 60 60 * found, we can hopefully stop hardcoding 32MB of RAM. ··· 473 473 arch_initcall(sandpoint_request_io); 474 474 475 475 /* 476 - * Interrupt setup and service. Interrrupts on the Sandpoint come 476 + * Interrupt setup and service. Interrupts on the Sandpoint come 477 477 * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO). 478 478 * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4, 479 479 * IDE is on EPIC 7 and 8. ··· 505 505 if (bp->bi_memsize) 506 506 return bp->bi_memsize; 507 507 508 - /* DINK32 13.0 correctly initalizes things, so iff you use 508 + /* DINK32 13.0 correctly initializes things, so iff you use 509 509 * this you _should_ be able to change this instead of a 510 510 * hardcoded value. */ 511 511 #if 0 ··· 677 677 * are non-zero, then we should use the board info from the bd_t 678 678 * structure and the cmdline pointed to by r6 instead of the 679 679 * information from birecs, if any. Otherwise, use the information 680 - * from birecs as discovered by the preceeding call to 680 + * from birecs as discovered by the preceding call to 681 681 * parse_bootinfo(). This rule should work with both PPCBoot, which 682 682 * uses a bd_t board info structure, and the kernel boot wrapper, 683 683 * which uses birecs.
+1 -1
arch/ppc/syslib/harrier.c
··· 210 210 * This assumes that PPCBug has initialized the memory controller (SMC) 211 211 * on the Harrier correctly (i.e., it does no sanity checking). 212 212 * It also assumes that the memory base registers are set to configure the 213 - * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc. 213 + * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc. 214 214 * however, RAM base registers can be skipped (e.g. A, B, C are set, 215 215 * D is skipped but E is set is okay). 216 216 */
+2 -2
arch/ppc/syslib/hawk_common.c
··· 165 165 processor_pci_mem_start + 166 166 hose->mem_space.start) | 0x0); 167 167 168 - /* Map MPIC into vitual memory */ 168 + /* Map MPIC into virtual memory */ 169 169 OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE); 170 170 171 171 return 0; ··· 176 176 * This assumes that PPCBug has initialized the memory controller (SMC) 177 177 * on the Falcon/HAWK correctly (i.e., it does no sanity checking). 178 178 * It also assumes that the memory base registers are set to configure the 179 - * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc. 179 + * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc. 180 180 * however, RAM base registers can be skipped (e.g. A, B, C are set, 181 181 * D is skipped but E is set is okay). 182 182 */
+1 -1
arch/ppc/syslib/m82xx_pci.c
··· 197 197 CPM high 0b0000 198 198 CPM middle 0b0001 199 199 CPM low 0b0010 200 - PCI reguest 0b0011 200 + PCI request 0b0011 201 201 Reserved 0b0100 202 202 Reserved 0b0101 203 203 Internal Core 0b0110
+2 -2
arch/ppc/syslib/mpc10x_common.c
··· 432 432 phys_eumb_base); 433 433 } 434 434 435 - /* IRQ's are determined at runtime */ 435 + /* IRQs are determined at runtime */ 436 436 ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ; 437 437 ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ; 438 438 ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ; ··· 646 646 openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020); 647 647 /* Skip reserved space and map Message Unit Interrupt (I2O) */ 648 648 openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0); 649 - /* Skip reserved space and map Serial Interupts */ 649 + /* Skip reserved space and map Serial Interrupts */ 650 650 openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120); 651 651 652 652 openpic_init(NUM_8259_INTERRUPTS);
+1 -1
arch/ppc/syslib/mpc52xx_setup.c
··· 252 252 out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d); 253 253 254 254 /* Disable XLB pipelining */ 255 - /* (cfr errate 292. We could do this only just before ATA PIO 255 + /* (cfr errata 292. We could do this only just before ATA PIO 256 256 transaction and re-enable it after ...) */ 257 257 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); 258 258
+1 -1
arch/ppc/syslib/mpc8xx_devices.c
··· 21 21 #include <asm/irq.h> 22 22 #include <asm/ppc_sys.h> 23 23 24 - /* We use offsets for IORESOURCE_MEM to do not set dependences at compile time. 24 + /* We use offsets for IORESOURCE_MEM to do not set dependencies at compile time. 25 25 * They will get fixed up by mach_mpc8xx_fixup 26 26 */ 27 27
+5 -5
arch/ppc/syslib/mv64x60.c
··· 490 490 /* 491 491 * mv64x60_init() 492 492 * 493 - * Initialze the bridge based on setting passed in via 'si'. The bridge 493 + * Initialize the bridge based on setting passed in via 'si'. The bridge 494 494 * handle, 'bh', will be set so that it can be used to make subsequent 495 495 * calls to routines in this file. 496 496 */ ··· 1704 1704 /* 1705 1705 * gt64260a_chip_specific_init() 1706 1706 * 1707 - * Implement errata work arounds for the GT64260A. 1707 + * Implement errata workarounds for the GT64260A. 1708 1708 */ 1709 1709 static void __init 1710 1710 gt64260a_chip_specific_init(struct mv64x60_handle *bh, ··· 1776 1776 /* 1777 1777 * gt64260b_chip_specific_init() 1778 1778 * 1779 - * Implement errata work arounds for the GT64260B. 1779 + * Implement errata workarounds for the GT64260B. 1780 1780 */ 1781 1781 static void __init 1782 1782 gt64260b_chip_specific_init(struct mv64x60_handle *bh, ··· 2316 2316 /* 2317 2317 * mv64360_chip_specific_init() 2318 2318 * 2319 - * Implement errata work arounds for the MV64360. 2319 + * Implement errata workarounds for the MV64360. 2320 2320 */ 2321 2321 static void __init 2322 2322 mv64360_chip_specific_init(struct mv64x60_handle *bh, ··· 2336 2336 /* 2337 2337 * mv64460_chip_specific_init() 2338 2338 * 2339 - * Implement errata work arounds for the MV64460. 2339 + * Implement errata workarounds for the MV64460. 2340 2340 */ 2341 2341 static void __init 2342 2342 mv64460_chip_specific_init(struct mv64x60_handle *bh,
+1 -1
arch/ppc/syslib/ocp.c
··· 27 27 * device model. The devices on the OCP bus are seeded by an 28 28 * an initial OCP device array created by the arch-specific 29 29 * Device entries can be added/removed/modified through OCP 30 - * helper functions to accomodate system and board-specific 30 + * helper functions to accommodate system and board-specific 31 31 * parameters commonly found in embedded systems. OCP also 32 32 * provides a standard method for devices to describe extended 33 33 * attributes about themselves to the system. A standard access
+1 -1
arch/ppc/syslib/ppc403_pic.c
··· 112 112 113 113 /* 114 114 * Disable all external interrupts until they are 115 - * explicity requested. 115 + * explicitly requested. 116 116 */ 117 117 ppc_cached_irq_mask[0] = 0; 118 118
+1 -1
arch/ppc/syslib/ppc405_pci.c
··· 137 137 hose_a->pci_mem_offset = 0; 138 138 139 139 /* Setup bridge memory/IO ranges & resources 140 - * TODO: Handle firmwares setting up a legacy ISA mem base 140 + * TODO: Handle firmware setting up a legacy ISA mem base 141 141 */ 142 142 hose_a->io_space.start = PPC405_PCI_LOWER_IO; 143 143 hose_a->io_space.end = PPC405_PCI_UPPER_IO;
+1 -1
arch/ppc/syslib/ppc4xx_dma.c
··· 241 241 } 242 242 243 243 /* 244 - * Returns the number of bytes left to be transfered. 244 + * Returns the number of bytes left to be transferred. 245 245 * After a DMA transfer, this should return zero. 246 246 * Reading this while a DMA transfer is still in progress will return 247 247 * unpredictable results.
+2 -2
arch/ppc/syslib/ppc85xx_rio.c
··· 349 349 * @dev_instance: Pointer to interrupt-specific data 350 350 * 351 351 * Handles outbound message interrupts. Executes a register outbound 352 - * mailbox event handler and acks the interrupt occurence. 352 + * mailbox event handler and acks the interrupt occurrence. 353 353 */ 354 354 static irqreturn_t 355 355 mpc85xx_rio_tx_handler(int irq, void *dev_instance) ··· 516 516 * @dev_instance: Pointer to interrupt-specific data 517 517 * 518 518 * Handles inbound message interrupts. Executes a registered inbound 519 - * mailbox event handler and acks the interrupt occurence. 519 + * mailbox event handler and acks the interrupt occurrence. 520 520 */ 521 521 static irqreturn_t 522 522 mpc85xx_rio_rx_handler(int irq, void *dev_instance)
+1 -1
arch/ppc/syslib/xilinx_pic.c
··· 130 130 131 131 /* 132 132 * Disable all external interrupts until they are 133 - * explicity requested. 133 + * explicitly requested. 134 134 */ 135 135 intc_out_be32(intc + IER, 0); 136 136
+1 -1
drivers/net/Kconfig
··· 2303 2303 2304 2304 config MV643XX_ETH 2305 2305 tristate "MV-643XX Ethernet support" 2306 - depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32) 2306 + depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32) 2307 2307 select MII 2308 2308 help 2309 2309 This driver supports the gigabit Ethernet on the Marvell MV643XX