Merge tag 'mmc-v5.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC fixes from Ulf Hansson:

- meson-mx-sdio: Fix support for HW busy detection

- sdhci-msm: Fix support for HW busy detection

- cqhci: Fix polling loop by converting to readx_poll_timeout()

- sdhci-xenon: Fix annoying 1.8V regulator warning

- sdhci-pci: Fix eMMC driver strength for BYT-based controllers

* tag 'mmc-v5.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci-pci: Fix eMMC driver strength for BYT-based controllers
mmc: sdhci-xenon: fix annoying 1.8V regulator warning
mmc: sdhci-msm: Enable host capabilities pertains to R1b response
mmc: cqhci: Avoid false "cqhci: CQE stuck on" by not open-coding timeout loop
mmc: meson-mx-sdio: remove the broken ->card_busy() op
mmc: meson-mx-sdio: Set MMC_CAP_WAIT_WHILE_BUSY
mmc: core: make mmc_interrupt_hpi() static

Linus Torvalds 6 years ago af4a32ad 1d2cc5ac

+27 -22

6 changed files

expand all

drivers

mmc

core

mmc_ops.c

host

cqhci.c

meson-mx-sdio.c

sdhci-msm.c

sdhci-pci-core.c

sdhci-xenon.c

+1 -1

drivers/mmc/core/mmc_ops.c

··· 878 878 * Issued High Priority Interrupt, and check for card status 879 879 * until out-of prg-state. 880 880 */ 881 - int mmc_interrupt_hpi(struct mmc_card *card) 881 + static int mmc_interrupt_hpi(struct mmc_card *card) 882 882 { 883 883 int err; 884 884 u32 status;

+10 -11

drivers/mmc/host/cqhci.c

··· 5 5 #include <linux/delay.h> 6 6 #include <linux/highmem.h> 7 7 #include <linux/io.h> 8 + #include <linux/iopoll.h> 8 9 #include <linux/module.h> 9 10 #include <linux/dma-mapping.h> 10 11 #include <linux/slab.h> ··· 350 349 /* CQHCI is idle and should halt immediately, so set a small timeout */ 351 350 #define CQHCI_OFF_TIMEOUT 100 352 351 352 + static u32 cqhci_read_ctl(struct cqhci_host *cq_host) 353 + { 354 + return cqhci_readl(cq_host, CQHCI_CTL); 355 + } 356 + 353 357 static void cqhci_off(struct mmc_host *mmc) 354 358 { 355 359 struct cqhci_host *cq_host = mmc->cqe_private; 356 - ktime_t timeout; 357 - bool timed_out; 358 360 u32 reg; 361 + int err; 359 362 360 363 if (!cq_host->enabled || !mmc->cqe_on || cq_host->recovery_halt) 361 364 return; ··· 369 364 370 365 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 371 366 372 - timeout = ktime_add_us(ktime_get(), CQHCI_OFF_TIMEOUT); 373 - while (1) { 374 - timed_out = ktime_compare(ktime_get(), timeout) > 0; 375 - reg = cqhci_readl(cq_host, CQHCI_CTL); 376 - if ((reg & CQHCI_HALT) || timed_out) 377 - break; 378 - } 379 - 380 - if (timed_out) 367 + err = readx_poll_timeout(cqhci_read_ctl, cq_host, reg, 368 + reg & CQHCI_HALT, 0, CQHCI_OFF_TIMEOUT); 369 + if (err < 0) 381 370 pr_err("%s: cqhci: CQE stuck on\n", mmc_hostname(mmc)); 382 371 else 383 372 pr_debug("%s: cqhci: CQE off\n", mmc_hostname(mmc));

+1 -10

drivers/mmc/host/meson-mx-sdio.c

··· 357 357 meson_mx_mmc_start_cmd(mmc, mrq->cmd); 358 358 } 359 359 360 - static int meson_mx_mmc_card_busy(struct mmc_host *mmc) 361 - { 362 - struct meson_mx_mmc_host *host = mmc_priv(mmc); 363 - u32 irqc = readl(host->base + MESON_MX_SDIO_IRQC); 364 - 365 - return !!(irqc & MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK); 366 - } 367 - 368 360 static void meson_mx_mmc_read_response(struct mmc_host *mmc, 369 361 struct mmc_command *cmd) 370 362 { ··· 498 506 static struct mmc_host_ops meson_mx_mmc_ops = { 499 507 .request = meson_mx_mmc_request, 500 508 .set_ios = meson_mx_mmc_set_ios, 501 - .card_busy = meson_mx_mmc_card_busy, 502 509 .get_cd = mmc_gpio_get_cd, 503 510 .get_ro = mmc_gpio_get_ro, 504 511 }; ··· 561 570 mmc->f_max = clk_round_rate(host->cfg_div_clk, 562 571 clk_get_rate(host->parent_clk)); 563 572 564 - mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 573 + mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY; 565 574 mmc->ops = &meson_mx_mmc_ops; 566 575 567 576 ret = mmc_of_parse(mmc);

drivers/mmc/host/sdhci-msm.c

··· 2087 2087 goto clk_disable; 2088 2088 } 2089 2089 2090 + msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 2091 + 2090 2092 pm_runtime_get_noresume(&pdev->dev); 2091 2093 pm_runtime_set_active(&pdev->dev); 2092 2094 pm_runtime_enable(&pdev->dev);

drivers/mmc/host/sdhci-pci-core.c

··· 601 601 struct sdhci_pci_slot *slot = sdhci_priv(host); 602 602 struct intel_host *intel_host = sdhci_pci_priv(slot); 603 603 604 + if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 605 + return 0; 606 + 604 607 return intel_host->drv_strength; 605 608 } 606 609

+10

drivers/mmc/host/sdhci-xenon.c

··· 235 235 { 236 236 /* Wait for 5ms after set 1.8V signal enable bit */ 237 237 usleep_range(5000, 5500); 238 + 239 + /* 240 + * For some reason the controller's Host Control2 register reports 241 + * the bit representing 1.8V signaling as 0 when read after it was 242 + * written as 1. Subsequent read reports 1. 243 + * 244 + * Since this may cause some issues, do an empty read of the Host 245 + * Control2 register here to circumvent this. 246 + */ 247 + sdhci_readw(host, SDHCI_HOST_CONTROL2); 238 248 } 239 249 240 250 static const struct sdhci_ops sdhci_xenon_ops = {

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