Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+1 -1

MAINTAINERS

··· 11163 11163 F: drivers/input/touchscreen/melfas_mip4.c 11164 11164 11165 11165 MELLANOX BLUEFIELD I2C DRIVER 11166 - M: Khalil Blaiech <kblaiech@mellanox.com> 11166 + M: Khalil Blaiech <kblaiech@nvidia.com> 11167 11167 L: linux-i2c@vger.kernel.org 11168 11168 S: Supported 11169 11169 F: drivers/i2c/busses/i2c-mlxbf.c

+1 -1

drivers/i2c/busses/Kconfig

··· 733 733 734 734 config I2C_MLXBF 735 735 tristate "Mellanox BlueField I2C controller" 736 - depends on ARM64 736 + depends on MELLANOX_PLATFORM && ARM64 737 737 help 738 738 Enabling this option will add I2C SMBus support for Mellanox BlueField 739 739 system.

+18 -32

drivers/i2c/busses/i2c-designware-slave.c

··· 159 159 u32 raw_stat, stat, enabled, tmp; 160 160 u8 val = 0, slave_activity; 161 161 162 - regmap_read(dev->map, DW_IC_INTR_STAT, &stat); 163 162 regmap_read(dev->map, DW_IC_ENABLE, &enabled); 164 163 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_stat); 165 164 regmap_read(dev->map, DW_IC_STATUS, &tmp); ··· 167 168 if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave) 168 169 return 0; 169 170 171 + stat = i2c_dw_read_clear_intrbits_slave(dev); 170 172 dev_dbg(dev->dev, 171 173 "%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n", 172 174 enabled, slave_activity, raw_stat, stat); 173 175 174 - if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET)) 175 - i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val); 176 + if (stat & DW_IC_INTR_RX_FULL) { 177 + if (dev->status != STATUS_WRITE_IN_PROGRESS) { 178 + dev->status = STATUS_WRITE_IN_PROGRESS; 179 + i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, 180 + &val); 181 + } 182 + 183 + regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 184 + val = tmp; 185 + if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED, 186 + &val)) 187 + dev_vdbg(dev->dev, "Byte %X acked!", val); 188 + } 176 189 177 190 if (stat & DW_IC_INTR_RD_REQ) { 178 191 if (slave_activity) { 179 - if (stat & DW_IC_INTR_RX_FULL) { 180 - regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 181 - val = tmp; 192 + regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp); 182 193 183 - if (!i2c_slave_event(dev->slave, 184 - I2C_SLAVE_WRITE_RECEIVED, 185 - &val)) { 186 - dev_vdbg(dev->dev, "Byte %X acked!", 187 - val); 188 - } 189 - regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp); 190 - stat = i2c_dw_read_clear_intrbits_slave(dev); 191 - } else { 192 - regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp); 193 - regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &tmp); 194 - stat = i2c_dw_read_clear_intrbits_slave(dev); 195 - } 194 + dev->status = STATUS_READ_IN_PROGRESS; 196 195 if (!i2c_slave_event(dev->slave, 197 196 I2C_SLAVE_READ_REQUESTED, 198 197 &val)) ··· 202 205 if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED, 203 206 &val)) 204 207 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &tmp); 205 - 206 - i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); 207 - stat = i2c_dw_read_clear_intrbits_slave(dev); 208 - return 1; 209 208 } 210 209 211 - if (stat & DW_IC_INTR_RX_FULL) { 212 - regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 213 - val = tmp; 214 - if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED, 215 - &val)) 216 - dev_vdbg(dev->dev, "Byte %X acked!", val); 217 - } else { 210 + if (stat & DW_IC_INTR_STOP_DET) { 211 + dev->status = STATUS_IDLE; 218 212 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val); 219 - stat = i2c_dw_read_clear_intrbits_slave(dev); 220 213 } 221 214 222 215 return 1; ··· 217 230 struct dw_i2c_dev *dev = dev_id; 218 231 int ret; 219 232 220 - i2c_dw_read_clear_intrbits_slave(dev); 221 233 ret = i2c_dw_irq_handler_slave(dev); 222 234 if (ret > 0) 223 235 complete(&dev->cmd_complete);

+86 -118

drivers/i2c/busses/i2c-mlxbf.c

··· 62 62 * Master. Default value is set to 400MHz. 63 63 */ 64 64 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 65 - /* Reference clock for Bluefield 1 - 156 MHz. */ 66 - #define MLXBF_I2C_TYU_PLL_IN_FREQ (156 * 1000 * 1000) 67 - /* Reference clock for BlueField 2 - 200 MHz. */ 68 - #define MLXBF_I2C_YU_PLL_IN_FREQ (200 * 1000 * 1000) 65 + /* Reference clock for Bluefield - 156 MHz. */ 66 + #define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000) 69 67 70 68 /* Constant used to determine the PLL frequency. */ 71 69 #define MLNXBF_I2C_COREPLL_CONST 16384 ··· 487 489 488 490 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000 489 491 490 - static void mlxbf_i2c_write(void __iomem *io, int reg, u32 val) 491 - { 492 - writel(val, io + reg); 493 - } 494 - 495 - static u32 mlxbf_i2c_read(void __iomem *io, int reg) 496 - { 497 - return readl(io + reg); 498 - } 499 - 500 - /* 501 - * This function is used to read data from Master GW Data Descriptor. 502 - * Data bytes in the Master GW Data Descriptor are shifted left so the 503 - * data starts at the MSB of the descriptor registers as set by the 504 - * underlying hardware. TYU_READ_DATA enables byte swapping while 505 - * reading data bytes, and MUST be called by the SMBus read routines 506 - * to copy data from the 32 * 32-bit HW Data registers a.k.a Master GW 507 - * Data Descriptor. 508 - */ 509 - static u32 mlxbf_i2c_read_data(void __iomem *io, int reg) 510 - { 511 - return (u32)be32_to_cpu(mlxbf_i2c_read(io, reg)); 512 - } 513 - 514 - /* 515 - * This function is used to write data to the Master GW Data Descriptor. 516 - * Data copied to the Master GW Data Descriptor MUST be shifted left so 517 - * the data starts at the MSB of the descriptor registers as required by 518 - * the underlying hardware. TYU_WRITE_DATA enables byte swapping when 519 - * writing data bytes, and MUST be called by the SMBus write routines to 520 - * copy data to the 32 * 32-bit HW Data registers a.k.a Master GW Data 521 - * Descriptor. 522 - */ 523 - static void mlxbf_i2c_write_data(void __iomem *io, int reg, u32 val) 524 - { 525 - mlxbf_i2c_write(io, reg, (u32)cpu_to_be32(val)); 526 - } 527 - 528 492 /* 529 493 * Function to poll a set of bits at a specific address; it checks whether 530 494 * the bits are equal to zero when eq_zero is set to 'true', and not equal ··· 501 541 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1; 502 542 503 543 do { 504 - bits = mlxbf_i2c_read(io, addr) & mask; 544 + bits = readl(io + addr) & mask; 505 545 if (eq_zero ? bits == 0 : bits != 0) 506 546 return eq_zero ? 1 : bits; 507 547 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC); ··· 569 609 MLXBF_I2C_SMBUS_TIMEOUT); 570 610 571 611 /* Read cause status bits. */ 572 - cause_status_bits = mlxbf_i2c_read(priv->mst_cause->io, 573 - MLXBF_I2C_CAUSE_ARBITER); 612 + cause_status_bits = readl(priv->mst_cause->io + 613 + MLXBF_I2C_CAUSE_ARBITER); 574 614 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 575 615 576 616 /* 577 617 * Parse both Cause and Master GW bits, then return transaction status. 578 618 */ 579 619 580 - master_status_bits = mlxbf_i2c_read(priv->smbus->io, 581 - MLXBF_I2C_SMBUS_MASTER_STATUS); 620 + master_status_bits = readl(priv->smbus->io + 621 + MLXBF_I2C_SMBUS_MASTER_STATUS); 582 622 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 583 623 584 624 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, ··· 609 649 610 650 aligned_length = round_up(length, 4); 611 651 612 - /* Copy data bytes from 4-byte aligned source buffer. */ 652 + /* 653 + * Copy data bytes from 4-byte aligned source buffer. 654 + * Data copied to the Master GW Data Descriptor MUST be shifted 655 + * left so the data starts at the MSB of the descriptor registers 656 + * as required by the underlying hardware. Enable byte swapping 657 + * when writing data bytes to the 32 * 32-bit HW Data registers 658 + * a.k.a Master GW Data Descriptor. 659 + */ 613 660 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 614 661 data32 = *((u32 *)(data + offset)); 615 - mlxbf_i2c_write_data(priv->smbus->io, addr + offset, data32); 662 + iowrite32be(data32, priv->smbus->io + addr + offset); 616 663 } 617 664 } 618 665 ··· 631 664 632 665 mask = sizeof(u32) - 1; 633 666 667 + /* 668 + * Data bytes in the Master GW Data Descriptor are shifted left 669 + * so the data starts at the MSB of the descriptor registers as 670 + * set by the underlying hardware. Enable byte swapping while 671 + * reading data bytes from the 32 * 32-bit HW Data registers 672 + * a.k.a Master GW Data Descriptor. 673 + */ 674 + 634 675 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 635 - data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset); 676 + data32 = ioread32be(priv->smbus->io + addr + offset); 636 677 *((u32 *)(data + offset)) = data32; 637 678 } 638 679 639 680 if (!(length & mask)) 640 681 return; 641 682 642 - data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset); 683 + data32 = ioread32be(priv->smbus->io + addr + offset); 643 684 644 685 for (byte = 0; byte < (length & mask); byte++) { 645 686 data[offset + byte] = data32 & GENMASK(7, 0); ··· 673 698 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 674 699 675 700 /* Clear status bits. */ 676 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_STATUS, 0x0); 701 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 677 702 /* Set the cause data. */ 678 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0); 703 + writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR); 679 704 /* Zero PEC byte. */ 680 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_PEC, 0x0); 705 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC); 681 706 /* Zero byte count. */ 682 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_RS_BYTES, 0x0); 707 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES); 683 708 684 709 /* GW activation. */ 685 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, command); 710 + writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW); 686 711 687 712 /* 688 713 * Poll master status and check status bits. An ACK is sent when ··· 798 823 * needs to be 'manually' reset. This should be removed in 799 824 * next tag integration. 800 825 */ 801 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_FSM, 802 - MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK); 826 + writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 827 + priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM); 803 828 } 804 829 805 830 return ret; ··· 1088 1113 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1089 1114 false, MLXBF_I2C_MASK_16, 1090 1115 MLXBF_I2C_SHIFT_16); 1091 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH, 1092 - timer); 1116 + writel(timer, priv->smbus->io + 1117 + MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1093 1118 1094 1119 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1095 1120 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); ··· 1099 1124 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1100 1125 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1101 1126 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1102 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE, 1103 - timer); 1127 + writel(timer, priv->smbus->io + 1128 + MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1104 1129 1105 1130 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1106 1131 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1107 1132 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1108 1133 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1109 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_THOLD, timer); 1134 + writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1110 1135 1111 1136 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1112 1137 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1113 1138 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1114 1139 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1115 - mlxbf_i2c_write(priv->smbus->io, 1116 - MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP, timer); 1140 + writel(timer, priv->smbus->io + 1141 + MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1117 1142 1118 1143 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1119 1144 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1120 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA, 1121 - timer); 1145 + writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1122 1146 1123 1147 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1124 1148 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1125 1149 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1126 1150 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1127 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_THIGH_MAX_TBUF, 1128 - timer); 1151 + writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1129 1152 1130 1153 timer = timings->timeout; 1131 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT, 1132 - timer); 1154 + writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1133 1155 } 1134 1156 1135 1157 enum mlxbf_i2c_timings_config { ··· 1398 1426 * platform firmware; disabling the bus might compromise the system 1399 1427 * functionality. 1400 1428 */ 1401 - config_reg = mlxbf_i2c_read(gpio_res->io, 1402 - MLXBF_I2C_GPIO_0_FUNC_EN_0); 1429 + config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1403 1430 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1404 1431 config_reg); 1405 - mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FUNC_EN_0, 1406 - config_reg); 1432 + writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1407 1433 1408 - config_reg = mlxbf_i2c_read(gpio_res->io, 1409 - MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1434 + config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1410 1435 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1411 1436 config_reg); 1412 - mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FORCE_OE_EN, 1413 - config_reg); 1437 + writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1414 1438 1415 1439 mutex_unlock(gpio_res->lock); 1416 1440 ··· 1420 1452 u32 corepll_val; 1421 1453 u16 core_f; 1422 1454 1423 - pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ; 1455 + pad_frequency = MLXBF_I2C_PLL_IN_FREQ; 1424 1456 1425 - corepll_val = mlxbf_i2c_read(corepll_res->io, 1426 - MLXBF_I2C_CORE_PLL_REG1); 1457 + corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1427 1458 1428 1459 /* Get Core PLL configuration bits. */ 1429 1460 core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) & ··· 1455 1488 u8 core_od, core_r; 1456 1489 u32 core_f; 1457 1490 1458 - pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ; 1491 + pad_frequency = MLXBF_I2C_PLL_IN_FREQ; 1459 1492 1460 - corepll_reg1_val = mlxbf_i2c_read(corepll_res->io, 1461 - MLXBF_I2C_CORE_PLL_REG1); 1462 - corepll_reg2_val = mlxbf_i2c_read(corepll_res->io, 1463 - MLXBF_I2C_CORE_PLL_REG2); 1493 + corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1494 + corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1464 1495 1465 1496 /* Get Core PLL configuration bits */ 1466 1497 core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) & ··· 1550 1585 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1551 1586 */ 1552 1587 for (reg = 0; reg < reg_cnt; reg++) { 1553 - slave_reg = mlxbf_i2c_read(priv->smbus->io, 1588 + slave_reg = readl(priv->smbus->io + 1554 1589 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1555 1590 /* 1556 1591 * Each register holds 4 slave addresses. So, we have to keep ··· 1608 1643 1609 1644 /* Enable the slave address and update the register. */ 1610 1645 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8); 1611 - mlxbf_i2c_write(priv->smbus->io, 1612 - MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg); 1646 + writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1647 + reg * 0x4); 1613 1648 1614 1649 return 0; 1615 1650 } ··· 1633 1668 * (7-bit address, 1 status bit (1 if enabled, 0 if not)). 1634 1669 */ 1635 1670 for (reg = 0; reg < reg_cnt; reg++) { 1636 - slave_reg = mlxbf_i2c_read(priv->smbus->io, 1671 + slave_reg = readl(priv->smbus->io + 1637 1672 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1638 1673 1639 1674 /* Check whether the address slots are empty. */ ··· 1673 1708 1674 1709 /* Cleanup the slave address slot. */ 1675 1710 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8)); 1676 - mlxbf_i2c_write(priv->smbus->io, 1677 - MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg); 1711 + writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1712 + reg * 0x4); 1678 1713 1679 1714 return 0; 1680 1715 } ··· 1766 1801 int ret; 1767 1802 1768 1803 /* Reset FSM. */ 1769 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_FSM, 0); 1804 + writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1770 1805 1771 1806 /* 1772 1807 * Enable slave cause interrupt bits. Drive ··· 1775 1810 * masters issue a Read and Write, respectively. But, clear all 1776 1811 * interrupts first. 1777 1812 */ 1778 - mlxbf_i2c_write(priv->slv_cause->io, 1779 - MLXBF_I2C_CAUSE_OR_CLEAR, ~0); 1813 + writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1780 1814 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1781 1815 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1782 - mlxbf_i2c_write(priv->slv_cause->io, 1783 - MLXBF_I2C_CAUSE_OR_EVTEN0, int_reg); 1816 + writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1784 1817 1785 1818 /* Finally, set the 'ready' bit to start handling transactions. */ 1786 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1); 1819 + writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1787 1820 1788 1821 /* Initialize the cause coalesce resource. */ 1789 1822 ret = mlxbf_i2c_init_coalesce(pdev, priv); ··· 1807 1844 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1808 1845 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1809 1846 1810 - coalesce0_reg = mlxbf_i2c_read(priv->coalesce->io, 1811 - MLXBF_I2C_CAUSE_COALESCE_0); 1847 + coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1812 1848 is_set = coalesce0_reg & (1 << slave_shift); 1813 1849 1814 1850 if (!is_set) 1815 1851 return false; 1816 1852 1817 1853 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1818 - cause_reg = mlxbf_i2c_read(priv->slv_cause->io, 1819 - MLXBF_I2C_CAUSE_ARBITER); 1854 + cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1820 1855 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1821 1856 *read = true; 1822 1857 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1823 1858 *write = true; 1824 1859 1825 1860 /* Clear cause bits. */ 1826 - mlxbf_i2c_write(priv->slv_cause->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0); 1861 + writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1827 1862 1828 1863 return true; 1829 1864 } ··· 1861 1900 * address, if supplied. 1862 1901 */ 1863 1902 if (recv_bytes > 0) { 1864 - data32 = mlxbf_i2c_read_data(priv->smbus->io, 1865 - MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1903 + data32 = ioread32be(priv->smbus->io + 1904 + MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1866 1905 1867 1906 /* Parse the received bytes. */ 1868 1907 switch (recv_bytes) { ··· 1927 1966 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1928 1967 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1929 1968 1930 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_GW, control32); 1969 + writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1931 1970 1932 1971 /* 1933 1972 * Wait until the transfer is completed; the driver will wait ··· 1936 1975 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT); 1937 1976 1938 1977 /* Release the Slave GW. */ 1939 - mlxbf_i2c_write(priv->smbus->io, 1940 - MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0); 1941 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0); 1942 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1); 1978 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1979 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1980 + writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1943 1981 1944 1982 return 0; 1945 1983 } ··· 1983 2023 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1984 2024 1985 2025 /* Release the Slave GW. */ 1986 - mlxbf_i2c_write(priv->smbus->io, 1987 - MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0); 1988 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0); 1989 - mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1); 2026 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2027 + writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 2028 + writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1990 2029 1991 2030 return ret; 1992 2031 } ··· 2020 2061 * slave, if the higher 8 bits are sent then the slave expect N bytes 2021 2062 * from the master. 2022 2063 */ 2023 - rw_bytes_reg = mlxbf_i2c_read(priv->smbus->io, 2024 - MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2064 + rw_bytes_reg = readl(priv->smbus->io + 2065 + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2025 2066 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2026 2067 2027 2068 /* ··· 2223 2264 2224 2265 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids); 2225 2266 2267 + #ifdef CONFIG_ACPI 2226 2268 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2227 2269 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2228 2270 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, ··· 2265 2305 2266 2306 return ret; 2267 2307 } 2308 + #else 2309 + static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2310 + { 2311 + return -ENOENT; 2312 + } 2313 + #endif /* CONFIG_ACPI */ 2268 2314 2269 2315 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2270 2316 { ··· 2439 2473 .driver = { 2440 2474 .name = "i2c-mlxbf", 2441 2475 .of_match_table = mlxbf_i2c_dt_ids, 2476 + #ifdef CONFIG_ACPI 2442 2477 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2478 + #endif /* CONFIG_ACPI */ 2443 2479 }, 2444 2480 }; 2445 2481 ··· 2470 2502 module_exit(mlxbf_i2c_exit); 2471 2503 2472 2504 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2473 - MODULE_AUTHOR("Khalil Blaiech <kblaiech@mellanox.com>"); 2505 + MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2474 2506 MODULE_LICENSE("GPL v2");

+4 -4

drivers/i2c/busses/i2c-mt65xx.c

··· 475 475 { 476 476 u16 control_reg; 477 477 478 + writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 479 + udelay(50); 480 + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 481 + 478 482 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 479 483 480 484 /* Set ioconfig */ ··· 533 529 534 530 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 535 531 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 536 - 537 - writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 538 - udelay(50); 539 - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 540 532 } 541 533 542 534 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)

+65 -19

drivers/i2c/busses/i2c-sh_mobile.c

··· 129 129 int sr; 130 130 bool send_stop; 131 131 bool stop_after_dma; 132 + bool atomic_xfer; 132 133 133 134 struct resource *res; 134 135 struct dma_chan *dma_tx; ··· 331 330 ret = iic_rd(pd, ICDR); 332 331 break; 333 332 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 334 - iic_wr(pd, ICIC, 335 - ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 333 + if (!pd->atomic_xfer) 334 + iic_wr(pd, ICIC, 335 + ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 336 336 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 337 337 break; 338 338 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 339 - iic_wr(pd, ICIC, 340 - ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 339 + if (!pd->atomic_xfer) 340 + iic_wr(pd, ICIC, 341 + ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 341 342 ret = iic_rd(pd, ICDR); 342 343 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 343 344 break; ··· 432 429 433 430 if (wakeup) { 434 431 pd->sr |= SW_DONE; 435 - wake_up(&pd->wait); 432 + if (!pd->atomic_xfer) 433 + wake_up(&pd->wait); 436 434 } 437 435 438 436 /* defeat write posting to avoid spurious WAIT interrupts */ ··· 585 581 pd->pos = -1; 586 582 pd->sr = 0; 587 583 584 + if (pd->atomic_xfer) 585 + return; 586 + 588 587 pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8); 589 588 if (pd->dma_buf) 590 589 sh_mobile_i2c_xfer_dma(pd); ··· 644 637 return i ? 0 : -ETIMEDOUT; 645 638 } 646 639 647 - static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 648 - struct i2c_msg *msgs, 649 - int num) 640 + static int sh_mobile_xfer(struct sh_mobile_i2c_data *pd, 641 + struct i2c_msg *msgs, int num) 650 642 { 651 - struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 652 643 struct i2c_msg *msg; 653 644 int err = 0; 654 645 int i; 655 - long timeout; 646 + long time_left; 656 647 657 648 /* Wake up device and enable clock */ 658 649 pm_runtime_get_sync(pd->dev); ··· 667 662 if (do_start) 668 663 i2c_op(pd, OP_START); 669 664 670 - /* The interrupt handler takes care of the rest... */ 671 - timeout = wait_event_timeout(pd->wait, 672 - pd->sr & (ICSR_TACK | SW_DONE), 673 - adapter->timeout); 665 + if (pd->atomic_xfer) { 666 + unsigned long j = jiffies + pd->adap.timeout; 674 667 675 - /* 'stop_after_dma' tells if DMA transfer was complete */ 676 - i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma); 668 + time_left = time_before_eq(jiffies, j); 669 + while (time_left && 670 + !(pd->sr & (ICSR_TACK | SW_DONE))) { 671 + unsigned char sr = iic_rd(pd, ICSR); 677 672 678 - if (!timeout) { 673 + if (sr & (ICSR_AL | ICSR_TACK | 674 + ICSR_WAIT | ICSR_DTE)) { 675 + sh_mobile_i2c_isr(0, pd); 676 + udelay(150); 677 + } else { 678 + cpu_relax(); 679 + } 680 + time_left = time_before_eq(jiffies, j); 681 + } 682 + } else { 683 + /* The interrupt handler takes care of the rest... */ 684 + time_left = wait_event_timeout(pd->wait, 685 + pd->sr & (ICSR_TACK | SW_DONE), 686 + pd->adap.timeout); 687 + 688 + /* 'stop_after_dma' tells if DMA xfer was complete */ 689 + i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, 690 + pd->stop_after_dma); 691 + } 692 + 693 + if (!time_left) { 679 694 dev_err(pd->dev, "Transfer request timed out\n"); 680 695 if (pd->dma_direction != DMA_NONE) 681 696 sh_mobile_i2c_cleanup_dma(pd); ··· 721 696 return err ?: num; 722 697 } 723 698 699 + static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 700 + struct i2c_msg *msgs, 701 + int num) 702 + { 703 + struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 704 + 705 + pd->atomic_xfer = false; 706 + return sh_mobile_xfer(pd, msgs, num); 707 + } 708 + 709 + static int sh_mobile_i2c_xfer_atomic(struct i2c_adapter *adapter, 710 + struct i2c_msg *msgs, 711 + int num) 712 + { 713 + struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 714 + 715 + pd->atomic_xfer = true; 716 + return sh_mobile_xfer(pd, msgs, num); 717 + } 718 + 724 719 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 725 720 { 726 721 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 727 722 } 728 723 729 724 static const struct i2c_algorithm sh_mobile_i2c_algorithm = { 730 - .functionality = sh_mobile_i2c_func, 731 - .master_xfer = sh_mobile_i2c_xfer, 725 + .functionality = sh_mobile_i2c_func, 726 + .master_xfer = sh_mobile_i2c_xfer, 727 + .master_xfer_atomic = sh_mobile_i2c_xfer_atomic, 732 728 }; 733 729 734 730 static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {

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