tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6

Linus Torvalds af74c3a6 d7dd8a72

+91 -36
+91 -36
arch/sparc64/kernel/head.S
··· 382 382 nop 383 383 /* Not reached... */ 384 384 385 - /* IMPORTANT NOTE: Whenever making changes here, check 386 - * trampoline.S as well. -jj */ 387 - .globl setup_tba 388 - setup_tba: /* i0 = is_starfire */ 389 - save %sp, -160, %sp 385 + /* This is meant to allow the sharing of this code between 386 + * boot processor invocation (via setup_tba() below) and 387 + * secondary processor startup (via trampoline.S). The 388 + * former does use this code, the latter does not yet due 389 + * to some complexities. That should be fixed up at some 390 + * point. 391 + */ 392 + .globl setup_trap_table 393 + setup_trap_table: 394 + save %sp, -192, %sp 390 395 391 - rdpr %tba, %g7 392 - sethi %hi(prom_tba), %o1 393 - or %o1, %lo(prom_tba), %o1 394 - stx %g7, [%o1] 396 + /* Force interrupts to be disabled. Transferring over to 397 + * the Linux trap table is a very delicate operation. 398 + * Until we are actually on the Linux trap table, we cannot 399 + * get the PAGE_OFFSET linear mappings translated. We need 400 + * that mapping to be setup in order to initialize the firmware 401 + * page tables. 402 + * 403 + * So there is this window of time, from the return from 404 + * prom_set_trap_table() until inherit_prom_mappings_post() 405 + * (in arch/sparc64/mm/init.c) completes, during which no 406 + * firmware address space accesses can be made. 407 + */ 408 + rdpr %pstate, %o1 409 + andn %o1, PSTATE_IE, %o1 410 + wrpr %o1, 0x0, %pstate 411 + wrpr %g0, 15, %pil 395 412 396 - /* Setup "Linux" globals 8-) */ 413 + /* Ok, now make the final valid firmware call to jump over 414 + * to the Linux trap table. 415 + */ 416 + call prom_set_trap_table 417 + sethi %hi(sparc64_ttable_tl0), %o0 418 + 419 + /* Start using proper page size encodings in ctx register. */ 420 + sethi %hi(sparc64_kern_pri_context), %g3 421 + ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 422 + mov PRIMARY_CONTEXT, %g1 423 + stxa %g2, [%g1] ASI_DMMU 424 + membar #Sync 425 + 426 + /* The Linux trap handlers expect various trap global registers 427 + * to be setup with some fixed values. So here we set these 428 + * up very carefully. These globals are: 429 + * 430 + * Alternate Globals (PSTATE_AG): 431 + * 432 + * %g6 --> current_thread_info() 433 + * 434 + * MMU Globals (PSTATE_MG): 435 + * 436 + * %g1 --> TLB_SFSR 437 + * %g2 --> ((_PAGE_VALID | _PAGE_SZ4MB | 438 + * _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W) 439 + * ^ 0xfffff80000000000) 440 + * (this %g2 value is used for computing the PAGE_OFFSET kernel 441 + * TLB entries quickly, the virtual address of the fault XOR'd 442 + * with this %g2 value is the PTE to load into the TLB) 443 + * %g3 --> VPTE_BASE_CHEETAH or VPTE_BASE_SPITFIRE 444 + * 445 + * Interrupt Globals (PSTATE_IG, setup by init_irqwork_curcpu()): 446 + * 447 + * %g6 --> __irq_work[smp_processor_id()] 448 + */ 449 + 397 450 rdpr %pstate, %o1 398 451 mov %g6, %o2 399 - wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate 400 - sethi %hi(sparc64_ttable_tl0), %g1 401 - wrpr %g1, %tba 452 + wrpr %o1, PSTATE_AG, %pstate 402 453 mov %o2, %g6 403 454 404 - /* Set up MMU globals */ 405 - wrpr %o1, (PSTATE_MG|PSTATE_IE), %pstate 406 - 407 - /* Set fixed globals used by dTLB miss handler. */ 408 455 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000) 409 456 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W) 410 - 457 + wrpr %o1, PSTATE_MG, %pstate 411 458 mov TSB_REG, %g1 412 459 stxa %g0, [%g1] ASI_DMMU 413 460 membar #Sync ··· 466 419 sllx %g2, 32, %g2 467 420 or %g2, KERN_LOWBITS, %g2 468 421 469 - BRANCH_IF_ANY_CHEETAH(g3,g7,cheetah_vpte_base) 470 - ba,pt %xcc, spitfire_vpte_base 422 + BRANCH_IF_ANY_CHEETAH(g3,g7,8f) 423 + ba,pt %xcc, 9f 471 424 nop 472 425 473 - cheetah_vpte_base: 426 + 8: 474 427 sethi %uhi(VPTE_BASE_CHEETAH), %g3 475 428 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3 476 429 ba,pt %xcc, 2f 477 430 sllx %g3, 32, %g3 478 431 479 - spitfire_vpte_base: 432 + 9: 480 433 sethi %uhi(VPTE_BASE_SPITFIRE), %g3 481 434 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3 482 435 sllx %g3, 32, %g3 ··· 502 455 sllx %o2, 32, %o2 503 456 wr %o2, %asr25 504 457 505 - /* Ok, we're done setting up all the state our trap mechanims needs, 506 - * now get back into normal globals and let the PROM know what is up. 507 - */ 508 458 2: 509 459 wrpr %g0, %g0, %wstate 510 - wrpr %o1, PSTATE_IE, %pstate 460 + wrpr %o1, 0x0, %pstate 511 461 512 462 call init_irqwork_curcpu 513 463 nop 514 464 515 - call prom_set_trap_table 516 - sethi %hi(sparc64_ttable_tl0), %o0 517 - 518 - /* Start using proper page size encodings in ctx register. */ 519 - sethi %hi(sparc64_kern_pri_context), %g3 520 - ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 521 - mov PRIMARY_CONTEXT, %g1 522 - stxa %g2, [%g1] ASI_DMMU 523 - membar #Sync 524 - 465 + /* Now we can turn interrupts back on. */ 525 466 rdpr %pstate, %o1 526 467 or %o1, PSTATE_IE, %o1 527 468 wrpr %o1, 0, %pstate 469 + wrpr %g0, 0x0, %pil 470 + 471 + ret 472 + restore 473 + 474 + .globl setup_tba 475 + setup_tba: /* i0 = is_starfire */ 476 + save %sp, -192, %sp 477 + 478 + /* The boot processor is the only cpu which invokes this 479 + * routine, the other cpus set things up via trampoline.S. 480 + * So save the OBP trap table address here. 481 + */ 482 + rdpr %tba, %g7 483 + sethi %hi(prom_tba), %o1 484 + or %o1, %lo(prom_tba), %o1 485 + stx %g7, [%o1] 486 + 487 + call setup_trap_table 488 + nop 528 489 529 490 ret 530 491 restore