Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

+20 -26

drivers/net/ethernet/intel/e1000/e1000_hw.c

··· 5 5 * Shared functions for accessing and configuring the MAC 6 6 */ 7 7 8 + #include <linux/bitfield.h> 8 9 #include "e1000.h" 9 10 10 11 static s32 e1000_check_downshift(struct e1000_hw *hw); ··· 3261 3260 return ret_val; 3262 3261 3263 3262 phy_info->mdix_mode = 3264 - (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> 3265 - IGP01E1000_PSSR_MDIX_SHIFT); 3263 + (e1000_auto_x_mode)FIELD_GET(IGP01E1000_PSSR_MDIX, phy_data); 3266 3264 3267 3265 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3268 3266 IGP01E1000_PSSR_SPEED_1000MBPS) { ··· 3272 3272 if (ret_val) 3273 3273 return ret_val; 3274 3274 3275 - phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3276 - SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3275 + phy_info->local_rx = FIELD_GET(SR_1000T_LOCAL_RX_STATUS, 3276 + phy_data) ? 3277 3277 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3278 - phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3279 - SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3278 + phy_info->remote_rx = FIELD_GET(SR_1000T_REMOTE_RX_STATUS, 3279 + phy_data) ? 3280 3280 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3281 3281 3282 3282 /* Get cable length */ ··· 3326 3326 return ret_val; 3327 3327 3328 3328 phy_info->extended_10bt_distance = 3329 - ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3330 - M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3329 + FIELD_GET(M88E1000_PSCR_10BT_EXT_DIST_ENABLE, phy_data) ? 3331 3330 e1000_10bt_ext_dist_enable_lower : 3332 3331 e1000_10bt_ext_dist_enable_normal; 3333 3332 3334 3333 phy_info->polarity_correction = 3335 - ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3336 - M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3334 + FIELD_GET(M88E1000_PSCR_POLARITY_REVERSAL, phy_data) ? 3337 3335 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3338 3336 3339 3337 /* Check polarity status */ ··· 3345 3347 return ret_val; 3346 3348 3347 3349 phy_info->mdix_mode = 3348 - (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> 3349 - M88E1000_PSSR_MDIX_SHIFT); 3350 + (e1000_auto_x_mode)FIELD_GET(M88E1000_PSSR_MDIX, phy_data); 3350 3351 3351 3352 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3352 3353 /* Cable Length Estimation and Local/Remote Receiver Information 3353 3354 * are only valid at 1000 Mbps. 3354 3355 */ 3355 3356 phy_info->cable_length = 3356 - (e1000_cable_length) ((phy_data & 3357 - M88E1000_PSSR_CABLE_LENGTH) >> 3358 - M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3357 + (e1000_cable_length)FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, 3358 + phy_data); 3359 3359 3360 3360 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3361 3361 if (ret_val) 3362 3362 return ret_val; 3363 3363 3364 - phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3365 - SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3364 + phy_info->local_rx = FIELD_GET(SR_1000T_LOCAL_RX_STATUS, 3365 + phy_data) ? 3366 3366 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3367 - phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3368 - SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3367 + phy_info->remote_rx = FIELD_GET(SR_1000T_REMOTE_RX_STATUS, 3368 + phy_data) ? 3369 3369 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3370 3370 } 3371 3371 ··· 3511 3515 if (ret_val) 3512 3516 return ret_val; 3513 3517 eeprom_size = 3514 - (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3518 + FIELD_GET(EEPROM_SIZE_MASK, eeprom_size); 3515 3519 /* 256B eeprom size was not supported in earlier hardware, so we 3516 3520 * bump eeprom_size up one to ensure that "1" (which maps to 3517 3521 * 256B) is never the result used in the shifting logic below. ··· 4887 4891 &phy_data); 4888 4892 if (ret_val) 4889 4893 return ret_val; 4890 - cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4891 - M88E1000_PSSR_CABLE_LENGTH_SHIFT; 4894 + cable_length = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data); 4892 4895 4893 4896 /* Convert the enum value to ranged values */ 4894 4897 switch (cable_length) { ··· 4996 5001 &phy_data); 4997 5002 if (ret_val) 4998 5003 return ret_val; 4999 - *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 5000 - M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5004 + *polarity = FIELD_GET(M88E1000_PSSR_REV_POLARITY, phy_data) ? 5001 5005 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5002 5006 5003 5007 } else if (hw->phy_type == e1000_phy_igp) { ··· 5066 5072 if (ret_val) 5067 5073 return ret_val; 5068 5074 5069 - hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5070 - M88E1000_PSSR_DOWNSHIFT_SHIFT; 5075 + hw->speed_downgraded = FIELD_GET(M88E1000_PSSR_DOWNSHIFT, 5076 + phy_data); 5071 5077 } 5072 5078 5073 5079 return E1000_SUCCESS;

+11 -12

drivers/net/ethernet/intel/e1000e/80003es2lan.c

··· 92 92 93 93 nvm->type = e1000_nvm_eeprom_spi; 94 94 95 - size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 96 - E1000_EECD_SIZE_EX_SHIFT); 95 + size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd); 97 96 98 97 /* Added to a constant, "size" becomes the left-shift value 99 98 * for setting word_size. ··· 1034 1035 * iteration and increase the max iterations when 1035 1036 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1036 1037 */ 1037 - ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1038 - 0xFFFF); 1038 + /* these next three accesses were always meant to use page 0x34 using 1039 + * GG82563_REG(0x34, N) but never did, so we've just corrected the call 1040 + * to not drop bits 1041 + */ 1042 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 4, 0xFFFF); 1039 1043 if (ret_val) 1040 1044 return ret_val; 1041 - ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1042 - &reg_data); 1045 + ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 9, &reg_data); 1043 1046 if (ret_val) 1044 1047 return ret_val; 1045 1048 reg_data |= 0x3F; 1046 - ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1047 - reg_data); 1049 + ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 9, reg_data); 1048 1050 if (ret_val) 1049 1051 return ret_val; 1050 1052 ret_val = ··· 1209 1209 if (ret_val) 1210 1210 return ret_val; 1211 1211 1212 - kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1213 - E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1212 + kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | 1213 + E1000_KMRNCTRLSTA_REN; 1214 1214 ew32(KMRNCTRLSTA, kmrnctrlsta); 1215 1215 e1e_flush(); 1216 1216 ··· 1244 1244 if (ret_val) 1245 1245 return ret_val; 1246 1246 1247 - kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1248 - E1000_KMRNCTRLSTA_OFFSET) | data; 1247 + kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data; 1249 1248 ew32(KMRNCTRLSTA, kmrnctrlsta); 1250 1249 e1e_flush(); 1251 1250

+1 -2

drivers/net/ethernet/intel/e1000e/82571.c

··· 157 157 fallthrough; 158 158 default: 159 159 nvm->type = e1000_nvm_eeprom_spi; 160 - size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 161 - E1000_EECD_SIZE_EX_SHIFT); 160 + size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd); 162 161 /* Added to a constant, "size" becomes the left-shift value 163 162 * for setting word_size. 164 163 */

+3 -4

drivers/net/ethernet/intel/e1000e/ethtool.c

··· 654 654 */ 655 655 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 656 656 "%d.%d-%d", 657 - (adapter->eeprom_vers & 0xF000) >> 12, 658 - (adapter->eeprom_vers & 0x0FF0) >> 4, 657 + FIELD_GET(0xF000, adapter->eeprom_vers), 658 + FIELD_GET(0x0FF0, adapter->eeprom_vers), 659 659 (adapter->eeprom_vers & 0x000F)); 660 660 661 661 strscpy(drvinfo->bus_info, pci_name(adapter->pdev), ··· 925 925 } 926 926 927 927 if (mac->type >= e1000_pch_lpt) 928 - wlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >> 929 - E1000_FWSM_WLOCK_MAC_SHIFT; 928 + wlock_mac = FIELD_GET(E1000_FWSM_WLOCK_MAC_MASK, er32(FWSM)); 930 929 931 930 for (i = 0; i < mac->rar_entry_count; i++) { 932 931 if (mac->type >= e1000_pch_lpt) {

+7 -11

drivers/net/ethernet/intel/e1000e/ich8lan.c

··· 1072 1072 1073 1073 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) * 1074 1074 (1U << (E1000_LTRV_SCALE_FACTOR * 1075 - ((lat_enc & E1000_LTRV_SCALE_MASK) 1076 - >> E1000_LTRV_SCALE_SHIFT))); 1075 + FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc))); 1077 1076 1078 1077 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) * 1079 - (1U << (E1000_LTRV_SCALE_FACTOR * 1080 - ((max_ltr_enc & E1000_LTRV_SCALE_MASK) 1081 - >> E1000_LTRV_SCALE_SHIFT))); 1078 + (1U << (E1000_LTRV_SCALE_FACTOR * 1079 + FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc))); 1082 1080 1083 1081 if (lat_enc_d > max_ltr_enc_d) 1084 1082 lat_enc = max_ltr_enc; ··· 2073 2075 { 2074 2076 u16 phy_data; 2075 2077 u32 strap = er32(STRAP); 2076 - u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2077 - E1000_STRAP_SMT_FREQ_SHIFT; 2078 + u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap); 2078 2079 s32 ret_val; 2079 2080 2080 2081 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; ··· 2559 2562 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2560 2563 (u16)(mac_reg & 0xFFFF)); 2561 2564 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2562 - (u16)((mac_reg & E1000_RAH_AV) 2563 - >> 16)); 2565 + FIELD_GET(E1000_RAH_AV, mac_reg)); 2564 2566 } 2565 2567 2566 2568 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); ··· 3201 3205 &nvm_dword); 3202 3206 if (ret_val) 3203 3207 return ret_val; 3204 - sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3208 + sig_byte = FIELD_GET(0xFF00, nvm_dword); 3205 3209 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3206 3210 E1000_ICH_NVM_SIG_VALUE) { 3207 3211 *bank = 0; ··· 3214 3218 &nvm_dword); 3215 3219 if (ret_val) 3216 3220 return ret_val; 3217 - sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3221 + sig_byte = FIELD_GET(0xFF00, nvm_dword); 3218 3222 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3219 3223 E1000_ICH_NVM_SIG_VALUE) { 3220 3224 *bank = 1;

+1 -1

drivers/net/ethernet/intel/e1000e/mac.c

··· 50 50 * for the device regardless of function swap state. 51 51 */ 52 52 reg = er32(STATUS); 53 - bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 53 + bus->func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg); 54 54 } 55 55 56 56 /**

+4 -7

drivers/net/ethernet/intel/e1000e/netdev.c

··· 1788 1788 adapter->corr_errors += 1789 1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1790 1790 adapter->uncorr_errors += 1791 - (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1792 - E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1791 + FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1793 1792 1794 1793 /* Do the reset outside of interrupt context */ 1795 1794 schedule_work(&adapter->reset_task); ··· 1867 1868 adapter->corr_errors += 1868 1869 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 1869 1870 adapter->uncorr_errors += 1870 - (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 1871 - E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 1871 + FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 1872 1872 1873 1873 /* Do the reset outside of interrupt context */ 1874 1874 schedule_work(&adapter->reset_task); ··· 5029 5031 adapter->corr_errors += 5030 5032 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; 5031 5033 adapter->uncorr_errors += 5032 - (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> 5033 - E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; 5034 + FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts); 5034 5035 } 5035 5036 } 5036 5037 ··· 6246 6249 phy_reg |= BM_RCTL_MPE; 6247 6250 phy_reg &= ~(BM_RCTL_MO_MASK); 6248 6251 if (mac_reg & E1000_RCTL_MO_3) 6249 - phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 6252 + phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg) 6250 6253 << BM_RCTL_MO_SHIFT); 6251 6254 if (mac_reg & E1000_RCTL_BAM) 6252 6255 phy_reg |= BM_RCTL_BAM;

+9 -15

drivers/net/ethernet/intel/e1000e/phy.c

··· 154 154 e_dbg("MDI Read PHY Reg Address %d Error\n", offset); 155 155 return -E1000_ERR_PHY; 156 156 } 157 - if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 157 + if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) { 158 158 e_dbg("MDI Read offset error - requested %d, returned %d\n", 159 - offset, 160 - (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 159 + offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic)); 161 160 return -E1000_ERR_PHY; 162 161 } 163 162 *data = (u16)mdic; ··· 166 167 */ 167 168 if (hw->mac.type == e1000_pch2lan) 168 169 udelay(100); 169 - 170 170 return 0; 171 171 } 172 172 ··· 216 218 e_dbg("MDI Write PHY Red Address %d Error\n", offset); 217 219 return -E1000_ERR_PHY; 218 220 } 219 - if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 221 + if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) { 220 222 e_dbg("MDI Write offset error - requested %d, returned %d\n", 221 - offset, 222 - (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 223 + offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic)); 223 224 return -E1000_ERR_PHY; 224 225 } 225 226 ··· 460 463 return ret_val; 461 464 } 462 465 463 - kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 464 - E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 466 + kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | 467 + E1000_KMRNCTRLSTA_REN; 465 468 ew32(KMRNCTRLSTA, kmrnctrlsta); 466 469 e1e_flush(); 467 470 ··· 533 536 return ret_val; 534 537 } 535 538 536 - kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 537 - E1000_KMRNCTRLSTA_OFFSET) | data; 539 + kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data; 538 540 ew32(KMRNCTRLSTA, kmrnctrlsta); 539 541 e1e_flush(); 540 542 ··· 1789 1793 if (ret_val) 1790 1794 return ret_val; 1791 1795 1792 - index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1793 - M88E1000_PSSR_CABLE_LENGTH_SHIFT); 1796 + index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data); 1794 1797 1795 1798 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 1796 1799 return -E1000_ERR_PHY; ··· 3229 3234 if (ret_val) 3230 3235 return ret_val; 3231 3236 3232 - length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3233 - I82577_DSTATUS_CABLE_LENGTH_SHIFT); 3237 + length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data); 3234 3238 3235 3239 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3236 3240 return -E1000_ERR_PHY;

+3 -4

drivers/net/ethernet/intel/fm10k/fm10k_pf.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2019 Intel Corporation. */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include "fm10k_pf.h" 5 6 #include "fm10k_vf.h" 6 7 ··· 866 865 * register is RO from the VF, so the PF must do this even in the 867 866 * case of notifying the VF of a new VID via the mailbox. 868 867 */ 869 - txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & 870 - FM10K_TXQCTL_VID_MASK; 868 + txqctl = FIELD_PREP(FM10K_TXQCTL_VID_MASK, vf_vid); 871 869 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | 872 870 FM10K_TXQCTL_VF | vf_idx; 873 871 ··· 1575 1575 if (func & FM10K_FAULT_FUNC_PF) 1576 1576 fault->func = 0; 1577 1577 else 1578 - fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> 1579 - FM10K_FAULT_FUNC_VF_SHIFT); 1578 + fault->func = 1 + FIELD_GET(FM10K_FAULT_FUNC_VF_MASK, func); 1580 1579 1581 1580 /* record fault type */ 1582 1581 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;

+5 -5

drivers/net/ethernet/intel/fm10k/fm10k_vf.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2019 Intel Corporation. */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include "fm10k_vf.h" 5 6 6 7 /** ··· 127 126 hw->mac.max_queues = i; 128 127 129 128 /* fetch default VLAN and ITR scale */ 130 - hw->mac.default_vid = (fm10k_read_reg(hw, FM10K_TXQCTL(0)) & 131 - FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT; 129 + hw->mac.default_vid = FIELD_GET(FM10K_TXQCTL_VID_MASK, 130 + fm10k_read_reg(hw, FM10K_TXQCTL(0))); 132 131 /* Read the ITR scale from TDLEN. See the definition of 133 132 * FM10K_TDLEN_ITR_SCALE_SHIFT for more information about how TDLEN is 134 133 * used here. 135 134 */ 136 - hw->mac.itr_scale = (fm10k_read_reg(hw, FM10K_TDLEN(0)) & 137 - FM10K_TDLEN_ITR_SCALE_MASK) >> 138 - FM10K_TDLEN_ITR_SCALE_SHIFT; 135 + hw->mac.itr_scale = FIELD_GET(FM10K_TDLEN_ITR_SCALE_MASK, 136 + fm10k_read_reg(hw, FM10K_TDLEN(0))); 139 137 140 138 return 0; 141 139

+58 -82

drivers/net/ethernet/intel/i40e/i40e_common.c

··· 2 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 3 4 4 #include <linux/avf/virtchnl.h> 5 + #include <linux/bitfield.h> 5 6 #include <linux/delay.h> 6 7 #include <linux/etherdevice.h> 7 8 #include <linux/pci.h> ··· 249 248 struct i40e_aqc_get_set_rss_lut *cmd_resp = 250 249 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 251 250 int status; 251 + u16 flags; 252 252 253 253 if (set) 254 254 i40e_fill_default_direct_cmd_desc(&desc, ··· 262 260 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 263 261 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 264 262 265 - cmd_resp->vsi_id = 266 - cpu_to_le16((u16)((vsi_id << 267 - I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 268 - I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 269 - cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 263 + vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 264 + FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1); 265 + cmd_resp->vsi_id = cpu_to_le16(vsi_id); 270 266 271 267 if (pf_lut) 272 - cmd_resp->flags |= cpu_to_le16((u16) 273 - ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 274 - I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 275 - I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 268 + flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 269 + I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 276 270 else 277 - cmd_resp->flags |= cpu_to_le16((u16) 278 - ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 279 - I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 280 - I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 271 + flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 272 + I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 281 273 274 + cmd_resp->flags = cpu_to_le16(flags); 282 275 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 283 276 284 277 return status; ··· 343 346 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 344 347 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 345 348 346 - cmd_resp->vsi_id = 347 - cpu_to_le16((u16)((vsi_id << 348 - I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 349 - I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 350 - cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 349 + vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 350 + FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1); 351 + cmd_resp->vsi_id = cpu_to_le16(vsi_id); 351 352 352 353 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 353 354 ··· 664 669 hw->phy.get_link_info = true; 665 670 666 671 /* Determine port number and PF number*/ 667 - port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 668 - >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 672 + port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK, 673 + rd32(hw, I40E_PFGEN_PORTNUM)); 669 674 hw->port = (u8)port; 670 - ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 671 - I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 675 + ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK, 676 + rd32(hw, I40E_GLPCI_CAPSUP)); 672 677 func_rid = rd32(hw, I40E_PF_FUNC_RID); 673 678 if (ari) 674 679 hw->pf_id = (u8)(func_rid & 0xff); ··· 986 991 * The grst delay value is in 100ms units, and we'll wait a 987 992 * couple counts longer to be sure we don't just miss the end. 988 993 */ 989 - grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 990 - I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 991 - I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 994 + grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK, 995 + rd32(hw, I40E_GLGEN_RSTCTL)); 992 996 993 997 /* It can take upto 15 secs for GRST steady state. 994 998 * Bump it to 16 secs max to be safe. ··· 1079 1085 1080 1086 /* get number of interrupts, queues, and VFs */ 1081 1087 val = rd32(hw, I40E_GLPCI_CNF2); 1082 - num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1083 - I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1084 - num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1085 - I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1088 + num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val); 1089 + num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val); 1086 1090 1087 1091 val = rd32(hw, I40E_PFLAN_QALLOC); 1088 - base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1089 - I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1090 - j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1091 - I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1092 + base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val); 1093 + j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val); 1092 1094 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) 1093 1095 num_queues = (j - base_queue) + 1; 1094 1096 else 1095 1097 num_queues = 0; 1096 1098 1097 1099 val = rd32(hw, I40E_PF_VT_PFALLOC); 1098 - i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1099 - I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1100 - j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1101 - I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1100 + i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val); 1101 + j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val); 1102 1102 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) 1103 1103 num_vfs = (j - i) + 1; 1104 1104 else ··· 1187 1199 !hw->func_caps.led[idx]) 1188 1200 return 0; 1189 1201 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1190 - port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1191 - I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1202 + port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val); 1192 1203 1193 1204 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1194 1205 * if it is not our port then ignore ··· 1231 1244 if (!gpio_val) 1232 1245 continue; 1233 1246 1234 - mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1235 - I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1247 + mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val); 1236 1248 break; 1237 1249 } 1238 1250 ··· 1274 1288 pin_func = I40E_PIN_FUNC_LED; 1275 1289 1276 1290 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1277 - gpio_val |= ((pin_func << 1278 - I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) & 1279 - I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK); 1291 + gpio_val |= 1292 + FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK, 1293 + pin_func); 1280 1294 } 1281 1295 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1282 1296 /* this & is a bit of paranoia, but serves as a range check */ 1283 - gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1284 - I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1297 + gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, 1298 + mode); 1285 1299 1286 1300 if (blink) 1287 1301 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); ··· 3500 3514 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3501 3515 3502 3516 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3503 - cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3504 - I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3517 + cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type); 3505 3518 3506 3519 desc.datalen = cpu_to_le16(buff_size); 3507 3520 ··· 4181 4196 4182 4197 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4183 4198 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4184 - fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4185 - >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4199 + fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val); 4186 4200 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4187 4201 return -EINVAL; 4188 4202 ··· 4217 4233 4218 4234 /* Program required PE hash buckets for the PF */ 4219 4235 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4220 - val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4221 - I40E_PFQF_CTL_0_PEHSIZE_MASK; 4236 + val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num); 4222 4237 /* Program required PE contexts for the PF */ 4223 4238 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4224 - val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4225 - I40E_PFQF_CTL_0_PEDSIZE_MASK; 4239 + val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num); 4226 4240 4227 4241 /* Program required FCoE hash buckets for the PF */ 4228 4242 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4229 - val |= ((u32)settings->fcoe_filt_num << 4230 - I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4231 - I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4243 + val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK, 4244 + settings->fcoe_filt_num); 4232 4245 /* Program required FCoE DDP contexts for the PF */ 4233 4246 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4234 - val |= ((u32)settings->fcoe_cntx_num << 4235 - I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4236 - I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4247 + val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK, 4248 + settings->fcoe_cntx_num); 4237 4249 4238 4250 /* Program Hash LUT size for the PF */ 4239 4251 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4240 4252 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4241 4253 hash_lut_size = 1; 4242 - val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4243 - I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4254 + val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size); 4244 4255 4245 4256 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4246 4257 if (settings->enable_fdir) ··· 4636 4657 "PHY: Can't write command to external PHY.\n"); 4637 4658 } else { 4638 4659 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4639 - *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4640 - I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4660 + *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4641 4661 } 4642 4662 4643 4663 return status; ··· 4745 4767 4746 4768 if (!status) { 4747 4769 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4748 - *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4749 - I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4770 + *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command); 4750 4771 } else { 4751 4772 i40e_debug(hw, I40E_DEBUG_PHY, 4752 4773 "PHY: Can't read register value from external PHY.\n"); ··· 5295 5318 u8 mdio_num, 5296 5319 struct i40e_aqc_phy_register_access *cmd) 5297 5320 { 5298 - if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) { 5299 - if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) 5300 - cmd->cmd_flags |= 5301 - I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 5302 - ((mdio_num << 5303 - I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) & 5304 - I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK); 5305 - else 5306 - i40e_debug(hw, I40E_DEBUG_PHY, 5307 - "MDIO I/F number selection not supported by current FW version.\n"); 5321 + if (!set_mdio || 5322 + cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL) 5323 + return; 5324 + 5325 + if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) { 5326 + cmd->cmd_flags |= 5327 + I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 5328 + FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK, 5329 + mdio_num); 5330 + } else { 5331 + i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n"); 5308 5332 } 5309 5333 } 5310 5334 ··· 5890 5912 u16 tnl_type; 5891 5913 u32 ti; 5892 5914 5893 - tnl_type = (le16_to_cpu(filters[i].element.flags) & 5894 - I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5895 - I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5915 + tnl_type = le16_get_bits(filters[i].element.flags, 5916 + I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5896 5917 5897 5918 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5898 5919 * one more byte further than normally used for Tenant ID in ··· 5983 6006 u16 tnl_type; 5984 6007 u32 ti; 5985 6008 5986 - tnl_type = (le16_to_cpu(filters[i].element.flags) & 5987 - I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5988 - I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 6009 + tnl_type = le16_get_bits(filters[i].element.flags, 6010 + I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK); 5989 6011 5990 6012 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5991 6013 * one more byte further than normally used for Tenant ID in

+110 -166

drivers/net/ethernet/intel/i40e/i40e_dcb.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 3 4 + #include <linux/bitfield.h> 5 + #include "i40e_adminq.h" 4 6 #include "i40e_alloc.h" 5 7 #include "i40e_dcb.h" 6 8 #include "i40e_prototype.h" ··· 22 20 return -EINVAL; 23 21 24 22 reg = rd32(hw, I40E_PRTDCB_GENS); 25 - *status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >> 26 - I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT); 23 + *status = FIELD_GET(I40E_PRTDCB_GENS_DCBX_STATUS_MASK, reg); 27 24 28 25 return 0; 29 26 } ··· 51 50 * |1bit | 1bit|3 bits|3bits| 52 51 */ 53 52 etscfg = &dcbcfg->etscfg; 54 - etscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >> 55 - I40E_IEEE_ETS_WILLING_SHIFT); 56 - etscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >> 57 - I40E_IEEE_ETS_CBS_SHIFT); 58 - etscfg->maxtcs = (u8)((buf[offset] & I40E_IEEE_ETS_MAXTC_MASK) >> 59 - I40E_IEEE_ETS_MAXTC_SHIFT); 53 + etscfg->willing = FIELD_GET(I40E_IEEE_ETS_WILLING_MASK, buf[offset]); 54 + etscfg->cbs = FIELD_GET(I40E_IEEE_ETS_CBS_MASK, buf[offset]); 55 + etscfg->maxtcs = FIELD_GET(I40E_IEEE_ETS_MAXTC_MASK, buf[offset]); 60 56 61 57 /* Move offset to Priority Assignment Table */ 62 58 offset++; ··· 67 69 * ----------------------------------------- 68 70 */ 69 71 for (i = 0; i < 4; i++) { 70 - priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >> 71 - I40E_IEEE_ETS_PRIO_1_SHIFT); 72 - etscfg->prioritytable[i * 2] = priority; 73 - priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >> 74 - I40E_IEEE_ETS_PRIO_0_SHIFT); 72 + priority = FIELD_GET(I40E_IEEE_ETS_PRIO_1_MASK, buf[offset]); 73 + etscfg->prioritytable[i * 2] = priority; 74 + priority = FIELD_GET(I40E_IEEE_ETS_PRIO_0_MASK, buf[offset]); 75 75 etscfg->prioritytable[i * 2 + 1] = priority; 76 76 offset++; 77 77 } ··· 120 124 * ----------------------------------------- 121 125 */ 122 126 for (i = 0; i < 4; i++) { 123 - priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >> 124 - I40E_IEEE_ETS_PRIO_1_SHIFT); 125 - dcbcfg->etsrec.prioritytable[i*2] = priority; 126 - priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >> 127 - I40E_IEEE_ETS_PRIO_0_SHIFT); 128 - dcbcfg->etsrec.prioritytable[i*2 + 1] = priority; 127 + priority = FIELD_GET(I40E_IEEE_ETS_PRIO_1_MASK, buf[offset]); 128 + dcbcfg->etsrec.prioritytable[i * 2] = priority; 129 + priority = FIELD_GET(I40E_IEEE_ETS_PRIO_0_MASK, buf[offset]); 130 + dcbcfg->etsrec.prioritytable[(i * 2) + 1] = priority; 129 131 offset++; 130 132 } 131 133 ··· 164 170 * ----------------------------------------- 165 171 * |1bit | 1bit|2 bits|4bits| 1 octet | 166 172 */ 167 - dcbcfg->pfc.willing = (u8)((buf[0] & I40E_IEEE_PFC_WILLING_MASK) >> 168 - I40E_IEEE_PFC_WILLING_SHIFT); 169 - dcbcfg->pfc.mbc = (u8)((buf[0] & I40E_IEEE_PFC_MBC_MASK) >> 170 - I40E_IEEE_PFC_MBC_SHIFT); 171 - dcbcfg->pfc.pfccap = (u8)((buf[0] & I40E_IEEE_PFC_CAP_MASK) >> 172 - I40E_IEEE_PFC_CAP_SHIFT); 173 + dcbcfg->pfc.willing = FIELD_GET(I40E_IEEE_PFC_WILLING_MASK, buf[0]); 174 + dcbcfg->pfc.mbc = FIELD_GET(I40E_IEEE_PFC_MBC_MASK, buf[0]); 175 + dcbcfg->pfc.pfccap = FIELD_GET(I40E_IEEE_PFC_CAP_MASK, buf[0]); 173 176 dcbcfg->pfc.pfcenable = buf[1]; 174 177 } 175 178 ··· 187 196 u8 *buf; 188 197 189 198 typelength = ntohs(tlv->typelength); 190 - length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 191 - I40E_LLDP_TLV_LEN_SHIFT); 199 + length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength); 192 200 buf = tlv->tlvinfo; 193 201 194 202 /* The App priority table starts 5 octets after TLV header */ ··· 205 215 * ----------------------------------------- 206 216 */ 207 217 while (offset < length) { 208 - dcbcfg->app[i].priority = (u8)((buf[offset] & 209 - I40E_IEEE_APP_PRIO_MASK) >> 210 - I40E_IEEE_APP_PRIO_SHIFT); 211 - dcbcfg->app[i].selector = (u8)((buf[offset] & 212 - I40E_IEEE_APP_SEL_MASK) >> 213 - I40E_IEEE_APP_SEL_SHIFT); 218 + dcbcfg->app[i].priority = FIELD_GET(I40E_IEEE_APP_PRIO_MASK, 219 + buf[offset]); 220 + dcbcfg->app[i].selector = FIELD_GET(I40E_IEEE_APP_SEL_MASK, 221 + buf[offset]); 214 222 dcbcfg->app[i].protocolid = (buf[offset + 1] << 0x8) | 215 223 buf[offset + 2]; 216 224 /* Move to next app */ ··· 236 248 u8 subtype; 237 249 238 250 ouisubtype = ntohl(tlv->ouisubtype); 239 - subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >> 240 - I40E_LLDP_TLV_SUBTYPE_SHIFT); 251 + subtype = FIELD_GET(I40E_LLDP_TLV_SUBTYPE_MASK, ouisubtype); 241 252 switch (subtype) { 242 253 case I40E_IEEE_SUBTYPE_ETS_CFG: 243 254 i40e_parse_ieee_etscfg_tlv(tlv, dcbcfg); ··· 286 299 * ----------------------------------------- 287 300 */ 288 301 for (i = 0; i < 4; i++) { 289 - priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >> 290 - I40E_CEE_PGID_PRIO_1_SHIFT); 291 - etscfg->prioritytable[i * 2] = priority; 292 - priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >> 293 - I40E_CEE_PGID_PRIO_0_SHIFT); 302 + priority = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK, buf[offset]); 303 + etscfg->prioritytable[i * 2] = priority; 304 + priority = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK, buf[offset]); 294 305 etscfg->prioritytable[i * 2 + 1] = priority; 295 306 offset++; 296 307 } ··· 345 360 u8 i; 346 361 347 362 typelength = ntohs(tlv->hdr.typelen); 348 - length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 349 - I40E_LLDP_TLV_LEN_SHIFT); 363 + length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength); 350 364 351 365 dcbcfg->numapps = length / sizeof(*app); 352 366 ··· 401 417 u32 ouisubtype; 402 418 403 419 ouisubtype = ntohl(tlv->ouisubtype); 404 - subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >> 405 - I40E_LLDP_TLV_SUBTYPE_SHIFT); 420 + subtype = FIELD_GET(I40E_LLDP_TLV_SUBTYPE_MASK, ouisubtype); 406 421 /* Return if not CEE DCBX */ 407 422 if (subtype != I40E_CEE_DCBX_TYPE) 408 423 return; 409 424 410 425 typelength = ntohs(tlv->typelength); 411 - tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 412 - I40E_LLDP_TLV_LEN_SHIFT); 426 + tlvlen = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength); 413 427 len = sizeof(tlv->typelength) + sizeof(ouisubtype) + 414 428 sizeof(struct i40e_cee_ctrl_tlv); 415 429 /* Return if no CEE DCBX Feature TLVs */ ··· 417 435 sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len); 418 436 while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) { 419 437 typelength = ntohs(sub_tlv->hdr.typelen); 420 - sublen = (u16)((typelength & 421 - I40E_LLDP_TLV_LEN_MASK) >> 422 - I40E_LLDP_TLV_LEN_SHIFT); 423 - subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >> 424 - I40E_LLDP_TLV_TYPE_SHIFT); 438 + sublen = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength); 439 + subtype = FIELD_GET(I40E_LLDP_TLV_TYPE_MASK, typelength); 425 440 switch (subtype) { 426 441 case I40E_CEE_SUBTYPE_PG_CFG: 427 442 i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg); ··· 455 476 u32 oui; 456 477 457 478 ouisubtype = ntohl(tlv->ouisubtype); 458 - oui = (u32)((ouisubtype & I40E_LLDP_TLV_OUI_MASK) >> 459 - I40E_LLDP_TLV_OUI_SHIFT); 479 + oui = FIELD_GET(I40E_LLDP_TLV_OUI_MASK, ouisubtype); 460 480 switch (oui) { 461 481 case I40E_IEEE_8021QAZ_OUI: 462 482 i40e_parse_ieee_tlv(tlv, dcbcfg); ··· 493 515 tlv = (struct i40e_lldp_org_tlv *)lldpmib; 494 516 while (1) { 495 517 typelength = ntohs(tlv->typelength); 496 - type = (u16)((typelength & I40E_LLDP_TLV_TYPE_MASK) >> 497 - I40E_LLDP_TLV_TYPE_SHIFT); 498 - length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 499 - I40E_LLDP_TLV_LEN_SHIFT); 518 + type = FIELD_GET(I40E_LLDP_TLV_TYPE_MASK, typelength); 519 + length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength); 500 520 offset += sizeof(typelength) + length; 501 521 502 522 /* END TLV or beyond LLDPDU size */ ··· 568 592 { 569 593 u16 status, tlv_status = le16_to_cpu(cee_cfg->tlv_status); 570 594 u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio); 571 - u8 i, tc, err; 595 + u8 i, err; 572 596 573 597 /* CEE PG data to ETS config */ 574 598 dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc; ··· 577 601 * from those in the CEE Priority Group sub-TLV. 578 602 */ 579 603 for (i = 0; i < 4; i++) { 580 - tc = (u8)((cee_cfg->oper_prio_tc[i] & 581 - I40E_CEE_PGID_PRIO_0_MASK) >> 582 - I40E_CEE_PGID_PRIO_0_SHIFT); 583 - dcbcfg->etscfg.prioritytable[i * 2] = tc; 584 - tc = (u8)((cee_cfg->oper_prio_tc[i] & 585 - I40E_CEE_PGID_PRIO_1_MASK) >> 586 - I40E_CEE_PGID_PRIO_1_SHIFT); 604 + u8 tc; 605 + 606 + tc = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK, 607 + cee_cfg->oper_prio_tc[i]); 608 + dcbcfg->etscfg.prioritytable[i * 2] = tc; 609 + tc = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK, 610 + cee_cfg->oper_prio_tc[i]); 587 611 dcbcfg->etscfg.prioritytable[i*2 + 1] = tc; 588 612 } 589 613 ··· 605 629 dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en; 606 630 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 607 631 608 - status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >> 609 - I40E_AQC_CEE_APP_STATUS_SHIFT; 632 + status = FIELD_GET(I40E_AQC_CEE_APP_STATUS_MASK, tlv_status); 610 633 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 611 634 /* Add APPs if Error is False */ 612 635 if (!err) { ··· 614 639 615 640 /* FCoE APP */ 616 641 dcbcfg->app[0].priority = 617 - (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >> 618 - I40E_AQC_CEE_APP_FCOE_SHIFT; 642 + FIELD_GET(I40E_AQC_CEE_APP_FCOE_MASK, app_prio); 619 643 dcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE; 620 644 dcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE; 621 645 622 646 /* iSCSI APP */ 623 647 dcbcfg->app[1].priority = 624 - (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >> 625 - I40E_AQC_CEE_APP_ISCSI_SHIFT; 648 + FIELD_GET(I40E_AQC_CEE_APP_ISCSI_MASK, app_prio); 626 649 dcbcfg->app[1].selector = I40E_APP_SEL_TCPIP; 627 650 dcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI; 628 651 629 652 /* FIP APP */ 630 653 dcbcfg->app[2].priority = 631 - (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >> 632 - I40E_AQC_CEE_APP_FIP_SHIFT; 654 + FIELD_GET(I40E_AQC_CEE_APP_FIP_MASK, app_prio); 633 655 dcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE; 634 656 dcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP; 635 657 } ··· 645 673 { 646 674 u32 status, tlv_status = le32_to_cpu(cee_cfg->tlv_status); 647 675 u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio); 648 - u8 i, tc, err, sync, oper; 676 + u8 i, err, sync, oper; 649 677 650 678 /* CEE PG data to ETS config */ 651 679 dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc; ··· 654 682 * from those in the CEE Priority Group sub-TLV. 655 683 */ 656 684 for (i = 0; i < 4; i++) { 657 - tc = (u8)((cee_cfg->oper_prio_tc[i] & 658 - I40E_CEE_PGID_PRIO_0_MASK) >> 659 - I40E_CEE_PGID_PRIO_0_SHIFT); 660 - dcbcfg->etscfg.prioritytable[i * 2] = tc; 661 - tc = (u8)((cee_cfg->oper_prio_tc[i] & 662 - I40E_CEE_PGID_PRIO_1_MASK) >> 663 - I40E_CEE_PGID_PRIO_1_SHIFT); 685 + u8 tc; 686 + 687 + tc = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK, 688 + cee_cfg->oper_prio_tc[i]); 689 + dcbcfg->etscfg.prioritytable[i * 2] = tc; 690 + tc = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK, 691 + cee_cfg->oper_prio_tc[i]); 664 692 dcbcfg->etscfg.prioritytable[i * 2 + 1] = tc; 665 693 } 666 694 ··· 683 711 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 684 712 685 713 i = 0; 686 - status = (tlv_status & I40E_AQC_CEE_FCOE_STATUS_MASK) >> 687 - I40E_AQC_CEE_FCOE_STATUS_SHIFT; 714 + status = FIELD_GET(I40E_AQC_CEE_FCOE_STATUS_MASK, tlv_status); 688 715 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 689 716 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0; 690 717 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0; ··· 691 720 if (!err && sync && oper) { 692 721 /* FCoE APP */ 693 722 dcbcfg->app[i].priority = 694 - (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >> 695 - I40E_AQC_CEE_APP_FCOE_SHIFT; 723 + FIELD_GET(I40E_AQC_CEE_APP_FCOE_MASK, app_prio); 696 724 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE; 697 725 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FCOE; 698 726 i++; 699 727 } 700 728 701 - status = (tlv_status & I40E_AQC_CEE_ISCSI_STATUS_MASK) >> 702 - I40E_AQC_CEE_ISCSI_STATUS_SHIFT; 729 + status = FIELD_GET(I40E_AQC_CEE_ISCSI_STATUS_MASK, tlv_status); 703 730 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 704 731 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0; 705 732 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0; ··· 705 736 if (!err && sync && oper) { 706 737 /* iSCSI APP */ 707 738 dcbcfg->app[i].priority = 708 - (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >> 709 - I40E_AQC_CEE_APP_ISCSI_SHIFT; 739 + FIELD_GET(I40E_AQC_CEE_APP_ISCSI_MASK, app_prio); 710 740 dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP; 711 741 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_ISCSI; 712 742 i++; 713 743 } 714 744 715 - status = (tlv_status & I40E_AQC_CEE_FIP_STATUS_MASK) >> 716 - I40E_AQC_CEE_FIP_STATUS_SHIFT; 745 + status = FIELD_GET(I40E_AQC_CEE_FIP_STATUS_MASK, tlv_status); 717 746 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 718 747 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0; 719 748 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0; ··· 719 752 if (!err && sync && oper) { 720 753 /* FIP APP */ 721 754 dcbcfg->app[i].priority = 722 - (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >> 723 - I40E_AQC_CEE_APP_FIP_SHIFT; 755 + FIELD_GET(I40E_AQC_CEE_APP_FIP_MASK, app_prio); 724 756 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE; 725 757 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FIP; 726 758 i++; ··· 1152 1186 selector = dcbcfg->app[i].selector & 0x7; 1153 1187 buf[offset] = (priority << I40E_IEEE_APP_PRIO_SHIFT) | selector; 1154 1188 buf[offset + 1] = (dcbcfg->app[i].protocolid >> 0x8) & 0xFF; 1155 - buf[offset + 2] = dcbcfg->app[i].protocolid & 0xFF; 1189 + buf[offset + 2] = dcbcfg->app[i].protocolid & 0xFF; 1156 1190 /* Move to next app */ 1157 1191 offset += 3; 1158 1192 i++; ··· 1248 1282 do { 1249 1283 i40e_add_dcb_tlv(tlv, dcbcfg, tlvid++); 1250 1284 typelength = ntohs(tlv->typelength); 1251 - length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 1252 - I40E_LLDP_TLV_LEN_SHIFT); 1285 + length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength); 1253 1286 if (length) 1254 1287 offset += length + I40E_IEEE_TLV_HEADER_LENGTH; 1255 1288 /* END TLV or beyond LLDPDU size */ ··· 1283 1318 u32 reg = rd32(hw, I40E_PRTDCB_RETSC); 1284 1319 1285 1320 reg &= ~I40E_PRTDCB_RETSC_ETS_MODE_MASK; 1286 - reg |= ((u32)ets_mode << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) & 1287 - I40E_PRTDCB_RETSC_ETS_MODE_MASK; 1321 + reg |= FIELD_PREP(I40E_PRTDCB_RETSC_ETS_MODE_MASK, ets_mode); 1288 1322 1289 1323 reg &= ~I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK; 1290 - reg |= ((u32)non_ets_mode << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) & 1291 - I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK; 1324 + reg |= FIELD_PREP(I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK, non_ets_mode); 1292 1325 1293 1326 reg &= ~I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK; 1294 - reg |= (max_exponent << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) & 1295 - I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK; 1327 + reg |= FIELD_PREP(I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK, max_exponent); 1296 1328 1297 1329 reg &= ~I40E_PRTDCB_RETSC_LLTC_MASK; 1298 - reg |= (lltc_map << I40E_PRTDCB_RETSC_LLTC_SHIFT) & 1299 - I40E_PRTDCB_RETSC_LLTC_MASK; 1330 + reg |= FIELD_PREP(I40E_PRTDCB_RETSC_LLTC_MASK, lltc_map); 1300 1331 wr32(hw, I40E_PRTDCB_RETSC, reg); 1301 1332 } 1302 1333 ··· 1347 1386 */ 1348 1387 reg = rd32(hw, I40E_PRT_SWR_PM_THR); 1349 1388 reg &= ~I40E_PRT_SWR_PM_THR_THRESHOLD_MASK; 1350 - reg |= (threshold << I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) & 1351 - I40E_PRT_SWR_PM_THR_THRESHOLD_MASK; 1389 + reg |= FIELD_PREP(I40E_PRT_SWR_PM_THR_THRESHOLD_MASK, threshold); 1352 1390 wr32(hw, I40E_PRT_SWR_PM_THR, reg); 1353 1391 1354 1392 reg = rd32(hw, I40E_PRTDCB_RPPMC); 1355 1393 reg &= ~I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK; 1356 - reg |= (fifo_size << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) & 1357 - I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK; 1394 + reg |= FIELD_PREP(I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK, fifo_size); 1358 1395 wr32(hw, I40E_PRTDCB_RPPMC, reg); 1359 1396 } 1360 1397 ··· 1394 1435 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK; 1395 1436 reg &= ~I40E_PRTDCB_MFLCN_RPFCE_MASK; 1396 1437 if (pfc_en) { 1397 - reg |= BIT(I40E_PRTDCB_MFLCN_RPFCM_SHIFT) & 1398 - I40E_PRTDCB_MFLCN_RPFCM_MASK; 1399 - reg |= ((u32)pfc_en << I40E_PRTDCB_MFLCN_RPFCE_SHIFT) & 1400 - I40E_PRTDCB_MFLCN_RPFCE_MASK; 1438 + reg |= FIELD_PREP(I40E_PRTDCB_MFLCN_RPFCM_MASK, 1); 1439 + reg |= FIELD_PREP(I40E_PRTDCB_MFLCN_RPFCE_MASK, 1440 + pfc_en); 1401 1441 } 1402 1442 wr32(hw, I40E_PRTDCB_MFLCN, reg); 1403 1443 1404 1444 reg = rd32(hw, I40E_PRTDCB_FCCFG); 1405 1445 reg &= ~I40E_PRTDCB_FCCFG_TFCE_MASK; 1406 1446 if (pfc_en) 1407 - reg |= (I40E_DCB_PFC_ENABLED << 1408 - I40E_PRTDCB_FCCFG_TFCE_SHIFT) & 1409 - I40E_PRTDCB_FCCFG_TFCE_MASK; 1447 + reg |= FIELD_PREP(I40E_PRTDCB_FCCFG_TFCE_MASK, 1448 + I40E_DCB_PFC_ENABLED); 1410 1449 wr32(hw, I40E_PRTDCB_FCCFG, reg); 1411 1450 1412 1451 /* FCTTV and FCRTV to be set by default */ ··· 1422 1465 1423 1466 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE); 1424 1467 reg &= ~I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK; 1425 - reg |= ((u32)pfc_en << 1426 - I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) & 1427 - I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK; 1468 + reg |= FIELD_PREP(I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK, 1469 + pfc_en); 1428 1470 wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, reg); 1429 1471 1430 1472 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE); 1431 1473 reg &= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK; 1432 - reg |= ((u32)pfc_en << 1433 - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) & 1434 - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK; 1474 + reg |= FIELD_PREP(I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK, 1475 + pfc_en); 1435 1476 wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, reg); 1436 1477 1437 1478 for (i = 0; i < I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX; i++) { 1438 1479 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i)); 1439 1480 reg &= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK; 1440 1481 if (pfc_en) { 1441 - reg |= ((u32)refresh_time << 1442 - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) & 1443 - I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK; 1482 + reg |= FIELD_PREP(I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK, 1483 + refresh_time); 1444 1484 } 1445 1485 wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i), reg); 1446 1486 } ··· 1449 1495 1450 1496 reg = rd32(hw, I40E_PRTDCB_TC2PFC); 1451 1497 reg &= ~I40E_PRTDCB_TC2PFC_TC2PFC_MASK; 1452 - reg |= ((u32)tc2pfc << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) & 1453 - I40E_PRTDCB_TC2PFC_TC2PFC_MASK; 1498 + reg |= FIELD_PREP(I40E_PRTDCB_TC2PFC_TC2PFC_MASK, tc2pfc); 1454 1499 wr32(hw, I40E_PRTDCB_TC2PFC, reg); 1455 1500 1456 1501 reg = rd32(hw, I40E_PRTDCB_RUP); 1457 1502 reg &= ~I40E_PRTDCB_RUP_NOVLANUP_MASK; 1458 - reg |= ((u32)first_pfc_prio << I40E_PRTDCB_RUP_NOVLANUP_SHIFT) & 1459 - I40E_PRTDCB_RUP_NOVLANUP_MASK; 1503 + reg |= FIELD_PREP(I40E_PRTDCB_RUP_NOVLANUP_MASK, first_pfc_prio); 1460 1504 wr32(hw, I40E_PRTDCB_RUP, reg); 1461 1505 1462 1506 reg = rd32(hw, I40E_PRTDCB_TDPMC); ··· 1486 1534 u32 reg = rd32(hw, I40E_PRTDCB_GENC); 1487 1535 1488 1536 reg &= ~I40E_PRTDCB_GENC_NUMTC_MASK; 1489 - reg |= ((u32)num_tc << I40E_PRTDCB_GENC_NUMTC_SHIFT) & 1490 - I40E_PRTDCB_GENC_NUMTC_MASK; 1537 + reg |= FIELD_PREP(I40E_PRTDCB_GENC_NUMTC_MASK, num_tc); 1491 1538 wr32(hw, I40E_PRTDCB_GENC, reg); 1492 1539 } 1493 1540 ··· 1500 1549 { 1501 1550 u32 reg = rd32(hw, I40E_PRTDCB_GENC); 1502 1551 1503 - return (u8)((reg & I40E_PRTDCB_GENC_NUMTC_MASK) >> 1504 - I40E_PRTDCB_GENC_NUMTC_SHIFT); 1552 + return FIELD_GET(I40E_PRTDCB_GENC_NUMTC_MASK, reg); 1505 1553 } 1506 1554 1507 1555 /** ··· 1524 1574 reg &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK | 1525 1575 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK | 1526 1576 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT); 1527 - reg |= ((u32)bw_share[i] << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) & 1528 - I40E_PRTDCB_RETSTCC_BWSHARE_MASK; 1529 - reg |= ((u32)mode[i] << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) & 1530 - I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK; 1531 - reg |= ((u32)prio_type[i] << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) & 1532 - I40E_PRTDCB_RETSTCC_ETSTC_MASK; 1577 + reg |= FIELD_PREP(I40E_PRTDCB_RETSTCC_BWSHARE_MASK, 1578 + bw_share[i]); 1579 + reg |= FIELD_PREP(I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK, 1580 + mode[i]); 1581 + reg |= FIELD_PREP(I40E_PRTDCB_RETSTCC_ETSTC_MASK, 1582 + prio_type[i]); 1533 1583 wr32(hw, I40E_PRTDCB_RETSTCC(i), reg); 1534 1584 } 1535 1585 } ··· 1669 1719 if (new_val < old_val) { 1670 1720 reg = rd32(hw, I40E_PRTRPB_SLW); 1671 1721 reg &= ~I40E_PRTRPB_SLW_SLW_MASK; 1672 - reg |= (new_val << I40E_PRTRPB_SLW_SLW_SHIFT) & 1673 - I40E_PRTRPB_SLW_SLW_MASK; 1722 + reg |= FIELD_PREP(I40E_PRTRPB_SLW_SLW_MASK, new_val); 1674 1723 wr32(hw, I40E_PRTRPB_SLW, reg); 1675 1724 } 1676 1725 ··· 1682 1733 if (new_val < old_val) { 1683 1734 reg = rd32(hw, I40E_PRTRPB_SLT(i)); 1684 1735 reg &= ~I40E_PRTRPB_SLT_SLT_TCN_MASK; 1685 - reg |= (new_val << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) & 1686 - I40E_PRTRPB_SLT_SLT_TCN_MASK; 1736 + reg |= FIELD_PREP(I40E_PRTRPB_SLT_SLT_TCN_MASK, 1737 + new_val); 1687 1738 wr32(hw, I40E_PRTRPB_SLT(i), reg); 1688 1739 } 1689 1740 ··· 1692 1743 if (new_val < old_val) { 1693 1744 reg = rd32(hw, I40E_PRTRPB_DLW(i)); 1694 1745 reg &= ~I40E_PRTRPB_DLW_DLW_TCN_MASK; 1695 - reg |= (new_val << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) & 1696 - I40E_PRTRPB_DLW_DLW_TCN_MASK; 1746 + reg |= FIELD_PREP(I40E_PRTRPB_DLW_DLW_TCN_MASK, 1747 + new_val); 1697 1748 wr32(hw, I40E_PRTRPB_DLW(i), reg); 1698 1749 } 1699 1750 } ··· 1704 1755 if (new_val < old_val) { 1705 1756 reg = rd32(hw, I40E_PRTRPB_SHW); 1706 1757 reg &= ~I40E_PRTRPB_SHW_SHW_MASK; 1707 - reg |= (new_val << I40E_PRTRPB_SHW_SHW_SHIFT) & 1708 - I40E_PRTRPB_SHW_SHW_MASK; 1758 + reg |= FIELD_PREP(I40E_PRTRPB_SHW_SHW_MASK, new_val); 1709 1759 wr32(hw, I40E_PRTRPB_SHW, reg); 1710 1760 } 1711 1761 ··· 1717 1769 if (new_val < old_val) { 1718 1770 reg = rd32(hw, I40E_PRTRPB_SHT(i)); 1719 1771 reg &= ~I40E_PRTRPB_SHT_SHT_TCN_MASK; 1720 - reg |= (new_val << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) & 1721 - I40E_PRTRPB_SHT_SHT_TCN_MASK; 1772 + reg |= FIELD_PREP(I40E_PRTRPB_SHT_SHT_TCN_MASK, 1773 + new_val); 1722 1774 wr32(hw, I40E_PRTRPB_SHT(i), reg); 1723 1775 } 1724 1776 ··· 1727 1779 if (new_val < old_val) { 1728 1780 reg = rd32(hw, I40E_PRTRPB_DHW(i)); 1729 1781 reg &= ~I40E_PRTRPB_DHW_DHW_TCN_MASK; 1730 - reg |= (new_val << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) & 1731 - I40E_PRTRPB_DHW_DHW_TCN_MASK; 1782 + reg |= FIELD_PREP(I40E_PRTRPB_DHW_DHW_TCN_MASK, 1783 + new_val); 1732 1784 wr32(hw, I40E_PRTRPB_DHW(i), reg); 1733 1785 } 1734 1786 } ··· 1738 1790 new_val = new_pb_cfg->tc_pool_size[i]; 1739 1791 reg = rd32(hw, I40E_PRTRPB_DPS(i)); 1740 1792 reg &= ~I40E_PRTRPB_DPS_DPS_TCN_MASK; 1741 - reg |= (new_val << I40E_PRTRPB_DPS_DPS_TCN_SHIFT) & 1742 - I40E_PRTRPB_DPS_DPS_TCN_MASK; 1793 + reg |= FIELD_PREP(I40E_PRTRPB_DPS_DPS_TCN_MASK, new_val); 1743 1794 wr32(hw, I40E_PRTRPB_DPS(i), reg); 1744 1795 } 1745 1796 ··· 1746 1799 new_val = new_pb_cfg->shared_pool_size; 1747 1800 reg = rd32(hw, I40E_PRTRPB_SPS); 1748 1801 reg &= ~I40E_PRTRPB_SPS_SPS_MASK; 1749 - reg |= (new_val << I40E_PRTRPB_SPS_SPS_SHIFT) & 1750 - I40E_PRTRPB_SPS_SPS_MASK; 1802 + reg |= FIELD_PREP(I40E_PRTRPB_SPS_SPS_MASK, new_val); 1751 1803 wr32(hw, I40E_PRTRPB_SPS, reg); 1752 1804 1753 1805 /* Program the shared pool low water mark per port if increasing */ ··· 1755 1809 if (new_val > old_val) { 1756 1810 reg = rd32(hw, I40E_PRTRPB_SLW); 1757 1811 reg &= ~I40E_PRTRPB_SLW_SLW_MASK; 1758 - reg |= (new_val << I40E_PRTRPB_SLW_SLW_SHIFT) & 1759 - I40E_PRTRPB_SLW_SLW_MASK; 1812 + reg |= FIELD_PREP(I40E_PRTRPB_SLW_SLW_MASK, new_val); 1760 1813 wr32(hw, I40E_PRTRPB_SLW, reg); 1761 1814 } 1762 1815 ··· 1768 1823 if (new_val > old_val) { 1769 1824 reg = rd32(hw, I40E_PRTRPB_SLT(i)); 1770 1825 reg &= ~I40E_PRTRPB_SLT_SLT_TCN_MASK; 1771 - reg |= (new_val << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) & 1772 - I40E_PRTRPB_SLT_SLT_TCN_MASK; 1826 + reg |= FIELD_PREP(I40E_PRTRPB_SLT_SLT_TCN_MASK, 1827 + new_val); 1773 1828 wr32(hw, I40E_PRTRPB_SLT(i), reg); 1774 1829 } 1775 1830 ··· 1778 1833 if (new_val > old_val) { 1779 1834 reg = rd32(hw, I40E_PRTRPB_DLW(i)); 1780 1835 reg &= ~I40E_PRTRPB_DLW_DLW_TCN_MASK; 1781 - reg |= (new_val << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) & 1782 - I40E_PRTRPB_DLW_DLW_TCN_MASK; 1836 + reg |= FIELD_PREP(I40E_PRTRPB_DLW_DLW_TCN_MASK, 1837 + new_val); 1783 1838 wr32(hw, I40E_PRTRPB_DLW(i), reg); 1784 1839 } 1785 1840 } ··· 1790 1845 if (new_val > old_val) { 1791 1846 reg = rd32(hw, I40E_PRTRPB_SHW); 1792 1847 reg &= ~I40E_PRTRPB_SHW_SHW_MASK; 1793 - reg |= (new_val << I40E_PRTRPB_SHW_SHW_SHIFT) & 1794 - I40E_PRTRPB_SHW_SHW_MASK; 1848 + reg |= FIELD_PREP(I40E_PRTRPB_SHW_SHW_MASK, new_val); 1795 1849 wr32(hw, I40E_PRTRPB_SHW, reg); 1796 1850 } 1797 1851 ··· 1803 1859 if (new_val > old_val) { 1804 1860 reg = rd32(hw, I40E_PRTRPB_SHT(i)); 1805 1861 reg &= ~I40E_PRTRPB_SHT_SHT_TCN_MASK; 1806 - reg |= (new_val << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) & 1807 - I40E_PRTRPB_SHT_SHT_TCN_MASK; 1862 + reg |= FIELD_PREP(I40E_PRTRPB_SHT_SHT_TCN_MASK, 1863 + new_val); 1808 1864 wr32(hw, I40E_PRTRPB_SHT(i), reg); 1809 1865 } 1810 1866 ··· 1813 1869 if (new_val > old_val) { 1814 1870 reg = rd32(hw, I40E_PRTRPB_DHW(i)); 1815 1871 reg &= ~I40E_PRTRPB_DHW_DHW_TCN_MASK; 1816 - reg |= (new_val << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) & 1817 - I40E_PRTRPB_DHW_DHW_TCN_MASK; 1872 + reg |= FIELD_PREP(I40E_PRTRPB_DHW_DHW_TCN_MASK, 1873 + new_val); 1818 1874 wr32(hw, I40E_PRTRPB_DHW(i), reg); 1819 1875 } 1820 1876 }

+1 -2

drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c

··· 21 21 u32 val; 22 22 23 23 val = rd32(hw, I40E_PRTDCB_GENC); 24 - *delay = (u16)((val & I40E_PRTDCB_GENC_PFCLDA_MASK) >> 25 - I40E_PRTDCB_GENC_PFCLDA_SHIFT); 24 + *delay = FIELD_GET(I40E_PRTDCB_GENC_PFCLDA_MASK, val); 26 25 } 27 26 28 27 /**

+2 -2

drivers/net/ethernet/intel/i40e/i40e_ddp.c

··· 81 81 static bool i40e_ddp_profiles_overlap(struct i40e_profile_info *new, 82 82 struct i40e_profile_info *old) 83 83 { 84 - unsigned int group_id_old = (u8)((old->track_id & 0x00FF0000) >> 16); 85 - unsigned int group_id_new = (u8)((new->track_id & 0x00FF0000) >> 16); 84 + unsigned int group_id_old = FIELD_GET(0x00FF0000, old->track_id); 85 + unsigned int group_id_new = FIELD_GET(0x00FF0000, new->track_id); 86 86 87 87 /* 0x00 group must be only the first */ 88 88 if (group_id_new == 0)

+3 -4

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

··· 1952 1952 val = X722_EEPROM_SCOPE_LIMIT + 1; 1953 1953 return val; 1954 1954 } 1955 - val = (rd32(hw, I40E_GLPCI_LBARCTRL) 1956 - & I40E_GLPCI_LBARCTRL_FL_SIZE_MASK) 1957 - >> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT; 1955 + val = FIELD_GET(I40E_GLPCI_LBARCTRL_FL_SIZE_MASK, 1956 + rd32(hw, I40E_GLPCI_LBARCTRL)); 1958 1957 /* register returns value in power of 2, 64Kbyte chunks. */ 1959 1958 val = (64 * 1024) * BIT(val); 1960 1959 return val; ··· 3283 3284 } else if (valid) { 3284 3285 data->flex_word = value & I40E_USERDEF_FLEX_WORD; 3285 3286 data->flex_offset = 3286 - (value & I40E_USERDEF_FLEX_OFFSET) >> 16; 3287 + FIELD_GET(I40E_USERDEF_FLEX_OFFSET, value); 3287 3288 data->flex_filter = true; 3288 3289 } 3289 3290

+35 -50

drivers/net/ethernet/intel/i40e/i40e_main.c

··· 1197 1197 1198 1198 val = rd32(hw, I40E_PRTPM_EEE_STAT); 1199 1199 nsd->tx_lpi_status = 1200 - (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> 1201 - I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; 1200 + FIELD_GET(I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK, val); 1202 1201 nsd->rx_lpi_status = 1203 - (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> 1204 - I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; 1202 + FIELD_GET(I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK, val); 1205 1203 i40e_stat_update32(hw, I40E_PRTPM_TLPIC, 1206 1204 pf->stat_offsets_loaded, 1207 1205 &osd->tx_lpi_count, &nsd->tx_lpi_count); ··· 3534 3536 else 3535 3537 return -EINVAL; 3536 3538 3537 - qtx_ctl |= (ring->ch->vsi_number << 3538 - I40E_QTX_CTL_VFVM_INDX_SHIFT) & 3539 - I40E_QTX_CTL_VFVM_INDX_MASK; 3539 + qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK, 3540 + ring->ch->vsi_number); 3540 3541 } else { 3541 3542 if (vsi->type == I40E_VSI_VMDQ2) { 3542 3543 qtx_ctl = I40E_QTX_CTL_VM_QUEUE; 3543 - qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & 3544 - I40E_QTX_CTL_VFVM_INDX_MASK; 3544 + qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK, 3545 + vsi->id); 3545 3546 } else { 3546 3547 qtx_ctl = I40E_QTX_CTL_PF_QUEUE; 3547 3548 } 3548 3549 } 3549 3550 3550 - qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 3551 - I40E_QTX_CTL_PF_INDX_MASK); 3551 + qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_PF_INDX_MASK, hw->pf_id); 3552 3552 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); 3553 3553 i40e_flush(hw); 3554 3554 ··· 4338 4342 set_bit(__I40E_RESET_INTR_RECEIVED, pf->state); 4339 4343 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; 4340 4344 val = rd32(hw, I40E_GLGEN_RSTAT); 4341 - val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) 4342 - >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; 4345 + val = FIELD_GET(I40E_GLGEN_RSTAT_RESET_TYPE_MASK, val); 4343 4346 if (val == I40E_RESET_CORER) { 4344 4347 pf->corer_count++; 4345 4348 } else if (val == I40E_RESET_GLOBR) { ··· 5000 5005 * next_q field of the registers. 5001 5006 */ 5002 5007 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); 5003 - qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) 5004 - >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; 5008 + qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK, 5009 + val); 5005 5010 val |= I40E_QUEUE_END_OF_LIST 5006 5011 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; 5007 5012 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); ··· 5023 5028 5024 5029 val = rd32(hw, I40E_QINT_TQCTL(qp)); 5025 5030 5026 - next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) 5027 - >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; 5031 + next = FIELD_GET(I40E_QINT_TQCTL_NEXTQ_INDX_MASK, 5032 + val); 5028 5033 5029 5034 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | 5030 5035 I40E_QINT_TQCTL_MSIX0_INDX_MASK | ··· 5042 5047 free_irq(pf->pdev->irq, pf); 5043 5048 5044 5049 val = rd32(hw, I40E_PFINT_LNKLST0); 5045 - qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) 5046 - >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; 5050 + qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK, val); 5047 5051 val |= I40E_QUEUE_END_OF_LIST 5048 5052 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 5049 5053 wr32(hw, I40E_PFINT_LNKLST0, val); ··· 9545 9551 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", 9546 9552 queue, qtx_ctl); 9547 9553 9554 + if (FIELD_GET(I40E_QTX_CTL_PFVF_Q_MASK, qtx_ctl) != 9555 + I40E_QTX_CTL_VF_QUEUE) 9556 + return; 9557 + 9548 9558 /* Queue belongs to VF, find the VF and issue VF reset */ 9549 - if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) 9550 - >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { 9551 - vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) 9552 - >> I40E_QTX_CTL_VFVM_INDX_SHIFT); 9553 - vf_id -= hw->func_caps.vf_base_id; 9554 - vf = &pf->vf[vf_id]; 9555 - i40e_vc_notify_vf_reset(vf); 9556 - /* Allow VF to process pending reset notification */ 9557 - msleep(20); 9558 - i40e_reset_vf(vf, false); 9559 - } 9559 + vf_id = FIELD_GET(I40E_QTX_CTL_VFVM_INDX_MASK, qtx_ctl); 9560 + vf_id -= hw->func_caps.vf_base_id; 9561 + vf = &pf->vf[vf_id]; 9562 + i40e_vc_notify_vf_reset(vf); 9563 + /* Allow VF to process pending reset notification */ 9564 + msleep(20); 9565 + i40e_reset_vf(vf, false); 9560 9566 } 9561 9567 9562 9568 /** ··· 9582 9588 9583 9589 val = rd32(&pf->hw, I40E_PFQF_FDSTAT); 9584 9590 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + 9585 - ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> 9586 - I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); 9591 + FIELD_GET(I40E_PFQF_FDSTAT_BEST_CNT_MASK, val); 9587 9592 return fcnt_prog; 9588 9593 } 9589 9594 ··· 9596 9603 9597 9604 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); 9598 9605 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + 9599 - ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> 9600 - I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); 9606 + FIELD_GET(I40E_GLQF_FDCNT_0_BESTCNT_MASK, val); 9601 9607 return fcnt_prog; 9602 9608 } 9603 9609 ··· 11178 11186 /* find what triggered the MDD event */ 11179 11187 reg = rd32(hw, I40E_GL_MDET_TX); 11180 11188 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 11181 - u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 11182 - I40E_GL_MDET_TX_PF_NUM_SHIFT; 11183 - u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> 11184 - I40E_GL_MDET_TX_VF_NUM_SHIFT; 11185 - u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 11186 - I40E_GL_MDET_TX_EVENT_SHIFT; 11187 - u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 11188 - I40E_GL_MDET_TX_QUEUE_SHIFT) - 11189 + u8 pf_num = FIELD_GET(I40E_GL_MDET_TX_PF_NUM_MASK, reg); 11190 + u16 vf_num = FIELD_GET(I40E_GL_MDET_TX_VF_NUM_MASK, reg); 11191 + u8 event = FIELD_GET(I40E_GL_MDET_TX_EVENT_MASK, reg); 11192 + u16 queue = FIELD_GET(I40E_GL_MDET_TX_QUEUE_MASK, reg) - 11189 11193 pf->hw.func_caps.base_queue; 11190 11194 if (netif_msg_tx_err(pf)) 11191 11195 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", ··· 11191 11203 } 11192 11204 reg = rd32(hw, I40E_GL_MDET_RX); 11193 11205 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 11194 - u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 11195 - I40E_GL_MDET_RX_FUNCTION_SHIFT; 11196 - u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 11197 - I40E_GL_MDET_RX_EVENT_SHIFT; 11198 - u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 11199 - I40E_GL_MDET_RX_QUEUE_SHIFT) - 11206 + u8 func = FIELD_GET(I40E_GL_MDET_RX_FUNCTION_MASK, reg); 11207 + u8 event = FIELD_GET(I40E_GL_MDET_RX_EVENT_MASK, reg); 11208 + u16 queue = FIELD_GET(I40E_GL_MDET_RX_QUEUE_MASK, reg) - 11200 11209 pf->hw.func_caps.base_queue; 11201 11210 if (netif_msg_rx_err(pf)) 11202 11211 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", ··· 16157 16172 16158 16173 /* make sure the MFS hasn't been set lower than the default */ 16159 16174 #define MAX_FRAME_SIZE_DEFAULT 0x2600 16160 - val = (rd32(&pf->hw, I40E_PRTGL_SAH) & 16161 - I40E_PRTGL_SAH_MFS_MASK) >> I40E_PRTGL_SAH_MFS_SHIFT; 16175 + val = FIELD_GET(I40E_PRTGL_SAH_MFS_MASK, 16176 + rd32(&pf->hw, I40E_PRTGL_SAH)); 16162 16177 if (val < MAX_FRAME_SIZE_DEFAULT) 16163 16178 dev_warn(&pdev->dev, "MFS for port %x has been set below the default: %x\n", 16164 16179 pf->hw.port, val);

+6 -8

drivers/net/ethernet/intel/i40e/i40e_nvm.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include <linux/delay.h> 5 6 #include "i40e_alloc.h" 6 7 #include "i40e_prototype.h" ··· 27 26 * as the blank mode may be used in the factory line. 28 27 */ 29 28 gens = rd32(hw, I40E_GLNVM_GENS); 30 - sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> 31 - I40E_GLNVM_GENS_SR_SIZE_SHIFT); 29 + sr_size = FIELD_GET(I40E_GLNVM_GENS_SR_SIZE_MASK, gens); 32 30 /* Switching to words (sr_size contains power of 2KB) */ 33 31 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; 34 32 ··· 193 193 ret_code = i40e_poll_sr_srctl_done_bit(hw); 194 194 if (!ret_code) { 195 195 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); 196 - *data = (u16)((sr_reg & 197 - I40E_GLNVM_SRDATA_RDDATA_MASK) 198 - >> I40E_GLNVM_SRDATA_RDDATA_SHIFT); 196 + *data = FIELD_GET(I40E_GLNVM_SRDATA_RDDATA_MASK, 197 + sr_reg); 199 198 } 200 199 } 201 200 if (ret_code) ··· 770 771 } 771 772 static inline u8 i40e_nvmupd_get_transaction(u32 val) 772 773 { 773 - return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); 774 + return FIELD_GET(I40E_NVM_TRANS_MASK, val); 774 775 } 775 776 776 777 static inline u8 i40e_nvmupd_get_preservation_flags(u32 val) 777 778 { 778 - return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >> 779 - I40E_NVM_PRESERVATION_FLAGS_SHIFT); 779 + return FIELD_GET(I40E_NVM_PRESERVATION_FLAGS_MASK, val); 780 780 } 781 781 782 782 static const char * const i40e_nvm_update_state_str[] = {

+2 -2

drivers/net/ethernet/intel/i40e/i40e_ptp.c

··· 1480 1480 /* Only one PF is assigned to control 1588 logic per port. Do not 1481 1481 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 1482 1482 */ 1483 - pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 1484 - I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 1483 + pf_id = FIELD_GET(I40E_PRTTSYN_CTL0_PF_ID_MASK, 1484 + rd32(hw, I40E_PRTTSYN_CTL0)); 1485 1485 if (hw->pf_id != pf_id) { 1486 1486 clear_bit(I40E_FLAG_PTP_ENA, pf->flags); 1487 1487 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",

+27 -43

drivers/net/ethernet/intel/i40e/i40e_txrx.c

··· 33 33 i++; 34 34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 35 35 36 - flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & 37 - (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); 36 + flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata->q_index); 38 37 39 - flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & 40 - (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); 38 + flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_FLEXOFF_MASK, 39 + fdata->flex_off); 41 40 42 - flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & 43 - (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 41 + flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata->pctype); 44 42 45 43 /* Use LAN VSI Id if not programmed by user */ 46 - flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & 47 - ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << 48 - I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); 44 + flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_DEST_VSI_MASK, 45 + fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id); 49 46 50 47 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 51 48 ··· 52 55 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 53 56 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 54 57 55 - dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & 56 - (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); 58 + dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_DEST_MASK, fdata->dest_ctl); 57 59 58 - dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & 59 - (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); 60 + dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_FD_STATUS_MASK, 61 + fdata->fd_status); 60 62 61 63 if (fdata->cnt_index) { 62 64 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 63 - dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & 64 - ((u32)fdata->cnt_index << 65 - I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); 65 + dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 66 + fdata->cnt_index); 66 67 } 67 68 68 69 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); ··· 686 691 u32 error; 687 692 688 693 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw; 689 - error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 690 - I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 694 + error = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK, qword1); 691 695 692 696 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 693 697 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id); ··· 1397 1403 { 1398 1404 u8 id; 1399 1405 1400 - id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 1401 - I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 1406 + id = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK, qword1); 1402 1407 1403 1408 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 1404 1409 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id); ··· 1757 1764 u64 qword; 1758 1765 1759 1766 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1760 - ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; 1761 - rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1762 - I40E_RXD_QW1_ERROR_SHIFT; 1763 - rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1764 - I40E_RXD_QW1_STATUS_SHIFT; 1767 + ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword); 1768 + rx_error = FIELD_GET(I40E_RXD_QW1_ERROR_MASK, qword); 1769 + rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword); 1765 1770 decoded = decode_rx_desc_ptype(ptype); 1766 1771 1767 1772 skb->ip_summed = CHECKSUM_NONE; ··· 1892 1901 union i40e_rx_desc *rx_desc, struct sk_buff *skb) 1893 1902 { 1894 1903 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1895 - u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1896 - I40E_RXD_QW1_STATUS_SHIFT; 1904 + u32 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword); 1897 1905 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; 1898 - u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1899 - I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; 1900 - u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1901 - I40E_RXD_QW1_PTYPE_SHIFT; 1906 + u32 tsyn = FIELD_GET(I40E_RXD_QW1_STATUS_TSYNINDX_MASK, rx_status); 1907 + u8 rx_ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword); 1902 1908 1903 1909 if (unlikely(tsynvalid)) 1904 1910 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); ··· 2542 2554 continue; 2543 2555 } 2544 2556 2545 - size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 2546 - I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 2557 + size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword); 2547 2558 if (!size) 2548 2559 break; 2549 2560 ··· 2946 2959 i++; 2947 2960 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2948 2961 2949 - flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2950 - I40E_TXD_FLTR_QW0_QINDEX_MASK; 2962 + flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, 2963 + tx_ring->queue_index); 2951 2964 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2952 2965 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2953 2966 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : ··· 2973 2986 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2974 2987 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2975 2988 dtype_cmd |= 2976 - ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2977 - I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2978 - I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2989 + FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 2990 + I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)); 2979 2991 else 2980 2992 dtype_cmd |= 2981 - ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2982 - I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2983 - I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2993 + FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK, 2994 + I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)); 2984 2995 2985 2996 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) 2986 2997 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; ··· 3586 3601 3587 3602 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 3588 3603 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 3589 - td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 3590 - I40E_TX_FLAGS_VLAN_SHIFT; 3604 + td_tag = FIELD_GET(I40E_TX_FLAGS_VLAN_MASK, tx_flags); 3591 3605 } 3592 3606 3593 3607 first->tx_flags = tx_flags;

+13 -16

drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c

··· 474 474 */ 475 475 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx; 476 476 reg = rd32(hw, I40E_VPINT_CEQCTL(reg_idx)); 477 - next_q_index = (reg & I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK) 478 - >> I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT; 479 - next_q_type = (reg & I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK) 480 - >> I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT; 477 + next_q_index = FIELD_GET(I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK, 478 + reg); 479 + next_q_type = FIELD_GET(I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK, 480 + reg); 481 481 482 482 reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1); 483 483 reg = (next_q_index & ··· 555 555 * queue on top. Also link it with the new queue in CEQCTL. 556 556 */ 557 557 reg = rd32(hw, I40E_VPINT_LNKLSTN(reg_idx)); 558 - next_q_idx = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) >> 559 - I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT); 560 - next_q_type = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK) >> 561 - I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT); 558 + next_q_idx = FIELD_GET(I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK, 559 + reg); 560 + next_q_type = FIELD_GET(I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK, 561 + reg); 562 562 563 563 if (qv_info->ceq_idx != I40E_QUEUE_INVALID_IDX) { 564 564 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx; ··· 659 659 660 660 /* associate this queue with the PCI VF function */ 661 661 qtx_ctl = I40E_QTX_CTL_VF_QUEUE; 662 - qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) 663 - & I40E_QTX_CTL_PF_INDX_MASK); 664 - qtx_ctl |= (((vf->vf_id + hw->func_caps.vf_base_id) 665 - << I40E_QTX_CTL_VFVM_INDX_SHIFT) 666 - & I40E_QTX_CTL_VFVM_INDX_MASK); 662 + qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_PF_INDX_MASK, hw->pf_id); 663 + qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK, 664 + vf->vf_id + hw->func_caps.vf_base_id); 667 665 wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl); 668 666 i40e_flush(hw); 669 667 ··· 4673 4675 4674 4676 ivi->max_tx_rate = vf->tx_rate; 4675 4677 ivi->min_tx_rate = 0; 4676 - ivi->vlan = le16_to_cpu(vsi->info.pvid) & I40E_VLAN_MASK; 4677 - ivi->qos = (le16_to_cpu(vsi->info.pvid) & I40E_PRIORITY_MASK) >> 4678 - I40E_VLAN_PRIORITY_SHIFT; 4678 + ivi->vlan = le16_get_bits(vsi->info.pvid, I40E_VLAN_MASK); 4679 + ivi->qos = le16_get_bits(vsi->info.pvid, I40E_PRIORITY_MASK); 4679 4680 if (vf->link_forced == false) 4680 4681 ivi->linkstate = IFLA_VF_LINK_STATE_AUTO; 4681 4682 else if (vf->link_up == true)

+1 -2

drivers/net/ethernet/intel/i40e/i40e_xsk.c

··· 476 476 continue; 477 477 } 478 478 479 - size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 480 - I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 479 + size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword); 481 480 if (!size) 482 481 break; 483 482

+15 -19

drivers/net/ethernet/intel/iavf/iavf_common.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 3 4 + #include <linux/avf/virtchnl.h> 5 + #include <linux/bitfield.h> 4 6 #include "iavf_type.h" 5 7 #include "iavf_adminq.h" 6 8 #include "iavf_prototype.h" 7 - #include <linux/avf/virtchnl.h> 8 9 9 10 /** 10 11 * iavf_aq_str - convert AQ err code to a string ··· 331 330 struct iavf_aq_desc desc; 332 331 struct iavf_aqc_get_set_rss_lut *cmd_resp = 333 332 (struct iavf_aqc_get_set_rss_lut *)&desc.params.raw; 333 + u16 flags; 334 334 335 335 if (set) 336 336 iavf_fill_default_direct_cmd_desc(&desc, ··· 344 342 desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF); 345 343 desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD); 346 344 347 - cmd_resp->vsi_id = 348 - cpu_to_le16((u16)((vsi_id << 349 - IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 350 - IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK)); 351 - cmd_resp->vsi_id |= cpu_to_le16((u16)IAVF_AQC_SET_RSS_LUT_VSI_VALID); 345 + vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) | 346 + FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_VALID, 1); 347 + cmd_resp->vsi_id = cpu_to_le16(vsi_id); 352 348 353 349 if (pf_lut) 354 - cmd_resp->flags |= cpu_to_le16((u16) 355 - ((IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 356 - IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 357 - IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 350 + flags = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 351 + IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF); 358 352 else 359 - cmd_resp->flags |= cpu_to_le16((u16) 360 - ((IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 361 - IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 362 - IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 353 + flags = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK, 354 + IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI); 355 + 356 + cmd_resp->flags = cpu_to_le16(flags); 363 357 364 358 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); 365 359 ··· 409 411 desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF); 410 412 desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD); 411 413 412 - cmd_resp->vsi_id = 413 - cpu_to_le16((u16)((vsi_id << 414 - IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 415 - IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK)); 416 - cmd_resp->vsi_id |= cpu_to_le16((u16)IAVF_AQC_SET_RSS_KEY_VSI_VALID); 414 + vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) | 415 + FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_VALID, 1); 416 + cmd_resp->vsi_id = cpu_to_le16(vsi_id); 417 417 418 418 status = iavf_asq_send_command(hw, &desc, key, key_size, NULL); 419 419

+4 -4

drivers/net/ethernet/intel/iavf/iavf_ethtool.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 3 4 + #include <linux/bitfield.h> 5 + #include <linux/uaccess.h> 6 + 4 7 /* ethtool support for iavf */ 5 8 #include "iavf.h" 6 - 7 - #include <linux/uaccess.h> 8 9 9 10 /* ethtool statistics helpers */ 10 11 ··· 1017 1016 #define IAVF_USERDEF_FLEX_MAX_OFFS_VAL 504 1018 1017 flex = &fltr->flex_words[cnt++]; 1019 1018 flex->word = value & IAVF_USERDEF_FLEX_WORD_M; 1020 - flex->offset = (value & IAVF_USERDEF_FLEX_OFFS_M) >> 1021 - IAVF_USERDEF_FLEX_OFFS_S; 1019 + flex->offset = FIELD_GET(IAVF_USERDEF_FLEX_OFFS_M, value); 1022 1020 if (flex->offset > IAVF_USERDEF_FLEX_MAX_OFFS_VAL) 1023 1021 return -EINVAL; 1024 1022 }

+2 -1

drivers/net/ethernet/intel/iavf/iavf_fdir.c

··· 3 3 4 4 /* flow director ethtool support for iavf */ 5 5 6 + #include <linux/bitfield.h> 6 7 #include "iavf.h" 7 8 8 9 #define GTPU_PORT 2152 ··· 358 357 359 358 if (fltr->ip_mask.tclass == U8_MAX) { 360 359 iph->priority = (fltr->ip_data.tclass >> 4) & 0xF; 361 - iph->flow_lbl[0] = (fltr->ip_data.tclass << 4) & 0xF0; 360 + iph->flow_lbl[0] = FIELD_PREP(0xF0, fltr->ip_data.tclass); 362 361 VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, TC); 363 362 } 364 363

+8 -13

drivers/net/ethernet/intel/iavf/iavf_txrx.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include <linux/prefetch.h> 5 6 6 7 #include "iavf.h" ··· 989 988 u64 qword; 990 989 991 990 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 992 - ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT; 993 - rx_error = (qword & IAVF_RXD_QW1_ERROR_MASK) >> 994 - IAVF_RXD_QW1_ERROR_SHIFT; 995 - rx_status = (qword & IAVF_RXD_QW1_STATUS_MASK) >> 996 - IAVF_RXD_QW1_STATUS_SHIFT; 991 + ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword); 992 + rx_error = FIELD_GET(IAVF_RXD_QW1_ERROR_MASK, qword); 993 + rx_status = FIELD_GET(IAVF_RXD_QW1_STATUS_MASK, qword); 997 994 decoded = decode_rx_desc_ptype(ptype); 998 995 999 996 skb->ip_summed = CHECKSUM_NONE; ··· 1532 1533 if (!iavf_test_staterr(rx_desc, IAVF_RXD_DD)) 1533 1534 break; 1534 1535 1535 - size = (qword & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >> 1536 - IAVF_RXD_QW1_LENGTH_PBUF_SHIFT; 1536 + size = FIELD_GET(IAVF_RXD_QW1_LENGTH_PBUF_MASK, qword); 1537 1537 1538 1538 iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb); 1539 1539 rx_buffer = iavf_get_rx_buffer(rx_ring, size); ··· 1579 1581 total_rx_bytes += skb->len; 1580 1582 1581 1583 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1582 - rx_ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK) >> 1583 - IAVF_RXD_QW1_PTYPE_SHIFT; 1584 + rx_ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword); 1584 1585 1585 1586 /* populate checksum, VLAN, and protocol */ 1586 1587 iavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); ··· 2287 2290 2288 2291 if (tx_flags & IAVF_TX_FLAGS_HW_VLAN) { 2289 2292 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1; 2290 - td_tag = (tx_flags & IAVF_TX_FLAGS_VLAN_MASK) >> 2291 - IAVF_TX_FLAGS_VLAN_SHIFT; 2293 + td_tag = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags); 2292 2294 } 2293 2295 2294 2296 first->tx_flags = tx_flags; ··· 2463 2467 if (tx_flags & IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN) { 2464 2468 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2 << 2465 2469 IAVF_TXD_CTX_QW1_CMD_SHIFT; 2466 - cd_l2tag2 = (tx_flags & IAVF_TX_FLAGS_VLAN_MASK) >> 2467 - IAVF_TX_FLAGS_VLAN_SHIFT; 2470 + cd_l2tag2 = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags); 2468 2471 } 2469 2472 2470 2473 /* obtain protocol of skb */

+5 -5

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

··· 422 422 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 423 423 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 424 424 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 425 - #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 426 - #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 427 - #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 428 - #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 425 + #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 426 + #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 427 + #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 428 + #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 429 429 u8 inner_vlan_reserved2[3]; 430 430 /* ingress egress up sections */ 431 431 __le32 ingress_table; /* bitmap, 3 bits per up */ ··· 491 491 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 492 492 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 493 493 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 494 - #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 494 + #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 495 495 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 496 496 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 497 497 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U

+12 -20

drivers/net/ethernet/intel/ice/ice_base.c

··· 232 232 233 233 /* no need to update global register if ITR gran is already set */ 234 234 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 235 - (((regval & GLINT_CTL_ITR_GRAN_200_M) >> 236 - GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) && 237 - (((regval & GLINT_CTL_ITR_GRAN_100_M) >> 238 - GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) && 239 - (((regval & GLINT_CTL_ITR_GRAN_50_M) >> 240 - GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) && 241 - (((regval & GLINT_CTL_ITR_GRAN_25_M) >> 242 - GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US)) 235 + (FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) && 236 + (FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) && 237 + (FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) && 238 + (FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US)) 243 239 return; 244 240 245 - regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & 246 - GLINT_CTL_ITR_GRAN_200_M) | 247 - ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) & 248 - GLINT_CTL_ITR_GRAN_100_M) | 249 - ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) & 250 - GLINT_CTL_ITR_GRAN_50_M) | 251 - ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) & 252 - GLINT_CTL_ITR_GRAN_25_M); 241 + regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) | 242 + FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) | 243 + FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) | 244 + FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US); 253 245 wr32(hw, GLINT_CTL, regval); 254 246 } 255 247 ··· 928 936 struct ice_hw *hw = &pf->hw; 929 937 u32 val; 930 938 931 - itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M; 939 + itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx); 932 940 933 941 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 934 - ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M); 942 + FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx); 935 943 936 944 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 937 945 if (ice_is_xdp_ena_vsi(vsi)) { ··· 960 968 struct ice_hw *hw = &pf->hw; 961 969 u32 val; 962 970 963 - itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M; 971 + itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx); 964 972 965 973 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 966 - ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M); 974 + FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx); 967 975 968 976 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 969 977

+24 -30

drivers/net/ethernet/intel/ice/ice_common.c

··· 942 942 */ 943 943 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 944 944 { 945 - u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 946 - GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 947 - GL_PWR_MODE_CTL_CAR_MAX_BW_S; 945 + u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 946 + rd32(hw, GL_PWR_MODE_CTL)); 948 947 949 948 switch (max_agg_bw) { 950 949 case ICE_MAX_AGG_BW_200G: ··· 975 976 if (status) 976 977 return status; 977 978 978 - hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 979 - PF_FUNC_RID_FUNC_NUM_M) >> 980 - PF_FUNC_RID_FUNC_NUM_S; 979 + hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 981 980 982 981 status = ice_reset(hw, ICE_RESET_PFR); 983 982 if (status) ··· 1160 1163 * or EMPR has occurred. The grst delay value is in 100ms units. 1161 1164 * Add 1sec for outstanding AQ commands that can take a long time. 1162 1165 */ 1163 - grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1164 - GLGEN_RSTCTL_GRSTDEL_S) + 10; 1166 + grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1167 + rd32(hw, GLGEN_RSTCTL)) + 10; 1165 1168 1166 1169 for (cnt = 0; cnt < grst_timeout; cnt++) { 1167 1170 mdelay(100); ··· 2245 2248 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2246 2249 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2247 2250 2248 - info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2251 + info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2249 2252 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2250 2253 2251 2254 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { ··· 2446 2449 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2447 2450 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2448 2451 2449 - info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2452 + info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2450 2453 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2451 2454 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2452 2455 ··· 3881 3884 { 3882 3885 struct ice_aqc_sff_eeprom *cmd; 3883 3886 struct ice_aq_desc desc; 3887 + u16 i2c_bus_addr; 3884 3888 int status; 3885 3889 3886 3890 if (!data || (mem_addr & 0xff00)) ··· 3892 3894 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3893 3895 cmd->lport_num = (u8)(lport & 0xff); 3894 3896 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3895 - cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3896 - ICE_AQC_SFF_I2CBUS_7BIT_M) | 3897 - ((set_page << 3898 - ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3899 - ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3900 - cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3901 - cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3897 + i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 3898 + FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 3902 3899 if (write) 3903 - cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3900 + i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 3901 + cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 3902 + cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3903 + cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 3904 3904 3905 3905 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3906 3906 return status; ··· 4153 4157 struct ice_aqc_dis_txq_item *item; 4154 4158 struct ice_aqc_dis_txqs *cmd; 4155 4159 struct ice_aq_desc desc; 4160 + u16 vmvf_and_timeout; 4156 4161 u16 i, sz = 0; 4157 4162 int status; 4158 4163 ··· 4169 4172 4170 4173 cmd->num_entries = num_qgrps; 4171 4174 4172 - cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4173 - ICE_AQC_Q_DIS_TIMEOUT_M); 4175 + vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4174 4176 4175 4177 switch (rst_src) { 4176 4178 case ICE_VM_RESET: 4177 4179 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4178 - cmd->vmvf_and_timeout |= 4179 - cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4180 + vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4180 4181 break; 4181 4182 case ICE_VF_RESET: 4182 4183 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4183 4184 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4184 - cmd->vmvf_and_timeout |= 4185 - cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4186 - ICE_AQC_Q_DIS_VMVF_NUM_M); 4185 + vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4186 + ICE_AQC_Q_DIS_VMVF_NUM_M; 4187 4187 break; 4188 4188 case ICE_NO_RESET: 4189 4189 default: 4190 4190 break; 4191 4191 } 4192 + 4193 + cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4192 4194 4193 4195 /* flush pipe on time out */ 4194 4196 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; ··· 4263 4267 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; 4264 4268 cmd->num_qs = num_qs; 4265 4269 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4266 - cmd->port_num_chng |= (newport << ICE_AQC_Q_CFG_DST_PRT_S) & 4267 - ICE_AQC_Q_CFG_DST_PRT_M; 4268 - cmd->time_out = (5 << ICE_AQC_Q_CFG_TIMEOUT_S) & 4269 - ICE_AQC_Q_CFG_TIMEOUT_M; 4270 + cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4271 + cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4270 4272 cmd->blocked_cgds = 0; 4271 4273 4272 4274 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); ··· 5770 5776 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5771 5777 return status; 5772 5778 } 5773 - ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5779 + ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 5774 5780 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5775 5781 ICE_LINK_OVERRIDE_PHY_CFG_S; 5776 5782

+32 -47

drivers/net/ethernet/intel/ice/ice_dcb.c

··· 35 35 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_get_mib); 36 36 37 37 cmd->type = mib_type & ICE_AQ_LLDP_MIB_TYPE_M; 38 - cmd->type |= (bridge_type << ICE_AQ_LLDP_BRID_TYPE_S) & 39 - ICE_AQ_LLDP_BRID_TYPE_M; 38 + cmd->type |= FIELD_PREP(ICE_AQ_LLDP_BRID_TYPE_M, bridge_type); 40 39 41 40 desc.datalen = cpu_to_le16(buf_size); 42 41 ··· 146 147 u32 reg; 147 148 148 149 reg = rd32(hw, PRTDCB_GENS); 149 - return (u8)((reg & PRTDCB_GENS_DCBX_STATUS_M) >> 150 - PRTDCB_GENS_DCBX_STATUS_S); 150 + return FIELD_GET(PRTDCB_GENS_DCBX_STATUS_M, reg); 151 151 } 152 152 153 153 /** ··· 172 174 */ 173 175 for (i = 0; i < 4; i++) { 174 176 ets_cfg->prio_table[i * 2] = 175 - ((buf[offset] & ICE_IEEE_ETS_PRIO_1_M) >> 176 - ICE_IEEE_ETS_PRIO_1_S); 177 + FIELD_GET(ICE_IEEE_ETS_PRIO_1_M, buf[offset]); 177 178 ets_cfg->prio_table[i * 2 + 1] = 178 - ((buf[offset] & ICE_IEEE_ETS_PRIO_0_M) >> 179 - ICE_IEEE_ETS_PRIO_0_S); 179 + FIELD_GET(ICE_IEEE_ETS_PRIO_0_M, buf[offset]); 180 180 offset++; 181 181 } 182 182 ··· 218 222 * |1bit | 1bit|3 bits|3bits| 219 223 */ 220 224 etscfg = &dcbcfg->etscfg; 221 - etscfg->willing = ((buf[0] & ICE_IEEE_ETS_WILLING_M) >> 222 - ICE_IEEE_ETS_WILLING_S); 223 - etscfg->cbs = ((buf[0] & ICE_IEEE_ETS_CBS_M) >> ICE_IEEE_ETS_CBS_S); 224 - etscfg->maxtcs = ((buf[0] & ICE_IEEE_ETS_MAXTC_M) >> 225 - ICE_IEEE_ETS_MAXTC_S); 225 + etscfg->willing = FIELD_GET(ICE_IEEE_ETS_WILLING_M, buf[0]); 226 + etscfg->cbs = FIELD_GET(ICE_IEEE_ETS_CBS_M, buf[0]); 227 + etscfg->maxtcs = FIELD_GET(ICE_IEEE_ETS_MAXTC_M, buf[0]); 226 228 227 229 /* Begin parsing at Priority Assignment Table (offset 1 in buf) */ 228 230 ice_parse_ieee_ets_common_tlv(&buf[1], etscfg); ··· 262 268 * ----------------------------------------- 263 269 * |1bit | 1bit|2 bits|4bits| 1 octet | 264 270 */ 265 - dcbcfg->pfc.willing = ((buf[0] & ICE_IEEE_PFC_WILLING_M) >> 266 - ICE_IEEE_PFC_WILLING_S); 267 - dcbcfg->pfc.mbc = ((buf[0] & ICE_IEEE_PFC_MBC_M) >> ICE_IEEE_PFC_MBC_S); 268 - dcbcfg->pfc.pfccap = ((buf[0] & ICE_IEEE_PFC_CAP_M) >> 269 - ICE_IEEE_PFC_CAP_S); 271 + dcbcfg->pfc.willing = FIELD_GET(ICE_IEEE_PFC_WILLING_M, buf[0]); 272 + dcbcfg->pfc.mbc = FIELD_GET(ICE_IEEE_PFC_MBC_M, buf[0]); 273 + dcbcfg->pfc.pfccap = FIELD_GET(ICE_IEEE_PFC_CAP_M, buf[0]); 270 274 dcbcfg->pfc.pfcena = buf[1]; 271 275 } 272 276 ··· 286 294 u8 *buf; 287 295 288 296 typelen = ntohs(tlv->typelen); 289 - len = ((typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S); 297 + len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 290 298 buf = tlv->tlvinfo; 291 299 292 300 /* Removing sizeof(ouisubtype) and reserved byte from len. ··· 306 314 * ----------------------------------------- 307 315 */ 308 316 while (offset < len) { 309 - dcbcfg->app[i].priority = ((buf[offset] & 310 - ICE_IEEE_APP_PRIO_M) >> 311 - ICE_IEEE_APP_PRIO_S); 312 - dcbcfg->app[i].selector = ((buf[offset] & 313 - ICE_IEEE_APP_SEL_M) >> 314 - ICE_IEEE_APP_SEL_S); 317 + dcbcfg->app[i].priority = FIELD_GET(ICE_IEEE_APP_PRIO_M, 318 + buf[offset]); 319 + dcbcfg->app[i].selector = FIELD_GET(ICE_IEEE_APP_SEL_M, 320 + buf[offset]); 315 321 dcbcfg->app[i].prot_id = (buf[offset + 1] << 0x8) | 316 322 buf[offset + 2]; 317 323 /* Move to next app */ ··· 337 347 u8 subtype; 338 348 339 349 ouisubtype = ntohl(tlv->ouisubtype); 340 - subtype = (u8)((ouisubtype & ICE_LLDP_TLV_SUBTYPE_M) >> 341 - ICE_LLDP_TLV_SUBTYPE_S); 350 + subtype = FIELD_GET(ICE_LLDP_TLV_SUBTYPE_M, ouisubtype); 342 351 switch (subtype) { 343 352 case ICE_IEEE_SUBTYPE_ETS_CFG: 344 353 ice_parse_ieee_etscfg_tlv(tlv, dcbcfg); ··· 388 399 */ 389 400 for (i = 0; i < 4; i++) { 390 401 etscfg->prio_table[i * 2] = 391 - ((buf[offset] & ICE_CEE_PGID_PRIO_1_M) >> 392 - ICE_CEE_PGID_PRIO_1_S); 402 + FIELD_GET(ICE_CEE_PGID_PRIO_1_M, buf[offset]); 393 403 etscfg->prio_table[i * 2 + 1] = 394 - ((buf[offset] & ICE_CEE_PGID_PRIO_0_M) >> 395 - ICE_CEE_PGID_PRIO_0_S); 404 + FIELD_GET(ICE_CEE_PGID_PRIO_0_M, buf[offset]); 396 405 offset++; 397 406 } 398 407 ··· 453 466 u8 i; 454 467 455 468 typelen = ntohs(tlv->hdr.typelen); 456 - len = ((typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S); 469 + len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 457 470 458 471 dcbcfg->numapps = len / sizeof(*app); 459 472 if (!dcbcfg->numapps) ··· 508 521 u32 ouisubtype; 509 522 510 523 ouisubtype = ntohl(tlv->ouisubtype); 511 - subtype = (u8)((ouisubtype & ICE_LLDP_TLV_SUBTYPE_M) >> 512 - ICE_LLDP_TLV_SUBTYPE_S); 524 + subtype = FIELD_GET(ICE_LLDP_TLV_SUBTYPE_M, ouisubtype); 513 525 /* Return if not CEE DCBX */ 514 526 if (subtype != ICE_CEE_DCBX_TYPE) 515 527 return; 516 528 517 529 typelen = ntohs(tlv->typelen); 518 - tlvlen = ((typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S); 530 + tlvlen = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 519 531 len = sizeof(tlv->typelen) + sizeof(ouisubtype) + 520 532 sizeof(struct ice_cee_ctrl_tlv); 521 533 /* Return if no CEE DCBX Feature TLVs */ ··· 526 540 u16 sublen; 527 541 528 542 typelen = ntohs(sub_tlv->hdr.typelen); 529 - sublen = ((typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S); 530 - subtype = (u8)((typelen & ICE_LLDP_TLV_TYPE_M) >> 531 - ICE_LLDP_TLV_TYPE_S); 543 + sublen = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 544 + subtype = FIELD_GET(ICE_LLDP_TLV_TYPE_M, typelen); 532 545 switch (subtype) { 533 546 case ICE_CEE_SUBTYPE_PG_CFG: 534 547 ice_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg); ··· 564 579 u32 oui; 565 580 566 581 ouisubtype = ntohl(tlv->ouisubtype); 567 - oui = ((ouisubtype & ICE_LLDP_TLV_OUI_M) >> ICE_LLDP_TLV_OUI_S); 582 + oui = FIELD_GET(ICE_LLDP_TLV_OUI_M, ouisubtype); 568 583 switch (oui) { 569 584 case ICE_IEEE_8021QAZ_OUI: 570 585 ice_parse_ieee_tlv(tlv, dcbcfg); ··· 601 616 tlv = (struct ice_lldp_org_tlv *)lldpmib; 602 617 while (1) { 603 618 typelen = ntohs(tlv->typelen); 604 - type = ((typelen & ICE_LLDP_TLV_TYPE_M) >> ICE_LLDP_TLV_TYPE_S); 605 - len = ((typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S); 619 + type = FIELD_GET(ICE_LLDP_TLV_TYPE_M, typelen); 620 + len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 606 621 offset += sizeof(typelen) + len; 607 622 608 623 /* END TLV or beyond LLDPDU size */ ··· 791 806 */ 792 807 for (i = 0; i < ICE_MAX_TRAFFIC_CLASS / 2; i++) { 793 808 dcbcfg->etscfg.prio_table[i * 2] = 794 - ((cee_cfg->oper_prio_tc[i] & ICE_CEE_PGID_PRIO_0_M) >> 795 - ICE_CEE_PGID_PRIO_0_S); 809 + FIELD_GET(ICE_CEE_PGID_PRIO_0_M, 810 + cee_cfg->oper_prio_tc[i]); 796 811 dcbcfg->etscfg.prio_table[i * 2 + 1] = 797 - ((cee_cfg->oper_prio_tc[i] & ICE_CEE_PGID_PRIO_1_M) >> 798 - ICE_CEE_PGID_PRIO_1_S); 812 + FIELD_GET(ICE_CEE_PGID_PRIO_1_M, 813 + cee_cfg->oper_prio_tc[i]); 799 814 } 800 815 801 816 ice_for_each_traffic_class(i) { ··· 967 982 968 983 mib = (struct ice_aqc_lldp_get_mib *)&event->desc.params.raw; 969 984 970 - change_type = FIELD_GET(ICE_AQ_LLDP_MIB_TYPE_M, mib->type); 985 + change_type = FIELD_GET(ICE_AQ_LLDP_MIB_TYPE_M, mib->type); 971 986 if (change_type == ICE_AQ_LLDP_MIB_REMOTE) 972 987 dcbx_cfg = &pi->qos_cfg.remote_dcbx_cfg; 973 988 ··· 1468 1483 while (1) { 1469 1484 ice_add_dcb_tlv(tlv, dcbcfg, tlvid++); 1470 1485 typelen = ntohs(tlv->typelen); 1471 - len = (typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S; 1486 + len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 1472 1487 if (len) 1473 1488 offset += len + 2; 1474 1489 /* END TLV or beyond LLDPDU size */

+1 -1

drivers/net/ethernet/intel/ice/ice_dcb_lib.c

··· 934 934 skb->priority != TC_PRIO_CONTROL) { 935 935 first->vid &= ~VLAN_PRIO_MASK; 936 936 /* Mask the lower 3 bits to set the 802.1p priority */ 937 - first->vid |= (skb->priority << VLAN_PRIO_SHIFT) & VLAN_PRIO_MASK; 937 + first->vid |= FIELD_PREP(VLAN_PRIO_MASK, skb->priority); 938 938 /* if this is not already set it means a VLAN 0 + priority needs 939 939 * to be offloaded 940 940 */

+1 -1

drivers/net/ethernet/intel/ice/ice_dcb_nl.c

··· 227 227 u32 val; 228 228 229 229 val = rd32(hw, PRTDCB_GENC); 230 - *delay = (u16)((val & PRTDCB_GENC_PFCLDA_M) >> PRTDCB_GENC_PFCLDA_S); 230 + *delay = FIELD_GET(PRTDCB_GENC_PFCLDA_M, val); 231 231 } 232 232 233 233 /**

+2 -2

drivers/net/ethernet/intel/ice/ice_eswitch.c

··· 358 358 off->cd_qw1 |= (cd_cmd | ICE_TX_DESC_DTYPE_CTX); 359 359 } else { 360 360 cd_cmd = ICE_TX_CTX_DESC_SWTCH_VSI << ICE_TXD_CTX_QW1_CMD_S; 361 - dst_vsi = ((u64)dst->u.port_info.port_id << 362 - ICE_TXD_CTX_QW1_VSI_S) & ICE_TXD_CTX_QW1_VSI_M; 361 + dst_vsi = FIELD_PREP(ICE_TXD_CTX_QW1_VSI_M, 362 + dst->u.port_info.port_id); 363 363 off->cd_qw1 = cd_cmd | dst_vsi | ICE_TX_DESC_DTYPE_CTX; 364 364 } 365 365 }

+1 -2

drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c

··· 503 503 return -EINVAL; 504 504 505 505 data->flex_word = value & ICE_USERDEF_FLEX_WORD_M; 506 - data->flex_offset = (value & ICE_USERDEF_FLEX_OFFS_M) >> 507 - ICE_USERDEF_FLEX_OFFS_S; 506 + data->flex_offset = FIELD_GET(ICE_USERDEF_FLEX_OFFS_M, value); 508 507 if (data->flex_offset > ICE_USERDEF_FLEX_MAX_OFFS_VAL) 509 508 return -EINVAL; 510 509

+23 -46

drivers/net/ethernet/intel/ice/ice_fdir.c

··· 604 604 u64 qword; 605 605 606 606 /* prep QW0 of FD filter programming desc */ 607 - qword = ((u64)ctx->qindex << ICE_FXD_FLTR_QW0_QINDEX_S) & 608 - ICE_FXD_FLTR_QW0_QINDEX_M; 609 - qword |= ((u64)ctx->comp_q << ICE_FXD_FLTR_QW0_COMP_Q_S) & 610 - ICE_FXD_FLTR_QW0_COMP_Q_M; 611 - qword |= ((u64)ctx->comp_report << ICE_FXD_FLTR_QW0_COMP_REPORT_S) & 612 - ICE_FXD_FLTR_QW0_COMP_REPORT_M; 613 - qword |= ((u64)ctx->fd_space << ICE_FXD_FLTR_QW0_FD_SPACE_S) & 614 - ICE_FXD_FLTR_QW0_FD_SPACE_M; 615 - qword |= ((u64)ctx->cnt_index << ICE_FXD_FLTR_QW0_STAT_CNT_S) & 616 - ICE_FXD_FLTR_QW0_STAT_CNT_M; 617 - qword |= ((u64)ctx->cnt_ena << ICE_FXD_FLTR_QW0_STAT_ENA_S) & 618 - ICE_FXD_FLTR_QW0_STAT_ENA_M; 619 - qword |= ((u64)ctx->evict_ena << ICE_FXD_FLTR_QW0_EVICT_ENA_S) & 620 - ICE_FXD_FLTR_QW0_EVICT_ENA_M; 621 - qword |= ((u64)ctx->toq << ICE_FXD_FLTR_QW0_TO_Q_S) & 622 - ICE_FXD_FLTR_QW0_TO_Q_M; 623 - qword |= ((u64)ctx->toq_prio << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) & 624 - ICE_FXD_FLTR_QW0_TO_Q_PRI_M; 625 - qword |= ((u64)ctx->dpu_recipe << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) & 626 - ICE_FXD_FLTR_QW0_DPU_RECIPE_M; 627 - qword |= ((u64)ctx->drop << ICE_FXD_FLTR_QW0_DROP_S) & 628 - ICE_FXD_FLTR_QW0_DROP_M; 629 - qword |= ((u64)ctx->flex_prio << ICE_FXD_FLTR_QW0_FLEX_PRI_S) & 630 - ICE_FXD_FLTR_QW0_FLEX_PRI_M; 631 - qword |= ((u64)ctx->flex_mdid << ICE_FXD_FLTR_QW0_FLEX_MDID_S) & 632 - ICE_FXD_FLTR_QW0_FLEX_MDID_M; 633 - qword |= ((u64)ctx->flex_val << ICE_FXD_FLTR_QW0_FLEX_VAL_S) & 634 - ICE_FXD_FLTR_QW0_FLEX_VAL_M; 607 + qword = FIELD_PREP(ICE_FXD_FLTR_QW0_QINDEX_M, ctx->qindex); 608 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_COMP_Q_M, ctx->comp_q); 609 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_COMP_REPORT_M, ctx->comp_report); 610 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FD_SPACE_M, ctx->fd_space); 611 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_STAT_CNT_M, ctx->cnt_index); 612 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_STAT_ENA_M, ctx->cnt_ena); 613 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_EVICT_ENA_M, ctx->evict_ena); 614 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_TO_Q_M, ctx->toq); 615 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_TO_Q_PRI_M, ctx->toq_prio); 616 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_DPU_RECIPE_M, ctx->dpu_recipe); 617 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_DROP_M, ctx->drop); 618 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FLEX_PRI_M, ctx->flex_prio); 619 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FLEX_MDID_M, ctx->flex_mdid); 620 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FLEX_VAL_M, ctx->flex_val); 635 621 fdir_desc->qidx_compq_space_stat = cpu_to_le64(qword); 636 622 637 623 /* prep QW1 of FD filter programming desc */ 638 - qword = ((u64)ctx->dtype << ICE_FXD_FLTR_QW1_DTYPE_S) & 639 - ICE_FXD_FLTR_QW1_DTYPE_M; 640 - qword |= ((u64)ctx->pcmd << ICE_FXD_FLTR_QW1_PCMD_S) & 641 - ICE_FXD_FLTR_QW1_PCMD_M; 642 - qword |= ((u64)ctx->desc_prof_prio << ICE_FXD_FLTR_QW1_PROF_PRI_S) & 643 - ICE_FXD_FLTR_QW1_PROF_PRI_M; 644 - qword |= ((u64)ctx->desc_prof << ICE_FXD_FLTR_QW1_PROF_S) & 645 - ICE_FXD_FLTR_QW1_PROF_M; 646 - qword |= ((u64)ctx->fd_vsi << ICE_FXD_FLTR_QW1_FD_VSI_S) & 647 - ICE_FXD_FLTR_QW1_FD_VSI_M; 648 - qword |= ((u64)ctx->swap << ICE_FXD_FLTR_QW1_SWAP_S) & 649 - ICE_FXD_FLTR_QW1_SWAP_M; 650 - qword |= ((u64)ctx->fdid_prio << ICE_FXD_FLTR_QW1_FDID_PRI_S) & 651 - ICE_FXD_FLTR_QW1_FDID_PRI_M; 652 - qword |= ((u64)ctx->fdid_mdid << ICE_FXD_FLTR_QW1_FDID_MDID_S) & 653 - ICE_FXD_FLTR_QW1_FDID_MDID_M; 654 - qword |= ((u64)ctx->fdid << ICE_FXD_FLTR_QW1_FDID_S) & 655 - ICE_FXD_FLTR_QW1_FDID_M; 624 + qword = FIELD_PREP(ICE_FXD_FLTR_QW1_DTYPE_M, ctx->dtype); 625 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_PCMD_M, ctx->pcmd); 626 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_PROF_PRI_M, ctx->desc_prof_prio); 627 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_PROF_M, ctx->desc_prof); 628 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FD_VSI_M, ctx->fd_vsi); 629 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_SWAP_M, ctx->swap); 630 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FDID_PRI_M, ctx->fdid_prio); 631 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FDID_MDID_M, ctx->fdid_mdid); 632 + qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FDID_M, ctx->fdid); 656 633 fdir_desc->dtype_cmd_vsi_fdid = cpu_to_le64(qword); 657 634 } 658 635

+4 -4

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

··· 1414 1414 switch (blk) { 1415 1415 case ICE_BLK_RSS: 1416 1416 offset = GLQF_HMASK(mask_idx); 1417 - val = (idx << GLQF_HMASK_MSK_INDEX_S) & GLQF_HMASK_MSK_INDEX_M; 1418 - val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; 1417 + val = FIELD_PREP(GLQF_HMASK_MSK_INDEX_M, idx); 1418 + val |= FIELD_PREP(GLQF_HMASK_MASK_M, mask); 1419 1419 break; 1420 1420 case ICE_BLK_FD: 1421 1421 offset = GLQF_FDMASK(mask_idx); 1422 - val = (idx << GLQF_FDMASK_MSK_INDEX_S) & GLQF_FDMASK_MSK_INDEX_M; 1423 - val |= (mask << GLQF_FDMASK_MASK_S) & GLQF_FDMASK_MASK_M; 1422 + val = FIELD_PREP(GLQF_FDMASK_MSK_INDEX_M, idx); 1423 + val |= FIELD_PREP(GLQF_FDMASK_MASK_M, mask); 1424 1424 break; 1425 1425 default: 1426 1426 ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n",

+2 -5

drivers/net/ethernet/intel/ice/ice_lag.c

··· 208 208 eth_hdr = s_rule->hdr_data; 209 209 ice_fill_eth_hdr(eth_hdr); 210 210 211 - act |= (vsi_num << ICE_SINGLE_ACT_VSI_ID_S) & 212 - ICE_SINGLE_ACT_VSI_ID_M; 211 + act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M, vsi_num); 213 212 214 213 s_rule->hdr.type = cpu_to_le16(ICE_AQC_SW_RULES_T_LKUP_RX); 215 214 s_rule->recipe_id = cpu_to_le16(recipe_id); ··· 753 754 s_rule->act = cpu_to_le32(ICE_FWD_TO_VSI | 754 755 ICE_SINGLE_ACT_LAN_ENABLE | 755 756 ICE_SINGLE_ACT_VALID_BIT | 756 - ((vsi->vsi_num << 757 - ICE_SINGLE_ACT_VSI_ID_S) & 758 - ICE_SINGLE_ACT_VSI_ID_M)); 757 + FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M, vsi->vsi_num)); 759 758 s_rule->hdr_len = cpu_to_le16(ICE_LAG_SRIOV_TRAIN_PKT_LEN); 760 759 memcpy(s_rule->hdr_data, lacp_train_pkt, LACP_TRAIN_PKT_LEN); 761 760 opc = ice_aqc_opc_add_sw_rules;

+20 -34

drivers/net/ethernet/intel/ice/ice_lib.c

··· 974 974 /* Traffic from VSI can be sent to LAN */ 975 975 ctxt->info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; 976 976 /* allow all untagged/tagged packets by default on Tx */ 977 - ctxt->info.inner_vlan_flags = ((ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL & 978 - ICE_AQ_VSI_INNER_VLAN_TX_MODE_M) >> 979 - ICE_AQ_VSI_INNER_VLAN_TX_MODE_S); 977 + ctxt->info.inner_vlan_flags = FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_TX_MODE_M, 978 + ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL); 980 979 /* SVM - by default bits 3 and 4 in inner_vlan_flags are 0's which 981 980 * results in legacy behavior (show VLAN, DEI, and UP) in descriptor. 982 981 * ··· 983 984 */ 984 985 if (ice_is_dvm_ena(hw)) { 985 986 ctxt->info.inner_vlan_flags |= 986 - ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 987 + FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_EMODE_M, 988 + ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING); 987 989 ctxt->info.outer_vlan_flags = 988 - (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << 989 - ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 990 - ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M; 990 + FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M, 991 + ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL); 991 992 ctxt->info.outer_vlan_flags |= 992 - (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 << 993 - ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 994 - ICE_AQ_VSI_OUTER_TAG_TYPE_M; 993 + FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, 994 + ICE_AQ_VSI_OUTER_TAG_VLAN_8100); 995 995 ctxt->info.outer_vlan_flags |= 996 996 FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_EMODE_M, 997 997 ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING); ··· 1069 1071 vsi->tc_cfg.tc_info[i].qcount_tx = num_txq_per_tc; 1070 1072 vsi->tc_cfg.tc_info[i].netdev_tc = netdev_tc++; 1071 1073 1072 - qmap = ((offset << ICE_AQ_VSI_TC_Q_OFFSET_S) & 1073 - ICE_AQ_VSI_TC_Q_OFFSET_M) | 1074 - ((pow << ICE_AQ_VSI_TC_Q_NUM_S) & 1075 - ICE_AQ_VSI_TC_Q_NUM_M); 1074 + qmap = FIELD_PREP(ICE_AQ_VSI_TC_Q_OFFSET_M, offset); 1075 + qmap |= FIELD_PREP(ICE_AQ_VSI_TC_Q_NUM_M, pow); 1076 1076 offset += num_rxq_per_tc; 1077 1077 tx_count += num_txq_per_tc; 1078 1078 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); ··· 1153 1157 ctxt->info.max_fd_fltr_shared = 1154 1158 cpu_to_le16(vsi->num_bfltr); 1155 1159 /* default queue index within the VSI of the default FD */ 1156 - val = ((dflt_q << ICE_AQ_VSI_FD_DEF_Q_S) & 1157 - ICE_AQ_VSI_FD_DEF_Q_M); 1160 + val = FIELD_PREP(ICE_AQ_VSI_FD_DEF_Q_M, dflt_q); 1158 1161 /* target queue or queue group to the FD filter */ 1159 - val |= ((dflt_q_group << ICE_AQ_VSI_FD_DEF_GRP_S) & 1160 - ICE_AQ_VSI_FD_DEF_GRP_M); 1162 + val |= FIELD_PREP(ICE_AQ_VSI_FD_DEF_GRP_M, dflt_q_group); 1161 1163 ctxt->info.fd_def_q = cpu_to_le16(val); 1162 1164 /* queue index on which FD filter completion is reported */ 1163 - val = ((report_q << ICE_AQ_VSI_FD_REPORT_Q_S) & 1164 - ICE_AQ_VSI_FD_REPORT_Q_M); 1165 + val = FIELD_PREP(ICE_AQ_VSI_FD_REPORT_Q_M, report_q); 1165 1166 /* priority of the default qindex action */ 1166 - val |= ((dflt_q_prio << ICE_AQ_VSI_FD_DEF_PRIORITY_S) & 1167 - ICE_AQ_VSI_FD_DEF_PRIORITY_M); 1167 + val |= FIELD_PREP(ICE_AQ_VSI_FD_DEF_PRIORITY_M, dflt_q_prio); 1168 1168 ctxt->info.fd_report_opt = cpu_to_le16(val); 1169 1169 } 1170 1170 ··· 1213 1221 qcount = min_t(int, vsi->num_rxq, pf->num_lan_msix); 1214 1222 1215 1223 pow = order_base_2(qcount); 1216 - qmap = ((offset << ICE_AQ_VSI_TC_Q_OFFSET_S) & 1217 - ICE_AQ_VSI_TC_Q_OFFSET_M) | 1218 - ((pow << ICE_AQ_VSI_TC_Q_NUM_S) & 1219 - ICE_AQ_VSI_TC_Q_NUM_M); 1224 + qmap = FIELD_PREP(ICE_AQ_VSI_TC_Q_OFFSET_M, offset); 1225 + qmap |= FIELD_PREP(ICE_AQ_VSI_TC_Q_NUM_M, pow); 1220 1226 1221 1227 ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); 1222 1228 ctxt->info.mapping_flags |= cpu_to_le16(ICE_AQ_VSI_Q_MAP_CONTIG); ··· 1785 1795 QRXFLXP_CNTXT_RXDID_PRIO_M | 1786 1796 QRXFLXP_CNTXT_TS_M); 1787 1797 1788 - regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & 1789 - QRXFLXP_CNTXT_RXDID_IDX_M; 1790 - 1791 - regval |= (prio << QRXFLXP_CNTXT_RXDID_PRIO_S) & 1792 - QRXFLXP_CNTXT_RXDID_PRIO_M; 1798 + regval |= FIELD_PREP(QRXFLXP_CNTXT_RXDID_IDX_M, rxdid); 1799 + regval |= FIELD_PREP(QRXFLXP_CNTXT_RXDID_PRIO_M, prio); 1793 1800 1794 1801 if (ena_ts) 1795 1802 /* Enable TimeSync on this queue */ ··· 3378 3391 vsi->tc_cfg.ena_tc = ena_tc ? ena_tc : 1; 3379 3392 3380 3393 pow = order_base_2(tc0_qcount); 3381 - qmap = ((tc0_offset << ICE_AQ_VSI_TC_Q_OFFSET_S) & 3382 - ICE_AQ_VSI_TC_Q_OFFSET_M) | 3383 - ((pow << ICE_AQ_VSI_TC_Q_NUM_S) & ICE_AQ_VSI_TC_Q_NUM_M); 3394 + qmap = FIELD_PREP(ICE_AQ_VSI_TC_Q_OFFSET_M, tc0_offset); 3395 + qmap |= FIELD_PREP(ICE_AQ_VSI_TC_Q_NUM_M, pow); 3384 3396 3385 3397 ice_for_each_traffic_class(i) { 3386 3398 if (!(vsi->tc_cfg.ena_tc & BIT(i))) {

+18 -30

drivers/net/ethernet/intel/ice/ice_main.c

··· 980 980 * Octets 13 - 20 are TSA values - leave as zeros 981 981 */ 982 982 buf[5] = 0x64; 983 - len = (typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S; 983 + len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 984 984 offset += len + 2; 985 985 tlv = (struct ice_lldp_org_tlv *) 986 986 ((char *)tlv + sizeof(tlv->typelen) + len); ··· 1014 1014 1015 1015 /* Octet 1 left as all zeros - PFC disabled */ 1016 1016 buf[0] = 0x08; 1017 - len = (typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S; 1017 + len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen); 1018 1018 offset += len + 2; 1019 1019 1020 1020 if (ice_aq_set_lldp_mib(hw, mib_type, (void *)lldpmib, offset, NULL)) ··· 1771 1771 /* find what triggered an MDD event */ 1772 1772 reg = rd32(hw, GL_MDET_TX_PQM); 1773 1773 if (reg & GL_MDET_TX_PQM_VALID_M) { 1774 - u8 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> 1775 - GL_MDET_TX_PQM_PF_NUM_S; 1776 - u16 vf_num = (reg & GL_MDET_TX_PQM_VF_NUM_M) >> 1777 - GL_MDET_TX_PQM_VF_NUM_S; 1778 - u8 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> 1779 - GL_MDET_TX_PQM_MAL_TYPE_S; 1780 - u16 queue = ((reg & GL_MDET_TX_PQM_QNUM_M) >> 1781 - GL_MDET_TX_PQM_QNUM_S); 1774 + u8 pf_num = FIELD_GET(GL_MDET_TX_PQM_PF_NUM_M, reg); 1775 + u16 vf_num = FIELD_GET(GL_MDET_TX_PQM_VF_NUM_M, reg); 1776 + u8 event = FIELD_GET(GL_MDET_TX_PQM_MAL_TYPE_M, reg); 1777 + u16 queue = FIELD_GET(GL_MDET_TX_PQM_QNUM_M, reg); 1782 1778 1783 1779 if (netif_msg_tx_err(pf)) 1784 1780 dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n", ··· 1784 1788 1785 1789 reg = rd32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw)); 1786 1790 if (reg & GL_MDET_TX_TCLAN_VALID_M) { 1787 - u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> 1788 - GL_MDET_TX_TCLAN_PF_NUM_S; 1789 - u16 vf_num = (reg & GL_MDET_TX_TCLAN_VF_NUM_M) >> 1790 - GL_MDET_TX_TCLAN_VF_NUM_S; 1791 - u8 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> 1792 - GL_MDET_TX_TCLAN_MAL_TYPE_S; 1793 - u16 queue = ((reg & GL_MDET_TX_TCLAN_QNUM_M) >> 1794 - GL_MDET_TX_TCLAN_QNUM_S); 1791 + u8 pf_num = FIELD_GET(GL_MDET_TX_TCLAN_PF_NUM_M, reg); 1792 + u16 vf_num = FIELD_GET(GL_MDET_TX_TCLAN_VF_NUM_M, reg); 1793 + u8 event = FIELD_GET(GL_MDET_TX_TCLAN_MAL_TYPE_M, reg); 1794 + u16 queue = FIELD_GET(GL_MDET_TX_TCLAN_QNUM_M, reg); 1795 1795 1796 1796 if (netif_msg_tx_err(pf)) 1797 1797 dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n", ··· 1797 1805 1798 1806 reg = rd32(hw, GL_MDET_RX); 1799 1807 if (reg & GL_MDET_RX_VALID_M) { 1800 - u8 pf_num = (reg & GL_MDET_RX_PF_NUM_M) >> 1801 - GL_MDET_RX_PF_NUM_S; 1802 - u16 vf_num = (reg & GL_MDET_RX_VF_NUM_M) >> 1803 - GL_MDET_RX_VF_NUM_S; 1804 - u8 event = (reg & GL_MDET_RX_MAL_TYPE_M) >> 1805 - GL_MDET_RX_MAL_TYPE_S; 1806 - u16 queue = ((reg & GL_MDET_RX_QNUM_M) >> 1807 - GL_MDET_RX_QNUM_S); 1808 + u8 pf_num = FIELD_GET(GL_MDET_RX_PF_NUM_M, reg); 1809 + u16 vf_num = FIELD_GET(GL_MDET_RX_VF_NUM_M, reg); 1810 + u8 event = FIELD_GET(GL_MDET_RX_MAL_TYPE_M, reg); 1811 + u16 queue = FIELD_GET(GL_MDET_RX_QNUM_M, reg); 1808 1812 1809 1813 if (netif_msg_rx_err(pf)) 1810 1814 dev_info(dev, "Malicious Driver Detection event %d on RX queue %d PF# %d VF# %d\n", ··· 3123 3135 3124 3136 /* we have a reset warning */ 3125 3137 ena_mask &= ~PFINT_OICR_GRST_M; 3126 - reset = (rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_RESET_TYPE_M) >> 3127 - GLGEN_RSTAT_RESET_TYPE_S; 3138 + reset = FIELD_GET(GLGEN_RSTAT_RESET_TYPE_M, 3139 + rd32(hw, GLGEN_RSTAT)); 3128 3140 3129 3141 if (reset == ICE_RESET_CORER) 3130 3142 pf->corer_count++; ··· 8004 8016 struct ice_hw *hw = &pf->hw; 8005 8017 u32 head, val = 0; 8006 8018 8007 - head = (rd32(hw, QTX_COMM_HEAD(vsi->txq_map[txqueue])) & 8008 - QTX_COMM_HEAD_HEAD_M) >> QTX_COMM_HEAD_HEAD_S; 8019 + head = FIELD_GET(QTX_COMM_HEAD_HEAD_M, 8020 + rd32(hw, QTX_COMM_HEAD(vsi->txq_map[txqueue]))); 8009 8021 /* Read interrupt register */ 8010 8022 val = rd32(hw, GLINT_DYN_CTL(tx_ring->q_vector->reg_idx)); 8011 8023

+8 -7

drivers/net/ethernet/intel/ice/ice_nvm.c

··· 571 571 return status; 572 572 } 573 573 574 - nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT; 575 - nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT; 574 + nvm->major = FIELD_GET(ICE_NVM_VER_HI_MASK, ver); 575 + nvm->minor = FIELD_GET(ICE_NVM_VER_LO_MASK, ver); 576 576 577 577 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); 578 578 if (status) { ··· 706 706 707 707 combo_ver = le32_to_cpu(civd.combo_ver); 708 708 709 - orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT); 710 - orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK); 711 - orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT); 709 + orom->major = FIELD_GET(ICE_OROM_VER_MASK, combo_ver); 710 + orom->patch = FIELD_GET(ICE_OROM_VER_PATCH_MASK, combo_ver); 711 + orom->build = FIELD_GET(ICE_OROM_VER_BUILD_MASK, combo_ver); 712 712 713 713 return 0; 714 714 } ··· 950 950 } 951 951 952 952 /* Check that the control word indicates validity */ 953 - if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) { 953 + if (FIELD_GET(ICE_SR_CTRL_WORD_1_M, ctrl_word) != 954 + ICE_SR_CTRL_WORD_VALID) { 954 955 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n"); 955 956 return -EIO; 956 957 } ··· 1028 1027 * as the blank mode may be used in the factory line. 1029 1028 */ 1030 1029 gens_stat = rd32(hw, GLNVM_GENS); 1031 - sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S; 1030 + sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat); 1032 1031 1033 1032 /* Switching to words (sr_size contains power of 2) */ 1034 1033 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;

+6 -7

drivers/net/ethernet/intel/ice/ice_ptp.c

··· 1140 1140 } 1141 1141 1142 1142 if (offs & 0x1) 1143 - phy_sts = (val & Q_REG_FIFO13_M) >> Q_REG_FIFO13_S; 1143 + phy_sts = FIELD_GET(Q_REG_FIFO13_M, val); 1144 1144 else 1145 - phy_sts = (val & Q_REG_FIFO02_M) >> Q_REG_FIFO02_S; 1145 + phy_sts = FIELD_GET(Q_REG_FIFO02_M, val); 1146 1146 1147 1147 if (phy_sts & FIFO_EMPTY) { 1148 1148 port->tx_fifo_busy_cnt = FIFO_OK; ··· 1359 1359 if (ena) { 1360 1360 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 1361 1361 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 1362 - val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) & 1363 - Q_REG_TX_MEM_GBL_CFG_INTR_THR_M); 1362 + val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, 1363 + threshold); 1364 1364 } else { 1365 1365 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 1366 1366 } ··· 1505 1505 * + num_in_channels * tmr_idx 1506 1506 */ 1507 1507 func = 1 + chan + (tmr_idx * 3); 1508 - gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & 1509 - GLGEN_GPIO_CTL_PIN_FUNC_M); 1508 + gpio_reg = FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func); 1510 1509 pf->ptp.ext_ts_chan |= (1 << chan); 1511 1510 } else { 1512 1511 /* clear the values we set to reset defaults */ ··· 1615 1616 /* 4. write GPIO CTL reg */ 1616 1617 func = 8 + chan + (tmr_idx * 4); 1617 1618 val = GLGEN_GPIO_CTL_PIN_DIR_M | 1618 - ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M); 1619 + FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func); 1619 1620 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val); 1620 1621 1621 1622 /* Store the value if requested */

+1 -2

drivers/net/ethernet/intel/ice/ice_sched.c

··· 1387 1387 u32 val, clk_src; 1388 1388 1389 1389 val = rd32(hw, GLGEN_CLKSTAT_SRC); 1390 - clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> 1391 - GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; 1390 + clk_src = FIELD_GET(GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M, val); 1392 1391 1393 1392 #define PSM_CLK_SRC_367_MHZ 0x0 1394 1393 #define PSM_CLK_SRC_416_MHZ 0x1

+15 -26

drivers/net/ethernet/intel/ice/ice_sriov.c

··· 106 106 for (v = first; v <= last; v++) { 107 107 u32 reg; 108 108 109 - reg = (((1 << GLINT_VECT2FUNC_IS_PF_S) & 110 - GLINT_VECT2FUNC_IS_PF_M) | 111 - ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) & 112 - GLINT_VECT2FUNC_PF_NUM_M)); 109 + reg = FIELD_PREP(GLINT_VECT2FUNC_IS_PF_M, 1) | 110 + FIELD_PREP(GLINT_VECT2FUNC_PF_NUM_M, hw->pf_id); 113 111 wr32(hw, GLINT_VECT2FUNC(v), reg); 114 112 } 115 113 ··· 273 275 (device_based_first_msix + vf->num_msix) - 1; 274 276 device_based_vf_id = vf->vf_id + hw->func_caps.vf_base_id; 275 277 276 - reg = (((device_based_first_msix << VPINT_ALLOC_FIRST_S) & 277 - VPINT_ALLOC_FIRST_M) | 278 - ((device_based_last_msix << VPINT_ALLOC_LAST_S) & 279 - VPINT_ALLOC_LAST_M) | VPINT_ALLOC_VALID_M); 278 + reg = FIELD_PREP(VPINT_ALLOC_FIRST_M, device_based_first_msix) | 279 + FIELD_PREP(VPINT_ALLOC_LAST_M, device_based_last_msix) | 280 + VPINT_ALLOC_VALID_M; 280 281 wr32(hw, VPINT_ALLOC(vf->vf_id), reg); 281 282 282 - reg = (((device_based_first_msix << VPINT_ALLOC_PCI_FIRST_S) 283 - & VPINT_ALLOC_PCI_FIRST_M) | 284 - ((device_based_last_msix << VPINT_ALLOC_PCI_LAST_S) & 285 - VPINT_ALLOC_PCI_LAST_M) | VPINT_ALLOC_PCI_VALID_M); 283 + reg = FIELD_PREP(VPINT_ALLOC_PCI_FIRST_M, device_based_first_msix) | 284 + FIELD_PREP(VPINT_ALLOC_PCI_LAST_M, device_based_last_msix) | 285 + VPINT_ALLOC_PCI_VALID_M; 286 286 wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), reg); 287 287 288 288 /* map the interrupts to its functions */ 289 289 for (v = pf_based_first_msix; v <= pf_based_last_msix; v++) { 290 - reg = (((device_based_vf_id << GLINT_VECT2FUNC_VF_NUM_S) & 291 - GLINT_VECT2FUNC_VF_NUM_M) | 292 - ((hw->pf_id << GLINT_VECT2FUNC_PF_NUM_S) & 293 - GLINT_VECT2FUNC_PF_NUM_M)); 290 + reg = FIELD_PREP(GLINT_VECT2FUNC_VF_NUM_M, device_based_vf_id) | 291 + FIELD_PREP(GLINT_VECT2FUNC_PF_NUM_M, hw->pf_id); 294 292 wr32(hw, GLINT_VECT2FUNC(v), reg); 295 293 } 296 294 ··· 319 325 * VFNUMQ value should be set to (number of queues - 1). A value 320 326 * of 0 means 1 queue and a value of 255 means 256 queues 321 327 */ 322 - reg = (((vsi->txq_map[0] << VPLAN_TX_QBASE_VFFIRSTQ_S) & 323 - VPLAN_TX_QBASE_VFFIRSTQ_M) | 324 - (((max_txq - 1) << VPLAN_TX_QBASE_VFNUMQ_S) & 325 - VPLAN_TX_QBASE_VFNUMQ_M)); 328 + reg = FIELD_PREP(VPLAN_TX_QBASE_VFFIRSTQ_M, vsi->txq_map[0]) | 329 + FIELD_PREP(VPLAN_TX_QBASE_VFNUMQ_M, max_txq - 1); 326 330 wr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg); 327 331 } else { 328 332 dev_err(dev, "Scattered mode for VF Tx queues is not yet implemented\n"); ··· 335 343 * VFNUMQ value should be set to (number of queues - 1). A value 336 344 * of 0 means 1 queue and a value of 255 means 256 queues 337 345 */ 338 - reg = (((vsi->rxq_map[0] << VPLAN_RX_QBASE_VFFIRSTQ_S) & 339 - VPLAN_RX_QBASE_VFFIRSTQ_M) | 340 - (((max_rxq - 1) << VPLAN_RX_QBASE_VFNUMQ_S) & 341 - VPLAN_RX_QBASE_VFNUMQ_M)); 346 + reg = FIELD_PREP(VPLAN_RX_QBASE_VFFIRSTQ_M, vsi->rxq_map[0]) | 347 + FIELD_PREP(VPLAN_RX_QBASE_VFNUMQ_M, max_rxq - 1); 342 348 wr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg); 343 349 } else { 344 350 dev_err(dev, "Scattered mode for VF Rx queues is not yet implemented\n"); ··· 1318 1328 dev_dbg(ice_pf_to_dev(pf), "GLDCB_RTCTQ: 0x%08x\n", gldcb_rtctq); 1319 1329 1320 1330 /* event returns device global Rx queue number */ 1321 - queue = (gldcb_rtctq & GLDCB_RTCTQ_RXQNUM_M) >> 1322 - GLDCB_RTCTQ_RXQNUM_S; 1331 + queue = FIELD_GET(GLDCB_RTCTQ_RXQNUM_M, gldcb_rtctq); 1323 1332 1324 1333 vf = ice_get_vf_from_pfq(pf, ice_globalq_to_pfq(pf, queue)); 1325 1334 if (!vf)

+34 -41

drivers/net/ethernet/intel/ice/ice_switch.c

··· 2492 2492 2493 2493 switch (f_info->fltr_act) { 2494 2494 case ICE_FWD_TO_VSI: 2495 - act |= (f_info->fwd_id.hw_vsi_id << ICE_SINGLE_ACT_VSI_ID_S) & 2496 - ICE_SINGLE_ACT_VSI_ID_M; 2495 + act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M, 2496 + f_info->fwd_id.hw_vsi_id); 2497 2497 if (f_info->lkup_type != ICE_SW_LKUP_VLAN) 2498 2498 act |= ICE_SINGLE_ACT_VSI_FORWARDING | 2499 2499 ICE_SINGLE_ACT_VALID_BIT; 2500 2500 break; 2501 2501 case ICE_FWD_TO_VSI_LIST: 2502 2502 act |= ICE_SINGLE_ACT_VSI_LIST; 2503 - act |= (f_info->fwd_id.vsi_list_id << 2504 - ICE_SINGLE_ACT_VSI_LIST_ID_S) & 2505 - ICE_SINGLE_ACT_VSI_LIST_ID_M; 2503 + act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_LIST_ID_M, 2504 + f_info->fwd_id.vsi_list_id); 2506 2505 if (f_info->lkup_type != ICE_SW_LKUP_VLAN) 2507 2506 act |= ICE_SINGLE_ACT_VSI_FORWARDING | 2508 2507 ICE_SINGLE_ACT_VALID_BIT; 2509 2508 break; 2510 2509 case ICE_FWD_TO_Q: 2511 2510 act |= ICE_SINGLE_ACT_TO_Q; 2512 - act |= (f_info->fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) & 2513 - ICE_SINGLE_ACT_Q_INDEX_M; 2511 + act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M, 2512 + f_info->fwd_id.q_id); 2514 2513 break; 2515 2514 case ICE_DROP_PACKET: 2516 2515 act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP | ··· 2519 2520 q_rgn = f_info->qgrp_size > 0 ? 2520 2521 (u8)ilog2(f_info->qgrp_size) : 0; 2521 2522 act |= ICE_SINGLE_ACT_TO_Q; 2522 - act |= (f_info->fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) & 2523 - ICE_SINGLE_ACT_Q_INDEX_M; 2524 - act |= (q_rgn << ICE_SINGLE_ACT_Q_REGION_S) & 2525 - ICE_SINGLE_ACT_Q_REGION_M; 2523 + act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M, 2524 + f_info->fwd_id.q_id); 2525 + act |= FIELD_PREP(ICE_SINGLE_ACT_Q_REGION_M, q_rgn); 2526 2526 break; 2527 2527 default: 2528 2528 return; ··· 2647 2649 m_ent->fltr_info.fwd_id.hw_vsi_id; 2648 2650 2649 2651 act = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT; 2650 - act |= (id << ICE_LG_ACT_VSI_LIST_ID_S) & ICE_LG_ACT_VSI_LIST_ID_M; 2652 + act |= FIELD_PREP(ICE_LG_ACT_VSI_LIST_ID_M, id); 2651 2653 if (m_ent->vsi_count > 1) 2652 2654 act |= ICE_LG_ACT_VSI_LIST; 2653 2655 lg_act->act[0] = cpu_to_le32(act); ··· 2655 2657 /* Second action descriptor type */ 2656 2658 act = ICE_LG_ACT_GENERIC; 2657 2659 2658 - act |= (1 << ICE_LG_ACT_GENERIC_VALUE_S) & ICE_LG_ACT_GENERIC_VALUE_M; 2660 + act |= FIELD_PREP(ICE_LG_ACT_GENERIC_VALUE_M, 1); 2659 2661 lg_act->act[1] = cpu_to_le32(act); 2660 2662 2661 - act = (ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX << 2662 - ICE_LG_ACT_GENERIC_OFFSET_S) & ICE_LG_ACT_GENERIC_OFFSET_M; 2663 + act = FIELD_PREP(ICE_LG_ACT_GENERIC_OFFSET_M, 2664 + ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX); 2663 2665 2664 2666 /* Third action Marker value */ 2665 2667 act |= ICE_LG_ACT_GENERIC; 2666 - act |= (sw_marker << ICE_LG_ACT_GENERIC_VALUE_S) & 2667 - ICE_LG_ACT_GENERIC_VALUE_M; 2668 + act |= FIELD_PREP(ICE_LG_ACT_GENERIC_VALUE_M, sw_marker); 2668 2669 2669 2670 lg_act->act[2] = cpu_to_le32(act); 2670 2671 ··· 2672 2675 ice_aqc_opc_update_sw_rules); 2673 2676 2674 2677 /* Update the action to point to the large action ID */ 2675 - rx_tx->act = cpu_to_le32(ICE_SINGLE_ACT_PTR | 2676 - ((l_id << ICE_SINGLE_ACT_PTR_VAL_S) & 2677 - ICE_SINGLE_ACT_PTR_VAL_M)); 2678 + act = ICE_SINGLE_ACT_PTR; 2679 + act |= FIELD_PREP(ICE_SINGLE_ACT_PTR_VAL_M, l_id); 2680 + rx_tx->act = cpu_to_le32(act); 2678 2681 2679 2682 /* Use the filter rule ID of the previously created rule with single 2680 2683 * act. Once the update happens, hardware will treat this as large ··· 4423 4426 int status; 4424 4427 4425 4428 buf->num_elems = cpu_to_le16(num_items); 4426 - buf->res_type = cpu_to_le16(((type << ICE_AQC_RES_TYPE_S) & 4427 - ICE_AQC_RES_TYPE_M) | alloc_shared); 4429 + buf->res_type = cpu_to_le16(FIELD_PREP(ICE_AQC_RES_TYPE_M, type) | 4430 + alloc_shared); 4428 4431 4429 4432 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 4430 4433 if (status) ··· 4451 4454 int status; 4452 4455 4453 4456 buf->num_elems = cpu_to_le16(num_items); 4454 - buf->res_type = cpu_to_le16(((type << ICE_AQC_RES_TYPE_S) & 4455 - ICE_AQC_RES_TYPE_M) | alloc_shared); 4457 + buf->res_type = cpu_to_le16(FIELD_PREP(ICE_AQC_RES_TYPE_M, type) | 4458 + alloc_shared); 4456 4459 buf->elem[0].e.sw_resp = cpu_to_le16(counter_id); 4457 4460 4458 4461 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); ··· 4478 4481 { 4479 4482 DEFINE_FLEX(struct ice_aqc_alloc_free_res_elem, buf, elem, 1); 4480 4483 u16 buf_len = __struct_size(buf); 4484 + u16 res_type; 4481 4485 int status; 4482 4486 4483 4487 buf->num_elems = cpu_to_le16(1); 4488 + res_type = FIELD_PREP(ICE_AQC_RES_TYPE_M, type); 4484 4489 if (shared) 4485 - buf->res_type = cpu_to_le16(((type << ICE_AQC_RES_TYPE_S) & 4486 - ICE_AQC_RES_TYPE_M) | 4487 - ICE_AQC_RES_TYPE_FLAG_SHARED); 4488 - else 4489 - buf->res_type = cpu_to_le16(((type << ICE_AQC_RES_TYPE_S) & 4490 - ICE_AQC_RES_TYPE_M) & 4491 - ~ICE_AQC_RES_TYPE_FLAG_SHARED); 4490 + res_type |= ICE_AQC_RES_TYPE_FLAG_SHARED; 4492 4491 4492 + buf->res_type = cpu_to_le16(res_type); 4493 4493 buf->elem[0].e.sw_resp = cpu_to_le16(res_id); 4494 4494 status = ice_aq_alloc_free_res(hw, buf, buf_len, 4495 4495 ice_aqc_opc_share_res); ··· 5018 5024 entry->chain_idx = chain_idx; 5019 5025 content->result_indx = 5020 5026 ICE_AQ_RECIPE_RESULT_EN | 5021 - ((chain_idx << ICE_AQ_RECIPE_RESULT_DATA_S) & 5022 - ICE_AQ_RECIPE_RESULT_DATA_M); 5027 + FIELD_PREP(ICE_AQ_RECIPE_RESULT_DATA_M, 5028 + chain_idx); 5023 5029 clear_bit(chain_idx, result_idx_bm); 5024 5030 chain_idx = find_first_bit(result_idx_bm, 5025 5031 ICE_MAX_FV_WORDS); ··· 6119 6125 6120 6126 switch (rinfo->sw_act.fltr_act) { 6121 6127 case ICE_FWD_TO_VSI: 6122 - act |= (rinfo->sw_act.fwd_id.hw_vsi_id << 6123 - ICE_SINGLE_ACT_VSI_ID_S) & ICE_SINGLE_ACT_VSI_ID_M; 6128 + act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M, 6129 + rinfo->sw_act.fwd_id.hw_vsi_id); 6124 6130 act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_VALID_BIT; 6125 6131 break; 6126 6132 case ICE_FWD_TO_Q: 6127 6133 act |= ICE_SINGLE_ACT_TO_Q; 6128 - act |= (rinfo->sw_act.fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) & 6129 - ICE_SINGLE_ACT_Q_INDEX_M; 6134 + act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M, 6135 + rinfo->sw_act.fwd_id.q_id); 6130 6136 break; 6131 6137 case ICE_FWD_TO_QGRP: 6132 6138 q_rgn = rinfo->sw_act.qgrp_size > 0 ? 6133 6139 (u8)ilog2(rinfo->sw_act.qgrp_size) : 0; 6134 6140 act |= ICE_SINGLE_ACT_TO_Q; 6135 - act |= (rinfo->sw_act.fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) & 6136 - ICE_SINGLE_ACT_Q_INDEX_M; 6137 - act |= (q_rgn << ICE_SINGLE_ACT_Q_REGION_S) & 6138 - ICE_SINGLE_ACT_Q_REGION_M; 6141 + act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M, 6142 + rinfo->sw_act.fwd_id.q_id); 6143 + act |= FIELD_PREP(ICE_SINGLE_ACT_Q_REGION_M, q_rgn); 6139 6144 break; 6140 6145 case ICE_DROP_PACKET: 6141 6146 act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP |

+3 -3

drivers/net/ethernet/intel/ice/ice_txrx.c

··· 1493 1493 * be static in non-adaptive mode (user configured) 1494 1494 */ 1495 1495 wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), 1496 - ((ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) & 1497 - GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | 1498 - GLINT_DYN_CTL_WB_ON_ITR_M); 1496 + FIELD_PREP(GLINT_DYN_CTL_ITR_INDX_M, ICE_ITR_NONE) | 1497 + FIELD_PREP(GLINT_DYN_CTL_INTENA_MSK_M, 1) | 1498 + FIELD_PREP(GLINT_DYN_CTL_WB_ON_ITR_M, 1)); 1499 1499 1500 1500 q_vector->wb_on_itr = true; 1501 1501 }

+1 -1

drivers/net/ethernet/intel/ice/ice_virtchnl.c

··· 3102 3102 { 3103 3103 struct ice_vlan vlan = { 0 }; 3104 3104 3105 - vlan.prio = (vc_vlan->tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 3105 + vlan.prio = FIELD_GET(VLAN_PRIO_MASK, vc_vlan->tci); 3106 3106 vlan.vid = vc_vlan->tci & VLAN_VID_MASK; 3107 3107 vlan.tpid = vc_vlan->tpid; 3108 3108

+5 -8

drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c

··· 1463 1463 int ret; 1464 1464 1465 1465 stat_err = le16_to_cpu(ctx->rx_desc.wb.status_error0); 1466 - if (((stat_err & ICE_FXD_FLTR_WB_QW1_DD_M) >> 1467 - ICE_FXD_FLTR_WB_QW1_DD_S) != ICE_FXD_FLTR_WB_QW1_DD_YES) { 1466 + if (FIELD_GET(ICE_FXD_FLTR_WB_QW1_DD_M, stat_err) != 1467 + ICE_FXD_FLTR_WB_QW1_DD_YES) { 1468 1468 *status = VIRTCHNL_FDIR_FAILURE_RULE_NORESOURCE; 1469 1469 dev_err(dev, "VF %d: Desc Done not set\n", vf->vf_id); 1470 1470 ret = -EINVAL; 1471 1471 goto err_exit; 1472 1472 } 1473 1473 1474 - prog_id = (stat_err & ICE_FXD_FLTR_WB_QW1_PROG_ID_M) >> 1475 - ICE_FXD_FLTR_WB_QW1_PROG_ID_S; 1474 + prog_id = FIELD_GET(ICE_FXD_FLTR_WB_QW1_PROG_ID_M, stat_err); 1476 1475 if (prog_id == ICE_FXD_FLTR_WB_QW1_PROG_ADD && 1477 1476 ctx->v_opcode != VIRTCHNL_OP_ADD_FDIR_FILTER) { 1478 1477 dev_err(dev, "VF %d: Desc show add, but ctx not", ··· 1490 1491 goto err_exit; 1491 1492 } 1492 1493 1493 - error = (stat_err & ICE_FXD_FLTR_WB_QW1_FAIL_M) >> 1494 - ICE_FXD_FLTR_WB_QW1_FAIL_S; 1494 + error = FIELD_GET(ICE_FXD_FLTR_WB_QW1_FAIL_M, stat_err); 1495 1495 if (error == ICE_FXD_FLTR_WB_QW1_FAIL_YES) { 1496 1496 if (prog_id == ICE_FXD_FLTR_WB_QW1_PROG_ADD) { 1497 1497 dev_err(dev, "VF %d, Failed to add FDIR rule due to no space in the table", ··· 1505 1507 goto err_exit; 1506 1508 } 1507 1509 1508 - error = (stat_err & ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M) >> 1509 - ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S; 1510 + error = FIELD_GET(ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M, stat_err); 1510 1511 if (error == ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES) { 1511 1512 dev_err(dev, "VF %d: Profile matching error", vf->vf_id); 1512 1513 *status = VIRTCHNL_FDIR_FAILURE_RULE_NORESOURCE;

+22 -19

drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c

··· 131 131 { 132 132 struct ice_hw *hw = &vsi->back->hw; 133 133 struct ice_vsi_ctx *ctxt; 134 + u8 *ivf; 134 135 int err; 135 136 136 137 /* do not allow modifying VLAN stripping when a port VLAN is configured ··· 144 143 if (!ctxt) 145 144 return -ENOMEM; 146 145 146 + ivf = &ctxt->info.inner_vlan_flags; 147 + 147 148 /* Here we are configuring what the VSI should do with the VLAN tag in 148 149 * the Rx packet. We can either leave the tag in the packet or put it in 149 150 * the Rx descriptor. 150 151 */ 151 - if (ena) 152 + if (ena) { 152 153 /* Strip VLAN tag from Rx packet and put it in the desc */ 153 - ctxt->info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH; 154 - else 154 + *ivf = FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_EMODE_M, 155 + ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH); 156 + } else { 155 157 /* Disable stripping. Leave tag in packet */ 156 - ctxt->info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING; 158 + *ivf = FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_EMODE_M, 159 + ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING); 160 + } 157 161 158 162 /* Allow all packets untagged/tagged */ 159 - ctxt->info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 163 + *ivf |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL; 160 164 161 165 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID); 162 166 ··· 487 481 ctxt->info.outer_vlan_flags = vsi->info.outer_vlan_flags & 488 482 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M); 489 483 ctxt->info.outer_vlan_flags |= 490 - ((ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH << 491 - ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | 492 - ((tag_type << ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 493 - ICE_AQ_VSI_OUTER_TAG_TYPE_M)); 484 + /* we want EMODE_SHOW_BOTH, but that value is zero, so the line 485 + * above clears it well enough that we don't need to try to set 486 + * zero here, so just do the tag type 487 + */ 488 + FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, tag_type); 494 489 495 490 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 496 491 if (err) ··· 596 589 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M | 597 590 ICE_AQ_VSI_OUTER_TAG_TYPE_M); 598 591 ctxt->info.outer_vlan_flags |= 599 - ((ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << 600 - ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 601 - ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M) | 602 - ((tag_type << ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 603 - ICE_AQ_VSI_OUTER_TAG_TYPE_M); 592 + FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M, 593 + ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL) | 594 + FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, tag_type); 604 595 605 596 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 606 597 if (err) ··· 647 642 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M); 648 643 ctxt->info.outer_vlan_flags |= 649 644 ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC | 650 - ((ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL << 651 - ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) & 652 - ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M); 645 + FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M, 646 + ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL); 653 647 654 648 err = ice_update_vsi(hw, vsi->idx, ctxt, NULL); 655 649 if (err) ··· 706 702 ctxt->info.outer_vlan_flags = 707 703 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW << 708 704 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | 709 - ((tag_type << ICE_AQ_VSI_OUTER_TAG_TYPE_S) & 710 - ICE_AQ_VSI_OUTER_TAG_TYPE_M) | 705 + FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, tag_type) | 711 706 ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC | 712 707 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED << 713 708 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) |

+3 -4

drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c

··· 328 328 329 329 if (offload->tso_segs) { 330 330 qw1 |= IDPF_TX_CTX_DESC_TSO << IDPF_TXD_CTX_QW1_CMD_S; 331 - qw1 |= ((u64)offload->tso_len << IDPF_TXD_CTX_QW1_TSO_LEN_S) & 332 - IDPF_TXD_CTX_QW1_TSO_LEN_M; 333 - qw1 |= ((u64)offload->mss << IDPF_TXD_CTX_QW1_MSS_S) & 334 - IDPF_TXD_CTX_QW1_MSS_M; 331 + qw1 |= FIELD_PREP(IDPF_TXD_CTX_QW1_TSO_LEN_M, 332 + offload->tso_len); 333 + qw1 |= FIELD_PREP(IDPF_TXD_CTX_QW1_MSS_M, offload->mss); 335 334 336 335 u64_stats_update_begin(&txq->stats_sync); 337 336 u64_stats_inc(&txq->q_stats.tx.lso_pkts);

+27 -31

drivers/net/ethernet/intel/idpf/idpf_txrx.c

··· 505 505 506 506 /* store the buffer ID and the SW maintained GEN bit to the refillq */ 507 507 refillq->ring[nta] = 508 - ((buf_id << IDPF_RX_BI_BUFID_S) & IDPF_RX_BI_BUFID_M) | 509 - (!!(test_bit(__IDPF_Q_GEN_CHK, refillq->flags)) << 510 - IDPF_RX_BI_GEN_S); 508 + FIELD_PREP(IDPF_RX_BI_BUFID_M, buf_id) | 509 + FIELD_PREP(IDPF_RX_BI_GEN_M, 510 + test_bit(__IDPF_Q_GEN_CHK, refillq->flags)); 511 511 512 512 if (unlikely(++nta == refillq->desc_count)) { 513 513 nta = 0; ··· 1825 1825 u16 gen; 1826 1826 1827 1827 /* if the descriptor isn't done, no work yet to do */ 1828 - gen = (le16_to_cpu(tx_desc->qid_comptype_gen) & 1829 - IDPF_TXD_COMPLQ_GEN_M) >> IDPF_TXD_COMPLQ_GEN_S; 1828 + gen = le16_get_bits(tx_desc->qid_comptype_gen, 1829 + IDPF_TXD_COMPLQ_GEN_M); 1830 1830 if (test_bit(__IDPF_Q_GEN_CHK, complq->flags) != gen) 1831 1831 break; 1832 1832 1833 1833 /* Find necessary info of TX queue to clean buffers */ 1834 - rel_tx_qid = (le16_to_cpu(tx_desc->qid_comptype_gen) & 1835 - IDPF_TXD_COMPLQ_QID_M) >> IDPF_TXD_COMPLQ_QID_S; 1834 + rel_tx_qid = le16_get_bits(tx_desc->qid_comptype_gen, 1835 + IDPF_TXD_COMPLQ_QID_M); 1836 1836 if (rel_tx_qid >= complq->txq_grp->num_txq || 1837 1837 !complq->txq_grp->txqs[rel_tx_qid]) { 1838 1838 dev_err(&complq->vport->adapter->pdev->dev, ··· 1842 1842 tx_q = complq->txq_grp->txqs[rel_tx_qid]; 1843 1843 1844 1844 /* Determine completion type */ 1845 - ctype = (le16_to_cpu(tx_desc->qid_comptype_gen) & 1846 - IDPF_TXD_COMPLQ_COMPL_TYPE_M) >> 1847 - IDPF_TXD_COMPLQ_COMPL_TYPE_S; 1845 + ctype = le16_get_bits(tx_desc->qid_comptype_gen, 1846 + IDPF_TXD_COMPLQ_COMPL_TYPE_M); 1848 1847 switch (ctype) { 1849 1848 case IDPF_TXD_COMPLT_RE: 1850 1849 hw_head = le16_to_cpu(tx_desc->q_head_compl_tag.q_head); ··· 1944 1945 u16 td_cmd, u16 size) 1945 1946 { 1946 1947 desc->q.qw1.cmd_dtype = 1947 - cpu_to_le16(params->dtype & IDPF_FLEX_TXD_QW1_DTYPE_M); 1948 + le16_encode_bits(params->dtype, IDPF_FLEX_TXD_QW1_DTYPE_M); 1948 1949 desc->q.qw1.cmd_dtype |= 1949 - cpu_to_le16((td_cmd << IDPF_FLEX_TXD_QW1_CMD_S) & 1950 - IDPF_FLEX_TXD_QW1_CMD_M); 1951 - desc->q.qw1.buf_size = cpu_to_le16((u16)size); 1950 + le16_encode_bits(td_cmd, IDPF_FLEX_TXD_QW1_CMD_M); 1951 + desc->q.qw1.buf_size = cpu_to_le16(size); 1952 1952 desc->q.qw1.l2tags.l2tag1 = cpu_to_le16(params->td_tag); 1953 1953 } 1954 1954 ··· 2841 2843 qword1); 2842 2844 csum->ipv6exadd = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_IPV6EXADD_M, 2843 2845 qword0); 2844 - csum->raw_csum_inv = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_M, 2845 - le16_to_cpu(rx_desc->ptype_err_fflags0)); 2846 + csum->raw_csum_inv = 2847 + le16_get_bits(rx_desc->ptype_err_fflags0, 2848 + VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_M); 2846 2849 csum->raw_csum = le16_to_cpu(rx_desc->misc.raw_cs); 2847 2850 } 2848 2851 ··· 2937 2938 struct idpf_rx_ptype_decoded decoded; 2938 2939 u16 rx_ptype; 2939 2940 2940 - rx_ptype = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M, 2941 - le16_to_cpu(rx_desc->ptype_err_fflags0)); 2941 + rx_ptype = le16_get_bits(rx_desc->ptype_err_fflags0, 2942 + VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M); 2942 2943 2943 2944 decoded = rxq->vport->rx_ptype_lkup[rx_ptype]; 2944 2945 /* If we don't know the ptype we can't do anything else with it. Just ··· 2952 2953 2953 2954 skb->protocol = eth_type_trans(skb, rxq->vport->netdev); 2954 2955 2955 - if (FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M, 2956 - le16_to_cpu(rx_desc->hdrlen_flags))) 2956 + if (le16_get_bits(rx_desc->hdrlen_flags, 2957 + VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M)) 2957 2958 return idpf_rx_rsc(rxq, skb, rx_desc, &decoded); 2958 2959 2959 2960 idpf_rx_splitq_extract_csum_bits(rx_desc, &csum_bits); ··· 3147 3148 dma_rmb(); 3148 3149 3149 3150 /* if the descriptor isn't done, no work yet to do */ 3150 - gen_id = le16_to_cpu(rx_desc->pktlen_gen_bufq_id); 3151 - gen_id = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M, gen_id); 3151 + gen_id = le16_get_bits(rx_desc->pktlen_gen_bufq_id, 3152 + VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M); 3152 3153 3153 3154 if (test_bit(__IDPF_Q_GEN_CHK, rxq->flags) != gen_id) 3154 3155 break; ··· 3163 3164 continue; 3164 3165 } 3165 3166 3166 - pkt_len = le16_to_cpu(rx_desc->pktlen_gen_bufq_id); 3167 - pkt_len = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M, 3168 - pkt_len); 3167 + pkt_len = le16_get_bits(rx_desc->pktlen_gen_bufq_id, 3168 + VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M); 3169 3169 3170 3170 hbo = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_HBO_M, 3171 3171 rx_desc->status_err0_qw1); ··· 3181 3183 goto bypass_hsplit; 3182 3184 } 3183 3185 3184 - hdr_len = le16_to_cpu(rx_desc->hdrlen_flags); 3185 - hdr_len = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M, 3186 - hdr_len); 3186 + hdr_len = le16_get_bits(rx_desc->hdrlen_flags, 3187 + VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M); 3187 3188 3188 3189 bypass_hsplit: 3189 - bufq_id = le16_to_cpu(rx_desc->pktlen_gen_bufq_id); 3190 - bufq_id = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M, 3191 - bufq_id); 3190 + bufq_id = le16_get_bits(rx_desc->pktlen_gen_bufq_id, 3191 + VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M); 3192 3192 3193 3193 rxq_set = container_of(rxq, struct idpf_rxq_set, rxq); 3194 3194 if (!bufq_id)

+11 -18

drivers/net/ethernet/intel/igb/e1000_82575.c

··· 222 222 } 223 223 224 224 /* set lan id */ 225 - hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 226 - E1000_STATUS_FUNC_SHIFT; 225 + hw->bus.func = FIELD_GET(E1000_STATUS_FUNC_MASK, rd32(E1000_STATUS)); 227 226 228 227 /* Set phy->phy_addr and phy->id. */ 229 228 ret_val = igb_get_phy_id_82575(hw); ··· 261 262 if (ret_val) 262 263 goto out; 263 264 264 - data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 265 - E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 265 + data = FIELD_GET(E1000_M88E1112_MAC_CTRL_1_MODE_MASK, 266 + data); 266 267 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 267 268 data == E1000_M88E1112_AUTO_COPPER_BASEX) 268 269 hw->mac.ops.check_for_link = ··· 329 330 u32 eecd = rd32(E1000_EECD); 330 331 u16 size; 331 332 332 - size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 333 - E1000_EECD_SIZE_EX_SHIFT); 333 + size = FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd); 334 334 335 335 /* Added to a constant, "size" becomes the left-shift value 336 336 * for setting word_size. ··· 2796 2798 return 0; 2797 2799 2798 2800 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2799 - if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2801 + if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg) 2800 2802 != NVM_ETS_TYPE_EMC) 2801 2803 return E1000_NOT_IMPLEMENTED; 2802 2804 ··· 2806 2808 2807 2809 for (i = 1; i < num_sensors; i++) { 2808 2810 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2809 - sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2810 - NVM_ETS_DATA_INDEX_SHIFT); 2811 - sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2812 - NVM_ETS_DATA_LOC_SHIFT); 2811 + sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor); 2812 + sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor); 2813 2813 2814 2814 if (sensor_location != 0) 2815 2815 hw->phy.ops.read_i2c_byte(hw, ··· 2855 2859 return 0; 2856 2860 2857 2861 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2858 - if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2862 + if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg) 2859 2863 != NVM_ETS_TYPE_EMC) 2860 2864 return E1000_NOT_IMPLEMENTED; 2861 2865 2862 - low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2863 - NVM_ETS_LTHRES_DELTA_SHIFT); 2866 + low_thresh_delta = FIELD_GET(NVM_ETS_LTHRES_DELTA_MASK, ets_cfg); 2864 2867 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2865 2868 2866 2869 for (i = 1; i <= num_sensors; i++) { 2867 2870 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2868 - sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2869 - NVM_ETS_DATA_INDEX_SHIFT); 2870 - sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2871 - NVM_ETS_DATA_LOC_SHIFT); 2871 + sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor); 2872 + sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor); 2872 2873 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2873 2874 2874 2875 hw->phy.ops.write_i2c_byte(hw,

+10 -9

drivers/net/ethernet/intel/igb/e1000_i210.c

··· 5 5 * e1000_i211 6 6 */ 7 7 8 - #include <linux/types.h> 8 + #include <linux/bitfield.h> 9 9 #include <linux/if_ether.h> 10 - 10 + #include <linux/types.h> 11 11 #include "e1000_hw.h" 12 12 #include "e1000_i210.h" 13 13 ··· 473 473 /* Check if we have second version location used */ 474 474 else if ((i == 1) && 475 475 ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) { 476 - version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; 476 + version = FIELD_GET(E1000_INVM_VER_FIELD_ONE, *record); 477 477 status = 0; 478 478 break; 479 479 } ··· 483 483 else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) && 484 484 ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) && 485 485 (i != 1))) { 486 - version = (*next_record & E1000_INVM_VER_FIELD_TWO) 487 - >> 13; 486 + version = FIELD_GET(E1000_INVM_VER_FIELD_TWO, 487 + *next_record); 488 488 status = 0; 489 489 break; 490 490 } ··· 493 493 */ 494 494 else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) && 495 495 ((*record & 0x3) == 0)) { 496 - version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; 496 + version = FIELD_GET(E1000_INVM_VER_FIELD_ONE, *record); 497 497 status = 0; 498 498 break; 499 499 } 500 500 } 501 501 502 502 if (!status) { 503 - invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK) 504 - >> E1000_INVM_MAJOR_SHIFT; 503 + invm_ver->invm_major = FIELD_GET(E1000_INVM_MAJOR_MASK, 504 + version); 505 505 invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK; 506 506 } 507 507 /* Read Image Type */ ··· 520 520 ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) || 521 521 ((((*record & 0x3) != 0) && (i != 1)))) { 522 522 invm_ver->invm_img_type = 523 - (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23; 523 + FIELD_GET(E1000_INVM_IMGTYPE_FIELD, 524 + *next_record); 524 525 status = 0; 525 526 break; 526 527 }

+1 -1

drivers/net/ethernet/intel/igb/e1000_mac.c

··· 56 56 } 57 57 58 58 reg = rd32(E1000_STATUS); 59 - bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 59 + bus->func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg); 60 60 61 61 return 0; 62 62 }

+8 -10

drivers/net/ethernet/intel/igb/e1000_nvm.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 3 4 - #include <linux/if_ether.h> 4 + #include <linux/bitfield.h> 5 5 #include <linux/delay.h> 6 - 6 + #include <linux/if_ether.h> 7 7 #include "e1000_mac.h" 8 8 #include "e1000_nvm.h" 9 9 ··· 708 708 */ 709 709 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { 710 710 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 711 - fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 712 - >> NVM_MAJOR_SHIFT; 713 - fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) 714 - >> NVM_MINOR_SHIFT; 711 + fw_vers->eep_major = FIELD_GET(NVM_MAJOR_MASK, 712 + fw_version); 713 + fw_vers->eep_minor = FIELD_GET(NVM_MINOR_MASK, 714 + fw_version); 715 715 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); 716 716 goto etrack_id; 717 717 } ··· 753 753 return; 754 754 } 755 755 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 756 - fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 757 - >> NVM_MAJOR_SHIFT; 756 + fw_vers->eep_major = FIELD_GET(NVM_MAJOR_MASK, fw_version); 758 757 759 758 /* check for old style version format in newer images*/ 760 759 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { 761 760 eeprom_verl = (fw_version & NVM_COMB_VER_MASK); 762 761 } else { 763 - eeprom_verl = (fw_version & NVM_MINOR_MASK) 764 - >> NVM_MINOR_SHIFT; 762 + eeprom_verl = FIELD_GET(NVM_MINOR_MASK, fw_version); 765 763 } 766 764 /* Convert minor value to hex before assigning to output struct 767 765 * Val to be converted will not be higher than 99, per tool output

+7 -10

drivers/net/ethernet/intel/igb/e1000_phy.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 3 4 - #include <linux/if_ether.h> 4 + #include <linux/bitfield.h> 5 5 #include <linux/delay.h> 6 - 6 + #include <linux/if_ether.h> 7 7 #include "e1000_mac.h" 8 8 #include "e1000_phy.h" 9 9 ··· 255 255 } 256 256 257 257 /* Need to byte-swap the 16-bit value. */ 258 - *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 258 + *data = ((i2ccmd >> 8) & 0x00FF) | FIELD_PREP(0xFF00, i2ccmd); 259 259 260 260 return 0; 261 261 } ··· 282 282 } 283 283 284 284 /* Swap the data bytes for the I2C interface */ 285 - phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 285 + phy_data_swapped = ((data >> 8) & 0x00FF) | FIELD_PREP(0xFF00, data); 286 286 287 287 /* Set up Op-code, Phy Address, and register address in the I2CCMD 288 288 * register. The MAC will take care of interfacing with the ··· 1682 1682 if (ret_val) 1683 1683 goto out; 1684 1684 1685 - index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1686 - M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1685 + index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data); 1687 1686 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) { 1688 1687 ret_val = -E1000_ERR_PHY; 1689 1688 goto out; ··· 1795 1796 if (ret_val) 1796 1797 goto out; 1797 1798 1798 - index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1799 - M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1799 + index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data); 1800 1800 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) { 1801 1801 ret_val = -E1000_ERR_PHY; 1802 1802 goto out; ··· 2576 2578 if (ret_val) 2577 2579 goto out; 2578 2580 2579 - length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2580 - I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2581 + length = FIELD_GET(I82580_DSTATUS_CABLE_LENGTH, phy_data); 2581 2582 2582 2583 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2583 2584 ret_val = -E1000_ERR_PHY;

+5 -6

drivers/net/ethernet/intel/igb/igb_ethtool.c

··· 2432 2432 } 2433 2433 } 2434 2434 2435 - #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2435 + #define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX)) 2436 2436 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter, 2437 2437 struct ethtool_rxnfc *cmd) 2438 2438 { ··· 2711 2711 etqf |= (etype & E1000_ETQF_ETYPE_MASK); 2712 2712 2713 2713 etqf &= ~E1000_ETQF_QUEUE_MASK; 2714 - etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT) 2715 - & E1000_ETQF_QUEUE_MASK); 2714 + etqf |= FIELD_PREP(E1000_ETQF_QUEUE_MASK, input->action); 2716 2715 etqf |= E1000_ETQF_QUEUE_ENABLE; 2717 2716 2718 2717 wr32(E1000_ETQF(i), etqf); ··· 2730 2731 u32 vlapqf; 2731 2732 2732 2733 vlapqf = rd32(E1000_VLAPQF); 2733 - vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) 2734 - >> VLAN_PRIO_SHIFT; 2734 + vlan_priority = FIELD_GET(VLAN_PRIO_MASK, 2735 + ntohs(input->filter.vlan_tci)); 2735 2736 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK; 2736 2737 2737 2738 /* check whether this vlan prio is already set */ ··· 2814 2815 u8 vlan_priority; 2815 2816 u32 vlapqf; 2816 2817 2817 - vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 2818 + vlan_priority = FIELD_GET(VLAN_PRIO_MASK, vlan_tci); 2818 2819 2819 2820 vlapqf = rd32(E1000_VLAPQF); 2820 2821 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);

+5 -8

drivers/net/ethernet/intel/igb/igb_main.c

··· 7295 7295 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7296 7296 u32 *msgbuf, u32 vf) 7297 7297 { 7298 - int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7298 + int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7299 7299 u16 *hash_list = (u16 *)&msgbuf[1]; 7300 7300 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7301 7301 int i; ··· 7555 7555 7556 7556 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7557 7557 { 7558 - int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 7558 + int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7559 7559 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7560 7560 int ret; 7561 7561 ··· 9810 9810 tx_rate; 9811 9811 9812 9812 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9813 - bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 9814 - E1000_RTTBCNRC_RF_INT_MASK); 9813 + bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9815 9814 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9816 9815 } else { 9817 9816 bcnrc_val = 0; ··· 9999 10000 hwm = 64 * (pba - 6); 10000 10001 reg = rd32(E1000_FCRTC); 10001 10002 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10002 - reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 10003 - & E1000_FCRTC_RTH_COAL_MASK); 10003 + reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10004 10004 wr32(E1000_FCRTC, reg); 10005 10005 10006 10006 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max ··· 10008 10010 dmac_thr = pba - 10; 10009 10011 reg = rd32(E1000_DMACR); 10010 10012 reg &= ~E1000_DMACR_DMACTHR_MASK; 10011 - reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 10012 - & E1000_DMACR_DMACTHR_MASK); 10013 + reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10013 10014 10014 10015 /* transition to L0x or L1 if available..*/ 10015 10016 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);

+1

drivers/net/ethernet/intel/igbvf/mbx.c

+16 -17

drivers/net/ethernet/intel/igbvf/netdev.c

··· 3 3 4 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 5 6 - #include <linux/module.h> 7 - #include <linux/types.h> 8 - #include <linux/init.h> 9 - #include <linux/pci.h> 10 - #include <linux/vmalloc.h> 11 - #include <linux/pagemap.h> 6 + #include <linux/bitfield.h> 12 7 #include <linux/delay.h> 13 - #include <linux/netdevice.h> 14 - #include <linux/tcp.h> 15 - #include <linux/ipv6.h> 16 - #include <linux/slab.h> 17 - #include <net/checksum.h> 18 - #include <net/ip6_checksum.h> 19 - #include <linux/mii.h> 20 8 #include <linux/ethtool.h> 21 9 #include <linux/if_vlan.h> 10 + #include <linux/init.h> 11 + #include <linux/ipv6.h> 12 + #include <linux/mii.h> 13 + #include <linux/module.h> 14 + #include <linux/netdevice.h> 15 + #include <linux/pagemap.h> 16 + #include <linux/pci.h> 22 17 #include <linux/prefetch.h> 23 18 #include <linux/sctp.h> 24 - 19 + #include <linux/slab.h> 20 + #include <linux/tcp.h> 21 + #include <linux/types.h> 22 + #include <linux/vmalloc.h> 23 + #include <net/checksum.h> 24 + #include <net/ip6_checksum.h> 25 25 #include "igbvf.h" 26 26 27 27 char igbvf_driver_name[] = "igbvf"; ··· 273 273 * that case, it fills the header buffer and spills the rest 274 274 * into the page. 275 275 */ 276 - hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info) 277 - & E1000_RXDADV_HDRBUFLEN_MASK) >> 278 - E1000_RXDADV_HDRBUFLEN_SHIFT; 276 + hlen = le16_get_bits(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info, 277 + E1000_RXDADV_HDRBUFLEN_MASK); 279 278 if (hlen > adapter->rx_ps_hdr_size) 280 279 hlen = adapter->rx_ps_hdr_size; 281 280

+2 -4

drivers/net/ethernet/intel/igc/igc_base.c

··· 68 68 u32 eecd = rd32(IGC_EECD); 69 69 u16 size; 70 70 71 - size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >> 72 - IGC_EECD_SIZE_EX_SHIFT); 71 + size = FIELD_GET(IGC_EECD_SIZE_EX_MASK, eecd); 73 72 74 73 /* Added to a constant, "size" becomes the left-shift value 75 74 * for setting word_size. ··· 161 162 phy->reset_delay_us = 100; 162 163 163 164 /* set lan id */ 164 - hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >> 165 - IGC_STATUS_FUNC_SHIFT; 165 + hw->bus.func = FIELD_GET(IGC_STATUS_FUNC_MASK, rd32(IGC_STATUS)); 166 166 167 167 /* Make sure the PHY is in a good state. Several people have reported 168 168 * firmware leaving the PHY's page select register set to something

+3 -3

drivers/net/ethernet/intel/igc/igc_i225.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright (c) 2018 Intel Corporation */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include <linux/delay.h> 5 6 6 7 #include "igc_hw.h" ··· 579 578 580 579 /* Calculate tw_system (nsec). */ 581 580 if (speed == SPEED_100) { 582 - tw_system = ((rd32(IGC_EEE_SU) & 583 - IGC_TW_SYSTEM_100_MASK) >> 584 - IGC_TW_SYSTEM_100_SHIFT) * 500; 581 + tw_system = FIELD_GET(IGC_TW_SYSTEM_100_MASK, 582 + rd32(IGC_EEE_SU)) * 500; 585 583 } else { 586 584 tw_system = (rd32(IGC_EEE_SU) & 587 585 IGC_TW_SYSTEM_1000_MASK) * 500;

+4 -6

drivers/net/ethernet/intel/igc/igc_main.c

··· 3452 3452 3453 3453 /* Configure filter */ 3454 3454 queuing = input->length & IGC_FHFT_LENGTH_MASK; 3455 - queuing |= (input->rx_queue << IGC_FHFT_QUEUE_SHIFT) & IGC_FHFT_QUEUE_MASK; 3456 - queuing |= (input->prio << IGC_FHFT_PRIO_SHIFT) & IGC_FHFT_PRIO_MASK; 3455 + queuing |= FIELD_PREP(IGC_FHFT_QUEUE_MASK, input->rx_queue); 3456 + queuing |= FIELD_PREP(IGC_FHFT_PRIO_MASK, input->prio); 3457 3457 3458 3458 if (input->immediate_irq) 3459 3459 queuing |= IGC_FHFT_IMM_INT; ··· 3712 3712 } 3713 3713 3714 3714 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3715 - int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >> 3716 - VLAN_PRIO_SHIFT; 3715 + int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci); 3717 3716 3718 3717 err = igc_add_vlan_prio_filter(adapter, prio, rule->action); 3719 3718 if (err) ··· 3734 3735 igc_del_etype_filter(adapter, rule->filter.etype); 3735 3736 3736 3737 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3737 - int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >> 3738 - VLAN_PRIO_SHIFT; 3738 + int prio = FIELD_GET(VLAN_PRIO_MASK, rule->filter.vlan_tci); 3739 3739 3740 3740 igc_del_vlan_prio_filter(adapter, prio); 3741 3741 }

+3 -2

drivers/net/ethernet/intel/igc/igc_phy.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Copyright (c) 2018 Intel Corporation */ 3 3 4 + #include <linux/bitfield.h> 4 5 #include "igc_phy.h" 5 6 6 7 /** ··· 727 726 */ 728 727 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 729 728 { 730 - u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 729 + u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset); 731 730 s32 ret_val; 732 731 733 732 offset = offset & GPY_REG_MASK; ··· 758 757 */ 759 758 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 760 759 { 761 - u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 760 + u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset); 762 761 s32 ret_val; 763 762 764 763 offset = offset & GPY_REG_MASK;

+1 -1

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

··· 794 794 795 795 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 796 796 rar_high &= ~IXGBE_RAH_VIND_MASK; 797 - rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 797 + rar_high |= FIELD_PREP(IXGBE_RAH_VIND_MASK, vmdq); 798 798 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 799 799 return 0; 800 800 }

+14 -16

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

··· 684 684 u32 reg; 685 685 686 686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 687 - bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 687 + bus->func = FIELD_GET(IXGBE_STATUS_LAN_ID, reg); 688 688 bus->lan_id = bus->func; 689 689 690 690 /* check for a port swap */ ··· 695 695 /* Get MAC instance from EEPROM for configuring CS4227 */ 696 696 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 697 697 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 698 - bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 699 - IXGBE_EE_CTRL_4_INST_ID_SHIFT; 698 + bus->instance_id = FIELD_GET(IXGBE_EE_CTRL_4_INST_ID, 699 + ee_ctrl_4); 700 700 } 701 701 } 702 702 ··· 870 870 * SPI EEPROM is assumed here. This code would need to 871 871 * change if a future EEPROM is not SPI. 872 872 */ 873 - eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 874 - IXGBE_EEC_SIZE_SHIFT); 873 + eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec); 875 874 eeprom->word_size = BIT(eeprom_size + 876 - IXGBE_EEPROM_WORD_SIZE_SHIFT); 875 + IXGBE_EEPROM_WORD_SIZE_SHIFT); 877 876 } 878 877 879 878 if (eec & IXGBE_EEC_ADDR_SIZE) ··· 3945 3946 if (status) 3946 3947 return status; 3947 3948 3948 - sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3949 - IXGBE_ETS_DATA_INDEX_SHIFT); 3950 - sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3951 - IXGBE_ETS_DATA_LOC_SHIFT); 3949 + sensor_index = FIELD_GET(IXGBE_ETS_DATA_INDEX_MASK, 3950 + ets_sensor); 3951 + sensor_location = FIELD_GET(IXGBE_ETS_DATA_LOC_MASK, 3952 + ets_sensor); 3952 3953 3953 3954 if (sensor_location != 0) { 3954 3955 status = hw->phy.ops.read_i2c_byte(hw, ··· 3992 3993 if (status) 3993 3994 return status; 3994 3995 3995 - low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3996 - IXGBE_ETS_LTHRES_DELTA_SHIFT); 3996 + low_thresh_delta = FIELD_GET(IXGBE_ETS_LTHRES_DELTA_MASK, ets_cfg); 3997 3997 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3998 3998 if (num_sensors > IXGBE_MAX_SENSORS) 3999 3999 num_sensors = IXGBE_MAX_SENSORS; ··· 4006 4008 ets_offset + 1 + i); 4007 4009 continue; 4008 4010 } 4009 - sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4010 - IXGBE_ETS_DATA_INDEX_SHIFT); 4011 - sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4012 - IXGBE_ETS_DATA_LOC_SHIFT); 4011 + sensor_index = FIELD_GET(IXGBE_ETS_DATA_INDEX_MASK, 4012 + ets_sensor); 4013 + sensor_location = FIELD_GET(IXGBE_ETS_DATA_LOC_MASK, 4014 + ets_sensor); 4013 4015 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4014 4016 4015 4017 hw->phy.ops.write_i2c_byte(hw,

+2 -2

drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c

··· 670 670 int fcoe_i_h = fcoe->offset + ((i + fcreta_size) % 671 671 fcoe->indices); 672 672 fcoe_q_h = adapter->rx_ring[fcoe_i_h]->reg_idx; 673 - fcoe_q_h = (fcoe_q_h << IXGBE_FCRETA_ENTRY_HIGH_SHIFT) & 674 - IXGBE_FCRETA_ENTRY_HIGH_MASK; 673 + fcoe_q_h = FIELD_PREP(IXGBE_FCRETA_ENTRY_HIGH_MASK, 674 + fcoe_q_h); 675 675 } 676 676 677 677 fcoe_i = fcoe->offset + (i % fcoe->indices);

+1 -1

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

··· 11371 11371 if ((pf_func & 1) == (pdev->devfn & 1)) { 11372 11372 unsigned int device_id; 11373 11373 11374 - vf = (req_id & 0x7F) >> 1; 11374 + vf = FIELD_GET(0x7F, req_id); 11375 11375 e_dev_err("VF %d has caused a PCIe error\n", vf); 11376 11376 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11377 11377 "%8.8x\tdw3: %8.8x\n",

+3 -5

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

··· 276 276 return 0; 277 277 278 278 if (hw->phy.nw_mng_if_sel) { 279 - phy_addr = (hw->phy.nw_mng_if_sel & 280 - IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 281 - IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 279 + phy_addr = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD, 280 + hw->phy.nw_mng_if_sel); 282 281 if (ixgbe_probe_phy(hw, phy_addr)) 283 282 return 0; 284 283 else ··· 1447 1448 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1448 1449 if (ret_val) 1449 1450 goto err_eeprom; 1450 - control = (eword & IXGBE_CONTROL_MASK_NL) >> 1451 - IXGBE_CONTROL_SHIFT_NL; 1451 + control = FIELD_GET(IXGBE_CONTROL_MASK_NL, eword); 1452 1452 edata = eword & IXGBE_DATA_MASK_NL; 1453 1453 switch (control) { 1454 1454 case IXGBE_DELAY_NL:

+3 -5

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

··· 363 363 static int ixgbe_set_vf_multicasts(struct ixgbe_adapter *adapter, 364 364 u32 *msgbuf, u32 vf) 365 365 { 366 - int entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) 367 - >> IXGBE_VT_MSGINFO_SHIFT; 366 + int entries = FIELD_GET(IXGBE_VT_MSGINFO_MASK, msgbuf[0]); 368 367 u16 *hash_list = (u16 *)&msgbuf[1]; 369 368 struct vf_data_storage *vfinfo = &adapter->vfinfo[vf]; 370 369 struct ixgbe_hw *hw = &adapter->hw; ··· 968 969 static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter, 969 970 u32 *msgbuf, u32 vf) 970 971 { 971 - u32 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT; 972 + u32 add = FIELD_GET(IXGBE_VT_MSGINFO_MASK, msgbuf[0]); 972 973 u32 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK); 973 974 u8 tcs = adapter->hw_tcs; 974 975 ··· 991 992 u32 *msgbuf, u32 vf) 992 993 { 993 994 u8 *new_mac = ((u8 *)(&msgbuf[1])); 994 - int index = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >> 995 - IXGBE_VT_MSGINFO_SHIFT; 995 + int index = FIELD_GET(IXGBE_VT_MSGINFO_MASK, msgbuf[0]); 996 996 int err; 997 997 998 998 if (adapter->vfinfo[vf].pf_set_mac && !adapter->vfinfo[vf].trusted &&

+4 -4

drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c

··· 187 187 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 188 188 { 189 189 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 190 - u32 eec; 191 - u16 eeprom_size; 192 190 193 191 if (eeprom->type == ixgbe_eeprom_uninitialized) { 192 + u16 eeprom_size; 193 + u32 eec; 194 + 194 195 eeprom->semaphore_delay = 10; 195 196 eeprom->type = ixgbe_flash; 196 197 197 198 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 198 - eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 199 - IXGBE_EEC_SIZE_SHIFT); 199 + eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec); 200 200 eeprom->word_size = BIT(eeprom_size + 201 201 IXGBE_EEPROM_WORD_SIZE_SHIFT); 202 202

+8 -11

drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

··· 628 628 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 629 629 { 630 630 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 631 - u32 eec; 632 - u16 eeprom_size; 633 631 634 632 if (eeprom->type == ixgbe_eeprom_uninitialized) { 633 + u16 eeprom_size; 634 + u32 eec; 635 + 635 636 eeprom->semaphore_delay = 10; 636 637 eeprom->type = ixgbe_flash; 637 638 638 639 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 639 - eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 640 - IXGBE_EEC_SIZE_SHIFT); 640 + eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec); 641 641 eeprom->word_size = BIT(eeprom_size + 642 642 IXGBE_EEPROM_WORD_SIZE_SHIFT); 643 643 ··· 712 712 ret = ixgbe_iosf_wait(hw, &command); 713 713 714 714 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 715 - error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 716 - IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 715 + error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command); 717 716 hw_dbg(hw, "Failed to read, error %x\n", error); 718 717 return IXGBE_ERR_PHY; 719 718 } ··· 1411 1412 ret = ixgbe_iosf_wait(hw, &command); 1412 1413 1413 1414 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1414 - error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1415 - IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1415 + error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command); 1416 1416 hw_dbg(hw, "Failed to write, error %x\n", error); 1417 1417 return IXGBE_ERR_PHY; 1418 1418 } ··· 3220 3222 */ 3221 3223 if (hw->mac.type == ixgbe_mac_x550em_a && 3222 3224 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3223 - hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3224 - IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3225 - IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3225 + hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD, 3226 + hw->phy.nw_mng_if_sel); 3226 3227 } 3227 3228 } 3228 3229

+1

include/linux/avf/virtchnl.h

··· 5 5 #define _VIRTCHNL_H_ 6 6 7 7 #include <linux/bitops.h> 8 + #include <linux/bits.h> 8 9 #include <linux/overflow.h> 9 10 #include <uapi/linux/if_ether.h> 10 11

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