Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC fixes from Ulf Hansson:
"MMC host:
- sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1
- sdhci-of-arasan: Ensure CD logic stabilization before power-up
- sdhci-pci-gli: Mask the replay timer timeout of AER for GL9763e
MEMSTICK:
- Fix deadlock by moving removing flag earlier"
* tag 'mmc-v6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1
memstick: Fix deadlock by moving removing flag earlier
mmc: sdhci-of-arasan: Ensure CD logic stabilization before power-up
mmc: sdhci-pci-gli: GL9763e: Mask the replay timer timeout of AER
mmc: sdhci-pci-gli: GL9763e: Rename the gli_set_gl9763e() for consistency
mmc: sdhci-pci-gli: Add a new function to simplify the code
+71
-19
-1
drivers/memstick/core/memstick.c
-1
drivers/memstick/core/memstick.c
+1
drivers/memstick/host/rtsx_usb_ms.c
+1
drivers/memstick/host/rtsx_usb_ms.c
+31
-2
drivers/mmc/host/sdhci-of-arasan.c
+31
-2
drivers/mmc/host/sdhci-of-arasan.c
···
99
99
#define HIWORD_UPDATE(val, mask, shift) \
100
100
((val) << (shift) | (mask) << ((shift) + 16))
101
101
102
+
#define CD_STABLE_TIMEOUT_US 1000000
103
+
#define CD_STABLE_MAX_SLEEP_US 10
104
+
102
105
/**
103
106
* struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
104
107
*
···
209
206
* 19MHz instead
210
207
*/
211
208
#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
209
+
/* Enable CD stable check before power-up */
210
+
#define SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE BIT(3)
212
211
};
213
212
214
213
struct sdhci_arasan_of_data {
215
214
const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
216
215
const struct sdhci_pltfm_data *pdata;
217
216
const struct sdhci_arasan_clk_ops *clk_ops;
217
+
u32 quirks;
218
218
};
219
219
220
220
static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
···
520
514
return -EINVAL;
521
515
}
522
516
517
+
static void sdhci_arasan_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode,
518
+
unsigned short vdd)
519
+
{
520
+
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
521
+
struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
522
+
u32 reg;
523
+
524
+
/*
525
+
* Ensure that the card detect logic has stabilized before powering up, this is
526
+
* necessary after a host controller reset.
527
+
*/
528
+
if (mode == MMC_POWER_UP && sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE)
529
+
read_poll_timeout(sdhci_readl, reg, reg & SDHCI_CD_STABLE, CD_STABLE_MAX_SLEEP_US,
530
+
CD_STABLE_TIMEOUT_US, false, host, SDHCI_PRESENT_STATE);
531
+
532
+
sdhci_set_power_and_bus_voltage(host, mode, vdd);
533
+
}
534
+
523
535
static const struct sdhci_ops sdhci_arasan_ops = {
524
536
.set_clock = sdhci_arasan_set_clock,
525
537
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
···
545
521
.set_bus_width = sdhci_set_bus_width,
546
522
.reset = sdhci_arasan_reset,
547
523
.set_uhs_signaling = sdhci_set_uhs_signaling,
548
-
.set_power = sdhci_set_power_and_bus_voltage,
524
+
.set_power = sdhci_arasan_set_power_and_bus_voltage,
549
525
.hw_reset = sdhci_arasan_hw_reset,
550
526
};
551
527
···
594
570
.set_bus_width = sdhci_set_bus_width,
595
571
.reset = sdhci_arasan_reset,
596
572
.set_uhs_signaling = sdhci_set_uhs_signaling,
597
-
.set_power = sdhci_set_power_and_bus_voltage,
573
+
.set_power = sdhci_arasan_set_power_and_bus_voltage,
598
574
.irq = sdhci_arasan_cqhci_irq,
599
575
};
600
576
···
1471
1447
static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1472
1448
.pdata = &sdhci_arasan_zynqmp_pdata,
1473
1449
.clk_ops = &zynqmp_clk_ops,
1450
+
.quirks = SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE,
1474
1451
};
1475
1452
1476
1453
static const struct sdhci_arasan_clk_ops versal_clk_ops = {
···
1482
1457
static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1483
1458
.pdata = &sdhci_arasan_zynqmp_pdata,
1484
1459
.clk_ops = &versal_clk_ops,
1460
+
.quirks = SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE,
1485
1461
};
1486
1462
1487
1463
static const struct sdhci_arasan_clk_ops versal_net_clk_ops = {
···
1493
1467
static struct sdhci_arasan_of_data sdhci_arasan_versal_net_data = {
1494
1468
.pdata = &sdhci_arasan_versal_net_pdata,
1495
1469
.clk_ops = &versal_net_clk_ops,
1470
+
.quirks = SDHCI_ARASAN_QUIRK_ENSURE_CD_STABLE,
1496
1471
};
1497
1472
1498
1473
static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
···
1963
1936
1964
1937
if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1965
1938
sdhci_arasan_update_clockmultiplier(host, 0x0);
1939
+
1940
+
sdhci_arasan->quirks |= data->quirks;
1966
1941
1967
1942
if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1968
1943
of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
+21
-16
drivers/mmc/host/sdhci-pci-gli.c
+21
-16
drivers/mmc/host/sdhci-pci-gli.c
···
287
287
#define GLI_MAX_TUNING_LOOP 40
288
288
289
289
/* Genesys Logic chipset */
290
+
static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev)
291
+
{
292
+
int aer;
293
+
u32 value;
294
+
295
+
/* mask the replay timer timeout of AER */
296
+
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
297
+
if (aer) {
298
+
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
299
+
value |= PCI_ERR_COR_REP_TIMER;
300
+
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
301
+
}
302
+
}
303
+
290
304
static inline void gl9750_wt_on(struct sdhci_host *host)
291
305
{
292
306
u32 wt_value;
···
621
607
{
622
608
struct sdhci_pci_slot *slot = sdhci_priv(host);
623
609
struct pci_dev *pdev;
624
-
int aer;
625
610
u32 value;
626
611
627
612
pdev = slot->chip->pdev;
···
639
626
pci_set_power_state(pdev, PCI_D0);
640
627
641
628
/* mask the replay timer timeout of AER */
642
-
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
643
-
if (aer) {
644
-
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
645
-
value |= PCI_ERR_COR_REP_TIMER;
646
-
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
647
-
}
629
+
sdhci_gli_mask_replay_timer_timeout(pdev);
648
630
649
631
gl9750_wt_off(host);
650
632
}
···
814
806
static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
815
807
{
816
808
struct pci_dev *pdev = slot->chip->pdev;
817
-
int aer;
818
809
u32 value;
819
810
820
811
gl9755_wt_on(pdev);
···
848
841
pci_set_power_state(pdev, PCI_D0);
849
842
850
843
/* mask the replay timer timeout of AER */
851
-
aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
852
-
if (aer) {
853
-
pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
854
-
value |= PCI_ERR_COR_REP_TIMER;
855
-
pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
856
-
}
844
+
sdhci_gli_mask_replay_timer_timeout(pdev);
857
845
858
846
gl9755_wt_off(pdev);
859
847
}
···
1753
1751
return ret;
1754
1752
}
1755
1753
1756
-
static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
1754
+
static void gl9763e_hw_setting(struct sdhci_pci_slot *slot)
1757
1755
{
1758
1756
struct pci_dev *pdev = slot->chip->pdev;
1759
1757
u32 value;
···
1781
1779
value &= ~GLI_9763E_HS400_RXDLY;
1782
1780
value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
1783
1781
pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
1782
+
1783
+
/* mask the replay timer timeout of AER */
1784
+
sdhci_gli_mask_replay_timer_timeout(pdev);
1784
1785
1785
1786
pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1786
1787
value &= ~GLI_9763E_VHS_REV;
···
1928
1923
gli_pcie_enable_msi(slot);
1929
1924
host->mmc_host_ops.hs400_enhanced_strobe =
1930
1925
gl9763e_hs400_enhanced_strobe;
1931
-
gli_set_gl9763e(slot);
1926
+
gl9763e_hw_setting(slot);
1932
1927
sdhci_enable_v4_mode(host);
1933
1928
1934
1929
return 0;
+18
drivers/mmc/host/sdhci_am654.c
+18
drivers/mmc/host/sdhci_am654.c
···
156
156
157
157
#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
158
158
#define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1)
159
+
#define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2)
159
160
};
160
161
161
162
struct window {
···
766
765
{
767
766
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
768
767
struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
768
+
struct device *dev = mmc_dev(host->mmc);
769
769
u32 ctl_cfg_2 = 0;
770
770
u32 mask;
771
771
u32 val;
···
821
819
ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
822
820
if (ret)
823
821
goto err_cleanup_host;
822
+
823
+
if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400 &&
824
+
host->mmc->caps2 & (MMC_CAP2_HS400 | MMC_CAP2_HS400_ES)) {
825
+
dev_info(dev, "HS400 mode not supported on this silicon revision, disabling it\n");
826
+
host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
827
+
}
824
828
825
829
ret = __sdhci_add_host(host);
826
830
if (ret)
···
890
882
891
883
return 0;
892
884
}
885
+
886
+
static const struct soc_device_attribute sdhci_am654_descope_hs400[] = {
887
+
{ .family = "AM62PX", .revision = "SR1.0" },
888
+
{ .family = "AM62PX", .revision = "SR1.1" },
889
+
{ /* sentinel */ }
890
+
};
893
891
894
892
static const struct of_device_id sdhci_am654_of_match[] = {
895
893
{
···
983
969
ret = mmc_of_parse(host->mmc);
984
970
if (ret)
985
971
return dev_err_probe(dev, ret, "parsing dt failed\n");
972
+
973
+
soc = soc_device_match(sdhci_am654_descope_hs400);
974
+
if (soc)
975
+
sdhci_am654->quirks |= SDHCI_AM654_QUIRK_DISABLE_HS400;
986
976
987
977
host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch;
988
978
host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;