Merge tag 'for-5.18/parisc-4' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

+7 -24

arch/parisc/include/asm/cacheflush.h

··· 59 59 flush_kernel_icache_range_asm(s,e); \ 60 60 } while (0) 61 61 62 - #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 63 - do { \ 64 - flush_cache_page(vma, vaddr, page_to_pfn(page)); \ 65 - memcpy(dst, src, len); \ 66 - flush_kernel_dcache_range_asm((unsigned long)dst, (unsigned long)dst + len); \ 67 - } while (0) 68 - 69 - #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 70 - do { \ 71 - flush_cache_page(vma, vaddr, page_to_pfn(page)); \ 72 - memcpy(dst, src, len); \ 73 - } while (0) 74 - 75 - void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn); 62 + void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 63 + unsigned long user_vaddr, void *dst, void *src, int len); 64 + void copy_from_user_page(struct vm_area_struct *vma, struct page *page, 65 + unsigned long user_vaddr, void *dst, void *src, int len); 66 + void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, 67 + unsigned long pfn); 76 68 void flush_cache_range(struct vm_area_struct *vma, 77 69 unsigned long start, unsigned long end); 78 70 ··· 72 80 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr); 73 81 74 82 #define ARCH_HAS_FLUSH_ANON_PAGE 75 - static inline void 76 - flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) 77 - { 78 - if (PageAnon(page)) { 79 - flush_tlb_page(vma, vmaddr); 80 - preempt_disable(); 81 - flush_dcache_page_asm(page_to_phys(page), vmaddr); 82 - preempt_enable(); 83 - } 84 - } 83 + void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr); 85 84 86 85 #define ARCH_HAS_FLUSH_ON_KUNMAP 87 86 static inline void kunmap_flush_on_unmap(void *addr)

+4 -2

arch/parisc/include/asm/page.h

··· 26 26 #define copy_page(to, from) copy_page_asm((void *)(to), (void *)(from)) 27 27 28 28 struct page; 29 + struct vm_area_struct; 29 30 30 31 void clear_page_asm(void *page); 31 32 void copy_page_asm(void *to, void *from); 32 33 #define clear_user_page(vto, vaddr, page) clear_page_asm(vto) 33 - void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, 34 - struct page *pg); 34 + void copy_user_highpage(struct page *to, struct page *from, unsigned long vaddr, 35 + struct vm_area_struct *vma); 36 + #define __HAVE_ARCH_COPY_USER_HIGHPAGE 35 37 36 38 /* 37 39 * These are used to make use of C type-checking..

+227 -103

arch/parisc/kernel/cache.c

··· 27 27 #include <asm/processor.h> 28 28 #include <asm/sections.h> 29 29 #include <asm/shmparam.h> 30 + #include <asm/mmu_context.h> 30 31 31 32 int split_tlb __ro_after_init; 32 33 int dcache_stride __ro_after_init; ··· 92 91 } 93 92 94 93 95 - /* Virtual address of pfn. */ 94 + /* Kernel virtual address of pfn. */ 96 95 #define pfn_va(pfn) __va(PFN_PHYS(pfn)) 97 96 98 97 void ··· 125 124 cache_info.ic_size/1024 ); 126 125 if (cache_info.dc_loop != 1) 127 126 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); 128 - seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n", 127 + seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s, alias=%d)\n", 129 128 cache_info.dc_size/1024, 130 129 (cache_info.dc_conf.cc_wt ? "WT":"WB"), 131 130 (cache_info.dc_conf.cc_sh ? ", shared I/D":""), 132 - ((cache_info.dc_loop == 1) ? "direct mapped" : buf)); 131 + ((cache_info.dc_loop == 1) ? "direct mapped" : buf), 132 + cache_info.dc_conf.cc_alias 133 + ); 133 134 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n", 134 135 cache_info.it_size, 135 136 cache_info.dt_size, ··· 327 324 preempt_enable(); 328 325 } 329 326 330 - static inline void 331 - __purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, 332 - unsigned long physaddr) 327 + static void flush_user_cache_page(struct vm_area_struct *vma, unsigned long vmaddr) 333 328 { 334 - if (!static_branch_likely(&parisc_has_cache)) 335 - return; 329 + unsigned long flags, space, pgd, prot; 330 + #ifdef CONFIG_TLB_PTLOCK 331 + unsigned long pgd_lock; 332 + #endif 333 + 334 + vmaddr &= PAGE_MASK; 335 + 336 336 preempt_disable(); 337 - purge_dcache_page_asm(physaddr, vmaddr); 337 + 338 + /* Set context for flush */ 339 + local_irq_save(flags); 340 + prot = mfctl(8); 341 + space = mfsp(SR_USER); 342 + pgd = mfctl(25); 343 + #ifdef CONFIG_TLB_PTLOCK 344 + pgd_lock = mfctl(28); 345 + #endif 346 + switch_mm_irqs_off(NULL, vma->vm_mm, NULL); 347 + local_irq_restore(flags); 348 + 349 + flush_user_dcache_range_asm(vmaddr, vmaddr + PAGE_SIZE); 338 350 if (vma->vm_flags & VM_EXEC) 339 - flush_icache_page_asm(physaddr, vmaddr); 351 + flush_user_icache_range_asm(vmaddr, vmaddr + PAGE_SIZE); 352 + flush_tlb_page(vma, vmaddr); 353 + 354 + /* Restore previous context */ 355 + local_irq_save(flags); 356 + #ifdef CONFIG_TLB_PTLOCK 357 + mtctl(pgd_lock, 28); 358 + #endif 359 + mtctl(pgd, 25); 360 + mtsp(space, SR_USER); 361 + mtctl(prot, 8); 362 + local_irq_restore(flags); 363 + 340 364 preempt_enable(); 365 + } 366 + 367 + static inline pte_t *get_ptep(struct mm_struct *mm, unsigned long addr) 368 + { 369 + pte_t *ptep = NULL; 370 + pgd_t *pgd = mm->pgd; 371 + p4d_t *p4d; 372 + pud_t *pud; 373 + pmd_t *pmd; 374 + 375 + if (!pgd_none(*pgd)) { 376 + p4d = p4d_offset(pgd, addr); 377 + if (!p4d_none(*p4d)) { 378 + pud = pud_offset(p4d, addr); 379 + if (!pud_none(*pud)) { 380 + pmd = pmd_offset(pud, addr); 381 + if (!pmd_none(*pmd)) 382 + ptep = pte_offset_map(pmd, addr); 383 + } 384 + } 385 + } 386 + return ptep; 387 + } 388 + 389 + static inline bool pte_needs_flush(pte_t pte) 390 + { 391 + return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_NO_CACHE)) 392 + == (_PAGE_PRESENT | _PAGE_ACCESSED); 341 393 } 342 394 343 395 void flush_dcache_page(struct page *page) ··· 401 343 struct vm_area_struct *mpnt; 402 344 unsigned long offset; 403 345 unsigned long addr, old_addr = 0; 346 + unsigned long count = 0; 404 347 pgoff_t pgoff; 405 348 406 349 if (mapping && !mapping_mapped(mapping)) { ··· 416 357 417 358 pgoff = page->index; 418 359 419 - /* We have carefully arranged in arch_get_unmapped_area() that 360 + /* 361 + * We have carefully arranged in arch_get_unmapped_area() that 420 362 * *any* mappings of a file are always congruently mapped (whether 421 363 * declared as MAP_PRIVATE or MAP_SHARED), so we only need 422 - * to flush one address here for them all to become coherent */ 423 - 364 + * to flush one address here for them all to become coherent 365 + * on machines that support equivalent aliasing 366 + */ 424 367 flush_dcache_mmap_lock(mapping); 425 368 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { 426 369 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; 427 370 addr = mpnt->vm_start + offset; 371 + if (parisc_requires_coherency()) { 372 + pte_t *ptep; 428 373 429 - /* The TLB is the engine of coherence on parisc: The 430 - * CPU is entitled to speculate any page with a TLB 431 - * mapping, so here we kill the mapping then flush the 432 - * page along a special flush only alias mapping. 433 - * This guarantees that the page is no-longer in the 434 - * cache for any process and nor may it be 435 - * speculatively read in (until the user or kernel 436 - * specifically accesses it, of course) */ 437 - 438 - flush_tlb_page(mpnt, addr); 439 - if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1)) 440 - != (addr & (SHM_COLOUR - 1))) { 441 - __flush_cache_page(mpnt, addr, page_to_phys(page)); 442 - if (parisc_requires_coherency() && old_addr) 443 - printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file); 444 - old_addr = addr; 374 + ptep = get_ptep(mpnt->vm_mm, addr); 375 + if (ptep && pte_needs_flush(*ptep)) 376 + flush_user_cache_page(mpnt, addr); 377 + } else { 378 + /* 379 + * The TLB is the engine of coherence on parisc: 380 + * The CPU is entitled to speculate any page 381 + * with a TLB mapping, so here we kill the 382 + * mapping then flush the page along a special 383 + * flush only alias mapping. This guarantees that 384 + * the page is no-longer in the cache for any 385 + * process and nor may it be speculatively read 386 + * in (until the user or kernel specifically 387 + * accesses it, of course) 388 + */ 389 + flush_tlb_page(mpnt, addr); 390 + if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1)) 391 + != (addr & (SHM_COLOUR - 1))) { 392 + __flush_cache_page(mpnt, addr, page_to_phys(page)); 393 + /* 394 + * Software is allowed to have any number 395 + * of private mappings to a page. 396 + */ 397 + if (!(mpnt->vm_flags & VM_SHARED)) 398 + continue; 399 + if (old_addr) 400 + pr_err("INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", 401 + old_addr, addr, mpnt->vm_file); 402 + old_addr = addr; 403 + } 445 404 } 405 + WARN_ON(++count == 4096); 446 406 } 447 407 flush_dcache_mmap_unlock(mapping); 448 408 } ··· 481 403 { 482 404 unsigned long rangetime, alltime; 483 405 unsigned long size; 484 - unsigned long threshold; 406 + unsigned long threshold, threshold2; 485 407 486 408 alltime = mfctl(16); 487 409 flush_data_cache(); ··· 495 417 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n", 496 418 alltime, size, rangetime); 497 419 498 - threshold = L1_CACHE_ALIGN(size * alltime / rangetime); 499 - if (threshold > cache_info.dc_size) 500 - threshold = cache_info.dc_size; 501 - if (threshold) 502 - parisc_cache_flush_threshold = threshold; 420 + threshold = L1_CACHE_ALIGN((unsigned long)((uint64_t)size * alltime / rangetime)); 421 + pr_info("Calculated flush threshold is %lu KiB\n", 422 + threshold/1024); 423 + 424 + /* 425 + * The threshold computed above isn't very reliable. The following 426 + * heuristic works reasonably well on c8000/rp3440. 427 + */ 428 + threshold2 = cache_info.dc_size * num_online_cpus(); 429 + parisc_cache_flush_threshold = threshold2; 503 430 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n", 504 431 parisc_cache_flush_threshold/1024); 505 432 ··· 560 477 } 561 478 EXPORT_SYMBOL(flush_kernel_dcache_page_addr); 562 479 563 - void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, 564 - struct page *pg) 480 + static void flush_cache_page_if_present(struct vm_area_struct *vma, 481 + unsigned long vmaddr, unsigned long pfn) 565 482 { 566 - /* Copy using kernel mapping. No coherency is needed (all in 567 - kunmap) for the `to' page. However, the `from' page needs to 568 - be flushed through a mapping equivalent to the user mapping 569 - before it can be accessed through the kernel mapping. */ 570 - preempt_disable(); 571 - flush_dcache_page_asm(__pa(vfrom), vaddr); 572 - copy_page_asm(vto, vfrom); 573 - preempt_enable(); 483 + pte_t *ptep = get_ptep(vma->vm_mm, vmaddr); 484 + 485 + /* 486 + * The pte check is racy and sometimes the flush will trigger 487 + * a non-access TLB miss. Hopefully, the page has already been 488 + * flushed. 489 + */ 490 + if (ptep && pte_needs_flush(*ptep)) 491 + flush_cache_page(vma, vmaddr, pfn); 574 492 } 575 - EXPORT_SYMBOL(copy_user_page); 493 + 494 + void copy_user_highpage(struct page *to, struct page *from, 495 + unsigned long vaddr, struct vm_area_struct *vma) 496 + { 497 + void *kto, *kfrom; 498 + 499 + kfrom = kmap_local_page(from); 500 + kto = kmap_local_page(to); 501 + flush_cache_page_if_present(vma, vaddr, page_to_pfn(from)); 502 + copy_page_asm(kto, kfrom); 503 + kunmap_local(kto); 504 + kunmap_local(kfrom); 505 + } 506 + 507 + void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 508 + unsigned long user_vaddr, void *dst, void *src, int len) 509 + { 510 + flush_cache_page_if_present(vma, user_vaddr, page_to_pfn(page)); 511 + memcpy(dst, src, len); 512 + flush_kernel_dcache_range_asm((unsigned long)dst, (unsigned long)dst + len); 513 + } 514 + 515 + void copy_from_user_page(struct vm_area_struct *vma, struct page *page, 516 + unsigned long user_vaddr, void *dst, void *src, int len) 517 + { 518 + flush_cache_page_if_present(vma, user_vaddr, page_to_pfn(page)); 519 + memcpy(dst, src, len); 520 + } 576 521 577 522 /* __flush_tlb_range() 578 523 * ··· 631 520 return 0; 632 521 } 633 522 634 - static inline unsigned long mm_total_size(struct mm_struct *mm) 635 - { 636 - struct vm_area_struct *vma; 637 - unsigned long usize = 0; 638 - 639 - for (vma = mm->mmap; vma; vma = vma->vm_next) 640 - usize += vma->vm_end - vma->vm_start; 641 - return usize; 642 - } 643 - 644 - static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr) 645 - { 646 - pte_t *ptep = NULL; 647 - 648 - if (!pgd_none(*pgd)) { 649 - p4d_t *p4d = p4d_offset(pgd, addr); 650 - if (!p4d_none(*p4d)) { 651 - pud_t *pud = pud_offset(p4d, addr); 652 - if (!pud_none(*pud)) { 653 - pmd_t *pmd = pmd_offset(pud, addr); 654 - if (!pmd_none(*pmd)) 655 - ptep = pte_offset_map(pmd, addr); 656 - } 657 - } 658 - } 659 - return ptep; 660 - } 661 - 662 - static void flush_cache_pages(struct vm_area_struct *vma, struct mm_struct *mm, 663 - unsigned long start, unsigned long end) 523 + static void flush_cache_pages(struct vm_area_struct *vma, unsigned long start, unsigned long end) 664 524 { 665 525 unsigned long addr, pfn; 666 526 pte_t *ptep; 667 527 668 528 for (addr = start; addr < end; addr += PAGE_SIZE) { 669 - ptep = get_ptep(mm->pgd, addr); 670 - if (ptep) { 671 - pfn = pte_pfn(*ptep); 672 - flush_cache_page(vma, addr, pfn); 529 + /* 530 + * The vma can contain pages that aren't present. Although 531 + * the pte search is expensive, we need the pte to find the 532 + * page pfn and to check whether the page should be flushed. 533 + */ 534 + ptep = get_ptep(vma->vm_mm, addr); 535 + if (ptep && pte_needs_flush(*ptep)) { 536 + if (parisc_requires_coherency()) { 537 + flush_user_cache_page(vma, addr); 538 + } else { 539 + pfn = pte_pfn(*ptep); 540 + if (WARN_ON(!pfn_valid(pfn))) 541 + return; 542 + __flush_cache_page(vma, addr, PFN_PHYS(pfn)); 543 + } 673 544 } 674 545 } 546 + } 547 + 548 + static inline unsigned long mm_total_size(struct mm_struct *mm) 549 + { 550 + struct vm_area_struct *vma; 551 + unsigned long usize = 0; 552 + 553 + for (vma = mm->mmap; vma && usize < parisc_cache_flush_threshold; vma = vma->vm_next) 554 + usize += vma->vm_end - vma->vm_start; 555 + return usize; 675 556 } 676 557 677 558 void flush_cache_mm(struct mm_struct *mm) 678 559 { 679 560 struct vm_area_struct *vma; 680 561 681 - /* Flushing the whole cache on each cpu takes forever on 682 - rp3440, etc. So, avoid it if the mm isn't too big. */ 683 - if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 684 - mm_total_size(mm) >= parisc_cache_flush_threshold) { 685 - if (mm->context.space_id) 686 - flush_tlb_all(); 562 + /* 563 + * Flushing the whole cache on each cpu takes forever on 564 + * rp3440, etc. So, avoid it if the mm isn't too big. 565 + * 566 + * Note that we must flush the entire cache on machines 567 + * with aliasing caches to prevent random segmentation 568 + * faults. 569 + */ 570 + if (!parisc_requires_coherency() 571 + || mm_total_size(mm) >= parisc_cache_flush_threshold) { 572 + if (WARN_ON(IS_ENABLED(CONFIG_SMP) && arch_irqs_disabled())) 573 + return; 574 + flush_tlb_all(); 687 575 flush_cache_all(); 688 576 return; 689 577 } 690 578 579 + /* Flush mm */ 691 580 for (vma = mm->mmap; vma; vma = vma->vm_next) 692 - flush_cache_pages(vma, mm, vma->vm_start, vma->vm_end); 581 + flush_cache_pages(vma, vma->vm_start, vma->vm_end); 693 582 } 694 583 695 - void flush_cache_range(struct vm_area_struct *vma, 696 - unsigned long start, unsigned long end) 584 + void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 697 585 { 698 - if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 699 - end - start >= parisc_cache_flush_threshold) { 700 - if (vma->vm_mm->context.space_id) 701 - flush_tlb_range(vma, start, end); 586 + if (!parisc_requires_coherency() 587 + || end - start >= parisc_cache_flush_threshold) { 588 + if (WARN_ON(IS_ENABLED(CONFIG_SMP) && arch_irqs_disabled())) 589 + return; 590 + flush_tlb_range(vma, start, end); 702 591 flush_cache_all(); 703 592 return; 704 593 } 705 594 706 - flush_cache_pages(vma, vma->vm_mm, start, end); 595 + flush_cache_pages(vma, start, end); 707 596 } 708 597 709 - void 710 - flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn) 598 + void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn) 711 599 { 712 - if (pfn_valid(pfn)) { 713 - if (likely(vma->vm_mm->context.space_id)) { 714 - flush_tlb_page(vma, vmaddr); 715 - __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn)); 716 - } else { 717 - __purge_cache_page(vma, vmaddr, PFN_PHYS(pfn)); 718 - } 600 + if (WARN_ON(!pfn_valid(pfn))) 601 + return; 602 + if (parisc_requires_coherency()) 603 + flush_user_cache_page(vma, vmaddr); 604 + else 605 + __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn)); 606 + } 607 + 608 + void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) 609 + { 610 + if (!PageAnon(page)) 611 + return; 612 + 613 + if (parisc_requires_coherency()) { 614 + flush_user_cache_page(vma, vmaddr); 615 + return; 719 616 } 617 + 618 + flush_tlb_page(vma, vmaddr); 619 + preempt_disable(); 620 + flush_dcache_page_asm(page_to_phys(page), vmaddr); 621 + preempt_enable(); 720 622 } 721 623 722 624 void flush_kernel_vmap_range(void *vaddr, int size)

+11 -14

arch/parisc/kernel/patch.c

··· 40 40 41 41 *need_unmap = 1; 42 42 set_fixmap(fixmap, page_to_phys(page)); 43 - if (flags) 44 - raw_spin_lock_irqsave(&patch_lock, *flags); 45 - else 46 - __acquire(&patch_lock); 43 + raw_spin_lock_irqsave(&patch_lock, *flags); 47 44 48 45 return (void *) (__fix_to_virt(fixmap) + (uintaddr & ~PAGE_MASK)); 49 46 } ··· 49 52 { 50 53 clear_fixmap(fixmap); 51 54 52 - if (flags) 53 - raw_spin_unlock_irqrestore(&patch_lock, *flags); 54 - else 55 - __release(&patch_lock); 55 + raw_spin_unlock_irqrestore(&patch_lock, *flags); 56 56 } 57 57 58 58 void __kprobes __patch_text_multiple(void *addr, u32 *insn, unsigned int len) ··· 61 67 int mapped; 62 68 63 69 /* Make sure we don't have any aliases in cache */ 64 - flush_kernel_vmap_range(addr, len); 65 - flush_icache_range(start, end); 70 + flush_kernel_dcache_range_asm(start, end); 71 + flush_kernel_icache_range_asm(start, end); 72 + flush_tlb_kernel_range(start, end); 66 73 67 74 p = fixmap = patch_map(addr, FIX_TEXT_POKE0, &flags, &mapped); 68 75 ··· 76 81 * We're crossing a page boundary, so 77 82 * need to remap 78 83 */ 79 - flush_kernel_vmap_range((void *)fixmap, 80 - (p-fixmap) * sizeof(*p)); 84 + flush_kernel_dcache_range_asm((unsigned long)fixmap, 85 + (unsigned long)p); 86 + flush_tlb_kernel_range((unsigned long)fixmap, 87 + (unsigned long)p); 81 88 if (mapped) 82 89 patch_unmap(FIX_TEXT_POKE0, &flags); 83 90 p = fixmap = patch_map(addr, FIX_TEXT_POKE0, &flags, ··· 87 90 } 88 91 } 89 92 90 - flush_kernel_vmap_range((void *)fixmap, (p-fixmap) * sizeof(*p)); 93 + flush_kernel_dcache_range_asm((unsigned long)fixmap, (unsigned long)p); 94 + flush_tlb_kernel_range((unsigned long)fixmap, (unsigned long)p); 91 95 if (mapped) 92 96 patch_unmap(FIX_TEXT_POKE0, &flags); 93 - flush_icache_range(start, end); 94 97 } 95 98 96 99 void __kprobes __patch_text(void *addr, u32 insn)

+4 -2

arch/parisc/mm/fault.c

··· 22 22 23 23 #include <asm/traps.h> 24 24 25 + #define DEBUG_NATLB 0 26 + 25 27 /* Various important other fields */ 26 28 #define bit22set(x) (x & 0x00000200) 27 29 #define bits23_25set(x) (x & 0x000001c0) ··· 452 450 fallthrough; 453 451 case 0x380: 454 452 /* PDC and FIC instructions */ 455 - if (printk_ratelimit()) { 456 - pr_warn("BUG: nullifying cache flush/purge instruction\n"); 453 + if (DEBUG_NATLB && printk_ratelimit()) { 454 + pr_warn("WARNING: nullifying cache flush/purge instruction\n"); 457 455 show_regs(regs); 458 456 } 459 457 if (insn & 0x20) {

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