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dt-bindings: clock: Convert silabs,si5341 to DT schema
Convert the Silicon Labs SI5341 binding to DT schema format. It's a
straight-forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250804222034.4083410-1-robh@kernel.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Rob Herring (Arm)
and committed by
Stephen Boyd
b02011c8
d903f5c6
+217
-175
-175
Documentation/devicetree/bindings/clock/silabs,si5341.txt
-175
Documentation/devicetree/bindings/clock/silabs,si5341.txt
···
1
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Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
2
-
i2c clock generator.
3
-
4
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Reference
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[1] Si5341 Data Sheet
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https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
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[2] Si5341 Reference Manual
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https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
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[3] Si5345 Reference Manual
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https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
11
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12
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The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13
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clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
14
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in turn can be directed to any of the 10 (or 4) outputs through a divider.
15
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The internal structure of the clock generators can be found in [2].
16
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The Si5345 is similar to the Si5341 with the addition of fractional input
17
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dividers and automatic input selection, as described in [3].
18
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The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
19
-
20
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The driver can be used in "as is" mode, reading the current settings from the
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chip at boot, in case you have a (pre-)programmed device. If the PLL is not
22
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configured when the driver probes, it assumes the driver must fully initialize
23
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it.
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25
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The device type, speed grade and revision are determined runtime by probing.
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The driver currently does not support any fancy input configurations. They can
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still be programmed into the chip and the driver will leave them "as is".
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==I2C device node==
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Required properties:
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- compatible: shall be one of the following:
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"silabs,si5340" - Si5340 A/B/C/D
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"silabs,si5341" - Si5341 A/B/C/D
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"silabs,si5342" - Si5342 A/B/C/D
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"silabs,si5344" - Si5344 A/B/C/D
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"silabs,si5345" - Si5345 A/B/C/D
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- reg: i2c device address, usually 0x74
40
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- #clock-cells: from common clock binding; shall be set to 2.
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The first value is "0" for outputs, "1" for synthesizers.
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The second value is the output or synthesizer index.
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- clocks: from common clock binding; list of parent clock handles,
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corresponding to inputs. Use a fixed clock for the "xtal" input.
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At least one must be present.
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- clock-names: One of: "xtal", "in0", "in1", "in2"
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Optional properties:
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- vdd-supply: Regulator node for VDD
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- vdda-supply: Regulator node for VDDA
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- vdds-supply: Regulator node for VDDS
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- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
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feedback divider. Must be such that the PLL output is in the valid range. For
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example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
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the fraction matters, using 3500 and 12 will deliver the exact same result.
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If these are not specified, and the PLL is not yet programmed when the driver
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probes, the PLL will be set to 14GHz.
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- silabs,reprogram: When present, the driver will always assume the device must
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be initialized, and always performs the soft-reset routine. Since this will
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temporarily stop all output clocks, don't do this if the chip is generating
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the CPU clock for example.
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- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
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in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
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- interrupts: Interrupt for INTRb pin.
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- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
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rather than 1.8V thresholds.
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- vddoX-supply (where X is an output index): Regulator node for VDDO for the
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specified output. The driver selects the output VDD_SEL setting based on this
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voltage.
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- #address-cells: shall be set to 1.
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- #size-cells: shall be set to 0.
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74
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== Child nodes: Outputs ==
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The child nodes list the output clocks.
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Each of the clock outputs can be overwritten individually by using a child node.
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If a child node for a clock output is not set, the configuration remains
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unchanged.
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Required child node properties:
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- reg: number of clock output.
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-
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Optional child node properties:
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- silabs,format: Output format, one of:
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1 = differential (defaults to LVDS levels)
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2 = low-power (defaults to HCSL levels)
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4 = LVCMOS
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- silabs,common-mode: Manually override output common mode, see [2] for values
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- silabs,amplitude: Manually override output amplitude, see [2] for values
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- silabs,synth-master: boolean. If present, this output is allowed to change the
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multisynth frequency dynamically.
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- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
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when disabled, otherwise it's driven LOW.
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-
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==Example==
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/* 48MHz reference crystal */
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ref48: ref48M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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i2c-master-node {
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/* Programmable clock (for logic) */
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si5341: clock-generator@74 {
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reg = <0x74>;
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compatible = "silabs,si5341";
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ref48>;
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clock-names = "xtal";
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-
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silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
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silabs,pll-m-den = <48>;
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silabs,reprogram; /* Chips are not programmed, always reset */
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out@0 {
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reg = <0>;
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silabs,format = <1>; /* LVDS 3v3 */
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silabs,common-mode = <3>;
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silabs,amplitude = <3>;
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silabs,synth-master;
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};
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/*
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* Output 6 configuration:
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* LVDS 1v8
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*/
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out@6 {
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reg = <6>;
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silabs,format = <1>; /* LVDS 1v8 */
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silabs,common-mode = <13>;
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silabs,amplitude = <3>;
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};
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/*
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* Output 8 configuration:
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* HCSL 3v3
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*/
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out@8 {
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reg = <8>;
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silabs,format = <2>;
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silabs,common-mode = <11>;
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silabs,amplitude = <3>;
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};
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};
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};
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some-video-node {
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/* Standard clock bindings */
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clock-names = "pixel";
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clocks = <&si5341 0 7>; /* Output 7 */
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/* Set output 7 to use syntesizer 3 as its parent */
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assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
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assigned-clock-parents = <&si5341 1 3>;
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/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
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assigned-clock-rates = <148500000>, <594000000>;
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};
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some-audio-node {
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clock-names = "i2s-clk";
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clocks = <&si5341 0 0>;
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/*
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* since output 0 is a synth-master, the synth will be automatically set
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* to an appropriate frequency when the audio driver requests another
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* frequency. We give control over synth 2 to this output here.
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*/
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assigned-clocks = <&si5341 0 0>;
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assigned-clock-parents = <&si5341 1 2>;
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};
+217
Documentation/devicetree/bindings/clock/silabs,si5341.yaml
+217
Documentation/devicetree/bindings/clock/silabs,si5341.yaml
···
1
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/silabs,si5341.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator
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maintainers:
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- Mike Looijmans <mike.looijmans@topic.nl>
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description: >
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Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock
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generator.
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+
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Reference
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[1] Si5341 Data Sheet
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https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
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[2] Si5341 Reference Manual
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https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
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[3] Si5345 Reference Manual
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https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
23
+
24
+
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
25
+
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
26
+
in turn can be directed to any of the 10 (or 4) outputs through a divider.
27
+
The internal structure of the clock generators can be found in [2].
28
+
The Si5345 is similar to the Si5341 with the addition of fractional input
29
+
dividers and automatic input selection, as described in [3].
30
+
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
31
+
32
+
The driver can be used in "as is" mode, reading the current settings from the
33
+
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
34
+
configured when the driver probes, it assumes the driver must fully initialize
35
+
it.
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+
37
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The device type, speed grade and revision are determined runtime by probing.
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+
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properties:
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compatible:
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enum:
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- silabs,si5340
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- silabs,si5341
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- silabs,si5342
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- silabs,si5344
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- silabs,si5345
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+
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reg:
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maxItems: 1
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+
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"#clock-cells":
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const: 2
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description: >
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The first value is "0" for outputs, "1" for synthesizers.
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+
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The second value is the output or synthesizer index.
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"#address-cells":
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const: 1
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+
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"#size-cells":
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const: 0
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+
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clocks:
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minItems: 1
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maxItems: 4
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+
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clock-names:
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minItems: 1
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items:
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- const: xtal
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- const: in0
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- const: in1
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- const: in2
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+
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interrupts:
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maxItems: 1
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description: Interrupt for INTRb pin
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+
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vdd-supply:
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description: Regulator node for VDD
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vdda-supply:
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description: Regulator node for VDDA
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vdds-supply:
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description: Regulator node for VDDS
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+
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silabs,pll-m-num:
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description:
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Numerator for PLL feedback divider. Must be such that the PLL output is in
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the valid range. For example, to create 14GHz from a 48MHz xtal, use
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m-num=14000 and m-den=48. Only the fraction matters, using 3500 and 12
94
+
will deliver the exact same result. If these are not specified, and the
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PLL is not yet programmed when the driver probes, the PLL will be set to
96
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14GHz.
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$ref: /schemas/types.yaml#/definitions/uint32
98
+
99
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silabs,pll-m-den:
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description: Denominator for PLL feedback divider
101
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$ref: /schemas/types.yaml#/definitions/uint32
102
+
103
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silabs,reprogram:
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description: Always perform soft-reset and reinitialize PLL
105
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type: boolean
106
+
107
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silabs,xaxb-ext-clk:
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description: Use XA/XB pins as external reference clock
109
+
type: boolean
110
+
111
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silabs,iovdd-33:
112
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description: I2C lines use 3.3V thresholds
113
+
type: boolean
114
+
115
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patternProperties:
116
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"^vddo[0-9]-supply$": true
117
+
118
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"^out@[0-9]$":
119
+
description: >
120
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Output-specific override nodes
121
+
122
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Each of the clock outputs can be overwritten individually by using a child
123
+
node. If a child node for a clock output is not set, the configuration
124
+
remains unchanged.
125
+
type: object
126
+
additionalProperties: false
127
+
128
+
properties:
129
+
reg:
130
+
description: Number of clock output
131
+
maximum: 9
132
+
133
+
silabs,format:
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+
description: Output format
135
+
$ref: /schemas/types.yaml#/definitions/uint32
136
+
enum: [1, 2, 4]
137
+
138
+
silabs,common-mode:
139
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description: Override output common mode
140
+
$ref: /schemas/types.yaml#/definitions/uint32
141
+
142
+
silabs,amplitude:
143
+
description: Override output amplitude
144
+
$ref: /schemas/types.yaml#/definitions/uint32
145
+
146
+
silabs,synth-master:
147
+
description: Allow dynamic multisynth rate control
148
+
type: boolean
149
+
150
+
silabs,disable-high:
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+
description: Drive output HIGH when disabled
152
+
type: boolean
153
+
154
+
required:
155
+
- reg
156
+
157
+
required:
158
+
- compatible
159
+
- reg
160
+
- "#clock-cells"
161
+
- "#address-cells"
162
+
- "#size-cells"
163
+
- clocks
164
+
- clock-names
165
+
166
+
additionalProperties: false
167
+
168
+
examples:
169
+
- |
170
+
i2c {
171
+
#address-cells = <1>;
172
+
#size-cells = <0>;
173
+
174
+
clock-generator@74 {
175
+
reg = <0x74>;
176
+
compatible = "silabs,si5341";
177
+
#clock-cells = <2>;
178
+
#address-cells = <1>;
179
+
#size-cells = <0>;
180
+
clocks = <&ref48>;
181
+
clock-names = "xtal";
182
+
183
+
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
184
+
silabs,pll-m-den = <48>;
185
+
silabs,reprogram; /* Chips are not programmed, always reset */
186
+
187
+
out@0 {
188
+
reg = <0>;
189
+
silabs,format = <1>; /* LVDS 3v3 */
190
+
silabs,common-mode = <3>;
191
+
silabs,amplitude = <3>;
192
+
silabs,synth-master;
193
+
};
194
+
195
+
/*
196
+
* Output 6 configuration:
197
+
* LVDS 1v8
198
+
*/
199
+
out@6 {
200
+
reg = <6>;
201
+
silabs,format = <1>; /* LVDS 1v8 */
202
+
silabs,common-mode = <13>;
203
+
silabs,amplitude = <3>;
204
+
};
205
+
206
+
/*
207
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* Output 8 configuration:
208
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* HCSL 3v3
209
+
*/
210
+
out@8 {
211
+
reg = <8>;
212
+
silabs,format = <2>;
213
+
silabs,common-mode = <11>;
214
+
silabs,amplitude = <3>;
215
+
};
216
+
};
217
+
};