Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: realtek: Add Kent SoC and EVB device trees
Add Device Tree hierarchy for Realtek Kent SoC family:
- kent.dtsi: base SoC layer
- rtd<variant>.dtsi: SoC variant layer
- rtd<variant>-<board>.dtsi: board layer
- rtd<variant>-<board>-<config>.dts: board configuration layer
Include RTD1501s Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and
RTD1920s Smallville EVB (4GB).
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20260127071530.25426-3-eleanor15x@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
authored by
Yu-Chun Lin
and committed by
Arnd Bergmann
b095c27f
d83bcab6
+596
-4
+3
-4
arch/arm64/boot/dts/realtek/Makefile
+3
-4
arch/arm64/boot/dts/realtek/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0-only
2
2
3
3
dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb
4
-
5
4
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
6
5
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
7
6
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb
8
7
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
9
-
10
8
dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
11
-
12
9
dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
13
10
dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
14
-
11
+
dtb-$(CONFIG_ARCH_REALTEK) += rtd1501s-phantom-8gb.dtb
15
12
dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb
13
+
dtb-$(CONFIG_ARCH_REALTEK) += rtd1861b-krypton-8gb.dtb
14
+
dtb-$(CONFIG_ARCH_REALTEK) += rtd1920s-smallville-4gb.dtb
+166
arch/arm64/boot/dts/realtek/kent.dtsi
+166
arch/arm64/boot/dts/realtek/kent.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek Kent SoC family
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
#include <dt-bindings/interrupt-controller/irq.h>
10
+
11
+
/ {
12
+
interrupt-parent = <&gic>;
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
aliases {
17
+
serial0 = &uart0;
18
+
};
19
+
20
+
timer {
21
+
compatible = "arm,armv8-timer";
22
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
23
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
24
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
25
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
26
+
<GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
27
+
};
28
+
29
+
cpus {
30
+
#address-cells = <1>;
31
+
#size-cells = <0>;
32
+
33
+
cpu0: cpu@0 {
34
+
device_type = "cpu";
35
+
compatible = "arm,cortex-a78";
36
+
reg = <0x0>;
37
+
enable-method = "psci";
38
+
next-level-cache = <&l2_0>;
39
+
dynamic-power-coefficient = <454>;
40
+
#cooling-cells = <2>;
41
+
42
+
l2_0: l2-cache {
43
+
compatible = "cache";
44
+
cache-level = <2>;
45
+
cache-line-size = <64>;
46
+
cache-sets = <256>;
47
+
cache-size = <0x40000>;
48
+
cache-unified;
49
+
next-level-cache = <&l3>;
50
+
};
51
+
};
52
+
53
+
cpu1: cpu@100 {
54
+
device_type = "cpu";
55
+
compatible = "arm,cortex-a78";
56
+
reg = <0x100>;
57
+
enable-method = "psci";
58
+
next-level-cache = <&l2_1>;
59
+
dynamic-power-coefficient = <454>;
60
+
#cooling-cells = <2>;
61
+
62
+
l2_1: l2-cache {
63
+
compatible = "cache";
64
+
cache-level = <2>;
65
+
cache-line-size = <64>;
66
+
cache-sets = <256>;
67
+
cache-size = <0x40000>;
68
+
cache-unified;
69
+
next-level-cache = <&l3>;
70
+
};
71
+
};
72
+
73
+
cpu2: cpu@200 {
74
+
device_type = "cpu";
75
+
compatible = "arm,cortex-a78";
76
+
reg = <0x200>;
77
+
enable-method = "psci";
78
+
next-level-cache = <&l2_2>;
79
+
dynamic-power-coefficient = <454>;
80
+
#cooling-cells = <2>;
81
+
82
+
l2_2: l2-cache {
83
+
compatible = "cache";
84
+
cache-level = <2>;
85
+
cache-line-size = <64>;
86
+
cache-sets = <256>;
87
+
cache-size = <0x40000>;
88
+
cache-unified;
89
+
next-level-cache = <&l3>;
90
+
};
91
+
};
92
+
93
+
cpu3: cpu@300 {
94
+
device_type = "cpu";
95
+
compatible = "arm,cortex-a78";
96
+
reg = <0x300>;
97
+
enable-method = "psci";
98
+
next-level-cache = <&l2_3>;
99
+
dynamic-power-coefficient = <454>;
100
+
#cooling-cells = <2>;
101
+
102
+
l2_3: l2-cache {
103
+
compatible = "cache";
104
+
cache-level = <2>;
105
+
cache-line-size = <64>;
106
+
cache-sets = <256>;
107
+
cache-size = <0x40000>;
108
+
cache-unified;
109
+
next-level-cache = <&l3>;
110
+
};
111
+
};
112
+
113
+
l3: l3-cache {
114
+
compatible = "cache";
115
+
cache-level = <3>;
116
+
cache-line-size = <64>;
117
+
cache-sets = <512>;
118
+
cache-size = <0x200000>;
119
+
cache-unified;
120
+
};
121
+
};
122
+
123
+
psci: psci {
124
+
compatible = "arm,psci-1.0";
125
+
method = "smc";
126
+
};
127
+
128
+
soc@0 {
129
+
compatible = "simple-bus";
130
+
ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
131
+
<0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
132
+
<0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
133
+
<0xff000000 0x0 0xff000000 0x200000>; /* GIC */
134
+
#address-cells = <1>;
135
+
#size-cells = <1>;
136
+
137
+
rbus: bus@98000000 {
138
+
compatible = "simple-bus";
139
+
ranges = <0x0 0x98000000 0xef0000>,
140
+
<0xa0000000 0xa0000000 0x10000000>; /* PCIE */
141
+
#address-cells = <1>;
142
+
#size-cells = <1>;
143
+
144
+
uart0: serial@7800 {
145
+
compatible = "snps,dw-apb-uart";
146
+
reg = <0x7800 0x100>;
147
+
clock-frequency = <432000000>;
148
+
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
149
+
reg-io-width = <4>;
150
+
reg-shift = <2>;
151
+
status = "disabled";
152
+
};
153
+
};
154
+
155
+
gic: interrupt-controller@ff100000 {
156
+
compatible = "arm,gic-v3";
157
+
reg = <0xff100000 0x10000>,
158
+
<0xff140000 0x80000>;
159
+
interrupt-controller;
160
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
161
+
#address-cells = <1>;
162
+
#interrupt-cells = <3>;
163
+
#size-cells = <1>;
164
+
};
165
+
};
166
+
};
+12
arch/arm64/boot/dts/realtek/rtd1501.dtsi
+12
arch/arm64/boot/dts/realtek/rtd1501.dtsi
+25
arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts
+25
arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek RTD1501S Phantom EVB
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "rtd1501s-phantom.dtsi"
11
+
12
+
/ {
13
+
compatible = "realtek,phantom", "realtek,rtd1501s";
14
+
model = "Realtek Phantom EVB Chromium (8GB)";
15
+
16
+
memory@40000 {
17
+
device_type = "memory";
18
+
reg = <0x0 0x50000 0x0 0x7ffb0000>,
19
+
<0x0 0x8a100000 0x0 0xdef0000>,
20
+
<0x0 0x98700000 0x0 0x7900000>,
21
+
<0x0 0xa0600000 0x0 0x5ea00000>,
22
+
<0x1 0x0 0x0 0xa0000000>,
23
+
<0x1 0xa0600000 0x0 0x5fa00000>;
24
+
};
25
+
};
+118
arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi
+118
arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek RTD1501S Phantom EVB
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include <dt-bindings/thermal/thermal.h>
11
+
#include "rtd1501.dtsi"
12
+
13
+
/ {
14
+
chosen {
15
+
stdout-path = "serial0:460800n8";
16
+
};
17
+
18
+
reserved_memory: reserved-memory {
19
+
#address-cells = <2>;
20
+
#size-cells = <2>;
21
+
ranges;
22
+
23
+
linux,cma {
24
+
compatible = "shared-dma-pool";
25
+
alignment = <0x0 0x400000>;
26
+
alloc-ranges = <0x0 0x0 0x0 0x20000000>;
27
+
size = <0x0 0x2000000>;
28
+
reusable;
29
+
linux,cma-default;
30
+
};
31
+
};
32
+
33
+
cpu_opps: opp-table-cpu {
34
+
compatible = "operating-points-v2";
35
+
opp-shared;
36
+
37
+
opp800: opp-800000000 {
38
+
opp-hz = /bits/ 64 <800000000>;
39
+
opp-microvolt = <830000 830000 1100000>;
40
+
};
41
+
42
+
opp900: opp-900000000 {
43
+
opp-hz = /bits/ 64 <900000000>;
44
+
opp-microvolt = <850000 850000 1100000>;
45
+
};
46
+
47
+
opp1000: opp-1000000000 {
48
+
opp-hz = /bits/ 64 <1000000000>;
49
+
opp-microvolt = <870000 870000 1100000>;
50
+
};
51
+
52
+
opp1100: opp-1100000000 {
53
+
opp-hz = /bits/ 64 <1100000000>;
54
+
opp-microvolt = <890000 890000 1100000>;
55
+
};
56
+
57
+
opp1200: opp-1200000000 {
58
+
opp-hz = /bits/ 64 <1200000000>;
59
+
opp-microvolt = <910000 910000 1100000>;
60
+
};
61
+
62
+
opp1300: opp-1300000000 {
63
+
opp-hz = /bits/ 64 <1300000000>;
64
+
opp-microvolt = <930000 930000 1100000>;
65
+
};
66
+
67
+
opp1400: opp-1400000000 {
68
+
opp-hz = /bits/ 64 <1400000000>;
69
+
opp-microvolt = <950000 950000 1100000>;
70
+
};
71
+
72
+
opp1500: opp-1500000000 {
73
+
opp-hz = /bits/ 64 <1500000000>;
74
+
opp-microvolt = <970000 970000 1100000>;
75
+
};
76
+
77
+
opp1600: opp-1600000000 {
78
+
opp-hz = /bits/ 64 <1600000000>;
79
+
opp-microvolt = <990000 990000 1100000>;
80
+
opp-suspend;
81
+
};
82
+
83
+
opp1700: opp-1700000000 {
84
+
opp-hz = /bits/ 64 <1700000000>;
85
+
opp-microvolt = <1010000 1010000 1100000>;
86
+
};
87
+
88
+
opp1800: opp-1800000000 {
89
+
opp-hz = /bits/ 64 <1800000000>;
90
+
opp-microvolt = <1030000 1030000 1100000>;
91
+
};
92
+
93
+
opp1900: opp-1900000000 {
94
+
opp-hz = /bits/ 64 <1900000000>;
95
+
opp-microvolt = <1050000 1050000 1100000>;
96
+
};
97
+
};
98
+
};
99
+
100
+
&cpu0 {
101
+
operating-points-v2 = <&cpu_opps>;
102
+
#cooling-cells = <2>;
103
+
};
104
+
105
+
&cpu1 {
106
+
operating-points-v2 = <&cpu_opps>;
107
+
#cooling-cells = <2>;
108
+
};
109
+
110
+
&cpu2 {
111
+
operating-points-v2 = <&cpu_opps>;
112
+
#cooling-cells = <2>;
113
+
};
114
+
115
+
&cpu3 {
116
+
operating-points-v2 = <&cpu_opps>;
117
+
#cooling-cells = <2>;
118
+
};
+12
arch/arm64/boot/dts/realtek/rtd1861.dtsi
+12
arch/arm64/boot/dts/realtek/rtd1861.dtsi
+25
arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts
+25
arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek RTD1861B Krypton EVB
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "rtd1861b-krypton.dtsi"
11
+
12
+
/ {
13
+
compatible = "realtek,krypton", "realtek,rtd1861b";
14
+
model = "Realtek Krypton EVB (8GB)";
15
+
16
+
memory@40000 {
17
+
device_type = "memory";
18
+
reg = <0x0 0x50000 0x0 0x7ffb0000>,
19
+
<0x0 0x8a100000 0x0 0xdef0000>,
20
+
<0x0 0x98700000 0x0 0x7900000>,
21
+
<0x0 0xa0600000 0x0 0x5ea00000>,
22
+
<0x1 0x0 0x0 0xa0000000>,
23
+
<0x1 0xa0600000 0x0 0x5fa00000>;
24
+
};
25
+
};
+72
arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi
+72
arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek RTD1861B Krypton EVB
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "rtd1861.dtsi"
11
+
12
+
/ {
13
+
chosen {
14
+
stdout-path = "serial0:460800n8";
15
+
};
16
+
17
+
reserved_memory: reserved-memory {
18
+
#address-cells = <2>;
19
+
#size-cells = <2>;
20
+
ranges;
21
+
22
+
linux,cma {
23
+
compatible = "shared-dma-pool";
24
+
alignment = <0x0 0x400000>;
25
+
alloc-ranges = <0x0 0x0 0x0 0x20000000>;
26
+
size = <0x0 0x2000000>;
27
+
reusable;
28
+
linux,cma-default;
29
+
};
30
+
};
31
+
32
+
cpu_opps: opp-table-cpu {
33
+
compatible = "operating-points-v2";
34
+
opp-shared;
35
+
36
+
opp1200: opp-1200000000 {
37
+
opp-hz = /bits/ 64 <1200000000>;
38
+
opp-microvolt = <900000>;
39
+
};
40
+
41
+
opp1600: opp-1600000000 {
42
+
opp-hz = /bits/ 64 <1600000000>;
43
+
opp-microvolt = <1000000>;
44
+
opp-suspend;
45
+
};
46
+
47
+
opp1800: opp-1800000000 {
48
+
opp-hz = /bits/ 64 <1800000000>;
49
+
opp-microvolt = <1050000>;
50
+
};
51
+
};
52
+
};
53
+
54
+
&cpu0 {
55
+
operating-points-v2 = <&cpu_opps>;
56
+
#cooling-cells = <2>;
57
+
};
58
+
59
+
&cpu1 {
60
+
operating-points-v2 = <&cpu_opps>;
61
+
#cooling-cells = <2>;
62
+
};
63
+
64
+
&cpu2 {
65
+
operating-points-v2 = <&cpu_opps>;
66
+
#cooling-cells = <2>;
67
+
};
68
+
69
+
&cpu3 {
70
+
operating-points-v2 = <&cpu_opps>;
71
+
#cooling-cells = <2>;
72
+
};
+12
arch/arm64/boot/dts/realtek/rtd1920.dtsi
+12
arch/arm64/boot/dts/realtek/rtd1920.dtsi
+23
arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts
+23
arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek RTD1920S Smallville EVB
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include "rtd1920s-smallville.dtsi"
11
+
12
+
/ {
13
+
compatible = "realtek,smallville", "realtek,rtd1920s";
14
+
model = "Realtek Smallville EVB (4GB)";
15
+
16
+
memory@40000 {
17
+
device_type = "memory";
18
+
reg = <0x0 0x50000 0x0 0x7ffb0000>,
19
+
<0x0 0x8a100000 0x0 0xdef0000>,
20
+
<0x0 0x98700000 0x0 0x7900000>,
21
+
<0x0 0xa1000000 0x0 0x5e000000>;
22
+
};
23
+
};
+128
arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi
+128
arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Realtek RTD1920S Smallville EVB
4
+
*
5
+
* Copyright (c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
#include <dt-bindings/thermal/thermal.h>
11
+
#include "rtd1920.dtsi"
12
+
13
+
/ {
14
+
chosen {
15
+
stdout-path = "serial0:460800n8";
16
+
};
17
+
18
+
reserved_memory: reserved-memory {
19
+
#address-cells = <2>;
20
+
#size-cells = <2>;
21
+
ranges;
22
+
23
+
protected_mem: protected-mem@50000 {
24
+
reg = <0x0 0x50000 0x0 0xbf0000>;
25
+
no-map;
26
+
};
27
+
28
+
metadata: metadata@c40000 {
29
+
reg = <0x0 0xc40000 0x0 0x3c4000>;
30
+
no-map;
31
+
};
32
+
33
+
linux,cma {
34
+
compatible = "shared-dma-pool";
35
+
alignment = <0x0 0x400000>;
36
+
alloc-ranges = <0x0 0x0 0x0 0x20000000>;
37
+
size = <0x0 0x2000000>;
38
+
reusable;
39
+
linux,cma-default;
40
+
};
41
+
};
42
+
43
+
cpu_opps: opp-table-cpu {
44
+
compatible = "operating-points-v2";
45
+
opp-shared;
46
+
47
+
opp800: opp-800000000 {
48
+
opp-hz = /bits/ 64 <800000000>;
49
+
opp-microvolt = <830000 830000 1100000>;
50
+
};
51
+
52
+
opp900: opp-900000000 {
53
+
opp-hz = /bits/ 64 <900000000>;
54
+
opp-microvolt = <850000 850000 1100000>;
55
+
};
56
+
57
+
opp1000: opp-1000000000 {
58
+
opp-hz = /bits/ 64 <1000000000>;
59
+
opp-microvolt = <870000 870000 1100000>;
60
+
};
61
+
62
+
opp1100: opp-1100000000 {
63
+
opp-hz = /bits/ 64 <1100000000>;
64
+
opp-microvolt = <890000 890000 1100000>;
65
+
};
66
+
67
+
opp1200: opp-1200000000 {
68
+
opp-hz = /bits/ 64 <1200000000>;
69
+
opp-microvolt = <910000 910000 1100000>;
70
+
};
71
+
72
+
opp1300: opp-1300000000 {
73
+
opp-hz = /bits/ 64 <1300000000>;
74
+
opp-microvolt = <930000 930000 1100000>;
75
+
};
76
+
77
+
opp1400: opp-1400000000 {
78
+
opp-hz = /bits/ 64 <1400000000>;
79
+
opp-microvolt = <950000 950000 1100000>;
80
+
};
81
+
82
+
opp1500: opp-1500000000 {
83
+
opp-hz = /bits/ 64 <1500000000>;
84
+
opp-microvolt = <970000 970000 1100000>;
85
+
};
86
+
87
+
opp1600: opp-1600000000 {
88
+
opp-hz = /bits/ 64 <1600000000>;
89
+
opp-microvolt = <990000 990000 1100000>;
90
+
opp-suspend;
91
+
};
92
+
93
+
opp1700: opp-1700000000 {
94
+
opp-hz = /bits/ 64 <1700000000>;
95
+
opp-microvolt = <1010000 1010000 1100000>;
96
+
};
97
+
98
+
opp1800: opp-1800000000 {
99
+
opp-hz = /bits/ 64 <1800000000>;
100
+
opp-microvolt = <1030000 1030000 1100000>;
101
+
};
102
+
103
+
opp1900: opp-1900000000 {
104
+
opp-hz = /bits/ 64 <1900000000>;
105
+
opp-microvolt = <1050000 1050000 1100000>;
106
+
};
107
+
};
108
+
};
109
+
110
+
&cpu0 {
111
+
operating-points-v2 = <&cpu_opps>;
112
+
#cooling-cells = <2>;
113
+
};
114
+
115
+
&cpu1 {
116
+
operating-points-v2 = <&cpu_opps>;
117
+
#cooling-cells = <2>;
118
+
};
119
+
120
+
&cpu2 {
121
+
operating-points-v2 = <&cpu_opps>;
122
+
#cooling-cells = <2>;
123
+
};
124
+
125
+
&cpu3 {
126
+
operating-points-v2 = <&cpu_opps>;
127
+
#cooling-cells = <2>;
128
+
};