Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64/sysreg: Replace TCR_EL1 field macros
This just replaces all used TCR_EL1 field macros with tools sysreg variant
based fields and subsequently drops them from the header (pgtable-hwdef.h),
although while retaining the ones used for KVM (represented via the sysreg
tools format).
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
authored by
Anshuman Khandual
and committed by
Catalin Marinas
b0a3f0e8
3a866087
+75
-114
+3
-3
arch/arm64/include/asm/assembler.h
+3
-3
arch/arm64/include/asm/assembler.h
···
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* tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
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*/
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.macro tcr_set_t0sz, valreg, t0sz
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-
bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
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+
bfi \valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH
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.endm
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/*
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* tcr_set_t1sz - update TCR.T1SZ
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*/
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.macro tcr_set_t1sz, valreg, t1sz
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bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
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+
bfi \valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH
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.endm
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/*
···
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.macro offset_ttbr1, ttbr, tmp
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#if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2)
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mrs \tmp, tcr_el1
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-
and \tmp, \tmp, #TCR_T1SZ_MASK
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+
and \tmp, \tmp, #TCR_EL1_T1SZ_MASK
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cmp \tmp, #TCR_T1SZ(VA_BITS_MIN)
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orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET
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csel \ttbr, \tmp, \ttbr, eq
+1
-1
arch/arm64/include/asm/cputype.h
+1
-1
arch/arm64/include/asm/cputype.h
···
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
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#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
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#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0)
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#ifndef __ASSEMBLY__
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+2
-2
arch/arm64/include/asm/mmu_context.h
+2
-2
arch/arm64/include/asm/mmu_context.h
+38
-87
arch/arm64/include/asm/pgtable-hwdef.h
+38
-87
arch/arm64/include/asm/pgtable-hwdef.h
···
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/*
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* TCR flags.
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*/
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-
#define TCR_T0SZ_OFFSET 0
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-
#define TCR_T1SZ_OFFSET 16
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-
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
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-
#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
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#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
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-
#define TCR_TxSZ_WIDTH 6
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#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
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-
#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
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#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT)
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#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT)
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-
#define TCR_EPD0_SHIFT 7
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-
#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
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-
#define TCR_IRGN0_SHIFT 8
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-
#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
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-
#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
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-
#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
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-
#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
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-
#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
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#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK
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#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK
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-
#define TCR_EPD1_SHIFT 23
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-
#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
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-
#define TCR_IRGN1_SHIFT 24
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-
#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
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-
#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
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-
#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
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-
#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
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-
#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
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#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK
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#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK
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-
#define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC)
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#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
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#define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT)
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#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
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#define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
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#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK
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#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT)
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#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK
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#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT)
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-
#define TCR_ORGN0_SHIFT 10
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#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
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-
#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
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-
#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
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+
#define TCR_SH0_MASK TCR_EL1_SH0_MASK
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#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT)
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-
#define TCR_ORGN1_SHIFT 26
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#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
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-
#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
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-
#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
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-
#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
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+
#define TCR_SH1_MASK TCR_EL1_SH1_MASK
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-
#define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC)
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#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
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-
#define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT)
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-
#define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
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-
#define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
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+
#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT
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+
#define TCR_TG0_MASK TCR_EL1_TG0_MASK
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+
#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT)
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#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT)
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+
#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT)
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256
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-
#define TCR_SH0_SHIFT 12
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#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
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-
#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
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+
#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT
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#define TCR_TG1_MASK TCR_EL1_TG1_MASK
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#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT)
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#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT)
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+
#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT)
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-
#define TCR_SH1_SHIFT 28
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-
#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
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-
#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
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-
#define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER)
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-
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#define TCR_TG0_SHIFT 14
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#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
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#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
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#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
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#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
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-
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-
#define TCR_TG1_SHIFT 30
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-
#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
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#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
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-
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#define TCR_IPS_SHIFT 32
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#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
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-
#define TCR_A1 (UL(1) << 22)
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#define TCR_ASID16 (UL(1) << 36)
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#define TCR_TBI0 (UL(1) << 37)
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#define TCR_TBI1 (UL(1) << 38)
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#define TCR_HA (UL(1) << 39)
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#define TCR_HD (UL(1) << 40)
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-
#define TCR_HPD0_SHIFT 41
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#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT)
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#define TCR_HPD1_SHIFT 42
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#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT)
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#define TCR_TBID0 (UL(1) << 51)
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-
#define TCR_TBID1 (UL(1) << 52)
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-
#define TCR_NFD0 (UL(1) << 53)
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#define TCR_NFD1 (UL(1) << 54)
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#define TCR_E0PD0 (UL(1) << 55)
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#define TCR_E0PD1 (UL(1) << 56)
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#define TCR_TCMA0 (UL(1) << 57)
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#define TCR_TCMA1 (UL(1) << 58)
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#define TCR_DS (UL(1) << 59)
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+
#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT
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#define TCR_IPS_MASK TCR_EL1_IPS_MASK
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#define TCR_A1 TCR_EL1_A1
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#define TCR_ASID16 TCR_EL1_AS
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#define TCR_TBI0 TCR_EL1_TBI0
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#define TCR_TBI1 TCR_EL1_TBI1
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#define TCR_HA TCR_EL1_HA
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#define TCR_HD TCR_EL1_HD
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+
#define TCR_HPD0 TCR_EL1_HPD0
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+
#define TCR_HPD1 TCR_EL1_HPD1
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+
#define TCR_TBID0 TCR_EL1_TBID0
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+
#define TCR_TBID1 TCR_EL1_TBID1
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#define TCR_E0PD0 TCR_EL1_E0PD0
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#define TCR_E0PD1 TCR_EL1_E0PD1
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#define TCR_DS TCR_EL1_DS
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/*
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* TTBR.
+1
-1
arch/arm64/include/asm/pgtable-prot.h
+1
-1
arch/arm64/include/asm/pgtable-prot.h
+2
-2
arch/arm64/kernel/cpufeature.c
+2
-2
arch/arm64/kernel/cpufeature.c
···
1969
1969
1970
1970
static inline void __cpu_enable_hw_dbm(void)
1971
1971
{
1972
-
u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1972
+
u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD;
1973
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write_sysreg(tcr, tcr_el1);
1975
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isb();
···
2255
2255
static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2256
2256
{
2257
2257
if (this_cpu_has_cap(ARM64_HAS_E0PD))
2258
-
sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2258
+
sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1);
2259
2259
}
2260
2260
#endif /* CONFIG_ARM64_E0PD */
2261
2261
+4
-4
arch/arm64/kernel/pi/map_kernel.c
+4
-4
arch/arm64/kernel/pi/map_kernel.c
···
141
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static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(phys_addr_t ttbr)
142
142
{
143
143
u64 sctlr = read_sysreg(sctlr_el1);
144
-
u64 tcr = read_sysreg(tcr_el1) | TCR_DS;
144
+
u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_DS;
145
145
u64 mmfr0 = read_sysreg(id_aa64mmfr0_el1);
146
146
u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,
147
147
ID_AA64MMFR0_EL1_PARANGE_SHIFT);
148
148
149
-
tcr &= ~TCR_IPS_MASK;
150
-
tcr |= parange << TCR_IPS_SHIFT;
149
+
tcr &= ~TCR_EL1_IPS_MASK;
150
+
tcr |= parange << TCR_EL1_IPS_SHIFT;
151
151
152
152
asm(" msr sctlr_el1, %0 ;"
153
153
" isb ;"
···
263
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}
264
264
265
265
if (va_bits > VA_BITS_MIN)
266
-
sysreg_clear_set(tcr_el1, TCR_T1SZ_MASK, TCR_T1SZ(va_bits));
266
+
sysreg_clear_set(tcr_el1, TCR_EL1_T1SZ_MASK, TCR_T1SZ(va_bits));
267
267
268
268
/*
269
269
* The virtual KASLR displacement modulo 2MiB is decided by the
+1
-1
arch/arm64/kernel/vmcore_info.c
+1
-1
arch/arm64/kernel/vmcore_info.c
+23
-13
arch/arm64/mm/proc.S
+23
-13
arch/arm64/mm/proc.S
···
23
23
#include <asm/sysreg.h>
24
24
25
25
#ifdef CONFIG_ARM64_64K_PAGES
26
-
#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
26
+
#define TCR_TG_FLAGS ((TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT) |\
27
+
(TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT))
27
28
#elif defined(CONFIG_ARM64_16K_PAGES)
28
-
#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
29
+
#define TCR_TG_FLAGS ((TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT) |\
30
+
(TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT))
29
31
#else /* CONFIG_ARM64_4K_PAGES */
30
-
#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
32
+
#define TCR_TG_FLAGS ((TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT) |\
33
+
(TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT))
31
34
#endif
32
35
33
36
#ifdef CONFIG_RANDOMIZE_BASE
34
-
#define TCR_KASLR_FLAGS TCR_NFD1
37
+
#define TCR_KASLR_FLAGS TCR_EL1_NFD1
35
38
#else
36
39
#define TCR_KASLR_FLAGS 0
37
40
#endif
···
43
40
#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
44
41
45
42
#ifdef CONFIG_KASAN_SW_TAGS
46
-
#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
43
+
#define TCR_KASAN_SW_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1
47
44
#else
48
45
#define TCR_KASAN_SW_FLAGS 0
49
46
#endif
50
47
51
48
#ifdef CONFIG_KASAN_HW_TAGS
52
-
#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
49
+
#define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1
53
50
#elif defined(CONFIG_ARM64_MTE)
54
51
/*
55
52
* The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
56
53
* TBI being enabled at EL1.
57
54
*/
58
-
#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
55
+
#define TCR_MTE_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1
59
56
#else
60
57
#define TCR_MTE_FLAGS 0
61
58
#endif
59
+
60
+
#define TCR_IRGN_WBWA ((TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT) |\
61
+
(TCR_EL1_IRGN1_WBWA << TCR_EL1_IRGN1_SHIFT))
62
+
#define TCR_ORGN_WBWA ((TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT) |\
63
+
(TCR_EL1_ORGN1_WBWA << TCR_EL1_ORGN1_SHIFT))
64
+
#define TCR_SHARED ((TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT) |\
65
+
(TCR_EL1_SH1_INNER << TCR_EL1_SH1_SHIFT))
62
66
63
67
/*
64
68
* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
···
139
129
140
130
/* Don't change t0sz here, mask those bits when restoring */
141
131
mrs x7, tcr_el1
142
-
bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
132
+
bfi x8, x7, TCR_EL1_T0SZ_SHIFT, TCR_EL1_T0SZ_WIDTH
143
133
144
134
msr tcr_el1, x8
145
135
msr vbar_el1, x9
···
491
481
tcr2 .req x15
492
482
mov_q mair, MAIR_EL1_SET
493
483
mov_q tcr, TCR_T0SZ(IDMAP_VA_BITS) | TCR_T1SZ(VA_BITS_MIN) | TCR_CACHE_FLAGS | \
494
-
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
495
-
TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
484
+
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_EL1_AS | \
485
+
TCR_EL1_TBI0 | TCR_EL1_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
496
486
mov tcr2, xzr
497
487
498
488
tcr_clear_errata_bits tcr, x9, x5
···
502
492
alternative_if ARM64_HAS_VA52
503
493
tcr_set_t1sz tcr, x9
504
494
#ifdef CONFIG_ARM64_LPA2
505
-
orr tcr, tcr, #TCR_DS
495
+
orr tcr, tcr, #TCR_EL1_DS
506
496
#endif
507
497
alternative_else_nop_endif
508
498
#endif
···
510
500
/*
511
501
* Set the IPS bits in TCR_EL1.
512
502
*/
513
-
tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
503
+
tcr_compute_pa_size tcr, #TCR_EL1_IPS_SHIFT, x5, x6
514
504
#ifdef CONFIG_ARM64_HW_AFDBM
515
505
/*
516
506
* Enable hardware update of the Access Flags bit.
···
520
510
mrs x9, ID_AA64MMFR1_EL1
521
511
ubfx x9, x9, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, #4
522
512
cbz x9, 1f
523
-
orr tcr, tcr, #TCR_HA // hardware Access flag update
513
+
orr tcr, tcr, #TCR_EL1_HA // hardware Access flag update
524
514
#ifdef CONFIG_ARM64_HAFT
525
515
cmp x9, ID_AA64MMFR1_EL1_HAFDBS_HAFT
526
516
b.lt 1f