Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'irq-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull misc irq fixes from Ingo Molnar:
- Fix BCM2712 irqchip driver Kconfig dependencies required on the
Raspberry PI5
- Fix spurious interrupts on RZ/G3E SMARC EVK systems
- Fix crash regression on Sun/NIU hardware
- Apply MSI driver quirk for Sun Neptune chips
* tag 'irq-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/irq-bcm2712-mip: Enable driver when ARCH_BCM2835 is enabled
irqchip/renesas-rzv2h: Prevent TINT spurious interrupt
net/niu: Niu requires MSIX ENTRY_DATA fields touch before entry reads
PCI/MSI: Add an option to write MSIX ENTRY_DATA before any reads
+17
-2
+2
-2
drivers/irqchip/Kconfig
+2
-2
drivers/irqchip/Kconfig
···
114
114
115
115
config BCM2712_MIP
116
116
tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
117
-
depends on ARCH_BRCMSTB || COMPILE_TEST
118
-
default m if ARCH_BRCMSTB
117
+
depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
118
+
default m if ARCH_BRCMSTB || ARCH_BCM2835
119
119
depends on ARM_GIC
120
120
select GENERIC_IRQ_CHIP
121
121
select IRQ_DOMAIN_HIERARCHY
+8
drivers/irqchip/irq-renesas-rzv2h.c
+8
drivers/irqchip/irq-renesas-rzv2h.c
···
170
170
else
171
171
tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
172
172
writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
173
+
174
+
/*
175
+
* A glitch in the edge detection circuit can cause a spurious
176
+
* interrupt. Clear the status flag after setting the ICU_TSSRk
177
+
* registers, which is recommended by the hardware manual as a
178
+
* countermeasure.
179
+
*/
180
+
writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR);
173
181
}
174
182
175
183
static void rzv2h_icu_irq_disable(struct irq_data *d)
+2
drivers/net/ethernet/sun/niu.c
+2
drivers/net/ethernet/sun/niu.c
+3
drivers/pci/msi/msi.c
+3
drivers/pci/msi/msi.c
···
615
615
void __iomem *addr = pci_msix_desc_addr(desc);
616
616
617
617
desc->pci.msi_attrib.can_mask = 1;
618
+
/* Workaround for SUN NIU insanity, which requires write before read */
619
+
if (dev->dev_flags & PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST)
620
+
writel(0, addr + PCI_MSIX_ENTRY_DATA);
618
621
desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
619
622
}
620
623
}
+2
include/linux/pci.h
+2
include/linux/pci.h
···
245
245
PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246
246
/* Device does honor MSI masking despite saying otherwise */
247
247
PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
248
+
/* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
249
+
PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),
248
250
};
249
251
250
252
enum pci_irq_reroute_variant {