Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"There is an ACPI stubs fix which is ACKed by the ACPI maintainer for
merging through my tree.
One item stand out and that is that I delete the <linux/sdb.h> header
that is used by nothing. I deleted this subsystem (through the GPIO
tree) a while back so I feel responsible for tidying up the floor.
Other than that it is the usual mistakes, a bit noisy around build
issue and Kconfig then driver fixes.
Specifics:
- Fix some stubs causing compile issues for ACPI.
- Fix some wakeups on AMD IRQs shared between GPIO and SCI.
- Fix a build warning in the Tegra driver.
- Fix a Kconfig issue in the Qualcomm driver.
- Add a missing include the RALink driver.
- Return a valid type for the Apple pinctrl IRQs.
- Implement some Qualcomm SDM845 dual-edge errata.
- Remove the unused <linux/sdb.h> header. (The subsystem was once
deleted by the pinctrl maintainer...)
- Fix a duplicate initialized in the Tegra driver.
- Fix register offsets for UFS and SDC in the Qualcomm SM8350 driver"
* tag 'pinctrl-v5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: qcom: sm8350: Correct UFS and SDC offsets
pinctrl: tegra194: remove duplicate initializer again
Remove unused header <linux/sdb.h>
pinctrl: qcom: sdm845: Enable dual edge errata
pinctrl: apple: Always return valid type in apple_gpio_irq_type
pinctrl: ralink: include 'ralink_regs.h' in 'pinctrl-mt7620.c'
pinctrl: qcom: fix unmet dependencies on GPIOLIB for GPIOLIB_IRQCHIP
pinctrl: tegra: Return const pointer from tegra_pinctrl_get_group()
pinctrl: amd: Fix wakeups when IRQ is shared with SCI
ACPI: Add stubs for wakeup handler functions
+51
-176
+26
-3
drivers/pinctrl/pinctrl-amd.c
+26
-3
drivers/pinctrl/pinctrl-amd.c
···
598
598
599
599
#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
600
600
601
-
static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
601
+
static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
602
602
{
603
603
struct amd_gpio *gpio_dev = dev_id;
604
604
struct gpio_chip *gc = &gpio_dev->gc;
605
-
irqreturn_t ret = IRQ_NONE;
606
605
unsigned int i, irqnr;
607
606
unsigned long flags;
608
607
u32 __iomem *regs;
608
+
bool ret = false;
609
609
u32 regval;
610
610
u64 status, mask;
611
611
···
627
627
/* Each status bit covers four pins */
628
628
for (i = 0; i < 4; i++) {
629
629
regval = readl(regs + i);
630
+
/* caused wake on resume context for shared IRQ */
631
+
if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) {
632
+
dev_dbg(&gpio_dev->pdev->dev,
633
+
"Waking due to GPIO %d: 0x%x",
634
+
irqnr + i, regval);
635
+
return true;
636
+
}
637
+
630
638
if (!(regval & PIN_IRQ_PENDING) ||
631
639
!(regval & BIT(INTERRUPT_MASK_OFF)))
632
640
continue;
···
658
650
}
659
651
writel(regval, regs + i);
660
652
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
661
-
ret = IRQ_HANDLED;
653
+
ret = true;
662
654
}
663
655
}
656
+
/* did not cause wake on resume context for shared IRQ */
657
+
if (irq < 0)
658
+
return false;
664
659
665
660
/* Signal EOI to the GPIO unit */
666
661
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
···
673
662
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
674
663
675
664
return ret;
665
+
}
666
+
667
+
static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
668
+
{
669
+
return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
670
+
}
671
+
672
+
static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
673
+
{
674
+
return do_amd_gpio_irq_handler(-1, dev_id);
676
675
}
677
676
678
677
static int amd_get_groups_count(struct pinctrl_dev *pctldev)
···
1054
1033
goto out2;
1055
1034
1056
1035
platform_set_drvdata(pdev, gpio_dev);
1036
+
acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1057
1037
1058
1038
dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1059
1039
return ret;
···
1072
1050
gpio_dev = platform_get_drvdata(pdev);
1073
1051
1074
1052
gpiochip_remove(&gpio_dev->gc);
1053
+
acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1075
1054
1076
1055
return 0;
1077
1056
}
+6
-6
drivers/pinctrl/pinctrl-apple-gpio.c
+6
-6
drivers/pinctrl/pinctrl-apple-gpio.c
···
258
258
pctl->base + REG_IRQ(irqgrp, data->hwirq));
259
259
}
260
260
261
-
static int apple_gpio_irq_type(unsigned int type)
261
+
static unsigned int apple_gpio_irq_type(unsigned int type)
262
262
{
263
263
switch (type & IRQ_TYPE_SENSE_MASK) {
264
264
case IRQ_TYPE_EDGE_RISING:
···
272
272
case IRQ_TYPE_LEVEL_LOW:
273
273
return REG_GPIOx_IN_IRQ_LO;
274
274
default:
275
-
return -EINVAL;
275
+
return REG_GPIOx_IN_IRQ_OFF;
276
276
}
277
277
}
278
278
···
288
288
{
289
289
struct apple_gpio_pinctrl *pctl =
290
290
gpiochip_get_data(irq_data_get_irq_chip_data(data));
291
-
int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
291
+
unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
292
292
293
293
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
294
294
FIELD_PREP(REG_GPIOx_MODE, irqtype));
···
313
313
{
314
314
struct apple_gpio_pinctrl *pctl =
315
315
gpiochip_get_data(irq_data_get_irq_chip_data(data));
316
-
int irqtype = apple_gpio_irq_type(type);
316
+
unsigned int irqtype = apple_gpio_irq_type(type);
317
317
318
-
if (irqtype < 0)
319
-
return irqtype;
318
+
if (irqtype == REG_GPIOx_IN_IRQ_OFF)
319
+
return -EINVAL;
320
320
321
321
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
322
322
FIELD_PREP(REG_GPIOx_MODE, irqtype));
+2
drivers/pinctrl/qcom/Kconfig
+2
drivers/pinctrl/qcom/Kconfig
···
197
197
select PINMUX
198
198
select PINCONF
199
199
select GENERIC_PINCONF
200
+
select GPIOLIB
200
201
select GPIOLIB_IRQCHIP
201
202
select IRQ_DOMAIN_HIERARCHY
202
203
help
···
212
211
select PINMUX
213
212
select PINCONF
214
213
select GENERIC_PINCONF
214
+
select GPIOLIB
215
215
select GPIOLIB_IRQCHIP
216
216
select IRQ_DOMAIN_HIERARCHY
217
217
help
+1
drivers/pinctrl/qcom/pinctrl-sdm845.c
+1
drivers/pinctrl/qcom/pinctrl-sdm845.c
+4
-4
drivers/pinctrl/qcom/pinctrl-sm8350.c
+4
-4
drivers/pinctrl/qcom/pinctrl-sm8350.c
···
1597
1597
[200] = PINGROUP(200, qdss_gpio, _, _, _, _, _, _, _, _),
1598
1598
[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _),
1599
1599
[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _),
1600
-
[203] = UFS_RESET(ufs_reset, 0x1d8000),
1601
-
[204] = SDC_PINGROUP(sdc2_clk, 0x1cf000, 14, 6),
1602
-
[205] = SDC_PINGROUP(sdc2_cmd, 0x1cf000, 11, 3),
1603
-
[206] = SDC_PINGROUP(sdc2_data, 0x1cf000, 9, 0),
1600
+
[203] = UFS_RESET(ufs_reset, 0xd8000),
1601
+
[204] = SDC_PINGROUP(sdc2_clk, 0xcf000, 14, 6),
1602
+
[205] = SDC_PINGROUP(sdc2_cmd, 0xcf000, 11, 3),
1603
+
[206] = SDC_PINGROUP(sdc2_data, 0xcf000, 9, 0),
1604
1604
};
1605
1605
1606
1606
static const struct msm_gpio_wakeirq_map sm8350_pdc_map[] = {
+1
drivers/pinctrl/ralink/pinctrl-mt7620.c
+1
drivers/pinctrl/ralink/pinctrl-mt7620.c
+2
-2
drivers/pinctrl/tegra/pinctrl-tegra.c
+2
-2
drivers/pinctrl/tegra/pinctrl-tegra.c
···
275
275
return 0;
276
276
}
277
277
278
-
static struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
278
+
static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
279
279
unsigned int offset)
280
280
{
281
281
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
···
289
289
continue;
290
290
for (j = 0; j < num_pins; j++) {
291
291
if (offset == pins[j])
292
-
return (struct tegra_pingroup *)&pmx->soc->groups[group];
292
+
return &pmx->soc->groups[group];
293
293
}
294
294
}
295
295
-1
drivers/pinctrl/tegra/pinctrl-tegra194.c
-1
drivers/pinctrl/tegra/pinctrl-tegra194.c
···
1387
1387
.schmitt_bit = schmitt_b, \
1388
1388
.drvtype_bit = 13, \
1389
1389
.lpdr_bit = e_lpdr, \
1390
-
.drv_reg = -1, \
1391
1390
1392
1391
#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1393
1392
#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
+9
include/linux/acpi.h
+9
include/linux/acpi.h
···
974
974
return -ENODEV;
975
975
}
976
976
977
+
static inline int acpi_register_wakeup_handler(int wake_irq,
978
+
bool (*wakeup)(void *context), void *context)
979
+
{
980
+
return -ENXIO;
981
+
}
982
+
983
+
static inline void acpi_unregister_wakeup_handler(
984
+
bool (*wakeup)(void *context), void *context) { }
985
+
977
986
#endif /* !CONFIG_ACPI */
978
987
979
988
#ifdef CONFIG_ACPI_HOTPLUG_IOAPIC
-160
include/linux/sdb.h
-160
include/linux/sdb.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* This is the official version 1.1 of sdb.h
4
-
*/
5
-
#ifndef __SDB_H__
6
-
#define __SDB_H__
7
-
#ifdef __KERNEL__
8
-
#include <linux/types.h>
9
-
#else
10
-
#include <stdint.h>
11
-
#endif
12
-
13
-
/*
14
-
* All structures are 64 bytes long and are expected
15
-
* to live in an array, one for each interconnect.
16
-
* Most fields of the structures are shared among the
17
-
* various types, and most-specific fields are at the
18
-
* beginning (for alignment reasons, and to keep the
19
-
* magic number at the head of the interconnect record
20
-
*/
21
-
22
-
/* Product, 40 bytes at offset 24, 8-byte aligned
23
-
*
24
-
* device_id is vendor-assigned; version is device-specific,
25
-
* date is hex (e.g 0x20120501), name is UTF-8, blank-filled
26
-
* and not terminated with a 0 byte.
27
-
*/
28
-
struct sdb_product {
29
-
uint64_t vendor_id; /* 0x18..0x1f */
30
-
uint32_t device_id; /* 0x20..0x23 */
31
-
uint32_t version; /* 0x24..0x27 */
32
-
uint32_t date; /* 0x28..0x2b */
33
-
uint8_t name[19]; /* 0x2c..0x3e */
34
-
uint8_t record_type; /* 0x3f */
35
-
};
36
-
37
-
/*
38
-
* Component, 56 bytes at offset 8, 8-byte aligned
39
-
*
40
-
* The address range is first to last, inclusive
41
-
* (for example 0x100000 - 0x10ffff)
42
-
*/
43
-
struct sdb_component {
44
-
uint64_t addr_first; /* 0x08..0x0f */
45
-
uint64_t addr_last; /* 0x10..0x17 */
46
-
struct sdb_product product; /* 0x18..0x3f */
47
-
};
48
-
49
-
/* Type of the SDB record */
50
-
enum sdb_record_type {
51
-
sdb_type_interconnect = 0x00,
52
-
sdb_type_device = 0x01,
53
-
sdb_type_bridge = 0x02,
54
-
sdb_type_integration = 0x80,
55
-
sdb_type_repo_url = 0x81,
56
-
sdb_type_synthesis = 0x82,
57
-
sdb_type_empty = 0xFF,
58
-
};
59
-
60
-
/* Type 0: interconnect (first of the array)
61
-
*
62
-
* sdb_records is the length of the table including this first
63
-
* record, version is 1. The bus type is enumerated later.
64
-
*/
65
-
#define SDB_MAGIC 0x5344422d /* "SDB-" */
66
-
struct sdb_interconnect {
67
-
uint32_t sdb_magic; /* 0x00-0x03 */
68
-
uint16_t sdb_records; /* 0x04-0x05 */
69
-
uint8_t sdb_version; /* 0x06 */
70
-
uint8_t sdb_bus_type; /* 0x07 */
71
-
struct sdb_component sdb_component; /* 0x08-0x3f */
72
-
};
73
-
74
-
/* Type 1: device
75
-
*
76
-
* class is 0 for "custom device", other values are
77
-
* to be standardized; ABI version is for the driver,
78
-
* bus-specific bits are defined by each bus (see below)
79
-
*/
80
-
struct sdb_device {
81
-
uint16_t abi_class; /* 0x00-0x01 */
82
-
uint8_t abi_ver_major; /* 0x02 */
83
-
uint8_t abi_ver_minor; /* 0x03 */
84
-
uint32_t bus_specific; /* 0x04-0x07 */
85
-
struct sdb_component sdb_component; /* 0x08-0x3f */
86
-
};
87
-
88
-
/* Type 2: bridge
89
-
*
90
-
* child is the address of the nested SDB table
91
-
*/
92
-
struct sdb_bridge {
93
-
uint64_t sdb_child; /* 0x00-0x07 */
94
-
struct sdb_component sdb_component; /* 0x08-0x3f */
95
-
};
96
-
97
-
/* Type 0x80: integration
98
-
*
99
-
* all types with bit 7 set are meta-information, so
100
-
* software can ignore the types it doesn't know. Here we
101
-
* just provide product information for an aggregate device
102
-
*/
103
-
struct sdb_integration {
104
-
uint8_t reserved[24]; /* 0x00-0x17 */
105
-
struct sdb_product product; /* 0x08-0x3f */
106
-
};
107
-
108
-
/* Type 0x81: Top module repository url
109
-
*
110
-
* again, an informative field that software can ignore
111
-
*/
112
-
struct sdb_repo_url {
113
-
uint8_t repo_url[63]; /* 0x00-0x3e */
114
-
uint8_t record_type; /* 0x3f */
115
-
};
116
-
117
-
/* Type 0x82: Synthesis tool information
118
-
*
119
-
* this informative record
120
-
*/
121
-
struct sdb_synthesis {
122
-
uint8_t syn_name[16]; /* 0x00-0x0f */
123
-
uint8_t commit_id[16]; /* 0x10-0x1f */
124
-
uint8_t tool_name[8]; /* 0x20-0x27 */
125
-
uint32_t tool_version; /* 0x28-0x2b */
126
-
uint32_t date; /* 0x2c-0x2f */
127
-
uint8_t user_name[15]; /* 0x30-0x3e */
128
-
uint8_t record_type; /* 0x3f */
129
-
};
130
-
131
-
/* Type 0xff: empty
132
-
*
133
-
* this allows keeping empty slots during development,
134
-
* so they can be filled later with minimal efforts and
135
-
* no misleading description is ever shipped -- hopefully.
136
-
* It can also be used to pad a table to a desired length.
137
-
*/
138
-
struct sdb_empty {
139
-
uint8_t reserved[63]; /* 0x00-0x3e */
140
-
uint8_t record_type; /* 0x3f */
141
-
};
142
-
143
-
/* The type of bus, for bus-specific flags */
144
-
enum sdb_bus_type {
145
-
sdb_wishbone = 0x00,
146
-
sdb_data = 0x01,
147
-
};
148
-
149
-
#define SDB_WB_WIDTH_MASK 0x0f
150
-
#define SDB_WB_ACCESS8 0x01
151
-
#define SDB_WB_ACCESS16 0x02
152
-
#define SDB_WB_ACCESS32 0x04
153
-
#define SDB_WB_ACCESS64 0x08
154
-
#define SDB_WB_LITTLE_ENDIAN 0x80
155
-
156
-
#define SDB_DATA_READ 0x04
157
-
#define SDB_DATA_WRITE 0x02
158
-
#define SDB_DATA_EXEC 0x01
159
-
160
-
#endif /* __SDB_H__ */