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drm/msm: convert all pixel format logging to use %p4cc

Logging u32 pixel formats using %4.4s format string with a pointer to
the u32 is somewhat questionable, as well as dependent on byte
order. There's a kernel extension format specifier %p4cc to format 4cc
codes. Use it across the board in msm for pixel format logging.

This should also fix the reported build warning:

include/drm/drm_print.h:536:35: warning: '%4.4s' directive argument is
null [-Wformat-overflow=]

Reported-by: Aishwarya TCV <aishwarya.tcv@arm.com>
Closes: https://lore.kernel.org/r/2ac758ce-a196-4e89-a397-488ba31014c4@arm.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Aishwarya TCV <aishwarya.tcv@arm.com>
Patchwork: https://patchwork.freedesktop.org/patch/587758/
Link: https://lore.kernel.org/r/20240405092907.2334007-1-jani.nikula@intel.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Jani Nikula and committed by
Dmitry Baryshkov b11a89a5 4ccd0277

+24 -24
+4 -4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
··· 2203 2203 return; 2204 2204 2205 2205 if (!DPU_FORMAT_IS_YUV(dpu_fmt)) { 2206 - DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent), 2207 - dpu_fmt->base.pixel_format); 2206 + DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), 2207 + &dpu_fmt->base.pixel_format); 2208 2208 if (hw_cdm->ops.bind_pingpong_blk) 2209 2209 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); 2210 2210 ··· 2244 2244 break; 2245 2245 } 2246 2246 2247 - DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n", 2247 + DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n", 2248 2248 DRMID(phys_enc->parent), cdm_cfg->output_width, 2249 - cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format, 2249 + cdm_cfg->output_height, &cdm_cfg->output_fmt->base.pixel_format, 2250 2250 cdm_cfg->output_type, cdm_cfg->output_bit_depth, 2251 2251 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); 2252 2252
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
··· 580 580 format->pixel_format, job->fb->modifier); 581 581 if (!wb_cfg->dest.format) { 582 582 /* this error should be detected during atomic_check */ 583 - DPU_ERROR("failed to get format %x\n", format->pixel_format); 583 + DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format); 584 584 return; 585 585 } 586 586
+2 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
··· 647 647 648 648 color = _dpu_format_get_media_color_ubwc(fmt); 649 649 if (color < 0) { 650 - DRM_ERROR("UBWC format not supported for fmt: %4.4s\n", 651 - (char *)&fmt->base.pixel_format); 650 + DRM_ERROR("UBWC format not supported for fmt: %p4cc\n", 651 + &fmt->base.pixel_format); 652 652 return -EINVAL; 653 653 } 654 654
+12 -12
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
··· 234 234 } 235 235 } 236 236 237 - DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 237 + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n", 238 238 pipe->sspp->idx - SSPP_VIG0, 239 - (char *)&fmt->base.pixel_format, 239 + &fmt->base.pixel_format, 240 240 src_width, total_fl); 241 241 242 242 return total_fl; ··· 287 287 (fmt) ? fmt->base.pixel_format : 0, 288 288 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 289 289 290 - DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 290 + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n", 291 291 pdpu->pipe - SSPP_VIG0, 292 - fmt ? (char *)&fmt->base.pixel_format : NULL, 292 + fmt ? &fmt->base.pixel_format : NULL, 293 293 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 294 294 295 295 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, ··· 298 298 cfg.danger_lut, 299 299 cfg.safe_lut); 300 300 301 - DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 302 - pdpu->pipe - SSPP_VIG0, 303 - fmt ? (char *)&fmt->base.pixel_format : NULL, 304 - fmt ? fmt->fetch_mode : -1, 305 - cfg.danger_lut, 306 - cfg.safe_lut); 301 + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n", 302 + pdpu->pipe - SSPP_VIG0, 303 + fmt ? &fmt->base.pixel_format : NULL, 304 + fmt ? fmt->fetch_mode : -1, 305 + cfg.danger_lut, 306 + cfg.safe_lut); 307 307 308 308 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 309 309 } ··· 1118 1118 pdpu->is_rt_pipe = is_rt_pipe; 1119 1119 1120 1120 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1121 - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1121 + ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1122 1122 crtc->base.id, DRM_RECT_ARG(&state->dst), 1123 - (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1123 + &fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1124 1124 1125 1125 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1126 1126 drm_mode_vrefresh(&crtc->mode),
+5 -5
drivers/gpu/drm/msm/msm_fb.c
··· 176 176 const struct msm_format *format; 177 177 int ret, i, n; 178 178 179 - drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%4.4s)\n", 180 - mode_cmd, mode_cmd->width, mode_cmd->height, 181 - (char *)&mode_cmd->pixel_format); 179 + drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%p4cc)\n", 180 + mode_cmd, mode_cmd->width, mode_cmd->height, 181 + &mode_cmd->pixel_format); 182 182 183 183 n = info->num_planes; 184 184 format = kms->funcs->get_format(kms, mode_cmd->pixel_format, 185 185 mode_cmd->modifier[0]); 186 186 if (!format) { 187 - DRM_DEV_ERROR(dev->dev, "unsupported pixel format: %4.4s\n", 188 - (char *)&mode_cmd->pixel_format); 187 + DRM_DEV_ERROR(dev->dev, "unsupported pixel format: %p4cc\n", 188 + &mode_cmd->pixel_format); 189 189 ret = -EINVAL; 190 190 goto fail; 191 191 }