Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net/mlx5: implement swp_l4_csum_mode via devlink params
swp_l4_csum_mode controls how L4 transmit checksums are computed when
using Software Parser (SWP) hints for header locations.
Supported values:
1. default: device will choose between full_csum or l4_only. Driver
will discover the device's choice during initialization.
2. full_csum: calculate L4 checksum with the pseudo-header.
3. l4_only: calculate L4 checksum without the pseudo-header. Only
available when swp_l4_csum_mode_l4_only is set in
mlx5_ifc_nv_sw_offload_cap_bits.
Note that 'default' might be returned from the device and passed to
userspace, and it might also be set during a
devlink_param::reset_default() call, but attempts to set a value of
default directly with param-set will be rejected.
The l4_only setting is a dependency for PSP initialization in
mlx5e_psp_init().
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Daniel Zahka <daniel.zahka@gmail.com>
Link: https://patch.msgid.link/20251119025038.651131-5-daniel.zahka@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Daniel Zahka
and committed by
Jakub Kicinski
b11d358b
2a367002
+245
-1
+14
Documentation/networking/devlink/mlx5.rst
+14
Documentation/networking/devlink/mlx5.rst
···
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* ``balanced`` : Merges fewer CQEs, resulting in a moderate compression ratio but maintaining a balance between bandwidth savings and performance
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* ``aggressive`` : Merges more CQEs into a single entry, achieving a higher compression rate and maximizing performance, particularly under high traffic loads
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* - ``swp_l4_csum_mode``
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- string
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- permanent
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- Configure how the L4 checksum is calculated by the device when using
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Software Parser (SWP) hints for header locations.
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* ``default`` : Use the device's default checksum calculation
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mode. The driver will discover during init whether or
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full_csum or l4_only is in use. Setting this value explicitly
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from userspace is not allowed, but some firmware versions may
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return this value on param read.
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* ``full_csum`` : Calculate full checksum including the pseudo-header
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* ``l4_only`` : Calculate L4-only checksum, excluding the pseudo-header
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+
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The ``mlx5`` driver supports reloading via ``DEVLINK_CMD_RELOAD``
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Info versions
+2
-1
drivers/net/ethernet/mellanox/mlx5/core/devlink.h
+2
-1
drivers/net/ethernet/mellanox/mlx5/core/devlink.h
···
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MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH,
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MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW,
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MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH,
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-
MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE
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MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE,
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MLX5_DEVLINK_PARAM_ID_SWP_L4_CSUM_MODE,
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};
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struct mlx5_trap_ctx {
+229
drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c
+229
drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c
···
8
8
MLX5_CLASS_0_CTRL_ID_NV_GLOBAL_PCI_CONF = 0x80,
9
9
MLX5_CLASS_0_CTRL_ID_NV_GLOBAL_PCI_CAP = 0x81,
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MLX5_CLASS_0_CTRL_ID_NV_SW_OFFLOAD_CONFIG = 0x10a,
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+
MLX5_CLASS_0_CTRL_ID_NV_SW_OFFLOAD_CAP = 0x10b,
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+
MLX5_CLASS_0_CTRL_ID_NV_SW_ACCELERATE_CONF = 0x11d,
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MLX5_CLASS_3_CTRL_ID_NV_PF_PCI_CONF = 0x80,
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};
···
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struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits
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configuration_item_type_class_per_host_pf;
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u8 reserved_at_0[0x20];
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};
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+
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enum {
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MLX5_ACCESS_MODE_NEXT = 0,
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MLX5_ACCESS_MODE_CURRENT,
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MLX5_ACCESS_MODE_DEFAULT,
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};
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struct mlx5_ifc_config_item_bits {
···
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u8 lro_log_timeout0[0x4];
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};
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+
struct mlx5_ifc_nv_sw_offload_cap_bits {
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u8 reserved_at_0[0x19];
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u8 swp_l4_csum_mode_l4_only[0x1];
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u8 reserved_at_1a[0x6];
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};
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+
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struct mlx5_ifc_nv_sw_accelerate_conf_bits {
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u8 swp_l4_csum_mode[0x2];
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u8 reserved_at_2[0x3e];
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};
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+
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#define MNVDA_HDR_SZ \
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(MLX5_ST_SZ_BYTES(mnvda_reg) - \
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MLX5_BYTE_OFF(mnvda_reg, configuration_item_data))
···
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MLX5_SET_CFG_ITEM_TYPE(global, mnvda, parameter_index,
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MLX5_CLASS_0_CTRL_ID_NV_SW_OFFLOAD_CONFIG);
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MLX5_SET_CFG_HDR_LEN(mnvda, nv_sw_offload_conf);
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+
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return mlx5_nv_param_read(dev, mnvda, len);
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}
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+
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static int
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mlx5_nv_param_read_sw_offload_cap(struct mlx5_core_dev *dev, void *mnvda,
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size_t len)
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{
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MLX5_SET_CFG_ITEM_TYPE(global, mnvda, type_class, 0);
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MLX5_SET_CFG_ITEM_TYPE(global, mnvda, parameter_index,
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MLX5_CLASS_0_CTRL_ID_NV_SW_OFFLOAD_CAP);
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MLX5_SET_CFG_HDR_LEN(mnvda, nv_sw_offload_cap);
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+
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return mlx5_nv_param_read(dev, mnvda, len);
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}
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+
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static int
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mlx5_nv_param_read_sw_accelerate_conf(struct mlx5_core_dev *dev, void *mnvda,
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size_t len, int access_mode)
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{
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MLX5_SET_CFG_ITEM_TYPE(global, mnvda, type_class, 0);
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MLX5_SET_CFG_ITEM_TYPE(global, mnvda, parameter_index,
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MLX5_CLASS_0_CTRL_ID_NV_SW_ACCELERATE_CONF);
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MLX5_SET_CFG_HDR_LEN(mnvda, nv_sw_accelerate_conf);
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MLX5_SET(mnvda_reg, mnvda, configuration_item_header.access_mode,
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access_mode);
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return mlx5_nv_param_read(dev, mnvda, len);
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}
···
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MLX5_SET(nv_sw_offload_conf, data, cqe_compression, value);
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return mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
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}
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+
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enum swp_l4_csum_mode {
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SWP_L4_CSUM_MODE_DEFAULT = 0,
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SWP_L4_CSUM_MODE_FULL_CSUM = 1,
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SWP_L4_CSUM_MODE_L4_ONLY = 2,
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};
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static const char *const
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swp_l4_csum_mode_str[] = { "default", "full_csum", "l4_only" };
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static int
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mlx5_swp_l4_csum_mode_get(struct devlink *devlink, u32 id,
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int access_mode, u8 *value,
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struct netlink_ext_ack *extack)
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{
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struct mlx5_core_dev *dev = devlink_priv(devlink);
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u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
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void *data;
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int err;
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err = mlx5_nv_param_read_sw_accelerate_conf(dev, mnvda, sizeof(mnvda),
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access_mode);
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if (err) {
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NL_SET_ERR_MSG_MOD(extack,
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"Failed to read sw_accelerate_conf mnvda reg");
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return err;
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}
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+
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data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
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*value = MLX5_GET(nv_sw_accelerate_conf, data, swp_l4_csum_mode);
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+
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if (*value >= ARRAY_SIZE(swp_l4_csum_mode_str)) {
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NL_SET_ERR_MSG_FMT_MOD(extack,
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"Invalid swp_l4_csum_mode value %u read from device",
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*value);
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return -EINVAL;
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}
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return 0;
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}
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static int
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mlx5_devlink_swp_l4_csum_mode_get(struct devlink *devlink, u32 id,
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struct devlink_param_gset_ctx *ctx,
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struct netlink_ext_ack *extack)
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{
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u8 value;
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int err;
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err = mlx5_swp_l4_csum_mode_get(devlink, id, MLX5_ACCESS_MODE_NEXT,
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&value, extack);
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if (err)
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return err;
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strscpy(ctx->val.vstr, swp_l4_csum_mode_str[value],
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sizeof(ctx->val.vstr));
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return 0;
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}
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static int
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mlx5_devlink_swp_l4_csum_mode_validate(struct devlink *devlink, u32 id,
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union devlink_param_value val,
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struct netlink_ext_ack *extack)
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{
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struct mlx5_core_dev *dev = devlink_priv(devlink);
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u32 cap[MLX5_ST_SZ_DW(mnvda_reg)] = {};
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void *data;
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int err, i;
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+
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for (i = 0; i < ARRAY_SIZE(swp_l4_csum_mode_str); i++) {
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if (!strcmp(val.vstr, swp_l4_csum_mode_str[i]))
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break;
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}
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if (i >= ARRAY_SIZE(swp_l4_csum_mode_str) ||
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i == SWP_L4_CSUM_MODE_DEFAULT) {
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NL_SET_ERR_MSG_MOD(extack,
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"Invalid value, supported values are full_csum/l4_only");
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return -EINVAL;
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}
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+
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if (i == SWP_L4_CSUM_MODE_L4_ONLY) {
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err = mlx5_nv_param_read_sw_offload_cap(dev, cap, sizeof(cap));
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if (err) {
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NL_SET_ERR_MSG_MOD(extack,
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"Failed to read sw_offload_cap");
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return err;
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}
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data = MLX5_ADDR_OF(mnvda_reg, cap, configuration_item_data);
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if (!MLX5_GET(nv_sw_offload_cap, data, swp_l4_csum_mode_l4_only)) {
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NL_SET_ERR_MSG_MOD(extack,
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"l4_only mode is not supported on this device");
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return -EOPNOTSUPP;
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}
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}
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return 0;
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}
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static int
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mlx5_swp_l4_csum_mode_set(struct devlink *devlink, u32 id, u8 value,
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struct netlink_ext_ack *extack)
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{
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struct mlx5_core_dev *dev = devlink_priv(devlink);
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u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {};
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void *data;
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int err;
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+
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err = mlx5_nv_param_read_sw_accelerate_conf(dev, mnvda, sizeof(mnvda),
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MLX5_ACCESS_MODE_NEXT);
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if (err) {
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NL_SET_ERR_MSG_MOD(extack,
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"Failed to read sw_accelerate_conf mnvda reg");
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return err;
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}
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data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data);
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MLX5_SET(nv_sw_accelerate_conf, data, swp_l4_csum_mode, value);
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err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda));
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if (err)
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NL_SET_ERR_MSG_MOD(extack,
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"Failed to write sw_accelerate_conf mnvda reg");
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return err;
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}
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static int
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mlx5_devlink_swp_l4_csum_mode_set(struct devlink *devlink, u32 id,
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struct devlink_param_gset_ctx *ctx,
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struct netlink_ext_ack *extack)
403
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{
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u8 value;
405
+
406
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if (!strcmp(ctx->val.vstr, "full_csum"))
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value = SWP_L4_CSUM_MODE_FULL_CSUM;
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else
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value = SWP_L4_CSUM_MODE_L4_ONLY;
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return mlx5_swp_l4_csum_mode_set(devlink, id, value, extack);
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}
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+
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static int
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mlx5_devlink_swp_l4_csum_mode_get_default(struct devlink *devlink, u32 id,
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struct devlink_param_gset_ctx *ctx,
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struct netlink_ext_ack *extack)
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{
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u8 value;
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int err;
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+
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err = mlx5_swp_l4_csum_mode_get(devlink, id, MLX5_ACCESS_MODE_DEFAULT,
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&value, extack);
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if (err)
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return err;
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+
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strscpy(ctx->val.vstr, swp_l4_csum_mode_str[value],
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sizeof(ctx->val.vstr));
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return 0;
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}
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+
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static int
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mlx5_devlink_swp_l4_csum_mode_set_default(struct devlink *devlink, u32 id,
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enum devlink_param_cmode cmode,
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struct netlink_ext_ack *extack)
436
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{
437
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u8 value;
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int err;
439
+
440
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err = mlx5_swp_l4_csum_mode_get(devlink, id, MLX5_ACCESS_MODE_DEFAULT,
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&value, extack);
442
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if (err)
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return err;
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+
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return mlx5_swp_l4_csum_mode_set(devlink, id, value, extack);
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}
316
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static int mlx5_nv_param_read_global_pci_conf(struct mlx5_core_dev *dev,
···
769
548
mlx5_nv_param_devlink_cqe_compress_get,
770
549
mlx5_nv_param_devlink_cqe_compress_set,
771
550
mlx5_nv_param_devlink_cqe_compress_validate),
551
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DEVLINK_PARAM_DRIVER_WITH_DEFAULTS(MLX5_DEVLINK_PARAM_ID_SWP_L4_CSUM_MODE,
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"swp_l4_csum_mode", DEVLINK_PARAM_TYPE_STRING,
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BIT(DEVLINK_PARAM_CMODE_PERMANENT),
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mlx5_devlink_swp_l4_csum_mode_get,
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mlx5_devlink_swp_l4_csum_mode_set,
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mlx5_devlink_swp_l4_csum_mode_validate,
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mlx5_devlink_swp_l4_csum_mode_get_default,
558
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mlx5_devlink_swp_l4_csum_mode_set_default),
772
559
};
773
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774
561
int mlx5_nv_param_register_dl_params(struct devlink *devlink)