drm/amd/pm: fulfill powerplay peak profiling mode shader/memory clock settings

+8 -2

drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c

··· 769 769 770 770 switch (idx) { 771 771 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 772 - *((uint32_t *)value) = hwmgr->pstate_sclk; 772 + *((uint32_t *)value) = hwmgr->pstate_sclk * 100; 773 773 return 0; 774 774 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 775 - *((uint32_t *)value) = hwmgr->pstate_mclk; 775 + *((uint32_t *)value) = hwmgr->pstate_mclk * 100; 776 + return 0; 777 + case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 778 + *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100; 779 + return 0; 780 + case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 781 + *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100; 776 782 return 0; 777 783 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 778 784 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;

+13 -3

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

··· 375 375 return 0; 376 376 } 377 377 378 + static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 379 + { 380 + hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK; 381 + hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK; 382 + 383 + smum_send_msg_to_smc(hwmgr, 384 + PPSMC_MSG_GetMaxGfxclkFrequency, 385 + &hwmgr->pstate_sclk_peak); 386 + hwmgr->pstate_mclk_peak = SMU10_UMD_PSTATE_PEAK_FCLK; 387 + } 388 + 378 389 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 379 390 { 380 391 struct amdgpu_device *adev = hwmgr->adev; ··· 408 397 if (ret) 409 398 return ret; 410 399 } 400 + 401 + smu10_populate_umdpstate_clocks(hwmgr); 411 402 412 403 return 0; 413 404 } ··· 586 573 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 587 574 588 575 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 589 - 590 - hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100; 591 - hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100; 592 576 593 577 /* enable the pp_od_clk_voltage sysfs file */ 594 578 hwmgr->od_enabled = 1;

+63 -13

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

··· 1501 1501 return ret; 1502 1502 } 1503 1503 1504 + static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1505 + { 1506 + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1507 + struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 1508 + struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk = 1509 + hwmgr->dyn_state.vddc_dependency_on_sclk; 1510 + struct phm_ppt_v1_information *table_info = 1511 + (struct phm_ppt_v1_information *)(hwmgr->pptable); 1512 + struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk = 1513 + table_info->vdd_dep_on_sclk; 1514 + int32_t tmp_sclk, count, percentage; 1515 + 1516 + if (golden_dpm_table->mclk_table.count == 1) { 1517 + percentage = 70; 1518 + hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value; 1519 + } else { 1520 + percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 1521 + golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1522 + hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 1523 + } 1524 + 1525 + tmp_sclk = hwmgr->pstate_mclk * percentage / 100; 1526 + 1527 + if (hwmgr->pp_table_version == PP_TABLE_V0) { 1528 + for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) { 1529 + if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) { 1530 + hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk; 1531 + break; 1532 + } 1533 + } 1534 + if (count < 0) 1535 + hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk; 1536 + 1537 + hwmgr->pstate_sclk_peak = 1538 + vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk; 1539 + } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 1540 + for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) { 1541 + if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) { 1542 + hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk; 1543 + break; 1544 + } 1545 + } 1546 + if (count < 0) 1547 + hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk; 1548 + 1549 + hwmgr->pstate_sclk_peak = 1550 + vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk; 1551 + } 1552 + 1553 + hwmgr->pstate_mclk_peak = 1554 + golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1555 + 1556 + /* make sure the output is in Mhz */ 1557 + hwmgr->pstate_sclk /= 100; 1558 + hwmgr->pstate_mclk /= 100; 1559 + hwmgr->pstate_sclk_peak /= 100; 1560 + hwmgr->pstate_mclk_peak /= 100; 1561 + } 1562 + 1504 1563 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1505 1564 { 1506 1565 int tmp_result = 0; ··· 1683 1624 tmp_result = smu7_pcie_performance_request(hwmgr); 1684 1625 PP_ASSERT_WITH_CODE((0 == tmp_result), 1685 1626 "pcie performance request failed!", result = tmp_result); 1627 + 1628 + smu7_populate_umdpstate_clocks(hwmgr); 1686 1629 1687 1630 return 0; 1688 1631 } ··· 3204 3143 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3205 3144 count >= 0; count--) { 3206 3145 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { 3207 - tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; 3208 3146 *sclk_mask = count; 3209 3147 break; 3210 3148 } 3211 3149 } 3212 - if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 3150 + if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3213 3151 *sclk_mask = 0; 3214 - tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; 3215 - } 3216 3152 3217 3153 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3218 3154 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; ··· 3219 3161 3220 3162 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { 3221 3163 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { 3222 - tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk; 3223 3164 *sclk_mask = count; 3224 3165 break; 3225 3166 } 3226 3167 } 3227 - if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 3168 + if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3228 3169 *sclk_mask = 0; 3229 - tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3230 - } 3231 3170 3232 3171 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3233 3172 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; ··· 3236 3181 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3237 3182 3238 3183 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; 3239 - hwmgr->pstate_sclk = tmp_sclk; 3240 - hwmgr->pstate_mclk = tmp_mclk; 3241 3184 3242 3185 return 0; 3243 3186 } ··· 3247 3194 uint32_t sclk_mask = 0; 3248 3195 uint32_t mclk_mask = 0; 3249 3196 uint32_t pcie_mask = 0; 3250 - 3251 - if (hwmgr->pstate_sclk == 0) 3252 - smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 3253 3197 3254 3198 switch (level) { 3255 3199 case AMD_DPM_FORCED_LEVEL_HIGH:

+14 -2

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

··· 1016 1016 data->acp_boot_level = 0xff; 1017 1017 } 1018 1018 1019 + static void smu8_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1020 + { 1021 + struct phm_clock_voltage_dependency_table *table = 1022 + hwmgr->dyn_state.vddc_dependency_on_sclk; 1023 + 1024 + hwmgr->pstate_sclk = table->entries[0].clk / 100; 1025 + hwmgr->pstate_mclk = 0; 1026 + 1027 + hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100; 1028 + hwmgr->pstate_mclk_peak = 0; 1029 + } 1030 + 1019 1031 static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1020 1032 { 1021 1033 smu8_program_voting_clients(hwmgr); ··· 1035 1023 return -EINVAL; 1036 1024 smu8_program_bootup_state(hwmgr); 1037 1025 smu8_reset_acp_boot_level(hwmgr); 1026 + 1027 + smu8_populate_umdpstate_clocks(hwmgr); 1038 1028 1039 1029 return 0; 1040 1030 } ··· 1181 1167 1182 1168 data->sclk_dpm.soft_min_clk = table->entries[0].clk; 1183 1169 data->sclk_dpm.hard_min_clk = table->entries[0].clk; 1184 - hwmgr->pstate_sclk = table->entries[0].clk; 1185 - hwmgr->pstate_mclk = 0; 1186 1170 1187 1171 level = smu8_get_max_sclk_level(hwmgr) - 1; 1188 1172

+26 -5

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

··· 3008 3008 return 0; 3009 3009 } 3010 3010 3011 + static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 3012 + { 3013 + struct phm_ppt_v2_information *table_info = 3014 + (struct phm_ppt_v2_information *)(hwmgr->pptable); 3015 + 3016 + if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 3017 + table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 3018 + hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; 3019 + hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; 3020 + } else { 3021 + hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3022 + hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; 3023 + } 3024 + 3025 + hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk; 3026 + hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk; 3027 + 3028 + /* make sure the output is in Mhz */ 3029 + hwmgr->pstate_sclk /= 100; 3030 + hwmgr->pstate_mclk /= 100; 3031 + hwmgr->pstate_sclk_peak /= 100; 3032 + hwmgr->pstate_mclk_peak /= 100; 3033 + } 3034 + 3011 3035 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 3012 3036 { 3013 3037 struct vega10_hwmgr *data = hwmgr->backend; ··· 3105 3081 "Failed to enable ULV!", 3106 3082 result = tmp_result); 3107 3083 } 3084 + 3085 + vega10_populate_umdpstate_clocks(hwmgr); 3108 3086 3109 3087 return result; 3110 3088 } ··· 4195 4169 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; 4196 4170 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; 4197 4171 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; 4198 - hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; 4199 - hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; 4200 4172 } 4201 4173 4202 4174 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { ··· 4304 4280 uint32_t sclk_mask = 0; 4305 4281 uint32_t mclk_mask = 0; 4306 4282 uint32_t soc_mask = 0; 4307 - 4308 - if (hwmgr->pstate_sclk == 0) 4309 - vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 4310 4283 4311 4284 switch (level) { 4312 4285 case AMD_DPM_FORCED_LEVEL_HIGH:

+22

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

··· 1026 1026 return 0; 1027 1027 } 1028 1028 1029 + static void vega12_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1030 + { 1031 + struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1032 + struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 1033 + struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 1034 + 1035 + if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && 1036 + mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL) { 1037 + hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 1038 + hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 1039 + } else { 1040 + hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[0].value; 1041 + hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[0].value; 1042 + } 1043 + 1044 + hwmgr->pstate_sclk_peak = gfx_dpm_table->dpm_levels[gfx_dpm_table->count].value; 1045 + hwmgr->pstate_mclk_peak = mem_dpm_table->dpm_levels[mem_dpm_table->count].value; 1046 + } 1047 + 1029 1048 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1030 1049 { 1031 1050 int tmp_result, result = 0; ··· 1096 1077 PP_ASSERT_WITH_CODE(!result, 1097 1078 "Failed to setup default DPM tables!", 1098 1079 return result); 1080 + 1081 + vega12_populate_umdpstate_clocks(hwmgr); 1082 + 1099 1083 return result; 1100 1084 } 1101 1085

+7 -13

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

··· 1555 1555 return 0; 1556 1556 } 1557 1557 1558 - static int vega20_populate_umdpstate_clocks( 1559 - struct pp_hwmgr *hwmgr) 1558 + static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1560 1559 { 1561 1560 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1562 1561 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); 1563 1562 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); 1564 1563 1565 - hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; 1566 - hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; 1567 - 1568 1564 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && 1569 1565 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) { 1570 1566 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 1571 1567 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 1568 + } else { 1569 + hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; 1570 + hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; 1572 1571 } 1573 1572 1574 - hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100; 1575 - hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100; 1576 - 1577 - return 0; 1573 + hwmgr->pstate_sclk_peak = gfx_table->dpm_levels[gfx_table->count - 1].value; 1574 + hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value; 1578 1575 } 1579 1576 1580 1577 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, ··· 1750 1753 "[EnableDPMTasks] Failed to initialize odn settings!", 1751 1754 return result); 1752 1755 1753 - result = vega20_populate_umdpstate_clocks(hwmgr); 1754 - PP_ASSERT_WITH_CODE(!result, 1755 - "[EnableDPMTasks] Failed to populate umdpstate clocks!", 1756 - return result); 1756 + vega20_populate_umdpstate_clocks(hwmgr); 1757 1757 1758 1758 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit, 1759 1759 POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);

+2

drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

··· 809 809 uint32_t workload_prority[Workload_Policy_Max]; 810 810 uint32_t workload_setting[Workload_Policy_Max]; 811 811 bool gfxoff_state_changed_by_workload; 812 + uint32_t pstate_sclk_peak; 813 + uint32_t pstate_mclk_peak; 812 814 }; 813 815 814 816 int hwmgr_early_init(struct pp_hwmgr *hwmgr);

Configure Feed

Configure Feed