Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-2025-09-05' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Cross-subsystem Changes:
- iopoll: Generalize read_poll_timeout() into poll_timeout_us() (Ville)
Non-display related:
- PREEMPT_RT fix (Sebastian)
- Replace DRM_DEBUG_SELFTEST with DRM_KUNIT_TEST (Ruben, Imre)
- Some changes oeveral like in RPS, SoC, debugfs targeting display separation (Jani)
Display related:
- General refactor in favor of intel_display (Suraj)
- Prune modes for YUV420 (Suraj)
- Reject HBR3 in any eDP Panel (Ankit)
- Change AUX DPCD probe address (Imre)
- Display Wa fix, additions, and updates (Ankit, Vinod, Nemesa, Suraj, Jouni))
- DP: Fix 2.7 Gbps link training on g4x (Ville)
- DP: Adjust the idle pattern handling (Ville)
- DP: Shuffle the link training code a bit (Ville)
- Don't set/read the DSI C clock divider on GLK (Ville)
- Precompute plane SURF address/etc (Ville)
- Enable_psr kernel parameter changes (Jouni)
- PHY LFPS sending configuration fixes (Jouni)
- Fix dma_fence_wait_timeout() return value handling (Aakash)
- DP: Fix disabling training pattern (Imre)
- Small code clean-ups (Gustavo, Colin, Jani, Juha-Pekka)
- Change vblank log from err to debug (Suraj)
- More display clean-up towards intel_display split (Jani)
- Use the recomended min_hblank values (Arun)
- Block hpd during suspend (Dibin)
- DSI: Fix overflow issue in pclk parsing (Jouni)
- PSR: Do not trigger Frame Change events from frontbuffer flush (Jouni)
- VBT cleanups and new fields (Jani, Suraj)
- Type-C enabled/disconnected dp-alt sink (Imre)
- Optimize panel power-on wait time (Dibin)
- Wildcat Lake enabling (Imre, Chaitanya)
- DP HDR updates (Chaitanya)
- Fix divide by 0 error in i9xx_set_backlight (Suraj)
- Fixes for PSR (Jouni)
- Remove the encoder check in hdcp enable (Suraj)
- Control HDMI output bpc (Lee)
- Fix possible overflow on tc power (Mika)
- Convert code towards poll_timeout_* (Jani)
- Use REG_BIT on FW_BLC_SELF_* macros (Luca)
- ALPM LFPS and silence period calculation (Jouni)
- Remove power state verification before HW readout (Imre)
- Fix HPD mtp_tc_hpd_enable_detection (Ville)
- DRAM detection (Ville)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/aLtc-gk3jhwcWxZh@intel.com
+2129
-1402
+1
-1
drivers/gpu/drm/i915/Kconfig.debug
+1
-1
drivers/gpu/drm/i915/Kconfig.debug
···
50
50
select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
51
51
select DRM_DEBUG_MM if DRM=y
52
52
select DRM_EXPORT_FOR_TESTS if m
53
-
select DRM_DEBUG_SELFTEST
53
+
select DRM_KUNIT_TEST if KUNIT
54
54
select DMABUF_SELFTESTS
55
55
select SW_SYNC # signaling validation framework (igt/syncobj*)
56
56
select DRM_I915_WERROR
+32
-19
drivers/gpu/drm/i915/display/g4x_dp.c
+32
-19
drivers/gpu/drm/i915/display/g4x_dp.c
···
424
424
425
425
drm_dbg_kms(display->drm, "\n");
426
426
427
-
if ((display->platform.ivybridge && port == PORT_A) ||
428
-
(HAS_PCH_CPT(display) && port != PORT_A)) {
429
-
intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
430
-
intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
431
-
} else {
432
-
intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
433
-
intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
434
-
}
435
-
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
436
-
intel_de_posting_read(display, intel_dp->output_reg);
437
-
438
427
intel_dp->DP &= ~DP_PORT_EN;
439
428
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
440
429
intel_de_posting_read(display, intel_dp->output_reg);
···
601
612
}
602
613
603
614
static void
615
+
cpt_set_idle_link_train(struct intel_dp *intel_dp,
616
+
const struct intel_crtc_state *crtc_state)
617
+
{
618
+
struct intel_display *display = to_intel_display(intel_dp);
619
+
620
+
intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
621
+
intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
622
+
623
+
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
624
+
intel_de_posting_read(display, intel_dp->output_reg);
625
+
}
626
+
627
+
static void
604
628
g4x_set_link_train(struct intel_dp *intel_dp,
605
629
const struct intel_crtc_state *crtc_state,
606
630
u8 dp_train_pat)
···
636
634
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
637
635
return;
638
636
}
637
+
638
+
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
639
+
intel_de_posting_read(display, intel_dp->output_reg);
640
+
}
641
+
642
+
static void
643
+
g4x_set_idle_link_train(struct intel_dp *intel_dp,
644
+
const struct intel_crtc_state *crtc_state)
645
+
{
646
+
struct intel_display *display = to_intel_display(intel_dp);
647
+
648
+
intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
649
+
intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
639
650
640
651
intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
641
652
intel_de_posting_read(display, intel_dp->output_reg);
···
1300
1285
drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
1301
1286
port_name(port));
1302
1287
1303
-
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
1288
+
dig_port = intel_dig_port_alloc();
1304
1289
if (!dig_port)
1305
1290
return false;
1306
-
1307
-
dig_port->aux_ch = AUX_CH_NONE;
1308
1291
1309
1292
intel_connector = intel_connector_alloc();
1310
1293
if (!intel_connector)
···
1312
1299
encoder = &intel_encoder->base;
1313
1300
1314
1301
intel_encoder->devdata = devdata;
1315
-
1316
-
mutex_init(&dig_port->hdcp.mutex);
1317
1302
1318
1303
if (drm_encoder_init(display->drm, &intel_encoder->base,
1319
1304
&intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
···
1353
1342
intel_encoder->audio_disable = g4x_dp_audio_disable;
1354
1343
1355
1344
if ((display->platform.ivybridge && port == PORT_A) ||
1356
-
(HAS_PCH_CPT(display) && port != PORT_A))
1345
+
(HAS_PCH_CPT(display) && port != PORT_A)) {
1357
1346
dig_port->dp.set_link_train = cpt_set_link_train;
1358
-
else
1347
+
dig_port->dp.set_idle_link_train = cpt_set_idle_link_train;
1348
+
} else {
1359
1349
dig_port->dp.set_link_train = g4x_set_link_train;
1350
+
dig_port->dp.set_idle_link_train = g4x_set_idle_link_train;
1351
+
}
1360
1352
1361
1353
if (display->platform.cherryview)
1362
1354
intel_encoder->set_signal_levels = chv_set_signal_levels;
···
1382
1368
}
1383
1369
1384
1370
dig_port->dp.output_reg = output_reg;
1385
-
dig_port->max_lanes = 4;
1386
1371
1387
1372
intel_encoder->type = INTEL_OUTPUT_DP;
1388
1373
intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
+3
-12
drivers/gpu/drm/i915/display/g4x_hdmi.c
+3
-12
drivers/gpu/drm/i915/display/g4x_hdmi.c
···
19
19
#include "intel_display_types.h"
20
20
#include "intel_dp_aux.h"
21
21
#include "intel_dpio_phy.h"
22
-
#include "intel_fdi.h"
22
+
#include "intel_encoder.h"
23
23
#include "intel_fifo_underrun.h"
24
24
#include "intel_hdmi.h"
25
25
#include "intel_hotplug.h"
···
135
135
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
136
136
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
137
137
138
-
if (HAS_PCH_SPLIT(display)) {
138
+
if (HAS_PCH_SPLIT(display))
139
139
crtc_state->has_pch_encoder = true;
140
-
if (!intel_fdi_compute_pipe_bpp(crtc_state))
141
-
return -EINVAL;
142
-
}
143
140
144
141
if (display->platform.g4x)
145
142
crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
···
687
690
drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",
688
691
port_name(port));
689
692
690
-
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
693
+
dig_port = intel_dig_port_alloc();
691
694
if (!dig_port)
692
695
return false;
693
-
694
-
dig_port->aux_ch = AUX_CH_NONE;
695
696
696
697
intel_connector = intel_connector_alloc();
697
698
if (!intel_connector)
···
698
703
intel_encoder = &dig_port->base;
699
704
700
705
intel_encoder->devdata = devdata;
701
-
702
-
mutex_init(&dig_port->hdcp.mutex);
703
706
704
707
if (drm_encoder_init(display->drm, &intel_encoder->base,
705
708
&intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
···
760
767
intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);
761
768
762
769
dig_port->hdmi.hdmi_reg = hdmi_reg;
763
-
dig_port->dp.output_reg = INVALID_MMIO_REG;
764
-
dig_port->max_lanes = 4;
765
770
766
771
intel_infoframe_init(dig_port);
767
772
+29
-29
drivers/gpu/drm/i915/display/i9xx_plane.c
+29
-29
drivers/gpu/drm/i915/display/i9xx_plane.c
···
155
155
i9xx_plane == PLANE_C;
156
156
}
157
157
158
-
static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
159
-
const struct intel_plane_state *plane_state)
158
+
static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state)
160
159
{
161
160
struct intel_display *display = to_intel_display(plane_state);
162
161
const struct drm_framebuffer *fb = plane_state->hw.fb;
···
354
355
if (ret)
355
356
return ret;
356
357
357
-
plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
358
+
plane_state->ctl = i9xx_plane_ctl(plane_state);
358
359
359
360
return 0;
361
+
}
362
+
363
+
static u32 i8xx_plane_surf_offset(const struct intel_plane_state *plane_state)
364
+
{
365
+
int x = plane_state->view.color_plane[0].x;
366
+
int y = plane_state->view.color_plane[0].y;
367
+
368
+
return intel_fb_xy_to_linear(x, y, plane_state, 0);
369
+
}
370
+
371
+
u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state)
372
+
{
373
+
return plane_state->view.color_plane[0].offset;
360
374
}
361
375
362
376
static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
···
475
463
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
476
464
int x = plane_state->view.color_plane[0].x;
477
465
int y = plane_state->view.color_plane[0].y;
478
-
u32 dspcntr, dspaddr_offset, linear_offset;
466
+
u32 dspcntr;
479
467
480
468
dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
481
469
···
483
471
if (plane->need_async_flip_toggle_wa &&
484
472
crtc_state->async_flip_planes & BIT(plane->id))
485
473
dspcntr |= DISP_ASYNC_FLIP;
486
-
487
-
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
488
-
489
-
if (DISPLAY_VER(display) >= 4)
490
-
dspaddr_offset = plane_state->view.color_plane[0].offset;
491
-
else
492
-
dspaddr_offset = linear_offset;
493
474
494
475
if (display->platform.cherryview && i9xx_plane == PLANE_B) {
495
476
int crtc_x = plane_state->uapi.dst.x1;
···
503
498
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
504
499
} else if (DISPLAY_VER(display) >= 4) {
505
500
intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane),
506
-
linear_offset);
501
+
intel_fb_xy_to_linear(x, y, plane_state, 0));
507
502
intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane),
508
503
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
509
504
}
···
516
511
intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
517
512
518
513
if (DISPLAY_VER(display) >= 4)
519
-
intel_de_write_fw(display, DSPSURF(display, i9xx_plane),
520
-
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
514
+
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);
521
515
else
522
-
intel_de_write_fw(display, DSPADDR(display, i9xx_plane),
523
-
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
516
+
intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);
524
517
}
525
518
526
519
static void i830_plane_update_arm(struct intel_dsb *dsb,
···
607
604
{
608
605
struct intel_display *display = to_intel_display(plane);
609
606
u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
610
-
u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
611
607
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
612
608
613
609
if (async_flip)
614
610
dspcntr |= DISP_ASYNC_FLIP;
615
611
616
612
intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);
617
-
618
-
intel_de_write_fw(display, DSPSURF(display, i9xx_plane),
619
-
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
613
+
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);
620
614
}
621
615
622
616
static void
···
624
624
bool async_flip)
625
625
{
626
626
struct intel_display *display = to_intel_display(plane);
627
-
u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
628
627
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
629
628
630
-
intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane),
631
-
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
629
+
intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);
632
630
}
633
631
634
632
static void
···
1035
1037
plane->get_hw_state = i9xx_plane_get_hw_state;
1036
1038
plane->check_plane = i9xx_plane_check;
1037
1039
1040
+
if (DISPLAY_VER(display) >= 4)
1041
+
plane->surf_offset = i965_plane_surf_offset;
1042
+
else
1043
+
plane->surf_offset = i8xx_plane_surf_offset;
1044
+
1038
1045
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1039
1046
plane->capture_error = g4x_primary_capture_error;
1040
1047
else if (DISPLAY_VER(display) >= 4)
···
1257
1254
const struct intel_plane_state *plane_state =
1258
1255
to_intel_plane_state(plane->base.state);
1259
1256
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1260
-
u32 base;
1261
1257
1262
1258
if (!plane_state->uapi.visible)
1263
1259
return false;
1264
-
1265
-
base = intel_plane_ggtt_offset(plane_state);
1266
1260
1267
1261
/*
1268
1262
* We may have moved the surface to a different
1269
1263
* part of ggtt, make the plane aware of that.
1270
1264
*/
1271
-
if (plane_config->base == base)
1265
+
if (plane_config->base == plane_state->surf)
1272
1266
return false;
1273
1267
1274
1268
if (DISPLAY_VER(display) >= 4)
1275
-
intel_de_write(display, DSPSURF(display, i9xx_plane), base);
1269
+
intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);
1276
1270
else
1277
-
intel_de_write(display, DSPADDR(display, i9xx_plane), base);
1271
+
intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);
1278
1272
1279
1273
return true;
1280
1274
}
+1
drivers/gpu/drm/i915/display/i9xx_plane.h
+1
drivers/gpu/drm/i915/display/i9xx_plane.h
···
24
24
const struct drm_framebuffer *fb,
25
25
int colot_plane);
26
26
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
27
+
u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state);
27
28
28
29
struct intel_plane *
29
30
intel_primary_plane_create(struct intel_display *display, enum pipe pipe);
+22
-10
drivers/gpu/drm/i915/display/i9xx_wm.c
+22
-10
drivers/gpu/drm/i915/display/i9xx_wm.c
···
3
3
* Copyright © 2023 Intel Corporation
4
4
*/
5
5
6
+
#include <linux/iopoll.h>
7
+
8
+
#include "soc/intel_dram.h"
9
+
6
10
#include "i915_drv.h"
7
11
#include "i915_reg.h"
8
12
#include "i9xx_wm.h"
···
89
85
90
86
static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)
91
87
{
92
-
struct drm_i915_private *i915 = to_i915(display->drm);
88
+
const struct dram_info *dram_info = intel_dram_info(display->drm);
89
+
bool is_ddr3 = dram_info->type == INTEL_DRAM_DDR3;
93
90
int i;
94
91
95
92
for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
···
98
93
bool is_desktop = !display->platform.mobile;
99
94
100
95
if (is_desktop == latency->is_desktop &&
101
-
i915->is_ddr3 == latency->is_ddr3 &&
102
-
DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
103
-
DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
96
+
is_ddr3 == latency->is_ddr3 &&
97
+
DIV_ROUND_CLOSEST(dram_info->fsb_freq, 1000) == latency->fsb_freq &&
98
+
DIV_ROUND_CLOSEST(dram_info->mem_freq, 1000) == latency->mem_freq)
104
99
return latency;
105
100
}
106
101
107
102
drm_dbg_kms(display->drm,
108
-
"Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
109
-
i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
103
+
"Could not find CxSR latency for %s, FSB %u kHz, MEM %u kHz\n",
104
+
intel_dram_type_str(dram_info->type),
105
+
dram_info->fsb_freq, dram_info->mem_freq);
110
106
111
107
return NULL;
112
108
}
···
115
109
static void chv_set_memory_dvfs(struct intel_display *display, bool enable)
116
110
{
117
111
u32 val;
112
+
int ret;
118
113
119
114
vlv_punit_get(display->drm);
120
115
···
128
121
val |= FORCE_DDR_FREQ_REQ_ACK;
129
122
vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);
130
123
131
-
if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) &
132
-
FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
124
+
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
125
+
(val & FORCE_DDR_FREQ_REQ_ACK) == 0,
126
+
500, 3000, false);
127
+
if (ret)
133
128
drm_err(display->drm,
134
129
"timed out waiting for Punit DDR DVFS request\n");
135
130
···
3911
3902
struct vlv_wm_values *wm = &display->wm.vlv;
3912
3903
struct intel_crtc *crtc;
3913
3904
u32 val;
3905
+
int ret;
3914
3906
3915
3907
vlv_read_wm_values(display, wm);
3916
3908
···
3938
3928
val |= FORCE_DDR_FREQ_REQ_ACK;
3939
3929
vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val);
3940
3930
3941
-
if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) &
3942
-
FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3931
+
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
3932
+
(val & FORCE_DDR_FREQ_REQ_ACK) == 0,
3933
+
500, 3000, false);
3934
+
if (ret) {
3943
3935
drm_dbg_kms(display->drm,
3944
3936
"Punit not acking DDR DVFS request, "
3945
3937
"assuming DDR DVFS is disabled\n");
+42
-17
drivers/gpu/drm/i915/display/icl_dsi.c
+42
-17
drivers/gpu/drm/i915/display/icl_dsi.c
···
25
25
* Jani Nikula <jani.nikula@intel.com>
26
26
*/
27
27
28
+
#include <linux/iopoll.h>
29
+
28
30
#include <drm/display/drm_dsc_helper.h>
29
31
#include <drm/drm_atomic_helper.h>
30
32
#include <drm/drm_fixed.h>
···
74
72
static bool wait_for_header_credits(struct intel_display *display,
75
73
enum transcoder dsi_trans, int hdr_credit)
76
74
{
77
-
if (wait_for_us(header_credits_available(display, dsi_trans) >=
78
-
hdr_credit, 100)) {
75
+
int ret, available;
76
+
77
+
ret = poll_timeout_us(available = header_credits_available(display, dsi_trans),
78
+
available >= hdr_credit,
79
+
10, 100, false);
80
+
if (ret) {
79
81
drm_err(display->drm, "DSI header credits not released\n");
80
82
return false;
81
83
}
···
90
84
static bool wait_for_payload_credits(struct intel_display *display,
91
85
enum transcoder dsi_trans, int payld_credit)
92
86
{
93
-
if (wait_for_us(payload_credits_available(display, dsi_trans) >=
94
-
payld_credit, 100)) {
87
+
int ret, available;
88
+
89
+
ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans),
90
+
available >= payld_credit,
91
+
10, 100, false);
92
+
if (ret) {
95
93
drm_err(display->drm, "DSI payload credits not released\n");
96
94
return false;
97
95
}
···
147
137
/* wait for LP TX in progress bit to be cleared */
148
138
for_each_dsi_port(port, intel_dsi->ports) {
149
139
dsi_trans = dsi_port_to_transcoder(port);
150
-
if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
151
-
LPTX_IN_PROGRESS), 20))
140
+
141
+
ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
142
+
LPTX_IN_PROGRESS, 0,
143
+
20, 0, NULL);
144
+
if (ret)
152
145
drm_err(display->drm, "LPTX bit not cleared\n");
153
146
}
154
147
}
···
529
516
struct intel_display *display = to_intel_display(encoder);
530
517
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
531
518
enum port port;
519
+
int ret;
532
520
533
521
for_each_dsi_port(port, intel_dsi->ports) {
534
522
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
535
523
536
-
if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
537
-
DDI_BUF_IS_IDLE),
538
-
500))
524
+
ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
525
+
DDI_BUF_IS_IDLE, 0,
526
+
500, 0, NULL);
527
+
if (ret)
539
528
drm_err(display->drm, "DDI port:%c buffer idle\n",
540
529
port_name(port));
541
530
}
···
853
838
854
839
/* wait for link ready */
855
840
for_each_dsi_port(port, intel_dsi->ports) {
841
+
int ret;
842
+
856
843
dsi_trans = dsi_port_to_transcoder(port);
857
-
if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
858
-
LINK_READY), 2500))
844
+
845
+
ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans),
846
+
LINK_READY, LINK_READY,
847
+
2500, 0, NULL);
848
+
if (ret)
859
849
drm_err(display->drm, "DSI link not ready\n");
860
850
}
861
851
}
···
1341
1321
enum port port;
1342
1322
enum transcoder dsi_trans;
1343
1323
u32 tmp;
1324
+
int ret;
1344
1325
1345
1326
/* disable periodic update mode */
1346
1327
if (is_cmd_mode(intel_dsi)) {
···
1358
1337
tmp &= ~LINK_ULPS_TYPE_LP11;
1359
1338
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
1360
1339
1361
-
if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
1362
-
LINK_IN_ULPS),
1363
-
10))
1340
+
ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
1341
+
LINK_IN_ULPS, LINK_IN_ULPS,
1342
+
10, 0, NULL);
1343
+
if (ret)
1364
1344
drm_err(display->drm, "DSI link not in ULPS\n");
1365
1345
}
1366
1346
···
1389
1367
struct intel_display *display = to_intel_display(encoder);
1390
1368
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1391
1369
enum port port;
1370
+
int ret;
1392
1371
1393
1372
gen11_dsi_ungate_clocks(encoder);
1394
1373
for_each_dsi_port(port, intel_dsi->ports) {
1395
1374
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1396
1375
1397
-
if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
1398
-
DDI_BUF_IS_IDLE),
1399
-
8))
1376
+
ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
1377
+
DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE,
1378
+
8, 0, NULL);
1379
+
1380
+
if (ret)
1400
1381
drm_err(display->drm,
1401
1382
"DDI port:%c buffer not idle\n",
1402
1383
port_name(port));
+58
-75
drivers/gpu/drm/i915/display/intel_alpm.c
+58
-75
drivers/gpu/drm/i915/display/intel_alpm.c
···
16
16
#include "intel_psr.h"
17
17
#include "intel_psr_regs.h"
18
18
19
+
#define SILENCE_PERIOD_MIN_TIME 80
20
+
#define SILENCE_PERIOD_MAX_TIME 180
21
+
#define SILENCE_PERIOD_TIME (SILENCE_PERIOD_MIN_TIME + \
22
+
(SILENCE_PERIOD_MAX_TIME - \
23
+
SILENCE_PERIOD_MIN_TIME) / 2)
24
+
25
+
#define LFPS_CYCLE_COUNT 10
26
+
19
27
bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
20
28
{
21
29
return intel_dp->alpm_dpcd & DP_ALPM_CAP;
···
52
44
mutex_init(&intel_dp->alpm_parameters.lock);
53
45
}
54
46
55
-
/*
56
-
* See Bspec: 71632 for the table
57
-
*
58
-
* Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)
59
-
*
60
-
* Half cycle duration:
61
-
*
62
-
* Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns
63
-
* FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )
64
-
*
65
-
* Link rates 5.4 - 8.1
66
-
* PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10
67
-
* LFPS Period chosen is the mid-point of the min:max values from the table
68
-
* FLOOR( LFPS Period in Symbol clocks /
69
-
* (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) )
70
-
*/
71
-
static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate,
72
-
int *silence_period,
73
-
int *lfps_half_cycle)
47
+
static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
74
48
{
75
-
switch (link_rate) {
76
-
case 162000:
77
-
*silence_period = 20;
78
-
*lfps_half_cycle = 5;
79
-
break;
80
-
case 216000:
81
-
*silence_period = 27;
82
-
*lfps_half_cycle = 7;
83
-
break;
84
-
case 243000:
85
-
*silence_period = 31;
86
-
*lfps_half_cycle = 8;
87
-
break;
88
-
case 270000:
89
-
*silence_period = 34;
90
-
*lfps_half_cycle = 9;
91
-
break;
92
-
case 324000:
93
-
*silence_period = 41;
94
-
*lfps_half_cycle = 11;
95
-
break;
96
-
case 432000:
97
-
*silence_period = 56;
98
-
*lfps_half_cycle = 15;
99
-
break;
100
-
case 540000:
101
-
*silence_period = 69;
102
-
*lfps_half_cycle = 12;
103
-
break;
104
-
case 648000:
105
-
*silence_period = 84;
106
-
*lfps_half_cycle = 15;
107
-
break;
108
-
case 675000:
109
-
*silence_period = 87;
110
-
*lfps_half_cycle = 15;
111
-
break;
112
-
case 810000:
113
-
*silence_period = 104;
114
-
*lfps_half_cycle = 19;
115
-
break;
116
-
default:
117
-
*silence_period = *lfps_half_cycle = -1;
118
-
return false;
49
+
return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /
50
+
1000 / 1000;
51
+
}
52
+
53
+
static int get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
54
+
int *min, int *max)
55
+
{
56
+
if (crtc_state->port_clock < 540000) {
57
+
*min = 65 * LFPS_CYCLE_COUNT;
58
+
*max = 75 * LFPS_CYCLE_COUNT;
59
+
} else if (crtc_state->port_clock <= 810000) {
60
+
*min = 140;
61
+
*max = 800;
62
+
} else {
63
+
*min = *max = -1;
64
+
return -1;
119
65
}
120
-
return true;
66
+
67
+
return 0;
68
+
}
69
+
70
+
static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
71
+
{
72
+
int tlfps_cycle_min, tlfps_cycle_max, ret;
73
+
74
+
ret = get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
75
+
&tlfps_cycle_max);
76
+
if (ret)
77
+
return ret;
78
+
79
+
return tlfps_cycle_min + (tlfps_cycle_max - tlfps_cycle_min) / 2;
80
+
}
81
+
82
+
static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
83
+
{
84
+
int lfps_cycle_time = get_lfps_cycle_time(crtc_state);
85
+
86
+
if (lfps_cycle_time < 0)
87
+
return -1;
88
+
89
+
return lfps_cycle_time * crtc_state->port_clock / 1000 / 1000 / (2 * LFPS_CYCLE_COUNT);
121
90
}
122
91
123
92
/*
···
116
131
* tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
117
132
* TPS4 Length = 252 Symbols
118
133
*/
119
-
static int _lnl_compute_aux_less_wake_time(int port_clock)
134
+
static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
120
135
{
121
136
int tphy2_p2_to_p0 = 12 * 1000;
122
-
int tlfps_period_max = 800;
123
-
int tsilence_max = 180;
124
137
int t1 = 50 * 1000;
125
138
int tps4 = 252;
126
139
/* port_clock is link rate in 10kbit/s units */
127
-
int tml_phy_lock = 1000 * 1000 * tps4 / port_clock;
140
+
int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
128
141
int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
129
142
int t2 = num_ml_phy_lock * tml_phy_lock;
130
143
int tcds = 1 * t2;
131
144
132
-
return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max +
133
-
t1 + tcds, 1000);
145
+
return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
146
+
SILENCE_PERIOD_TIME + t1 + tcds, 1000);
134
147
}
135
148
136
149
static int
···
140
157
lfps_half_cycle;
141
158
142
159
aux_less_wake_time =
143
-
_lnl_compute_aux_less_wake_time(crtc_state->port_clock);
160
+
_lnl_compute_aux_less_wake_time(crtc_state);
144
161
aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
145
162
aux_less_wake_time);
163
+
silence_period = get_silence_period_symbols(crtc_state);
146
164
147
-
if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock,
148
-
&silence_period,
149
-
&lfps_half_cycle))
165
+
lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
166
+
if (lfps_half_cycle < 0)
150
167
return false;
151
168
152
169
if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
···
389
406
PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
390
407
PORT_ALPM_CTL_SILENCE_PERIOD(
391
408
intel_dp->alpm_parameters.silence_period_sym_clocks);
392
-
lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
409
+
lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
393
410
PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
394
411
intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
395
412
PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
+2
-1
drivers/gpu/drm/i915/display/intel_backlight.c
+2
-1
drivers/gpu/drm/i915/display/intel_backlight.c
···
236
236
struct intel_panel *panel = &connector->panel;
237
237
u32 tmp, mask;
238
238
239
-
drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);
239
+
if (drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0))
240
+
return;
240
241
241
242
if (panel->backlight.combination_mode) {
242
243
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
+38
-8
drivers/gpu/drm/i915/display/intel_bios.c
+38
-8
drivers/gpu/drm/i915/display/intel_bios.c
···
36
36
#include "soc/intel_rom.h"
37
37
38
38
#include "i915_drv.h"
39
+
#include "i915_utils.h"
39
40
#include "intel_display.h"
40
41
#include "intel_display_core.h"
41
42
#include "intel_display_rpm.h"
···
1567
1566
1568
1567
panel->vbt.psr.full_link = psr_table->full_link;
1569
1568
panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
1570
-
1571
-
/* Allowed VBT values goes from 0 to 15 */
1572
-
panel->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
1573
-
psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
1569
+
panel->vbt.psr.idle_frames = psr_table->idle_frames;
1574
1570
1575
1571
/*
1576
1572
* New psr options 0=500us, 1=100us, 2=2500us, 3=0us
···
2478
2480
}
2479
2481
}
2480
2482
2483
+
static u32 edp_rate_override_mask(int rate)
2484
+
{
2485
+
switch (rate) {
2486
+
case 2000000: return BDB_263_VBT_EDP_LINK_RATE_20;
2487
+
case 1350000: return BDB_263_VBT_EDP_LINK_RATE_13_5;
2488
+
case 1000000: return BDB_263_VBT_EDP_LINK_RATE_10;
2489
+
case 810000: return BDB_263_VBT_EDP_LINK_RATE_8_1;
2490
+
case 675000: return BDB_263_VBT_EDP_LINK_RATE_6_75;
2491
+
case 540000: return BDB_263_VBT_EDP_LINK_RATE_5_4;
2492
+
case 432000: return BDB_263_VBT_EDP_LINK_RATE_4_32;
2493
+
case 324000: return BDB_263_VBT_EDP_LINK_RATE_3_24;
2494
+
case 270000: return BDB_263_VBT_EDP_LINK_RATE_2_7;
2495
+
case 243000: return BDB_263_VBT_EDP_LINK_RATE_2_43;
2496
+
case 216000: return BDB_263_VBT_EDP_LINK_RATE_2_16;
2497
+
case 162000: return BDB_263_VBT_EDP_LINK_RATE_1_62;
2498
+
default: return 0;
2499
+
}
2500
+
}
2501
+
2481
2502
int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata)
2482
2503
{
2483
2504
if (!devdata || devdata->display->vbt.version < 216)
···
2514
2497
return 0;
2515
2498
2516
2499
return devdata->child.dp_max_lane_count + 1;
2500
+
}
2501
+
2502
+
bool
2503
+
intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata,
2504
+
int rate)
2505
+
{
2506
+
if (!devdata || devdata->display->vbt.version < 263)
2507
+
return false;
2508
+
2509
+
if (devdata->child.edp_data_rate_override == BDB_263_VBT_EDP_RATES_MASK)
2510
+
return false;
2511
+
2512
+
return devdata->child.edp_data_rate_override & edp_rate_override_mask(rate);
2517
2513
}
2518
2514
2519
2515
static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
···
2777
2747
{
2778
2748
BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
2779
2749
2780
-
if (version > 256)
2750
+
if (version > 263)
2781
2751
return -ENOENT;
2752
+
else if (version >= 263)
2753
+
return 44;
2782
2754
else if (version >= 256)
2783
2755
return 40;
2784
2756
else if (version >= 216)
···
3775
3743
3776
3744
void intel_bios_debugfs_register(struct intel_display *display)
3777
3745
{
3778
-
struct drm_minor *minor = display->drm->primary;
3779
-
3780
-
debugfs_create_file("i915_vbt", 0444, minor->debugfs_root,
3746
+
debugfs_create_file("i915_vbt", 0444, display->drm->debugfs_root,
3781
3747
display, &intel_bios_vbt_fops);
3782
3748
}
+2
-174
drivers/gpu/drm/i915/display/intel_bios.h
+2
-174
drivers/gpu/drm/i915/display/intel_bios.h
···
50
50
INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
51
51
};
52
52
53
-
/*
54
-
* MIPI Sequence Block definitions
55
-
*
56
-
* Note the VBT spec has AssertReset / DeassertReset swapped from their
57
-
* usual naming, we use the proper names here to avoid confusion when
58
-
* reading the code.
59
-
*/
60
-
enum mipi_seq {
61
-
MIPI_SEQ_END = 0,
62
-
MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */
63
-
MIPI_SEQ_INIT_OTP,
64
-
MIPI_SEQ_DISPLAY_ON,
65
-
MIPI_SEQ_DISPLAY_OFF,
66
-
MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */
67
-
MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
68
-
MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
69
-
MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
70
-
MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
71
-
MIPI_SEQ_POWER_ON, /* sequence block v3+ */
72
-
MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
73
-
MIPI_SEQ_MAX
74
-
};
75
-
76
-
enum mipi_seq_element {
77
-
MIPI_SEQ_ELEM_END = 0,
78
-
MIPI_SEQ_ELEM_SEND_PKT,
79
-
MIPI_SEQ_ELEM_DELAY,
80
-
MIPI_SEQ_ELEM_GPIO,
81
-
MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
82
-
MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
83
-
MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
84
-
MIPI_SEQ_ELEM_MAX
85
-
};
86
-
87
-
#define MIPI_DSI_UNDEFINED_PANEL_ID 0
88
-
#define MIPI_DSI_GENERIC_PANEL_ID 1
89
-
90
-
struct mipi_config {
91
-
u16 panel_id;
92
-
93
-
/* General Params */
94
-
u32 enable_dithering:1;
95
-
u32 rsvd1:1;
96
-
u32 is_bridge:1;
97
-
98
-
u32 panel_arch_type:2;
99
-
u32 is_cmd_mode:1;
100
-
101
-
#define NON_BURST_SYNC_PULSE 0x1
102
-
#define NON_BURST_SYNC_EVENTS 0x2
103
-
#define BURST_MODE 0x3
104
-
u32 video_transfer_mode:2;
105
-
106
-
u32 cabc_supported:1;
107
-
#define PPS_BLC_PMIC 0
108
-
#define PPS_BLC_SOC 1
109
-
u32 pwm_blc:1;
110
-
111
-
/* Bit 13:10 */
112
-
#define PIXEL_FORMAT_RGB565 0x1
113
-
#define PIXEL_FORMAT_RGB666 0x2
114
-
#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
115
-
#define PIXEL_FORMAT_RGB888 0x4
116
-
u32 videomode_color_format:4;
117
-
118
-
/* Bit 15:14 */
119
-
#define ENABLE_ROTATION_0 0x0
120
-
#define ENABLE_ROTATION_90 0x1
121
-
#define ENABLE_ROTATION_180 0x2
122
-
#define ENABLE_ROTATION_270 0x3
123
-
u32 rotation:2;
124
-
u32 bta_enabled:1;
125
-
u32 rsvd2:15;
126
-
127
-
/* 2 byte Port Description */
128
-
#define DUAL_LINK_NOT_SUPPORTED 0
129
-
#define DUAL_LINK_FRONT_BACK 1
130
-
#define DUAL_LINK_PIXEL_ALT 2
131
-
u16 dual_link:2;
132
-
u16 lane_cnt:2;
133
-
u16 pixel_overlap:3;
134
-
u16 rgb_flip:1;
135
-
#define DL_DCS_PORT_A 0x00
136
-
#define DL_DCS_PORT_C 0x01
137
-
#define DL_DCS_PORT_A_AND_C 0x02
138
-
u16 dl_dcs_cabc_ports:2;
139
-
u16 dl_dcs_backlight_ports:2;
140
-
u16 rsvd3:4;
141
-
142
-
u16 rsvd4;
143
-
144
-
u8 rsvd5;
145
-
u32 target_burst_mode_freq;
146
-
u32 dsi_ddr_clk;
147
-
u32 bridge_ref_clk;
148
-
149
-
#define BYTE_CLK_SEL_20MHZ 0
150
-
#define BYTE_CLK_SEL_10MHZ 1
151
-
#define BYTE_CLK_SEL_5MHZ 2
152
-
u8 byte_clk_sel:2;
153
-
154
-
u8 rsvd6:6;
155
-
156
-
/* DPHY Flags */
157
-
u16 dphy_param_valid:1;
158
-
u16 eot_pkt_disabled:1;
159
-
u16 enable_clk_stop:1;
160
-
u16 rsvd7:13;
161
-
162
-
u32 hs_tx_timeout;
163
-
u32 lp_rx_timeout;
164
-
u32 turn_around_timeout;
165
-
u32 device_reset_timer;
166
-
u32 master_init_timer;
167
-
u32 dbi_bw_timer;
168
-
u32 lp_byte_clk_val;
169
-
170
-
/* 4 byte Dphy Params */
171
-
u32 prepare_cnt:6;
172
-
u32 rsvd8:2;
173
-
u32 clk_zero_cnt:8;
174
-
u32 trail_cnt:5;
175
-
u32 rsvd9:3;
176
-
u32 exit_zero_cnt:6;
177
-
u32 rsvd10:2;
178
-
179
-
u32 clk_lane_switch_cnt;
180
-
u32 hl_switch_cnt;
181
-
182
-
u32 rsvd11[6];
183
-
184
-
/* timings based on dphy spec */
185
-
u8 tclk_miss;
186
-
u8 tclk_post;
187
-
u8 rsvd12;
188
-
u8 tclk_pre;
189
-
u8 tclk_prepare;
190
-
u8 tclk_settle;
191
-
u8 tclk_term_enable;
192
-
u8 tclk_trail;
193
-
u16 tclk_prepare_clkzero;
194
-
u8 rsvd13;
195
-
u8 td_term_enable;
196
-
u8 teot;
197
-
u8 ths_exit;
198
-
u8 ths_prepare;
199
-
u16 ths_prepare_hszero;
200
-
u8 rsvd14;
201
-
u8 ths_settle;
202
-
u8 ths_skip;
203
-
u8 ths_trail;
204
-
u8 tinit;
205
-
u8 tlpx;
206
-
u8 rsvd15[3];
207
-
208
-
/* GPIOs */
209
-
u8 panel_enable;
210
-
u8 bl_enable;
211
-
u8 pwm_enable;
212
-
u8 reset_r_n;
213
-
u8 pwr_down_r;
214
-
u8 stdby_r_n;
215
-
216
-
} __packed;
217
-
218
-
/* all delays have a unit of 100us */
219
-
struct mipi_pps_data {
220
-
u16 panel_on_delay;
221
-
u16 bl_enable_delay;
222
-
u16 bl_disable_delay;
223
-
u16 panel_off_delay;
224
-
u16 panel_power_cycle_delay;
225
-
} __packed;
226
-
227
53
void intel_bios_init(struct intel_display *display);
228
54
void intel_bios_init_panel_early(struct intel_display *display,
229
55
struct intel_panel *panel,
···
85
259
bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata);
86
260
bool intel_bios_encoder_hpd_invert(const struct intel_bios_encoder_data *devdata);
87
261
enum port intel_bios_encoder_port(const struct intel_bios_encoder_data *devdata);
262
+
bool intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata,
263
+
int rate);
88
264
enum aux_ch intel_bios_dp_aux_ch(const struct intel_bios_encoder_data *devdata);
89
265
int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata);
90
266
int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata);
+1
-1
drivers/gpu/drm/i915/display/intel_bo.c
+1
-1
drivers/gpu/drm/i915/display/intel_bo.c
+1
-1
drivers/gpu/drm/i915/display/intel_bw.c
+1
-1
drivers/gpu/drm/i915/display/intel_bw.c
+31
-25
drivers/gpu/drm/i915/display/intel_cdclk.c
+31
-25
drivers/gpu/drm/i915/display/intel_cdclk.c
···
22
22
*/
23
23
24
24
#include <linux/debugfs.h>
25
+
#include <linux/iopoll.h>
25
26
#include <linux/time.h>
26
27
27
28
#include <drm/drm_fixed.h>
···
32
31
#include "hsw_ips.h"
33
32
#include "i915_drv.h"
34
33
#include "i915_reg.h"
34
+
#include "i915_utils.h"
35
35
#include "intel_atomic.h"
36
36
#include "intel_audio.h"
37
37
#include "intel_bw.h"
···
674
672
int cdclk = cdclk_config->cdclk;
675
673
u32 val, cmd = cdclk_config->voltage_level;
676
674
intel_wakeref_t wakeref;
675
+
int ret;
677
676
678
677
switch (cdclk) {
679
678
case 400000:
···
705
702
val &= ~DSPFREQGUAR_MASK;
706
703
val |= (cmd << DSPFREQGUAR_SHIFT);
707
704
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
708
-
if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) &
709
-
DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
710
-
50)) {
711
-
drm_err(display->drm,
712
-
"timed out waiting for CDclk change\n");
713
-
}
705
+
706
+
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
707
+
(val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
708
+
500, 50 * 1000, false);
709
+
if (ret)
710
+
drm_err(display->drm, "timed out waiting for CDCLK change\n");
714
711
715
712
if (cdclk == 400000) {
716
713
u32 divider;
···
724
721
val |= divider;
725
722
vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);
726
723
727
-
if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) &
728
-
CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
729
-
50))
730
-
drm_err(display->drm,
731
-
"timed out waiting for CDclk change\n");
724
+
ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),
725
+
(val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
726
+
500, 50 * 1000, false);
727
+
if (ret)
728
+
drm_err(display->drm, "timed out waiting for CDCLK change\n");
732
729
}
733
730
734
731
/* adjust self-refresh exit latency value */
···
764
761
int cdclk = cdclk_config->cdclk;
765
762
u32 val, cmd = cdclk_config->voltage_level;
766
763
intel_wakeref_t wakeref;
764
+
int ret;
767
765
768
766
switch (cdclk) {
769
767
case 333333:
···
790
786
val &= ~DSPFREQGUAR_MASK_CHV;
791
787
val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
792
788
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val);
793
-
if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) &
794
-
DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
795
-
50)) {
796
-
drm_err(display->drm,
797
-
"timed out waiting for CDclk change\n");
798
-
}
789
+
790
+
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
791
+
(val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
792
+
500, 50 * 1000, false);
793
+
if (ret)
794
+
drm_err(display->drm, "timed out waiting for CDCLK change\n");
799
795
800
796
vlv_punit_put(display->drm);
801
797
···
907
903
* According to the spec, it should be enough to poll for this 1 us.
908
904
* However, extensive testing shows that this can take longer.
909
905
*/
910
-
if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
911
-
LCPLL_CD_SOURCE_FCLK_DONE, 100))
906
+
ret = intel_de_wait_custom(display, LCPLL_CTL,
907
+
LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
908
+
100, 0, NULL);
909
+
if (ret)
912
910
drm_err(display->drm, "Switching to FCLK failed\n");
913
911
914
912
intel_de_rmw(display, LCPLL_CTL,
···
919
913
intel_de_rmw(display, LCPLL_CTL,
920
914
LCPLL_CD_SOURCE_FCLK, 0);
921
915
922
-
if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
923
-
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
916
+
ret = intel_de_wait_custom(display, LCPLL_CTL,
917
+
LCPLL_CD_SOURCE_FCLK_DONE, 0,
918
+
1, 0, NULL);
919
+
if (ret)
924
920
drm_err(display->drm, "Switching back to LCPLL failed\n");
925
921
926
922
intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
···
3577
3569
struct drm_i915_private *i915 = to_i915(display->drm);
3578
3570
3579
3571
/* hrawclock is 1/4 the FSB frequency */
3580
-
return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
3572
+
return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4);
3581
3573
}
3582
3574
3583
3575
/**
···
3630
3622
3631
3623
void intel_cdclk_debugfs_register(struct intel_display *display)
3632
3624
{
3633
-
struct drm_minor *minor = display->drm->primary;
3634
-
3635
-
debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3625
+
debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,
3636
3626
display, &i915_cdclk_info_fops);
3637
3627
}
3638
3628
+1
-1
drivers/gpu/drm/i915/display/intel_connector.c
+1
-1
drivers/gpu/drm/i915/display/intel_connector.c
-1
drivers/gpu/drm/i915/display/intel_connector.h
-1
drivers/gpu/drm/i915/display/intel_connector.h
···
14
14
struct intel_connector;
15
15
struct intel_encoder;
16
16
17
-
int intel_connector_init(struct intel_connector *connector);
18
17
struct intel_connector *intel_connector_alloc(void);
19
18
void intel_connector_free(struct intel_connector *connector);
20
19
void intel_connector_destroy(struct drm_connector *connector);
+3
-2
drivers/gpu/drm/i915/display/intel_crt.c
+3
-2
drivers/gpu/drm/i915/display/intel_crt.c
···
50
50
#include "intel_gmbus.h"
51
51
#include "intel_hotplug.h"
52
52
#include "intel_hotplug_irq.h"
53
+
#include "intel_link_bw.h"
53
54
#include "intel_load_detect.h"
54
55
#include "intel_pch_display.h"
55
56
#include "intel_pch_refclk.h"
···
422
421
return -EINVAL;
423
422
424
423
crtc_state->has_pch_encoder = true;
425
-
if (!intel_fdi_compute_pipe_bpp(crtc_state))
424
+
if (!intel_link_bw_compute_pipe_bpp(crtc_state))
426
425
return -EINVAL;
427
426
428
427
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
···
447
446
return -EINVAL;
448
447
449
448
crtc_state->has_pch_encoder = true;
450
-
if (!intel_fdi_compute_pipe_bpp(crtc_state))
449
+
if (!intel_link_bw_compute_pipe_bpp(crtc_state))
451
450
return -EINVAL;
452
451
453
452
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
+10
-18
drivers/gpu/drm/i915/display/intel_cursor.c
+10
-18
drivers/gpu/drm/i915/display/intel_cursor.c
···
33
33
DRM_FORMAT_ARGB8888,
34
34
};
35
35
36
-
static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
36
+
static u32 intel_cursor_surf_offset(const struct intel_plane_state *plane_state)
37
37
{
38
-
struct intel_display *display = to_intel_display(plane_state);
39
-
u32 base;
40
-
41
-
if (DISPLAY_INFO(display)->cursor_needs_physical)
42
-
base = plane_state->phys_dma_addr;
43
-
else
44
-
base = intel_plane_ggtt_offset(plane_state);
45
-
46
-
return base + plane_state->view.color_plane[0].offset;
38
+
return plane_state->view.color_plane[0].offset;
47
39
}
48
40
49
41
static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,
···
205
213
return cntl;
206
214
}
207
215
208
-
static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
209
-
const struct intel_plane_state *plane_state)
216
+
static u32 i845_cursor_ctl(const struct intel_plane_state *plane_state)
210
217
{
211
218
return CURSOR_ENABLE |
212
219
CURSOR_FORMAT_ARGB |
···
265
274
return -EINVAL;
266
275
}
267
276
268
-
plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
277
+
plane_state->ctl = i845_cursor_ctl(plane_state);
269
278
270
279
return 0;
271
280
}
···
288
297
289
298
size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
290
299
291
-
base = intel_cursor_base(plane_state);
300
+
base = plane_state->surf;
292
301
pos = intel_cursor_position(crtc_state, plane_state, false);
293
302
}
294
303
···
397
406
return cntl;
398
407
}
399
408
400
-
static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
401
-
const struct intel_plane_state *plane_state)
409
+
static u32 i9xx_cursor_ctl(const struct intel_plane_state *plane_state)
402
410
{
403
411
struct intel_display *display = to_intel_display(plane_state);
404
412
u32 cntl = 0;
···
524
534
return -EINVAL;
525
535
}
526
536
527
-
plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
537
+
plane_state->ctl = i9xx_cursor_ctl(plane_state);
528
538
529
539
return 0;
530
540
}
···
665
675
if (width != height)
666
676
fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
667
677
668
-
base = intel_cursor_base(plane_state);
678
+
base = plane_state->surf;
669
679
pos = intel_cursor_position(crtc_state, plane_state, false);
670
680
}
671
681
···
1040
1050
cursor->get_hw_state = i9xx_cursor_get_hw_state;
1041
1051
cursor->check_plane = i9xx_check_cursor;
1042
1052
}
1053
+
1054
+
cursor->surf_offset = intel_cursor_surf_offset;
1043
1055
1044
1056
if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1045
1057
cursor->capture_error = g4x_cursor_capture_error;
+34
-39
drivers/gpu/drm/i915/display/intel_ddi.c
+34
-39
drivers/gpu/drm/i915/display/intel_ddi.c
···
2166
2166
{
2167
2167
struct intel_display *display = to_intel_display(crtc_state);
2168
2168
enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
2169
-
u32 ln0, ln1, pin_assignment;
2169
+
enum intel_tc_pin_assignment pin_assignment;
2170
+
u32 ln0, ln1;
2170
2171
u8 width;
2171
2172
2172
2173
if (DISPLAY_VER(display) >= 14)
···
2189
2188
ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2190
2189
2191
2190
/* DPPATC */
2192
-
pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2191
+
pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
2193
2192
width = crtc_state->lane_count;
2194
2193
2195
2194
switch (pin_assignment) {
2196
-
case 0x0:
2195
+
case INTEL_TC_PIN_ASSIGNMENT_NONE:
2197
2196
drm_WARN_ON(display->drm,
2198
2197
!intel_tc_port_in_legacy_mode(dig_port));
2199
2198
if (width == 1) {
···
2203
2202
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2204
2203
}
2205
2204
break;
2206
-
case 0x1:
2205
+
case INTEL_TC_PIN_ASSIGNMENT_A:
2207
2206
if (width == 4) {
2208
2207
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2209
2208
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2210
2209
}
2211
2210
break;
2212
-
case 0x2:
2211
+
case INTEL_TC_PIN_ASSIGNMENT_B:
2213
2212
if (width == 2) {
2214
2213
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2215
2214
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2216
2215
}
2217
2216
break;
2218
-
case 0x3:
2219
-
case 0x5:
2217
+
case INTEL_TC_PIN_ASSIGNMENT_C:
2218
+
case INTEL_TC_PIN_ASSIGNMENT_E:
2220
2219
if (width == 1) {
2221
2220
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2222
2221
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
···
2225
2224
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2226
2225
}
2227
2226
break;
2228
-
case 0x4:
2229
-
case 0x6:
2227
+
case INTEL_TC_PIN_ASSIGNMENT_D:
2228
+
case INTEL_TC_PIN_ASSIGNMENT_F:
2230
2229
if (width == 1) {
2231
2230
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2232
2231
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
···
2340
2339
drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");
2341
2340
}
2342
2341
2343
-
static int read_fec_detected_status(struct drm_dp_aux *aux)
2344
-
{
2345
-
int ret;
2346
-
u8 status;
2347
-
2348
-
ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status);
2349
-
if (ret < 0)
2350
-
return ret;
2351
-
2352
-
return status;
2353
-
}
2354
-
2355
2342
static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2356
2343
{
2357
2344
struct intel_display *display = to_intel_display(aux->drm_dev);
2358
2345
int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
2359
-
int status;
2360
-
int err;
2346
+
u8 status = 0;
2347
+
int ret, err;
2361
2348
2362
-
err = readx_poll_timeout(read_fec_detected_status, aux, status,
2363
-
status & mask || status < 0,
2364
-
10000, 200000);
2349
+
ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status),
2350
+
err || (status & mask),
2351
+
10 * 1000, 200 * 1000, false);
2365
2352
2366
-
if (err || status < 0) {
2353
+
/* Either can be non-zero, but not both */
2354
+
ret = ret ?: err;
2355
+
if (ret) {
2367
2356
drm_dbg_kms(display->drm,
2368
-
"Failed waiting for FEC %s to get detected: %d (status %d)\n",
2369
-
str_enabled_disabled(enabled), err, status);
2370
-
return err ? err : status;
2357
+
"Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n",
2358
+
str_enabled_disabled(enabled), ret, status);
2359
+
return ret;
2371
2360
}
2372
2361
2373
2362
return 0;
···
2552
2561
enum port port = encoder->port;
2553
2562
i915_reg_t reg;
2554
2563
u32 set_bits, wait_bits;
2564
+
int ret;
2555
2565
2556
2566
if (DISPLAY_VER(display) < 14)
2557
2567
return;
···
2568
2576
}
2569
2577
2570
2578
intel_de_rmw(display, reg, 0, set_bits);
2571
-
if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) {
2579
+
2580
+
ret = intel_de_wait_custom(display, reg,
2581
+
wait_bits, wait_bits,
2582
+
100, 0, NULL);
2583
+
if (ret) {
2572
2584
drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
2573
2585
port_name(port));
2574
2586
}
···
3054
3058
enum port port = encoder->port;
3055
3059
i915_reg_t reg;
3056
3060
u32 clr_bits, wait_bits;
3061
+
int ret;
3057
3062
3058
3063
if (DISPLAY_VER(display) < 14)
3059
3064
return;
···
3070
3073
}
3071
3074
3072
3075
intel_de_rmw(display, reg, clr_bits, 0);
3073
-
if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100))
3076
+
3077
+
ret = intel_de_wait_custom(display, reg,
3078
+
wait_bits, 0,
3079
+
100, 0, NULL);
3080
+
if (ret)
3074
3081
drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
3075
3082
port_name(port));
3076
3083
}
···
5149
5148
phy_name(phy));
5150
5149
}
5151
5150
5152
-
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
5151
+
dig_port = intel_dig_port_alloc();
5153
5152
if (!dig_port)
5154
5153
return;
5155
-
5156
-
dig_port->aux_ch = AUX_CH_NONE;
5157
5154
5158
5155
encoder = &dig_port->base;
5159
5156
encoder->devdata = devdata;
···
5189
5190
}
5190
5191
5191
5192
intel_encoder_link_check_init(encoder, intel_ddi_link_check);
5192
-
5193
-
mutex_init(&dig_port->hdcp.mutex);
5194
-
dig_port->hdcp.num_streams = 0;
5195
5193
5196
5194
encoder->hotplug = intel_ddi_hotplug;
5197
5195
encoder->compute_output_type = intel_ddi_compute_output_type;
···
5327
5331
5328
5332
dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;
5329
5333
5330
-
dig_port->dp.output_reg = INVALID_MMIO_REG;
5331
5334
dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5332
5335
5333
5336
if (need_aux_ch(encoder, init_dp)) {
+6
drivers/gpu/drm/i915/display/intel_display.c
+6
drivers/gpu/drm/i915/display/intel_display.c
···
76
76
#include "intel_display_regs.h"
77
77
#include "intel_display_rpm.h"
78
78
#include "intel_display_types.h"
79
+
#include "intel_display_wa.h"
79
80
#include "intel_dmc.h"
80
81
#include "intel_dp.h"
81
82
#include "intel_dp_link_training.h"
···
1081
1080
1082
1081
if (audio_enabling(old_crtc_state, new_crtc_state))
1083
1082
intel_encoders_audio_enable(state, crtc);
1083
+
1084
+
if (intel_display_wa(display, 14011503117)) {
1085
+
if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)
1086
+
adl_scaler_ecc_unmask(new_crtc_state);
1087
+
}
1084
1088
1085
1089
intel_alpm_post_plane_update(state, crtc);
1086
1090
+1
-1
drivers/gpu/drm/i915/display/intel_display_conversion.c
+1
-1
drivers/gpu/drm/i915/display/intel_display_conversion.c
-12
drivers/gpu/drm/i915/display/intel_display_conversion.h
-12
drivers/gpu/drm/i915/display/intel_display_conversion.h
···
9
9
#define __INTEL_DISPLAY_CONVERSION__
10
10
11
11
struct drm_device;
12
-
struct drm_i915_private;
13
12
struct intel_display;
14
13
15
-
struct intel_display *__i915_to_display(struct drm_i915_private *i915);
16
14
struct intel_display *__drm_to_display(struct drm_device *drm);
17
-
/*
18
-
* Transitional macro to optionally convert struct drm_i915_private * to struct
19
-
* intel_display *, also accepting the latter.
20
-
*/
21
-
#define __to_intel_display(p) \
22
-
_Generic(p, \
23
-
const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(p)), \
24
-
struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(p)), \
25
-
const struct intel_display *: (p), \
26
-
struct intel_display *: (p))
27
15
28
16
#endif /* __INTEL_DISPLAY_CONVERSION__ */
+3
-3
drivers/gpu/drm/i915/display/intel_display_debugfs.c
+3
-3
drivers/gpu/drm/i915/display/intel_display_debugfs.c
···
820
820
821
821
void intel_display_debugfs_register(struct intel_display *display)
822
822
{
823
-
struct drm_minor *minor = display->drm->primary;
823
+
struct dentry *debugfs_root = display->drm->debugfs_root;
824
824
825
-
debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
825
+
debugfs_create_file("i915_fifo_underrun_reset", 0644, debugfs_root,
826
826
display, &i915_fifo_underrun_reset_ops);
827
827
828
828
drm_debugfs_create_files(intel_display_debugfs_list,
829
829
ARRAY_SIZE(intel_display_debugfs_list),
830
-
minor->debugfs_root, minor);
830
+
debugfs_root, display->drm->primary);
831
831
832
832
intel_bios_debugfs_register(display);
833
833
intel_cdclk_debugfs_register(display);
+3
-4
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
+3
-4
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
···
7
7
#include <linux/kernel.h>
8
8
9
9
#include <drm/drm_drv.h>
10
-
#include <drm/drm_file.h>
11
10
12
11
#include "intel_display_core.h"
13
12
#include "intel_display_debugfs_params.h"
···
153
154
/* add a subdirectory with files for each intel display param */
154
155
void intel_display_debugfs_params(struct intel_display *display)
155
156
{
156
-
struct drm_minor *minor = display->drm->primary;
157
+
struct dentry *debugfs_root = display->drm->debugfs_root;
157
158
struct dentry *dir;
158
159
char dirname[16];
159
160
160
161
snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);
161
-
dir = debugfs_lookup(dirname, minor->debugfs_root);
162
+
dir = debugfs_lookup(dirname, debugfs_root);
162
163
if (!dir)
163
-
dir = debugfs_create_dir(dirname, minor->debugfs_root);
164
+
dir = debugfs_create_dir(dirname, debugfs_root);
164
165
if (IS_ERR(dir))
165
166
return;
166
167
+14
-1
drivers/gpu/drm/i915/display/intel_display_device.c
+14
-1
drivers/gpu/drm/i915/display/intel_display_device.c
···
1354
1354
.__runtime_defaults.has_dbuf_overlap_detection = true,
1355
1355
};
1356
1356
1357
+
static const struct intel_display_device_info wcl_display = {
1358
+
XE_LPDP_FEATURES,
1359
+
1360
+
.__runtime_defaults.cpu_transcoder_mask =
1361
+
BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
1362
+
.__runtime_defaults.pipe_mask =
1363
+
BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
1364
+
.__runtime_defaults.fbc_mask =
1365
+
BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) | BIT(INTEL_FBC_C),
1366
+
.__runtime_defaults.port_mask =
1367
+
BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2),
1368
+
};
1369
+
1357
1370
static const struct intel_display_device_info xe2_hpd_display = {
1358
1371
XE_LPDP_FEATURES,
1359
1372
.__runtime_defaults.port_mask = BIT(PORT_A) |
···
1493
1480
{ 14, 1, &xe2_hpd_display },
1494
1481
{ 20, 0, &xe2_lpd_display },
1495
1482
{ 30, 0, &xe2_lpd_display },
1496
-
{ 30, 2, &xe2_lpd_display },
1483
+
{ 30, 2, &wcl_display },
1497
1484
};
1498
1485
1499
1486
static const struct intel_display_device_info *
+3
-4
drivers/gpu/drm/i915/display/intel_display_device.h
+3
-4
drivers/gpu/drm/i915/display/intel_display_device.h
···
9
9
#include <linux/bitops.h>
10
10
#include <linux/types.h>
11
11
12
-
#include "intel_display_conversion.h"
13
12
#include "intel_display_limits.h"
14
13
15
14
struct drm_printer;
···
223
224
(IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \
224
225
IS_DISPLAY_STEP((__display), (from), (until)))
225
226
226
-
#define DISPLAY_INFO(__display) (__to_intel_display(__display)->info.__device_info)
227
-
#define DISPLAY_RUNTIME_INFO(__display) (&__to_intel_display(__display)->info.__runtime_info)
227
+
#define DISPLAY_INFO(__display) ((__display)->info.__device_info)
228
+
#define DISPLAY_RUNTIME_INFO(__display) (&(__display)->info.__runtime_info)
228
229
229
230
#define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver)
230
231
#define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \
···
235
236
#define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step)
236
237
237
238
#define IS_DISPLAY_STEP(__display, since, until) \
238
-
(drm_WARN_ON(__to_intel_display(__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
239
+
(drm_WARN_ON((__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
239
240
INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until))
240
241
241
242
#define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C
+1
drivers/gpu/drm/i915/display/intel_display_driver.c
+1
drivers/gpu/drm/i915/display/intel_display_driver.c
+7
-6
drivers/gpu/drm/i915/display/intel_display_irq.c
+7
-6
drivers/gpu/drm/i915/display/intel_display_irq.c
···
1506
1506
if (!(master_ctl & GEN11_GU_MISC_IRQ))
1507
1507
return 0;
1508
1508
1509
+
intel_display_rpm_assert_block(display);
1510
+
1509
1511
iir = intel_de_read(display, GEN11_GU_MISC_IIR);
1510
1512
if (likely(iir))
1511
1513
intel_de_write(display, GEN11_GU_MISC_IIR, iir);
1514
+
1515
+
intel_display_rpm_assert_unblock(display);
1512
1516
1513
1517
return iir;
1514
1518
}
···
1990
1986
1991
1987
void ibx_display_irq_reset(struct intel_display *display)
1992
1988
{
1993
-
struct drm_i915_private *i915 = to_i915(display->drm);
1994
-
1995
-
if (HAS_PCH_NOP(i915))
1989
+
if (HAS_PCH_NOP(display))
1996
1990
return;
1997
1991
1998
1992
gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS);
1999
1993
2000
-
if (HAS_PCH_CPT(i915) || HAS_PCH_LPT(i915))
1994
+
if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))
2001
1995
intel_de_write(display, SERR_INT, 0xffffffff);
2002
1996
}
2003
1997
2004
1998
void gen8_display_irq_reset(struct intel_display *display)
2005
1999
{
2006
-
struct drm_i915_private *i915 = to_i915(display->drm);
2007
2000
enum pipe pipe;
2008
2001
2009
2002
if (!HAS_DISPLAY(display))
···
2017
2016
intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);
2018
2017
intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
2019
2018
2020
-
if (HAS_PCH_SPLIT(i915))
2019
+
if (HAS_PCH_SPLIT(display))
2021
2020
ibx_display_irq_reset(display);
2022
2021
}
2023
2022
+3
drivers/gpu/drm/i915/display/intel_display_params.c
+3
drivers/gpu/drm/i915/display/intel_display_params.c
···
120
120
"(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
121
121
"Default: -1 (use per-chip default)");
122
122
123
+
intel_display_param_named_unsafe(enable_panel_replay, int, 0400,
124
+
"Enable Panel Replay (0=disabled, 1=enabled). Default: -1 (use per-chip default)");
125
+
123
126
intel_display_param_named(psr_safest_params, bool, 0400,
124
127
"Replace PSR VBT parameters by the safest and not optimal ones. This "
125
128
"is helpful to detect if PSR issues are related to bad values set in "
+1
drivers/gpu/drm/i915/display/intel_display_params.h
+1
drivers/gpu/drm/i915/display/intel_display_params.h
···
46
46
param(bool, enable_dp_mst, true, 0600) \
47
47
param(int, enable_fbc, -1, 0600) \
48
48
param(int, enable_psr, -1, 0600) \
49
+
param(int, enable_panel_replay, -1, 0600) \
49
50
param(bool, psr_safest_params, false, 0400) \
50
51
param(bool, enable_psr2_sel_fetch, true, 0400) \
51
52
param(int, enable_dmc_wl, -1, 0400) \
+16
-8
drivers/gpu/drm/i915/display/intel_display_power.c
+16
-8
drivers/gpu/drm/i915/display/intel_display_power.c
···
3
3
* Copyright © 2019 Intel Corporation
4
4
*/
5
5
6
+
#include <linux/iopoll.h>
6
7
#include <linux/string_helpers.h>
7
8
8
9
#include "soc/intel_dram.h"
···
11
10
#include "i915_drv.h"
12
11
#include "i915_irq.h"
13
12
#include "i915_reg.h"
13
+
#include "i915_utils.h"
14
14
#include "intel_backlight_regs.h"
15
15
#include "intel_cdclk.h"
16
16
#include "intel_clock_gating.h"
···
1280
1278
bool switch_to_fclk, bool allow_power_down)
1281
1279
{
1282
1280
u32 val;
1281
+
int ret;
1283
1282
1284
1283
assert_can_disable_lcpll(display);
1285
1284
···
1290
1287
val |= LCPLL_CD_SOURCE_FCLK;
1291
1288
intel_de_write(display, LCPLL_CTL, val);
1292
1289
1293
-
if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
1294
-
LCPLL_CD_SOURCE_FCLK_DONE, 1))
1290
+
ret = intel_de_wait_custom(display, LCPLL_CTL,
1291
+
LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
1292
+
1, 0, NULL);
1293
+
if (ret)
1295
1294
drm_err(display->drm, "Switching to FCLK failed\n");
1296
1295
1297
1296
val = intel_de_read(display, LCPLL_CTL);
···
1311
1306
hsw_write_dcomp(display, val);
1312
1307
ndelay(100);
1313
1308
1314
-
if (wait_for((hsw_read_dcomp(display) &
1315
-
D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
1309
+
ret = poll_timeout_us(val = hsw_read_dcomp(display),
1310
+
(val & D_COMP_RCOMP_IN_PROGRESS) == 0,
1311
+
100, 1000, false);
1312
+
if (ret)
1316
1313
drm_err(display->drm, "D_COMP RCOMP still in progress\n");
1317
1314
1318
1315
if (allow_power_down) {
···
1331
1324
{
1332
1325
struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
1333
1326
u32 val;
1327
+
int ret;
1334
1328
1335
1329
val = intel_de_read(display, LCPLL_CTL);
1336
1330
···
1366
1358
if (val & LCPLL_CD_SOURCE_FCLK) {
1367
1359
intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
1368
1360
1369
-
if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
1370
-
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
1361
+
ret = intel_de_wait_custom(display, LCPLL_CTL,
1362
+
LCPLL_CD_SOURCE_FCLK_DONE, 0,
1363
+
1, 0, NULL);
1364
+
if (ret)
1371
1365
drm_err(display->drm,
1372
1366
"Switching back to LCPLL failed\n");
1373
1367
}
···
2165
2155
power_domains->init_wakeref =
2166
2156
intel_display_power_get(display, POWER_DOMAIN_INIT);
2167
2157
}
2168
-
2169
-
intel_power_domains_verify_state(display);
2170
2158
}
2171
2159
2172
2160
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+56
-1
drivers/gpu/drm/i915/display/intel_display_power_map.c
+56
-1
drivers/gpu/drm/i915/display/intel_display_power_map.c
···
1717
1717
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1718
1718
};
1719
1719
1720
+
static const struct i915_power_well_desc wcl_power_wells_main[] = {
1721
+
{
1722
+
.instances = &I915_PW_INSTANCES(
1723
+
I915_PW("PW_2", &xe3lpd_pwdoms_pw_2,
1724
+
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
1725
+
.id = SKL_DISP_PW_2),
1726
+
),
1727
+
.ops = &hsw_power_well_ops,
1728
+
.has_vga = true,
1729
+
.has_fuses = true,
1730
+
}, {
1731
+
.instances = &I915_PW_INSTANCES(
1732
+
I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1733
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1734
+
),
1735
+
.ops = &hsw_power_well_ops,
1736
+
.irq_pipe_mask = BIT(PIPE_A),
1737
+
.has_fuses = true,
1738
+
}, {
1739
+
.instances = &I915_PW_INSTANCES(
1740
+
I915_PW("PW_B", &xe3lpd_pwdoms_pw_b,
1741
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1742
+
),
1743
+
.ops = &hsw_power_well_ops,
1744
+
.irq_pipe_mask = BIT(PIPE_B),
1745
+
.has_fuses = true,
1746
+
}, {
1747
+
.instances = &I915_PW_INSTANCES(
1748
+
I915_PW("PW_C", &xe3lpd_pwdoms_pw_c,
1749
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1750
+
),
1751
+
.ops = &hsw_power_well_ops,
1752
+
.irq_pipe_mask = BIT(PIPE_C),
1753
+
.has_fuses = true,
1754
+
}, {
1755
+
.instances = &I915_PW_INSTANCES(
1756
+
I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
1757
+
I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
1758
+
I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
1759
+
I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
1760
+
),
1761
+
.ops = &xelpdp_aux_power_well_ops,
1762
+
},
1763
+
};
1764
+
1765
+
static const struct i915_power_well_desc_list wcl_power_wells[] = {
1766
+
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1767
+
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1768
+
I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff),
1769
+
I915_PW_DESCRIPTORS(wcl_power_wells_main),
1770
+
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1771
+
};
1772
+
1720
1773
static void init_power_well_domains(const struct i915_power_well_instance *inst,
1721
1774
struct i915_power_well *power_well)
1722
1775
{
···
1877
1824
return 0;
1878
1825
}
1879
1826
1880
-
if (DISPLAY_VER(display) >= 30)
1827
+
if (DISPLAY_VERx100(display) == 3002)
1828
+
return set_power_wells(power_domains, wcl_power_wells);
1829
+
else if (DISPLAY_VER(display) >= 30)
1881
1830
return set_power_wells(power_domains, xe3lpd_power_wells);
1882
1831
else if (DISPLAY_VER(display) >= 20)
1883
1832
return set_power_wells(power_domains, xe2lpd_power_wells);
+28
-24
drivers/gpu/drm/i915/display/intel_display_power_well.c
+28
-24
drivers/gpu/drm/i915/display/intel_display_power_well.c
···
3
3
* Copyright © 2022 Intel Corporation
4
4
*/
5
5
6
+
#include <linux/iopoll.h>
7
+
6
8
#include "i915_drv.h"
7
9
#include "i915_irq.h"
8
10
#include "i915_reg.h"
···
501
499
502
500
static void icl_tc_cold_exit(struct intel_display *display)
503
501
{
504
-
struct drm_i915_private *i915 = to_i915(display->drm);
505
502
int ret, tries = 0;
506
503
507
504
while (1) {
···
515
514
msleep(1);
516
515
517
516
/* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
518
-
drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
517
+
drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" :
519
518
"succeeded");
520
519
}
521
520
···
528
527
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
529
528
bool is_tbt = power_well->desc->is_tc_tbt;
530
529
bool timeout_expected;
530
+
u32 val;
531
+
int ret;
531
532
532
533
icl_tc_port_assert_ref_held(display, power_well, dig_port);
533
534
···
556
553
557
554
tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
558
555
559
-
if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) &
560
-
DKL_CMN_UC_DW27_UC_HEALTH, 1))
561
-
drm_warn(display->drm,
562
-
"Timeout waiting TC uC health\n");
556
+
ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),
557
+
val & DKL_CMN_UC_DW27_UC_HEALTH,
558
+
100, 1000, false);
559
+
if (ret)
560
+
drm_warn(display->drm, "Timeout waiting TC uC health\n");
563
561
}
564
562
}
565
563
···
1126
1122
u32 mask;
1127
1123
u32 state;
1128
1124
u32 ctrl;
1125
+
u32 val;
1126
+
int ret;
1129
1127
1130
1128
mask = PUNIT_PWRGT_MASK(pw_idx);
1131
1129
state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
···
1135
1129
1136
1130
vlv_punit_get(display->drm);
1137
1131
1138
-
#define COND \
1139
-
((vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask) == state)
1140
-
1141
-
if (COND)
1132
+
val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS);
1133
+
if ((val & mask) == state)
1142
1134
goto out;
1143
1135
1144
1136
ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL);
···
1144
1140
ctrl |= state;
1145
1141
vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl);
1146
1142
1147
-
if (wait_for(COND, 100))
1143
+
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),
1144
+
(val & mask) == state,
1145
+
500, 100 * 1000, false);
1146
+
if (ret)
1148
1147
drm_err(display->drm,
1149
1148
"timeout setting power well state %08x (%08x)\n",
1150
1149
state,
1151
1150
vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL));
1152
-
1153
-
#undef COND
1154
1151
1155
1152
out:
1156
1153
vlv_punit_put(display->drm);
···
1213
1208
* (and never recovering) in this case. intel_dsi_post_disable() will
1214
1209
* clear it when we turn off the display.
1215
1210
*/
1216
-
intel_de_rmw(display, DSPCLK_GATE_D(display),
1211
+
intel_de_rmw(display, VLV_DSPCLK_GATE_D,
1217
1212
~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);
1218
1213
1219
1214
/*
···
1716
1711
enum pipe pipe = PIPE_A;
1717
1712
u32 state;
1718
1713
u32 ctrl;
1714
+
int ret;
1719
1715
1720
1716
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1721
1717
1722
1718
vlv_punit_get(display->drm);
1723
1719
1724
-
#define COND \
1725
-
((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
1726
-
1727
-
if (COND)
1720
+
ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
1721
+
if ((ctrl & DP_SSS_MASK(pipe)) == state)
1728
1722
goto out;
1729
1723
1730
-
ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
1731
1724
ctrl &= ~DP_SSC_MASK(pipe);
1732
1725
ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1733
1726
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl);
1734
1727
1735
-
if (wait_for(COND, 100))
1728
+
ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
1729
+
(ctrl & DP_SSS_MASK(pipe)) == state,
1730
+
500, 100 * 1000, false);
1731
+
if (ret)
1736
1732
drm_err(display->drm,
1737
1733
"timeout setting power well state %08x (%08x)\n",
1738
1734
state,
···
1771
1765
static void
1772
1766
tgl_tc_cold_request(struct intel_display *display, bool block)
1773
1767
{
1774
-
struct drm_i915_private *i915 = to_i915(display->drm);
1775
1768
u8 tries = 0;
1776
1769
int ret;
1777
1770
···
1803
1798
}
1804
1799
1805
1800
if (ret)
1806
-
drm_err(&i915->drm, "TC cold %sblock failed\n",
1807
-
block ? "" : "un");
1801
+
drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un");
1808
1802
else
1809
-
drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
1803
+
drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n",
1810
1804
block ? "" : "un");
1811
1805
}
1812
1806
+2
drivers/gpu/drm/i915/display/intel_display_regs.h
+2
drivers/gpu/drm/i915/display/intel_display_regs.h
···
2890
2890
#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
2891
2891
#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
2892
2892
#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
2893
+
/* See enum intel_tc_pin_assignment for the pin assignment field values. */
2893
2894
2894
2895
#define _TCSS_DDI_STATUS_1 0x161500
2895
2896
#define _TCSS_DDI_STATUS_2 0x161504
···
2898
2897
_TCSS_DDI_STATUS_1, \
2899
2898
_TCSS_DDI_STATUS_2))
2900
2899
#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
2900
+
/* See enum intel_tc_pin_assignment for the pin assignment field values. */
2901
2901
#define TCSS_DDI_STATUS_READY REG_BIT(2)
2902
2902
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
2903
2903
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+9
-7
drivers/gpu/drm/i915/display/intel_display_types.h
+9
-7
drivers/gpu/drm/i915/display/intel_display_types.h
···
50
50
#include "intel_display_limits.h"
51
51
#include "intel_display_power.h"
52
52
#include "intel_dpll_mgr.h"
53
+
#include "intel_dsi_vbt_defs.h"
53
54
#include "intel_wm_types.h"
54
55
55
56
struct cec_notifier;
56
57
struct drm_printer;
57
-
struct __intel_global_objs_state;
58
58
struct intel_connector;
59
59
struct intel_ddi_buf_trans;
60
60
struct intel_fbc;
61
+
struct intel_global_objs_state;
61
62
struct intel_hdcp_shim;
62
63
struct intel_tc_port;
63
64
···
594
593
595
594
struct ref_tracker *wakeref;
596
595
597
-
struct __intel_global_objs_state *global_objs;
596
+
struct intel_global_objs_state *global_objs;
598
597
int num_global_objs;
599
598
600
599
/* Internal commit, as opposed to userspace/client initiated one */
···
643
642
#define PLANE_HAS_FENCE BIT(0)
644
643
645
644
struct intel_fb_view view;
646
-
u32 phys_dma_addr; /* for cursor_needs_physical */
647
645
648
646
/* for legacy cursor fb unpin */
649
647
struct drm_vblank_work unpin_work;
···
664
664
665
665
/* chroma upsampler control register */
666
666
u32 cus_ctl;
667
+
668
+
/* surface address register */
669
+
u32 surf;
667
670
668
671
/*
669
672
* scaler_id
···
944
941
u16 postoff[3];
945
942
};
946
943
947
-
void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val);
948
-
949
-
typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val);
950
-
951
944
struct intel_crtc_state {
952
945
/*
953
946
* uapi (drm) state. This is the software state shown to userspace.
···
1121
1122
bool req_psr2_sdp_prior_scanline;
1122
1123
bool has_panel_replay;
1123
1124
bool wm_level_disabled;
1125
+
bool pkg_c_latency_used;
1124
1126
u32 dc3co_exitline;
1125
1127
u16 su_y_granularity;
1126
1128
u8 active_non_psr_pipes;
···
1534
1534
bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1535
1535
int (*check_plane)(struct intel_crtc_state *crtc_state,
1536
1536
struct intel_plane_state *plane_state);
1537
+
u32 (*surf_offset)(const struct intel_plane_state *plane_state);
1537
1538
int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1538
1539
const struct intel_plane_state *plane_state);
1539
1540
void (*async_flip)(struct intel_dsb *dsb,
···
1684
1683
u8 entry_setup_frames;
1685
1684
1686
1685
bool link_ok;
1686
+
bool pkg_c_latency_used;
1687
1687
1688
1688
u8 active_non_psr_pipes;
1689
1689
};
+35
drivers/gpu/drm/i915/display/intel_display_wa.c
+35
drivers/gpu/drm/i915/display/intel_display_wa.c
···
3
3
* Copyright © 2023 Intel Corporation
4
4
*/
5
5
6
+
#include <drm/drm_print.h>
7
+
6
8
#include "i915_reg.h"
7
9
#include "intel_de.h"
8
10
#include "intel_display_core.h"
···
40
38
xe_d_display_wa_apply(display);
41
39
else if (DISPLAY_VER(display) == 11)
42
40
gen11_display_wa_apply(display);
41
+
}
42
+
43
+
/*
44
+
* Wa_16025573575:
45
+
* Fixes: Issue with bitbashing on Xe3 based platforms.
46
+
* Workaround: Set masks bits in GPIO CTL and preserve it during bitbashing sequence.
47
+
*/
48
+
static bool intel_display_needs_wa_16025573575(struct intel_display *display)
49
+
{
50
+
return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
51
+
}
52
+
53
+
/*
54
+
* Wa_14011503117:
55
+
* Fixes: Before enabling the scaler DE fatal error is masked
56
+
* Workaround: Unmask the DE fatal error register after enabling the scaler
57
+
* and after waiting of at least 1 frame.
58
+
*/
59
+
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
60
+
{
61
+
switch (wa) {
62
+
case INTEL_DISPLAY_WA_16023588340:
63
+
return intel_display_needs_wa_16023588340(display);
64
+
case INTEL_DISPLAY_WA_16025573575:
65
+
return intel_display_needs_wa_16025573575(display);
66
+
case INTEL_DISPLAY_WA_14011503117:
67
+
return DISPLAY_VER(display) == 13;
68
+
default:
69
+
drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
70
+
break;
71
+
}
72
+
73
+
return false;
43
74
}
+11
drivers/gpu/drm/i915/display/intel_display_wa.h
+11
drivers/gpu/drm/i915/display/intel_display_wa.h
···
21
21
bool intel_display_needs_wa_16023588340(struct intel_display *display);
22
22
#endif
23
23
24
+
enum intel_display_wa {
25
+
INTEL_DISPLAY_WA_16023588340,
26
+
INTEL_DISPLAY_WA_16025573575,
27
+
INTEL_DISPLAY_WA_14011503117,
28
+
};
29
+
30
+
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
31
+
32
+
#define intel_display_wa(__display, __wa) \
33
+
__intel_display_wa((__display), INTEL_DISPLAY_WA_##__wa, __stringify(__wa))
34
+
24
35
#endif
+1
-3
drivers/gpu/drm/i915/display/intel_dmc.c
+1
-3
drivers/gpu/drm/i915/display/intel_dmc.c
···
1603
1603
1604
1604
void intel_dmc_debugfs_register(struct intel_display *display)
1605
1605
{
1606
-
struct drm_minor *minor = display->drm->primary;
1607
-
1608
-
debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
1606
+
debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root,
1609
1607
display, &intel_dmc_debugfs_status_fops);
1610
1608
}
1611
1609
+92
-45
drivers/gpu/drm/i915/display/intel_dp.c
+92
-45
drivers/gpu/drm/i915/display/intel_dp.c
···
27
27
28
28
#include <linux/export.h>
29
29
#include <linux/i2c.h>
30
+
#include <linux/iopoll.h>
30
31
#include <linux/log2.h>
31
32
#include <linux/math.h>
32
33
#include <linux/notifier.h>
···
175
174
static int max_dprx_rate(struct intel_dp *intel_dp)
176
175
{
177
176
struct intel_display *display = to_intel_display(intel_dp);
178
-
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
179
177
int max_rate;
180
178
181
179
if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
···
183
183
max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
184
184
185
185
/*
186
-
* Some broken eDP sinks illegally declare support for
187
-
* HBR3 without TPS4, and are unable to produce a stable
188
-
* output. Reject HBR3 when TPS4 is not available.
186
+
* Some platforms + eDP panels may not reliably support HBR3
187
+
* due to signal integrity limitations, despite advertising it.
188
+
* Cap the link rate to HBR2 to avoid unstable configurations for the
189
+
* known machines.
189
190
*/
190
-
if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
191
-
drm_dbg_kms(display->drm,
192
-
"[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
193
-
encoder->base.base.id, encoder->base.name);
194
-
max_rate = 540000;
195
-
}
191
+
if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))
192
+
max_rate = min(max_rate, 540000);
196
193
197
194
return max_rate;
198
195
}
···
1415
1418
struct intel_display *display = to_intel_display(_connector->dev);
1416
1419
struct intel_connector *connector = to_intel_connector(_connector);
1417
1420
struct intel_dp *intel_dp = intel_attached_dp(connector);
1421
+
enum intel_output_format sink_format, output_format;
1418
1422
const struct drm_display_mode *fixed_mode;
1419
1423
int target_clock = mode->clock;
1420
1424
int max_rate, mode_rate, max_lanes, max_link_clock;
···
1449
1451
mode->hdisplay, target_clock);
1450
1452
max_dotclk *= num_joined_pipes;
1451
1453
1454
+
sink_format = intel_dp_sink_format(connector, mode);
1455
+
output_format = intel_dp_output_format(connector, sink_format);
1456
+
1457
+
status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
1458
+
if (status != MODE_OK)
1459
+
return status;
1460
+
1452
1461
if (target_clock > max_dotclk)
1453
1462
return MODE_CLOCK_HIGH;
1454
1463
···
1471
1466
intel_dp_mode_min_output_bpp(connector, mode));
1472
1467
1473
1468
if (intel_dp_has_dsc(connector)) {
1474
-
enum intel_output_format sink_format, output_format;
1475
1469
int pipe_bpp;
1476
1470
1477
-
sink_format = intel_dp_sink_format(connector, mode);
1478
-
output_format = intel_dp_output_format(connector, sink_format);
1479
1471
/*
1480
1472
* TBD pass the connector BPC,
1481
1473
* for now U8_MAX so that max BPC on that platform would be picked
···
2537
2535
2538
2536
bool
2539
2537
intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2540
-
struct intel_connector *connector,
2538
+
struct drm_connector_state *conn_state,
2541
2539
struct intel_crtc_state *crtc_state,
2542
2540
bool respect_downstream_limits,
2543
2541
bool dsc,
2544
2542
struct link_config_limits *limits)
2545
2543
{
2546
2544
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2545
+
struct intel_connector *connector =
2546
+
to_intel_connector(conn_state->connector);
2547
2547
2548
2548
limits->min_rate = intel_dp_min_link_rate(intel_dp);
2549
2549
limits->max_rate = intel_dp_max_link_rate(intel_dp);
···
2555
2551
limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2556
2552
limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2557
2553
2558
-
limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2554
+
limits->pipe.min_bpp = intel_dp_in_hdr_mode(conn_state) ? 30 :
2555
+
intel_dp_min_bpp(crtc_state->output_format);
2559
2556
if (is_mst) {
2560
2557
/*
2561
2558
* FIXME: If all the streams can't fit into the link with their
···
2655
2650
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2656
2651
2657
2652
dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2658
-
!intel_dp_compute_config_limits(intel_dp, connector, pipe_config,
2653
+
!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,
2659
2654
respect_downstream_limits,
2660
2655
false,
2661
2656
&limits);
···
2689
2684
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2690
2685
str_yes_no(intel_dp->force_dsc_en));
2691
2686
2692
-
if (!intel_dp_compute_config_limits(intel_dp, connector, pipe_config,
2687
+
if (!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,
2693
2688
respect_downstream_limits,
2694
2689
true,
2695
2690
&limits))
···
2919
2914
vsc->revision = 0x2;
2920
2915
vsc->length = 0x8;
2921
2916
}
2917
+
}
2918
+
2919
+
bool
2920
+
intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
2921
+
{
2922
+
struct hdr_output_metadata *hdr_metadata;
2923
+
2924
+
if (!conn_state->hdr_output_metadata)
2925
+
return false;
2926
+
2927
+
hdr_metadata = conn_state->hdr_output_metadata->data;
2928
+
2929
+
return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
2922
2930
}
2923
2931
2924
2932
static void
···
3199
3181
*/
3200
3182
min_hblank = min_hblank - 2;
3201
3183
3202
-
min_hblank = min(10, min_hblank);
3184
+
/*
3185
+
* min_hblank formula is undergoing a change, to avoid underrun use the
3186
+
* recomended value in spec to compare with the calculated one and use the
3187
+
* minimum value
3188
+
*/
3189
+
if (intel_dp_is_uhbr(crtc_state)) {
3190
+
/*
3191
+
* Note: Bspec requires a min_hblank of 2 for YCBCR420
3192
+
* with compressed bpp 6, but the minimum compressed bpp
3193
+
* supported by the driver is 8.
3194
+
*/
3195
+
drm_WARN_ON(display->drm,
3196
+
(crtc_state->dsc.compression_enable &&
3197
+
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3198
+
crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));
3199
+
min_hblank = min(3, min_hblank);
3200
+
} else {
3201
+
min_hblank = min(10, min_hblank);
3202
+
}
3203
+
3203
3204
crtc_state->min_hblank = min_hblank;
3204
3205
3205
3206
return 0;
···
3879
3842
if (ret < 0)
3880
3843
return ret;
3881
3844
/* Wait for PCON to be FRL Ready */
3882
-
wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3883
-
3884
-
if (!is_active)
3885
-
return -ETIMEDOUT;
3845
+
ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux),
3846
+
is_active,
3847
+
1000, TIMEOUT_FRL_READY_MS * 1000, false);
3848
+
if (ret)
3849
+
return ret;
3886
3850
3887
3851
ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3888
3852
DP_PCON_ENABLE_SEQUENTIAL_LINK);
···
3900
3862
* Wait for FRL to be completed
3901
3863
* Check if the HDMI Link is up and active.
3902
3864
*/
3903
-
wait_for(is_active =
3904
-
intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3905
-
TIMEOUT_HDMI_LINK_ACTIVE_MS);
3906
-
3907
-
if (!is_active)
3908
-
return -ETIMEDOUT;
3865
+
ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3866
+
is_active,
3867
+
1000, TIMEOUT_HDMI_LINK_ACTIVE_MS * 1000, false);
3868
+
if (ret)
3869
+
return ret;
3909
3870
3910
3871
frl_trained:
3911
3872
drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
···
4314
4277
}
4315
4278
4316
4279
static void
4280
+
intel_edp_set_data_override_rates(struct intel_dp *intel_dp)
4281
+
{
4282
+
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4283
+
int *sink_rates = intel_dp->sink_rates;
4284
+
int i, count = 0;
4285
+
4286
+
for (i = 0; i < intel_dp->num_sink_rates; i++) {
4287
+
if (intel_bios_encoder_reject_edp_rate(encoder->devdata,
4288
+
intel_dp->sink_rates[i]))
4289
+
continue;
4290
+
4291
+
sink_rates[count++] = intel_dp->sink_rates[i];
4292
+
}
4293
+
intel_dp->num_sink_rates = count;
4294
+
}
4295
+
4296
+
static void
4317
4297
intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4318
4298
{
4319
4299
struct intel_display *display = to_intel_display(intel_dp);
4320
-
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4321
4300
4322
4301
intel_dp->num_sink_rates = 0;
4323
4302
···
4359
4306
break;
4360
4307
4361
4308
/*
4362
-
* Some broken eDP sinks illegally declare support for
4363
-
* HBR3 without TPS4, and are unable to produce a stable
4364
-
* output. Reject HBR3 when TPS4 is not available.
4309
+
* Some platforms cannot reliably drive HBR3 rates due to PHY limitations,
4310
+
* even if the sink advertises support. Reject any sink rates above HBR2 on
4311
+
* the known machines for stable output.
4365
4312
*/
4366
-
if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
4367
-
drm_dbg_kms(display->drm,
4368
-
"[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
4369
-
encoder->base.base.id, encoder->base.name);
4313
+
if (rate > 540000 &&
4314
+
intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))
4370
4315
break;
4371
-
}
4372
4316
4373
4317
intel_dp->sink_rates[i] = rate;
4374
4318
}
···
4380
4330
intel_dp->use_rate_select = true;
4381
4331
else
4382
4332
intel_dp_set_sink_rates(intel_dp);
4333
+
4334
+
intel_edp_set_data_override_rates(intel_dp);
4383
4335
}
4384
4336
4385
4337
static bool
···
5663
5611
intel_wakeref_t wakeref;
5664
5612
5665
5613
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5666
-
unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5667
-
5668
-
do {
5669
-
is_connected = dig_port->connected(encoder);
5670
-
if (is_connected || is_glitch_free)
5671
-
break;
5672
-
usleep_range(10, 30);
5673
-
} while (time_before(jiffies, wait_expires));
5614
+
poll_timeout_us(is_connected = dig_port->connected(encoder),
5615
+
is_connected || is_glitch_free,
5616
+
30, 4000, false);
5674
5617
}
5675
5618
5676
5619
return is_connected;
+2
-1
drivers/gpu/drm/i915/display/intel_dp.h
+2
-1
drivers/gpu/drm/i915/display/intel_dp.h
···
193
193
int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
194
194
195
195
bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,
196
-
struct intel_connector *connector,
196
+
struct drm_connector_state *conn_state,
197
197
struct intel_crtc_state *crtc_state,
198
198
bool respect_downstream_limits,
199
199
bool dsc,
···
214
214
215
215
int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
216
216
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
217
+
bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
217
218
218
219
#endif /* __INTEL_DP_H__ */
-13
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
-13
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
···
225
225
connector->base.base.id, connector->base.name);
226
226
}
227
227
228
-
static bool
229
-
intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
230
-
{
231
-
struct hdr_output_metadata *hdr_metadata;
232
-
233
-
if (!conn_state->hdr_output_metadata)
234
-
return false;
235
-
236
-
hdr_metadata = conn_state->hdr_output_metadata->data;
237
-
238
-
return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
239
-
}
240
-
241
228
static void
242
229
intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state, u32 level)
243
230
{
+87
-69
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+87
-69
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
22
22
*/
23
23
24
24
#include <linux/debugfs.h>
25
+
#include <linux/iopoll.h>
25
26
26
27
#include <drm/display/drm_dp_helper.h>
27
28
#include <drm/drm_print.h>
···
479
478
_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
480
479
_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
481
480
482
-
void
481
+
bool
483
482
intel_dp_get_adjust_train(struct intel_dp *intel_dp,
484
483
const struct intel_crtc_state *crtc_state,
485
484
enum drm_dp_phy dp_phy,
486
485
const u8 link_status[DP_LINK_STATUS_SIZE])
487
486
{
487
+
bool changed = false;
488
488
int lane;
489
489
490
490
if (intel_dp_is_uhbr(crtc_state)) {
···
504
502
TRAIN_REQ_PREEMPH_ARGS(link_status));
505
503
}
506
504
507
-
for (lane = 0; lane < 4; lane++)
508
-
intel_dp->train_set[lane] =
509
-
intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
510
-
dp_phy, link_status, lane);
505
+
for (lane = 0; lane < 4; lane++) {
506
+
u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
507
+
dp_phy, link_status, lane);
508
+
if (intel_dp->train_set[lane] == new)
509
+
continue;
510
+
511
+
intel_dp->train_set[lane] = new;
512
+
changed = true;
513
+
}
514
+
515
+
return changed;
511
516
}
512
517
513
518
static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
···
767
758
}
768
759
}
769
760
761
+
/*
762
+
* Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
763
+
* for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
764
+
* 1.2 devices that support it, TPS2 otherwise.
765
+
*/
766
+
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
767
+
const struct intel_crtc_state *crtc_state,
768
+
enum drm_dp_phy dp_phy)
769
+
{
770
+
struct intel_display *display = to_intel_display(intel_dp);
771
+
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
772
+
773
+
/* UHBR+ use separate 128b/132b TPS2 */
774
+
if (intel_dp_is_uhbr(crtc_state))
775
+
return DP_TRAINING_PATTERN_2;
776
+
777
+
/*
778
+
* TPS4 support is mandatory for all downstream devices that
779
+
* support HBR3. There are no known eDP panels that support
780
+
* TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
781
+
* LTTPRs must support TPS4.
782
+
*/
783
+
source_tps4 = intel_dp_source_supports_tps4(display);
784
+
sink_tps4 = dp_phy != DP_PHY_DPRX ||
785
+
drm_dp_tps4_supported(intel_dp->dpcd);
786
+
if (source_tps4 && sink_tps4) {
787
+
return DP_TRAINING_PATTERN_4;
788
+
} else if (crtc_state->port_clock == 810000) {
789
+
if (!source_tps4)
790
+
lt_dbg(intel_dp, dp_phy,
791
+
"8.1 Gbps link rate without source TPS4 support\n");
792
+
if (!sink_tps4)
793
+
lt_dbg(intel_dp, dp_phy,
794
+
"8.1 Gbps link rate without sink TPS4 support\n");
795
+
}
796
+
797
+
/*
798
+
* TPS3 support is mandatory for downstream devices that
799
+
* support HBR2. However, not all sinks follow the spec.
800
+
*/
801
+
source_tps3 = intel_dp_source_supports_tps3(display);
802
+
sink_tps3 = dp_phy != DP_PHY_DPRX ||
803
+
drm_dp_tps3_supported(intel_dp->dpcd);
804
+
if (source_tps3 && sink_tps3) {
805
+
return DP_TRAINING_PATTERN_3;
806
+
} else if (crtc_state->port_clock >= 540000) {
807
+
if (!source_tps3)
808
+
lt_dbg(intel_dp, dp_phy,
809
+
">=5.4/6.48 Gbps link rate without source TPS3 support\n");
810
+
if (!sink_tps3)
811
+
lt_dbg(intel_dp, dp_phy,
812
+
">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
813
+
}
814
+
815
+
return DP_TRAINING_PATTERN_2;
816
+
}
817
+
770
818
static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
771
819
const struct intel_crtc_state *crtc_state,
772
820
u8 link_bw, u8 rate_select)
···
1016
950
}
1017
951
1018
952
/*
1019
-
* Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
1020
-
* for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
1021
-
* 1.2 devices that support it, TPS2 otherwise.
1022
-
*/
1023
-
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
1024
-
const struct intel_crtc_state *crtc_state,
1025
-
enum drm_dp_phy dp_phy)
1026
-
{
1027
-
struct intel_display *display = to_intel_display(intel_dp);
1028
-
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
1029
-
1030
-
/* UHBR+ use separate 128b/132b TPS2 */
1031
-
if (intel_dp_is_uhbr(crtc_state))
1032
-
return DP_TRAINING_PATTERN_2;
1033
-
1034
-
/*
1035
-
* TPS4 support is mandatory for all downstream devices that
1036
-
* support HBR3. There are no known eDP panels that support
1037
-
* TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
1038
-
* LTTPRs must support TPS4.
1039
-
*/
1040
-
source_tps4 = intel_dp_source_supports_tps4(display);
1041
-
sink_tps4 = dp_phy != DP_PHY_DPRX ||
1042
-
drm_dp_tps4_supported(intel_dp->dpcd);
1043
-
if (source_tps4 && sink_tps4) {
1044
-
return DP_TRAINING_PATTERN_4;
1045
-
} else if (crtc_state->port_clock == 810000) {
1046
-
if (!source_tps4)
1047
-
lt_dbg(intel_dp, dp_phy,
1048
-
"8.1 Gbps link rate without source TPS4 support\n");
1049
-
if (!sink_tps4)
1050
-
lt_dbg(intel_dp, dp_phy,
1051
-
"8.1 Gbps link rate without sink TPS4 support\n");
1052
-
}
1053
-
1054
-
/*
1055
-
* TPS3 support is mandatory for downstream devices that
1056
-
* support HBR2. However, not all sinks follow the spec.
1057
-
*/
1058
-
source_tps3 = intel_dp_source_supports_tps3(display);
1059
-
sink_tps3 = dp_phy != DP_PHY_DPRX ||
1060
-
drm_dp_tps3_supported(intel_dp->dpcd);
1061
-
if (source_tps3 && sink_tps3) {
1062
-
return DP_TRAINING_PATTERN_3;
1063
-
} else if (crtc_state->port_clock >= 540000) {
1064
-
if (!source_tps3)
1065
-
lt_dbg(intel_dp, dp_phy,
1066
-
">=5.4/6.48 Gbps link rate without source TPS3 support\n");
1067
-
if (!sink_tps3)
1068
-
lt_dbg(intel_dp, dp_phy,
1069
-
">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
1070
-
}
1071
-
1072
-
return DP_TRAINING_PATTERN_2;
1073
-
}
1074
-
1075
-
/*
1076
953
* Perform the link training channel equalization phase on the given DP PHY
1077
954
* using one of training pattern 2, 3 or 4 depending on the source and
1078
955
* sink capabilities.
···
1136
1127
{
1137
1128
struct intel_display *display = to_intel_display(intel_dp);
1138
1129
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1130
+
int ret;
1139
1131
1140
1132
intel_dp->link.active = true;
1141
1133
1142
-
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
1143
1134
intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
1144
1135
DP_TRAINING_PATTERN_DISABLE);
1145
1136
1146
-
if (intel_dp_is_uhbr(crtc_state) &&
1147
-
wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1148
-
lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
1137
+
if (intel_dp_is_uhbr(crtc_state)) {
1138
+
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
1139
+
ret == 0,
1140
+
500, 500 * 1000, false);
1141
+
if (ret)
1142
+
lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
1149
1143
}
1150
1144
1151
1145
intel_hpd_unblock(encoder);
···
1383
1371
if (ret)
1384
1372
ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
1385
1373
1386
-
if (intel_dp->set_idle_link_train)
1387
-
intel_dp->set_idle_link_train(intel_dp, crtc_state);
1374
+
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
1375
+
intel_dp->set_idle_link_train(intel_dp, crtc_state);
1388
1376
1389
1377
return ret;
1390
1378
}
···
1586
1574
int lttpr_count)
1587
1575
{
1588
1576
bool passed = false;
1577
+
int ret;
1589
1578
1590
-
if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1579
+
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
1580
+
ret == 0,
1581
+
500, 500 * 1000, false);
1582
+
if (ret) {
1591
1583
lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
1592
1584
goto out;
1593
1585
}
···
1617
1601
if (!passed)
1618
1602
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
1619
1603
DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
1604
+
1605
+
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
1620
1606
1621
1607
return passed;
1622
1608
}
+1
-1
drivers/gpu/drm/i915/display/intel_dp_link_training.h
+1
-1
drivers/gpu/drm/i915/display/intel_dp_link_training.h
···
23
23
int link_bw, int rate_select, int lane_count,
24
24
bool enhanced_framing);
25
25
26
-
void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
26
+
bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
27
27
const struct intel_crtc_state *crtc_state,
28
28
enum drm_dp_phy dp_phy,
29
29
const u8 link_status[DP_LINK_STATUS_SIZE]);
+7
-4
drivers/gpu/drm/i915/display/intel_dp_mst.c
+7
-4
drivers/gpu/drm/i915/display/intel_dp_mst.c
···
611
611
612
612
static bool
613
613
mst_stream_compute_config_limits(struct intel_dp *intel_dp,
614
-
struct intel_connector *connector,
614
+
struct drm_connector_state *conn_state,
615
615
struct intel_crtc_state *crtc_state,
616
616
bool dsc,
617
617
struct link_config_limits *limits)
618
618
{
619
-
if (!intel_dp_compute_config_limits(intel_dp, connector,
619
+
struct intel_connector *connector =
620
+
to_intel_connector(conn_state->connector);
621
+
622
+
if (!intel_dp_compute_config_limits(intel_dp, conn_state,
620
623
crtc_state, false, dsc,
621
624
limits))
622
625
return false;
···
668
665
joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
669
666
670
667
dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
671
-
!mst_stream_compute_config_limits(intel_dp, connector,
668
+
!mst_stream_compute_config_limits(intel_dp, conn_state,
672
669
pipe_config, false, &limits);
673
670
674
671
if (!dsc_needed) {
···
694
691
str_yes_no(intel_dp->force_dsc_en));
695
692
696
693
697
-
if (!mst_stream_compute_config_limits(intel_dp, connector,
694
+
if (!mst_stream_compute_config_limits(intel_dp, conn_state,
698
695
pipe_config, true,
699
696
&limits))
700
697
return -EINVAL;
+1
-3
drivers/gpu/drm/i915/display/intel_dp_test.c
+1
-3
drivers/gpu/drm/i915/display/intel_dp_test.c
···
6
6
#include <drm/display/drm_dp.h>
7
7
#include <drm/display/drm_dp_helper.h>
8
8
#include <drm/drm_edid.h>
9
-
#include <drm/drm_file.h>
10
9
#include <drm/drm_print.h>
11
10
#include <drm/drm_probe_helper.h>
12
11
···
752
753
753
754
void intel_dp_test_debugfs_register(struct intel_display *display)
754
755
{
755
-
struct drm_minor *minor = display->drm->primary;
756
756
int i;
757
757
758
758
for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) {
759
759
debugfs_create_file(intel_display_debugfs_files[i].name,
760
760
0644,
761
-
minor->debugfs_root,
761
+
display->drm->debugfs_root,
762
762
display,
763
763
intel_display_debugfs_files[i].fops);
764
764
}
+14
-6
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+14
-6
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
2046
2046
enum dpio_phy phy = DPIO_PHY0;
2047
2047
enum dpio_channel ch = DPIO_CH0;
2048
2048
u32 temp;
2049
+
int ret;
2049
2050
2050
2051
bxt_port_to_phy_channel(display, port, &phy, &ch);
2051
2052
···
2057
2056
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
2058
2057
0, PORT_PLL_POWER_ENABLE);
2059
2058
2060
-
if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
2061
-
PORT_PLL_POWER_STATE), 200))
2059
+
ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
2060
+
PORT_PLL_POWER_STATE, PORT_PLL_POWER_STATE,
2061
+
200, 0, NULL);
2062
+
if (ret)
2062
2063
drm_err(display->drm,
2063
2064
"Power state not set for PLL:%d\n", port);
2064
2065
}
···
2122
2119
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
2123
2120
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
2124
2121
2125
-
if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
2126
-
200))
2122
+
ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
2123
+
PORT_PLL_LOCK, PORT_PLL_LOCK,
2124
+
200, 0, NULL);
2125
+
if (ret)
2127
2126
drm_err(display->drm, "PLL %d not locked\n", port);
2128
2127
2129
2128
if (display->platform.geminilake) {
···
2149
2144
struct intel_dpll *pll)
2150
2145
{
2151
2146
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2147
+
int ret;
2152
2148
2153
2149
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
2154
2150
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
···
2158
2152
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
2159
2153
PORT_PLL_POWER_ENABLE, 0);
2160
2154
2161
-
if (wait_for_us(!(intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
2162
-
PORT_PLL_POWER_STATE), 200))
2155
+
ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
2156
+
PORT_PLL_POWER_STATE, 0,
2157
+
200, 0, NULL);
2158
+
if (ret)
2163
2159
drm_err(display->drm,
2164
2160
"Power state not reset for PLL:%d\n", port);
2165
2161
}
+1
-3
drivers/gpu/drm/i915/display/intel_dpt.c
+1
-3
drivers/gpu/drm/i915/display/intel_dpt.c
···
33
33
return container_of(vm, struct i915_dpt, vm);
34
34
}
35
35
36
-
#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
37
-
38
36
static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
39
37
{
40
38
writeq(pte, addr);
···
320
322
321
323
u64 intel_dpt_offset(struct i915_vma *dpt_vma)
322
324
{
323
-
return dpt_vma->node.start;
325
+
return i915_vma_offset(dpt_vma);
324
326
}
+8
-2
drivers/gpu/drm/i915/display/intel_dsb.c
+8
-2
drivers/gpu/drm/i915/display/intel_dsb.c
···
4
4
*
5
5
*/
6
6
7
+
#include <linux/iopoll.h>
8
+
7
9
#include <drm/drm_print.h>
8
10
#include <drm/drm_vblank.h>
9
11
10
-
#include "i915_utils.h"
11
12
#include "intel_crtc.h"
12
13
#include "intel_de.h"
13
14
#include "intel_display_regs.h"
···
872
871
struct intel_crtc *crtc = dsb->crtc;
873
872
struct intel_display *display = to_intel_display(crtc->base.dev);
874
873
enum pipe pipe = crtc->pipe;
874
+
bool is_busy;
875
+
int ret;
875
876
876
-
if (wait_for(!is_dsb_busy(display, pipe, dsb->id), 1)) {
877
+
ret = poll_timeout_us(is_busy = is_dsb_busy(display, pipe, dsb->id),
878
+
!is_busy,
879
+
100, 1000, false);
880
+
if (ret) {
877
881
u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);
878
882
879
883
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),
+1
-1
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+1
-1
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
···
777
777
intel_dsi->init_count = mipi_config->master_init_timer;
778
778
intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
779
779
intel_dsi->video_frmt_cfg_bits =
780
-
mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
780
+
mipi_config->bta_disable ? DISABLE_VIDEO_BTA : 0;
781
781
intel_dsi->bgr_enabled = mipi_config->rgb_flip;
782
782
783
783
/* Starting point, adjusted depending on dual link and burst mode */
+197
drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
+197
drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright © 2025 Intel Corporation */
3
+
4
+
#ifndef __INTEL_DSI_VBT_DEFS_H__
5
+
#define __INTEL_DSI_VBT_DEFS_H__
6
+
7
+
#include <linux/types.h>
8
+
9
+
/*
10
+
* MIPI Sequence Block definitions
11
+
*
12
+
* Note the VBT spec has AssertReset / DeassertReset swapped from their
13
+
* usual naming, we use the proper names here to avoid confusion when
14
+
* reading the code.
15
+
*/
16
+
enum mipi_seq {
17
+
MIPI_SEQ_END = 0,
18
+
MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */
19
+
MIPI_SEQ_INIT_OTP,
20
+
MIPI_SEQ_DISPLAY_ON,
21
+
MIPI_SEQ_DISPLAY_OFF,
22
+
MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */
23
+
MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
24
+
MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
25
+
MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
26
+
MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
27
+
MIPI_SEQ_POWER_ON, /* sequence block v3+ */
28
+
MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
29
+
MIPI_SEQ_MAX
30
+
};
31
+
32
+
enum mipi_seq_element {
33
+
MIPI_SEQ_ELEM_END = 0,
34
+
MIPI_SEQ_ELEM_SEND_PKT,
35
+
MIPI_SEQ_ELEM_DELAY,
36
+
MIPI_SEQ_ELEM_GPIO,
37
+
MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
38
+
MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
39
+
MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
40
+
MIPI_SEQ_ELEM_MAX
41
+
};
42
+
43
+
#define MIPI_DSI_UNDEFINED_PANEL_ID 0
44
+
#define MIPI_DSI_GENERIC_PANEL_ID 1
45
+
46
+
struct mipi_config {
47
+
u16 panel_id;
48
+
49
+
/* General Params */
50
+
struct {
51
+
u32 enable_dithering:1;
52
+
u32 rsvd1:1;
53
+
u32 is_bridge:1;
54
+
55
+
u32 panel_arch_type:2;
56
+
u32 is_cmd_mode:1;
57
+
58
+
#define NON_BURST_SYNC_PULSE 0x1
59
+
#define NON_BURST_SYNC_EVENTS 0x2
60
+
#define BURST_MODE 0x3
61
+
u32 video_transfer_mode:2;
62
+
63
+
u32 cabc_supported:1;
64
+
#define PPS_BLC_PMIC 0
65
+
#define PPS_BLC_SOC 1
66
+
u32 pwm_blc:1;
67
+
68
+
#define PIXEL_FORMAT_RGB565 0x1
69
+
#define PIXEL_FORMAT_RGB666 0x2
70
+
#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
71
+
#define PIXEL_FORMAT_RGB888 0x4
72
+
u32 videomode_color_format:4;
73
+
74
+
#define ENABLE_ROTATION_0 0x0
75
+
#define ENABLE_ROTATION_90 0x1
76
+
#define ENABLE_ROTATION_180 0x2
77
+
#define ENABLE_ROTATION_270 0x3
78
+
u32 rotation:2;
79
+
u32 bta_disable:1;
80
+
u32 rsvd2:15;
81
+
} __packed;
82
+
83
+
/* Port Desc */
84
+
struct {
85
+
#define DUAL_LINK_NOT_SUPPORTED 0
86
+
#define DUAL_LINK_FRONT_BACK 1
87
+
#define DUAL_LINK_PIXEL_ALT 2
88
+
u16 dual_link:2;
89
+
u16 lane_cnt:2;
90
+
u16 pixel_overlap:3;
91
+
u16 rgb_flip:1;
92
+
#define DL_DCS_PORT_A 0x00
93
+
#define DL_DCS_PORT_C 0x01
94
+
#define DL_DCS_PORT_A_AND_C 0x02
95
+
u16 dl_dcs_cabc_ports:2;
96
+
u16 dl_dcs_backlight_ports:2;
97
+
u16 port_sync:1; /* 219-230 */
98
+
u16 rsvd3:3;
99
+
} __packed;
100
+
101
+
/* DSI Controller Parameters */
102
+
struct {
103
+
u16 dsi_usage:1;
104
+
u16 rsvd4:15;
105
+
} __packed;
106
+
107
+
u8 rsvd5;
108
+
u32 target_burst_mode_freq;
109
+
u32 dsi_ddr_clk;
110
+
u32 bridge_ref_clk;
111
+
112
+
/* LP Byte Clock */
113
+
struct {
114
+
#define BYTE_CLK_SEL_20MHZ 0
115
+
#define BYTE_CLK_SEL_10MHZ 1
116
+
#define BYTE_CLK_SEL_5MHZ 2
117
+
u8 byte_clk_sel:2;
118
+
u8 rsvd6:6;
119
+
} __packed;
120
+
121
+
/* DPhy Flags */
122
+
struct {
123
+
u16 dphy_param_valid:1;
124
+
u16 eot_pkt_disabled:1;
125
+
u16 enable_clk_stop:1;
126
+
u16 blanking_packets_during_bllp:1; /* 219+ */
127
+
u16 lp_clock_during_lpm:1; /* 219+ */
128
+
u16 rsvd7:11;
129
+
} __packed;
130
+
131
+
u32 hs_tx_timeout;
132
+
u32 lp_rx_timeout;
133
+
u32 turn_around_timeout;
134
+
u32 device_reset_timer;
135
+
u32 master_init_timer;
136
+
u32 dbi_bw_timer;
137
+
u32 lp_byte_clk_val;
138
+
139
+
/* DPhy Params */
140
+
struct {
141
+
u32 prepare_cnt:6;
142
+
u32 rsvd8:2;
143
+
u32 clk_zero_cnt:8;
144
+
u32 trail_cnt:5;
145
+
u32 rsvd9:3;
146
+
u32 exit_zero_cnt:6;
147
+
u32 rsvd10:2;
148
+
} __packed;
149
+
150
+
u32 clk_lane_switch_cnt;
151
+
u32 hl_switch_cnt;
152
+
153
+
u32 rsvd11[6];
154
+
155
+
/* timings based on dphy spec */
156
+
u8 tclk_miss;
157
+
u8 tclk_post;
158
+
u8 rsvd12;
159
+
u8 tclk_pre;
160
+
u8 tclk_prepare;
161
+
u8 tclk_settle;
162
+
u8 tclk_term_enable;
163
+
u8 tclk_trail;
164
+
u16 tclk_prepare_clkzero;
165
+
u8 rsvd13;
166
+
u8 td_term_enable;
167
+
u8 teot;
168
+
u8 ths_exit;
169
+
u8 ths_prepare;
170
+
u16 ths_prepare_hszero;
171
+
u8 rsvd14;
172
+
u8 ths_settle;
173
+
u8 ths_skip;
174
+
u8 ths_trail;
175
+
u8 tinit;
176
+
u8 tlpx;
177
+
u8 rsvd15[3];
178
+
179
+
/* GPIOs */
180
+
u8 panel_enable;
181
+
u8 bl_enable;
182
+
u8 pwm_enable;
183
+
u8 reset_r_n;
184
+
u8 pwr_down_r;
185
+
u8 stdby_r_n;
186
+
} __packed;
187
+
188
+
/* all delays have a unit of 100us */
189
+
struct mipi_pps_data {
190
+
u16 panel_on_delay;
191
+
u16 bl_enable_delay;
192
+
u16 bl_disable_delay;
193
+
u16 panel_off_delay;
194
+
u16 panel_power_cycle_delay;
195
+
} __packed;
196
+
197
+
#endif /* __INTEL_DSI_VBT_DEFS_H__ */
+41
drivers/gpu/drm/i915/display/intel_encoder.c
+41
drivers/gpu/drm/i915/display/intel_encoder.c
···
8
8
#include "intel_display_core.h"
9
9
#include "intel_display_types.h"
10
10
#include "intel_encoder.h"
11
+
#include "intel_hotplug.h"
11
12
12
13
static void intel_encoder_link_check_work_fn(struct work_struct *work)
13
14
{
···
36
35
37
36
mod_delayed_work(display->wq.unordered,
38
37
&encoder->link_check_work, msecs_to_jiffies(delay_ms));
38
+
}
39
+
40
+
void intel_encoder_unblock_all_hpds(struct intel_display *display)
41
+
{
42
+
struct intel_encoder *encoder;
43
+
44
+
if (!HAS_DISPLAY(display))
45
+
return;
46
+
47
+
for_each_intel_encoder(display->drm, encoder)
48
+
intel_hpd_unblock(encoder);
49
+
}
50
+
51
+
void intel_encoder_block_all_hpds(struct intel_display *display)
52
+
{
53
+
struct intel_encoder *encoder;
54
+
55
+
if (!HAS_DISPLAY(display))
56
+
return;
57
+
58
+
for_each_intel_encoder(display->drm, encoder)
59
+
intel_hpd_block(encoder);
39
60
}
40
61
41
62
void intel_encoder_suspend_all(struct intel_display *display)
···
102
79
for_each_intel_encoder(display->drm, encoder)
103
80
if (encoder->shutdown_complete)
104
81
encoder->shutdown_complete(encoder);
82
+
}
83
+
84
+
struct intel_digital_port *intel_dig_port_alloc(void)
85
+
{
86
+
struct intel_digital_port *dig_port;
87
+
88
+
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
89
+
if (!dig_port)
90
+
return NULL;
91
+
92
+
dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG;
93
+
dig_port->dp.output_reg = INVALID_MMIO_REG;
94
+
dig_port->aux_ch = AUX_CH_NONE;
95
+
dig_port->max_lanes = 4;
96
+
97
+
mutex_init(&dig_port->hdcp.mutex);
98
+
99
+
return dig_port;
105
100
}
+6
drivers/gpu/drm/i915/display/intel_encoder.h
+6
drivers/gpu/drm/i915/display/intel_encoder.h
···
6
6
#ifndef __INTEL_ENCODER_H__
7
7
#define __INTEL_ENCODER_H__
8
8
9
+
struct intel_digital_port;
9
10
struct intel_display;
10
11
struct intel_encoder;
11
12
···
17
16
18
17
void intel_encoder_suspend_all(struct intel_display *display);
19
18
void intel_encoder_shutdown_all(struct intel_display *display);
19
+
20
+
void intel_encoder_block_all_hpds(struct intel_display *display);
21
+
void intel_encoder_unblock_all_hpds(struct intel_display *display);
22
+
23
+
struct intel_digital_port *intel_dig_port_alloc(void);
20
24
21
25
#endif /* __INTEL_ENCODER_H__ */
+1
drivers/gpu/drm/i915/display/intel_fb.c
+1
drivers/gpu/drm/i915/display/intel_fb.c
+26
-13
drivers/gpu/drm/i915/display/intel_fb_pin.c
+26
-13
drivers/gpu/drm/i915/display/intel_fb_pin.c
···
11
11
#include "gem/i915_gem_object.h"
12
12
13
13
#include "i915_drv.h"
14
+
#include "i915_vma.h"
14
15
#include "intel_display_core.h"
15
16
#include "intel_display_rpm.h"
16
17
#include "intel_display_types.h"
···
152
151
* happy to scanout from anywhere within its global aperture.
153
152
*/
154
153
pinctl = 0;
155
-
if (HAS_GMCH(dev_priv))
154
+
if (HAS_GMCH(display))
156
155
pinctl |= PIN_MAPPABLE;
157
156
158
157
i915_gem_ww_ctx_init(&ww, true);
···
193
192
* mode that matches the user configuration.
194
193
*/
195
194
ret = i915_vma_pin_fence(vma);
196
-
if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
195
+
if (ret != 0 && DISPLAY_VER(display) < 4) {
197
196
i915_vma_unpin(vma);
198
197
goto err_unpin;
199
198
}
···
261
260
int intel_plane_pin_fb(struct intel_plane_state *plane_state,
262
261
const struct intel_plane_state *old_plane_state)
263
262
{
263
+
struct intel_display *display = to_intel_display(plane_state);
264
264
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
265
265
const struct intel_framebuffer *fb =
266
266
to_intel_framebuffer(plane_state->hw.fb);
···
279
277
280
278
plane_state->ggtt_vma = vma;
281
279
282
-
/*
283
-
* Pre-populate the dma address before we enter the vblank
284
-
* evade critical section as i915_gem_object_get_dma_address()
285
-
* will trigger might_sleep() even if it won't actually sleep,
286
-
* which is the case when the fb has already been pinned.
287
-
*/
288
-
if (intel_plane_needs_physical(plane)) {
289
-
struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base));
290
-
291
-
plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0);
292
-
}
293
280
} else {
294
281
unsigned int alignment = intel_plane_fb_min_alignment(plane_state);
295
282
···
300
309
plane_state->dpt_vma = vma;
301
310
302
311
WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
312
+
313
+
/*
314
+
* The DPT object contains only one vma, and there is no VT-d
315
+
* guard, so the VMA's offset within the DPT is always 0.
316
+
*/
317
+
drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma));
318
+
}
319
+
320
+
/*
321
+
* Pre-populate the dma address before we enter the vblank
322
+
* evade critical section as i915_gem_object_get_dma_address()
323
+
* will trigger might_sleep() even if it won't actually sleep,
324
+
* which is the case when the fb has already been pinned.
325
+
*/
326
+
if (intel_plane_needs_physical(plane)) {
327
+
struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base));
328
+
329
+
plane_state->surf = i915_gem_object_get_dma_address(obj, 0) +
330
+
plane->surf_offset(plane_state);
331
+
} else {
332
+
plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma) +
333
+
plane->surf_offset(plane_state);
303
334
}
304
335
305
336
return 0;
+2
-3
drivers/gpu/drm/i915/display/intel_fbc.c
+2
-3
drivers/gpu/drm/i915/display/intel_fbc.c
···
1460
1460
return 0;
1461
1461
}
1462
1462
1463
-
if (intel_display_needs_wa_16023588340(display)) {
1463
+
if (intel_display_wa(display, 16023588340)) {
1464
1464
plane_state->no_fbc_reason = "Wa_16023588340";
1465
1465
return 0;
1466
1466
}
···
2240
2240
/* FIXME: remove this once igt is on board with per-crtc stuff */
2241
2241
void intel_fbc_debugfs_register(struct intel_display *display)
2242
2242
{
2243
-
struct drm_minor *minor = display->drm->primary;
2244
2243
struct intel_fbc *fbc;
2245
2244
2246
2245
fbc = display->fbc[INTEL_FBC_A];
2247
2246
if (fbc)
2248
-
intel_fbc_debugfs_add(fbc, minor->debugfs_root);
2247
+
intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
2249
2248
}
-28
drivers/gpu/drm/i915/display/intel_fdi.c
-28
drivers/gpu/drm/i915/display/intel_fdi.c
···
292
292
return display->fdi.pll_freq;
293
293
}
294
294
295
-
/**
296
-
* intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp
297
-
* @crtc_state: the crtc state
298
-
*
299
-
* Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
300
-
* call this function during state computation in the simple case where the
301
-
* link bpp will always match the pipe bpp. This is the case for all non-DP
302
-
* encoders, while DP encoders will use a link bpp lower than pipe bpp in case
303
-
* of DSC compression.
304
-
*
305
-
* Returns %true in case of success, %false if pipe bpp would need to be
306
-
* reduced below its valid range.
307
-
*/
308
-
bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
309
-
{
310
-
int pipe_bpp = min(crtc_state->pipe_bpp,
311
-
fxp_q4_to_int(crtc_state->max_link_bpp_x16));
312
-
313
-
pipe_bpp = rounddown(pipe_bpp, 2 * 3);
314
-
315
-
if (pipe_bpp < 6 * 3)
316
-
return false;
317
-
318
-
crtc_state->pipe_bpp = pipe_bpp;
319
-
320
-
return true;
321
-
}
322
-
323
295
int ilk_fdi_compute_config(struct intel_crtc *crtc,
324
296
struct intel_crtc_state *pipe_config)
325
297
{
-1
drivers/gpu/drm/i915/display/intel_fdi.h
-1
drivers/gpu/drm/i915/display/intel_fdi.h
···
20
20
int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
21
21
int intel_fdi_link_freq(struct intel_display *display,
22
22
const struct intel_crtc_state *pipe_config);
23
-
bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
24
23
int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
25
24
struct intel_crtc_state *pipe_config);
26
25
int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
+31
-1
drivers/gpu/drm/i915/display/intel_global_state.c
+31
-1
drivers/gpu/drm/i915/display/intel_global_state.c
···
13
13
#include "intel_display_types.h"
14
14
#include "intel_global_state.h"
15
15
16
+
#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
17
+
for ((__i) = 0; \
18
+
(__i) < (__state)->num_global_objs && \
19
+
((obj) = (__state)->global_objs[__i].ptr, \
20
+
(new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
21
+
(__i)++) \
22
+
for_each_if(obj)
23
+
24
+
#define for_each_old_global_obj_in_state(__state, obj, old_obj_state, __i) \
25
+
for ((__i) = 0; \
26
+
(__i) < (__state)->num_global_objs && \
27
+
((obj) = (__state)->global_objs[__i].ptr, \
28
+
(old_obj_state) = (__state)->global_objs[__i].old_state, 1); \
29
+
(__i)++) \
30
+
for_each_if(obj)
31
+
32
+
#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
33
+
for ((__i) = 0; \
34
+
(__i) < (__state)->num_global_objs && \
35
+
((obj) = (__state)->global_objs[__i].ptr, \
36
+
(old_obj_state) = (__state)->global_objs[__i].old_state, \
37
+
(new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
38
+
(__i)++) \
39
+
for_each_if(obj)
40
+
41
+
struct intel_global_objs_state {
42
+
struct intel_global_obj *ptr;
43
+
struct intel_global_state *state, *old_state, *new_state;
44
+
};
45
+
16
46
struct intel_global_commit {
17
47
struct kref ref;
18
48
struct completion done;
···
178
148
struct intel_display *display = to_intel_display(state);
179
149
int index, num_objs, i;
180
150
size_t size;
181
-
struct __intel_global_objs_state *arr;
151
+
struct intel_global_objs_state *arr;
182
152
struct intel_global_state *obj_state;
183
153
184
154
for (i = 0; i < state->num_global_objs; i++)
+1
-35
drivers/gpu/drm/i915/display/intel_global_state.h
+1
-35
drivers/gpu/drm/i915/display/intel_global_state.h
···
11
11
12
12
struct intel_atomic_state;
13
13
struct intel_display;
14
+
struct intel_global_commit;
14
15
struct intel_global_obj;
15
16
struct intel_global_state;
16
17
···
27
26
const struct intel_global_state_funcs *funcs;
28
27
};
29
28
30
-
#define intel_for_each_global_obj(obj, dev_priv) \
31
-
list_for_each_entry(obj, &(dev_priv)->display.global.obj_list, head)
32
-
33
-
#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \
34
-
for ((__i) = 0; \
35
-
(__i) < (__state)->num_global_objs && \
36
-
((obj) = (__state)->global_objs[__i].ptr, \
37
-
(new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
38
-
(__i)++) \
39
-
for_each_if(obj)
40
-
41
-
#define for_each_old_global_obj_in_state(__state, obj, old_obj_state, __i) \
42
-
for ((__i) = 0; \
43
-
(__i) < (__state)->num_global_objs && \
44
-
((obj) = (__state)->global_objs[__i].ptr, \
45
-
(old_obj_state) = (__state)->global_objs[__i].old_state, 1); \
46
-
(__i)++) \
47
-
for_each_if(obj)
48
-
49
-
#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \
50
-
for ((__i) = 0; \
51
-
(__i) < (__state)->num_global_objs && \
52
-
((obj) = (__state)->global_objs[__i].ptr, \
53
-
(old_obj_state) = (__state)->global_objs[__i].old_state, \
54
-
(new_obj_state) = (__state)->global_objs[__i].new_state, 1); \
55
-
(__i)++) \
56
-
for_each_if(obj)
57
-
58
-
struct intel_global_commit;
59
-
60
29
struct intel_global_state {
61
30
struct intel_global_obj *obj;
62
31
struct intel_atomic_state *state;
63
32
struct intel_global_commit *commit;
64
33
struct kref ref;
65
34
bool changed, serialized;
66
-
};
67
-
68
-
struct __intel_global_objs_state {
69
-
struct intel_global_obj *ptr;
70
-
struct intel_global_state *state, *old_state, *new_state;
71
35
};
72
36
73
37
void intel_atomic_global_obj_init(struct intel_display *display,
+43
-10
drivers/gpu/drm/i915/display/intel_gmbus.c
+43
-10
drivers/gpu/drm/i915/display/intel_gmbus.c
···
30
30
#include <linux/export.h>
31
31
#include <linux/i2c-algo-bit.h>
32
32
#include <linux/i2c.h>
33
+
#include <linux/iopoll.h>
33
34
34
35
#include <drm/display/drm_hdcp_helper.h>
35
36
···
40
39
#include "intel_de.h"
41
40
#include "intel_display_regs.h"
42
41
#include "intel_display_types.h"
42
+
#include "intel_display_wa.h"
43
43
#include "intel_gmbus.h"
44
44
#include "intel_gmbus_regs.h"
45
45
···
219
217
bool enable)
220
218
{
221
219
/* When using bit bashing for I2C, this bit needs to be set to 1 */
222
-
intel_de_rmw(display, DSPCLK_GATE_D(display),
220
+
intel_de_rmw(display, DSPCLK_GATE_D,
223
221
PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
224
222
!enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
225
223
}
···
242
240
static u32 get_reserved(struct intel_gmbus *bus)
243
241
{
244
242
struct intel_display *display = bus->display;
245
-
u32 reserved = 0;
243
+
u32 preserve_bits = 0;
244
+
245
+
if (display->platform.i830 || display->platform.i845g)
246
+
return 0;
246
247
247
248
/* On most chips, these bits must be preserved in software. */
248
-
if (!display->platform.i830 && !display->platform.i845g)
249
-
reserved = intel_de_read_notrace(display, bus->gpio_reg) &
250
-
(GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
249
+
preserve_bits |= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE;
251
250
252
-
return reserved;
251
+
/* Wa_16025573575: the masks bits need to be preserved through out */
252
+
if (intel_display_wa(display, 16025573575))
253
+
preserve_bits |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |
254
+
GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK;
255
+
256
+
return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits;
253
257
}
254
258
255
259
static int get_clock(void *data)
···
316
308
intel_de_posting_read(display, bus->gpio_reg);
317
309
}
318
310
311
+
static void
312
+
ptl_handle_mask_bits(struct intel_gmbus *bus, bool set)
313
+
{
314
+
struct intel_display *display = bus->display;
315
+
u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);
316
+
u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |
317
+
GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK;
318
+
if (set)
319
+
reg_val |= mask_bits;
320
+
else
321
+
reg_val &= ~mask_bits;
322
+
323
+
intel_de_write_notrace(display, bus->gpio_reg, reg_val);
324
+
intel_de_posting_read(display, bus->gpio_reg);
325
+
}
326
+
319
327
static int
320
328
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
321
329
{
···
342
318
343
319
if (display->platform.pineview)
344
320
pnv_gmbus_clock_gating(display, false);
321
+
322
+
if (intel_display_wa(display, 16025573575))
323
+
ptl_handle_mask_bits(bus, true);
345
324
346
325
set_data(bus, 1);
347
326
set_clock(bus, 1);
···
363
336
364
337
if (display->platform.pineview)
365
338
pnv_gmbus_clock_gating(display, true);
339
+
340
+
if (intel_display_wa(display, 16025573575))
341
+
ptl_handle_mask_bits(bus, false);
366
342
}
367
343
368
344
static void
···
415
385
intel_de_write_fw(display, GMBUS4(display), irq_en);
416
386
417
387
status |= GMBUS_SATOER;
418
-
ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
419
-
2);
388
+
389
+
ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
390
+
gmbus2 & status,
391
+
0, 2, false);
420
392
if (ret)
421
-
ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
422
-
50);
393
+
ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
394
+
gmbus2 & status,
395
+
500, 50 * 1000, false);
423
396
424
397
intel_de_write_fw(display, GMBUS4(display), 0);
425
398
remove_wait_queue(&display->gmbus.wait_queue, &wait);
+14
-19
drivers/gpu/drm/i915/display/intel_hdcp.c
+14
-19
drivers/gpu/drm/i915/display/intel_hdcp.c
···
11
11
#include <linux/component.h>
12
12
#include <linux/debugfs.h>
13
13
#include <linux/i2c.h>
14
+
#include <linux/iopoll.h>
14
15
#include <linux/random.h>
15
16
16
17
#include <drm/display/drm_hdcp_helper.h>
···
327
326
bool ksv_ready;
328
327
329
328
/* Poll for ksv list ready (spec says max time allowed is 5s) */
330
-
ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port,
331
-
&ksv_ready),
332
-
read_ret || ksv_ready, 5 * 1000 * 1000, 1000,
333
-
100 * 1000);
329
+
ret = poll_timeout_us(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready),
330
+
read_ret || ksv_ready,
331
+
100 * 1000, 5 * 1000 * 1000, false);
334
332
if (ret)
335
333
return ret;
336
334
if (read_ret)
337
335
return read_ret;
338
-
if (!ksv_ready)
339
-
return -ETIMEDOUT;
340
336
341
337
return 0;
342
338
}
···
815
817
enum port port = dig_port->base.port;
816
818
unsigned long r0_prime_gen_start;
817
819
int ret, i, tries = 2;
820
+
u32 val;
818
821
union {
819
822
u32 reg[2];
820
823
u8 shim[DRM_HDCP_AN_LEN];
···
904
905
HDCP_CONF_AUTH_AND_ENC);
905
906
906
907
/* Wait for R0 ready */
907
-
if (wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) &
908
-
(HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
908
+
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
909
+
val & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC),
910
+
100, 1000, false);
911
+
if (ret) {
909
912
drm_err(display->drm, "Timed out waiting for R0 ready\n");
910
913
return -ETIMEDOUT;
911
914
}
···
939
938
ri.reg);
940
939
941
940
/* Wait for Ri prime match */
942
-
if (!wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) &
943
-
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
941
+
ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),
942
+
val & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC),
943
+
100, 1000, false);
944
+
if (!ret)
944
945
break;
945
946
}
946
947
947
948
if (i == tries) {
948
949
drm_dbg_kms(display->drm,
949
-
"Timed out waiting for Ri prime match (%x)\n",
950
-
intel_de_read(display,
951
-
HDCP_STATUS(display, cpu_transcoder, port)));
950
+
"Timed out waiting for Ri prime match (%x)\n", val);
952
951
return -ETIMEDOUT;
953
952
}
954
953
···
2446
2445
2447
2446
if (!hdcp->shim)
2448
2447
return -ENOENT;
2449
-
2450
-
if (!connector->encoder) {
2451
-
drm_err(display->drm, "[CONNECTOR:%d:%s] encoder is not initialized\n",
2452
-
connector->base.base.id, connector->base.name);
2453
-
return -ENODEV;
2454
-
}
2455
2448
2456
2449
mutex_lock(&hdcp->mutex);
2457
2450
mutex_lock(&dig_port->hdcp.mutex);
+16
-8
drivers/gpu/drm/i915/display/intel_hdmi.c
+16
-8
drivers/gpu/drm/i915/display/intel_hdmi.c
···
29
29
#include <linux/delay.h>
30
30
#include <linux/hdmi.h>
31
31
#include <linux/i2c.h>
32
+
#include <linux/iopoll.h>
32
33
#include <linux/slab.h>
33
34
#include <linux/string_helpers.h>
34
35
···
61
60
#include "intel_hdcp_regs.h"
62
61
#include "intel_hdcp_shim.h"
63
62
#include "intel_hdmi.h"
63
+
#include "intel_link_bw.h"
64
64
#include "intel_lspcon.h"
65
65
#include "intel_panel.h"
66
66
#include "intel_pfit.h"
···
1584
1582
intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);
1585
1583
1586
1584
/* Wait for Ri prime match */
1587
-
if (wait_for((intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) &
1588
-
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1589
-
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1585
+
ret = intel_de_wait_for_set(display, HDCP_STATUS(display, cpu_transcoder, port),
1586
+
HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC, 1);
1587
+
if (ret) {
1590
1588
drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
1591
1589
intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,
1592
1590
port)));
···
1691
1689
if (timeout < 0)
1692
1690
return timeout;
1693
1691
1694
-
ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1695
-
msg_id, &msg_ready,
1696
-
&msg_sz),
1697
-
!ret && msg_ready && msg_sz, timeout * 1000,
1698
-
1000, 5 * 1000);
1692
+
ret = poll_timeout_us(ret = hdcp2_detect_msg_availability(dig_port, msg_id,
1693
+
&msg_ready, &msg_sz),
1694
+
!ret && msg_ready && msg_sz,
1695
+
4000, timeout * 1000, false);
1699
1696
if (ret)
1700
1697
drm_dbg_kms(display->drm,
1701
1698
"msg_id: %d, ret: %d, timeout: %d\n",
···
2054
2053
else
2055
2054
sink_format = INTEL_OUTPUT_FORMAT_RGB;
2056
2055
2056
+
status = intel_pfit_mode_valid(display, mode, sink_format, 0);
2057
+
if (status != MODE_OK)
2058
+
return status;
2059
+
2057
2060
status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
2058
2061
if (status != MODE_OK) {
2059
2062
if (ycbcr_420_only ||
···
2345
2340
2346
2341
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2347
2342
pipe_config->pixel_multiplier = 2;
2343
+
2344
+
if (!intel_link_bw_compute_pipe_bpp(pipe_config))
2345
+
return -EINVAL;
2348
2346
2349
2347
pipe_config->has_audio =
2350
2348
intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
+5
-6
drivers/gpu/drm/i915/display/intel_hotplug.c
+5
-6
drivers/gpu/drm/i915/display/intel_hotplug.c
···
28
28
29
29
#include "i915_drv.h"
30
30
#include "i915_irq.h"
31
+
#include "i915_utils.h"
31
32
#include "intel_connector.h"
32
33
#include "intel_display_power.h"
33
34
#include "intel_display_core.h"
···
972
971
973
972
spin_lock_irq(&display->irq.lock);
974
973
975
-
drm_WARN_ON(display->drm, get_blocked_hpd_pin_mask(display));
976
-
977
974
display->hotplug.long_hpd_pin_mask = 0;
978
975
display->hotplug.short_hpd_pin_mask = 0;
979
976
display->hotplug.event_bits = 0;
···
1332
1333
1333
1334
void intel_hpd_debugfs_register(struct intel_display *display)
1334
1335
{
1335
-
struct drm_minor *minor = display->drm->primary;
1336
+
struct dentry *debugfs_root = display->drm->debugfs_root;
1336
1337
1337
-
debugfs_create_file("i915_hpd_storm_ctl", 0644, minor->debugfs_root,
1338
+
debugfs_create_file("i915_hpd_storm_ctl", 0644, debugfs_root,
1338
1339
display, &i915_hpd_storm_ctl_fops);
1339
-
debugfs_create_file("i915_hpd_short_storm_ctl", 0644, minor->debugfs_root,
1340
+
debugfs_create_file("i915_hpd_short_storm_ctl", 0644, debugfs_root,
1340
1341
display, &i915_hpd_short_storm_ctl_fops);
1341
-
debugfs_create_bool("i915_ignore_long_hpd", 0644, minor->debugfs_root,
1342
+
debugfs_create_bool("i915_ignore_long_hpd", 0644, debugfs_root,
1342
1343
&display->hotplug.ignore_long_hpd);
1343
1344
}
+1
-1
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+1
-1
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+29
-5
drivers/gpu/drm/i915/display/intel_link_bw.c
+29
-5
drivers/gpu/drm/i915/display/intel_link_bw.c
···
165
165
}
166
166
167
167
/**
168
+
* intel_link_bw_compute_pipe_bpp - compute pipe bpp limited by max link bpp
169
+
* @crtc_state: the crtc state
170
+
*
171
+
* Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
172
+
* call this function during state computation in the simple case where the
173
+
* link bpp will always match the pipe bpp. This is the case for all non-DP
174
+
* encoders, while DP encoders will use a link bpp lower than pipe bpp in case
175
+
* of DSC compression.
176
+
*
177
+
* Returns %true in case of success, %false if pipe bpp would need to be
178
+
* reduced below its valid range.
179
+
*/
180
+
bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
181
+
{
182
+
int pipe_bpp = min(crtc_state->pipe_bpp,
183
+
fxp_q4_to_int(crtc_state->max_link_bpp_x16));
184
+
185
+
pipe_bpp = rounddown(pipe_bpp, 2 * 3);
186
+
187
+
if (pipe_bpp < 6 * 3)
188
+
return false;
189
+
190
+
crtc_state->pipe_bpp = pipe_bpp;
191
+
192
+
return true;
193
+
}
194
+
195
+
/**
168
196
* intel_link_bw_set_bpp_limit_for_pipe - set link bpp limit for a pipe to its minimum
169
197
* @state: atomic state
170
198
* @old_limits: link BW limits
···
477
449
switch (connector->base.connector_type) {
478
450
case DRM_MODE_CONNECTOR_DisplayPort:
479
451
case DRM_MODE_CONNECTOR_eDP:
452
+
case DRM_MODE_CONNECTOR_HDMIA:
480
453
break;
481
454
case DRM_MODE_CONNECTOR_VGA:
482
455
case DRM_MODE_CONNECTOR_SVIDEO:
483
456
case DRM_MODE_CONNECTOR_LVDS:
484
457
case DRM_MODE_CONNECTOR_DVID:
485
458
if (HAS_FDI(display))
486
-
break;
487
-
488
-
return;
489
-
case DRM_MODE_CONNECTOR_HDMIA:
490
-
if (HAS_FDI(display) && !HAS_DDI(display))
491
459
break;
492
460
493
461
return;
+1
drivers/gpu/drm/i915/display/intel_link_bw.h
+1
drivers/gpu/drm/i915/display/intel_link_bw.h
···
27
27
struct intel_link_bw_limits *limits,
28
28
u8 pipe_mask,
29
29
const char *reason);
30
+
bool intel_link_bw_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
30
31
bool intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state,
31
32
const struct intel_link_bw_limits *old_limits,
32
33
struct intel_link_bw_limits *new_limits,
+4
-7
drivers/gpu/drm/i915/display/intel_lpe_audio.c
+4
-7
drivers/gpu/drm/i915/display/intel_lpe_audio.c
···
68
68
#include <linux/platform_device.h>
69
69
#include <linux/pm_runtime.h>
70
70
71
+
#include <drm/drm_print.h>
71
72
#include <drm/intel/intel_lpe_audio.h>
72
73
73
-
#include "i915_drv.h"
74
74
#include "i915_irq.h"
75
75
#include "intel_audio_regs.h"
76
76
#include "intel_de.h"
···
170
170
171
171
static int lpe_audio_irq_init(struct intel_display *display)
172
172
{
173
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
174
173
int irq = display->audio.lpe.irq;
175
174
176
-
drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv));
177
-
irq_set_chip_and_handler_name(irq,
178
-
&lpe_audio_irqchip,
179
-
handle_simple_irq,
180
-
"hdmi_lpe_audio_irq_handler");
175
+
irq_set_chip_and_handler_name(irq, &lpe_audio_irqchip,
176
+
handle_simple_irq,
177
+
"hdmi_lpe_audio_irq_handler");
181
178
182
179
return 0;
183
180
}
+10
-3
drivers/gpu/drm/i915/display/intel_lspcon.c
+10
-3
drivers/gpu/drm/i915/display/intel_lspcon.c
···
23
23
*
24
24
*/
25
25
26
+
#include <linux/iopoll.h>
27
+
26
28
#include <drm/display/drm_dp_dual_mode_helper.h>
27
29
#include <drm/display/drm_hdmi_helper.h>
28
30
#include <drm/drm_atomic_helper.h>
···
183
181
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
184
182
struct intel_display *display = to_intel_display(intel_dp);
185
183
enum drm_lspcon_mode current_mode;
184
+
int timeout_us;
185
+
int ret;
186
186
187
187
current_mode = lspcon_get_current_mode(lspcon);
188
188
if (current_mode == mode)
···
193
189
drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n",
194
190
lspcon_mode_name(mode));
195
191
196
-
wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode,
197
-
lspcon_get_mode_settle_timeout(lspcon));
198
-
if (current_mode != mode)
192
+
timeout_us = lspcon_get_mode_settle_timeout(lspcon) * 1000;
193
+
194
+
ret = poll_timeout_us(current_mode = lspcon_get_current_mode(lspcon),
195
+
current_mode == mode,
196
+
5000, timeout_us, false);
197
+
if (ret)
199
198
drm_err(display->drm, "LSPCON mode hasn't settled\n");
200
199
201
200
out:
+2
-1
drivers/gpu/drm/i915/display/intel_lvds.c
+2
-1
drivers/gpu/drm/i915/display/intel_lvds.c
···
48
48
#include "intel_dpll.h"
49
49
#include "intel_fdi.h"
50
50
#include "intel_gmbus.h"
51
+
#include "intel_link_bw.h"
51
52
#include "intel_lvds.h"
52
53
#include "intel_lvds_regs.h"
53
54
#include "intel_panel.h"
···
434
433
435
434
if (HAS_PCH_SPLIT(display)) {
436
435
crtc_state->has_pch_encoder = true;
437
-
if (!intel_fdi_compute_pipe_bpp(crtc_state))
436
+
if (!intel_link_bw_compute_pipe_bpp(crtc_state))
438
437
return -EINVAL;
439
438
}
440
439
+7
-7
drivers/gpu/drm/i915/display/intel_opregion.c
+7
-7
drivers/gpu/drm/i915/display/intel_opregion.c
···
28
28
#include <linux/acpi.h>
29
29
#include <linux/debugfs.h>
30
30
#include <linux/dmi.h>
31
+
#include <linux/iopoll.h>
31
32
#include <acpi/video.h>
32
33
33
34
#include <drm/drm_edid.h>
34
35
#include <drm/drm_file.h>
35
36
#include <drm/drm_print.h>
36
37
37
-
#include "i915_utils.h"
38
38
#include "intel_acpi.h"
39
39
#include "intel_backlight.h"
40
40
#include "intel_display_core.h"
···
357
357
pci_write_config_word(pdev, SWSCI, swsci_val);
358
358
359
359
/* Poll for the result. */
360
-
#define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0)
361
-
if (wait_for(C, dslp)) {
360
+
ret = poll_timeout_us(scic = swsci->scic,
361
+
(scic & SWSCI_SCIC_INDICATOR) == 0,
362
+
1000, dslp * 1000, false);
363
+
if (ret) {
362
364
drm_dbg(display->drm, "SWSCI request timed out\n");
363
-
return -ETIMEDOUT;
365
+
return ret;
364
366
}
365
367
366
368
scic = (scic & SWSCI_SCIC_EXIT_STATUS_MASK) >>
···
1301
1299
1302
1300
void intel_opregion_debugfs_register(struct intel_display *display)
1303
1301
{
1304
-
struct drm_minor *minor = display->drm->primary;
1305
-
1306
-
debugfs_create_file("i915_opregion", 0444, minor->debugfs_root,
1302
+
debugfs_create_file("i915_opregion", 0444, display->drm->debugfs_root,
1307
1303
display, &intel_opregion_fops);
1308
1304
}
+2
-3
drivers/gpu/drm/i915/display/intel_overlay.c
+2
-3
drivers/gpu/drm/i915/display/intel_overlay.c
···
217
217
218
218
/* WA_OVERLAY_CLKGATE:alm */
219
219
if (enable)
220
-
intel_de_write(display, DSPCLK_GATE_D(display), 0);
220
+
intel_de_write(display, DSPCLK_GATE_D, 0);
221
221
else
222
-
intel_de_write(display, DSPCLK_GATE_D(display),
223
-
OVRUNIT_CLOCK_GATE_DISABLE);
222
+
intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
224
223
225
224
/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
226
225
pci_bus_read_config_byte(pdev->bus,
+1
-3
drivers/gpu/drm/i915/display/intel_pch.h
+1
-3
drivers/gpu/drm/i915/display/intel_pch.h
···
6
6
#ifndef __INTEL_PCH__
7
7
#define __INTEL_PCH__
8
8
9
-
#include "intel_display_conversion.h"
10
-
11
9
struct intel_display;
12
10
13
11
/*
···
34
36
PCH_LNL,
35
37
};
36
38
37
-
#define INTEL_PCH_TYPE(_display) (__to_intel_display(_display)->pch_type)
39
+
#define INTEL_PCH_TYPE(_display) ((_display)->pch_type)
38
40
#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2)
39
41
#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP)
40
42
#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1)
+10
-4
drivers/gpu/drm/i915/display/intel_pch_refclk.c
+10
-4
drivers/gpu/drm/i915/display/intel_pch_refclk.c
···
17
17
18
18
static void lpt_fdi_reset_mphy(struct intel_display *display)
19
19
{
20
+
int ret;
21
+
20
22
intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
21
23
22
-
if (wait_for_us(intel_de_read(display, SOUTH_CHICKEN2) &
23
-
FDI_MPHY_IOSFSB_RESET_STATUS, 100))
24
+
ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
25
+
FDI_MPHY_IOSFSB_RESET_STATUS, FDI_MPHY_IOSFSB_RESET_STATUS,
26
+
100, 0, NULL);
27
+
if (ret)
24
28
drm_err(display->drm, "FDI mPHY reset assert timeout\n");
25
29
26
30
intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
27
31
28
-
if (wait_for_us((intel_de_read(display, SOUTH_CHICKEN2) &
29
-
FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
32
+
ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
33
+
FDI_MPHY_IOSFSB_RESET_STATUS, 0,
34
+
100, 0, NULL);
35
+
if (ret)
30
36
drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
31
37
}
32
38
+11
drivers/gpu/drm/i915/display/intel_pfit.c
+11
drivers/gpu/drm/i915/display/intel_pfit.c
···
14
14
#include "intel_lvds_regs.h"
15
15
#include "intel_pfit.h"
16
16
#include "intel_pfit_regs.h"
17
+
#include "skl_scaler.h"
17
18
18
19
static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
19
20
{
···
545
544
return 0;
546
545
547
546
return intel_gmch_pfit_check_timings(crtc_state);
547
+
}
548
+
549
+
enum drm_mode_status
550
+
intel_pfit_mode_valid(struct intel_display *display,
551
+
const struct drm_display_mode *mode,
552
+
enum intel_output_format output_format,
553
+
int num_joined_pipes)
554
+
{
555
+
return skl_scaler_mode_valid(display, mode, output_format,
556
+
num_joined_pipes);
548
557
}
549
558
550
559
int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
+9
-1
drivers/gpu/drm/i915/display/intel_pfit.h
+9
-1
drivers/gpu/drm/i915/display/intel_pfit.h
···
6
6
#ifndef __INTEL_PFIT_H__
7
7
#define __INTEL_PFIT_H__
8
8
9
+
enum drm_mode_status;
10
+
struct drm_display_mode;
9
11
struct drm_connector_state;
10
12
struct intel_crtc_state;
13
+
struct intel_display;
14
+
enum intel_output_format;
11
15
12
16
int intel_pfit_compute_config(struct intel_crtc_state *crtc_state,
13
17
const struct drm_connector_state *conn_state);
···
21
17
void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state);
22
18
void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state);
23
19
void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state);
24
-
20
+
enum drm_mode_status
21
+
intel_pfit_mode_valid(struct intel_display *display,
22
+
const struct drm_display_mode *mode,
23
+
enum intel_output_format output_format,
24
+
int num_joined_pipes);
25
25
#endif /* __INTEL_PFIT_H__ */
-6
drivers/gpu/drm/i915/display/intel_plane.c
-6
drivers/gpu/drm/i915/display/intel_plane.c
···
46
46
47
47
#include "gem/i915_gem_object.h"
48
48
#include "i915_scheduler_types.h"
49
-
#include "i915_vma.h"
50
49
#include "i9xx_plane_regs.h"
51
50
#include "intel_bo.h"
52
51
#include "intel_cdclk.h"
···
1747
1748
}
1748
1749
1749
1750
return 0;
1750
-
}
1751
-
1752
-
u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
1753
-
{
1754
-
return i915_ggtt_offset(plane_state->ggtt_vma);
1755
1751
}
-1
drivers/gpu/drm/i915/display/intel_plane.h
-1
drivers/gpu/drm/i915/display/intel_plane.h
···
87
87
struct intel_crtc *crtc);
88
88
int intel_plane_atomic_check(struct intel_atomic_state *state);
89
89
90
-
u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state);
91
90
bool intel_plane_format_mod_supported_async(struct drm_plane *plane,
92
91
u32 format,
93
92
u64 modifier);
+2
drivers/gpu/drm/i915/display/intel_plane_initial.c
+2
drivers/gpu/drm/i915/display/intel_plane_initial.c
···
360
360
i915_vma_pin_fence(vma) == 0 && vma->fence)
361
361
plane_state->flags |= PLANE_HAS_FENCE;
362
362
363
+
plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma);
364
+
363
365
plane_state->uapi.src_x = 0;
364
366
plane_state->uapi.src_y = 0;
365
367
plane_state->uapi.src_w = fb->width << 16;
+9
-1
drivers/gpu/drm/i915/display/intel_pps.c
+9
-1
drivers/gpu/drm/i915/display/intel_pps.c
···
4
4
*/
5
5
6
6
#include <linux/debugfs.h>
7
+
#include <linux/iopoll.h>
7
8
8
9
#include <drm/drm_print.h>
9
10
···
609
608
struct intel_display *display = to_intel_display(intel_dp);
610
609
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
611
610
i915_reg_t pp_stat_reg, pp_ctrl_reg;
611
+
int ret;
612
+
u32 val;
612
613
613
614
lockdep_assert_held(&display->pps.mutex);
614
615
···
627
624
intel_de_read(display, pp_stat_reg),
628
625
intel_de_read(display, pp_ctrl_reg));
629
626
630
-
if (intel_de_wait(display, pp_stat_reg, mask, value, 5000))
627
+
ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),
628
+
(val & mask) == value,
629
+
10 * 1000, 5000 * 1000, true);
630
+
if (ret) {
631
631
drm_err(display->drm,
632
632
"[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
633
633
dig_port->base.base.base.id, dig_port->base.base.name,
634
634
pps_name(intel_dp),
635
635
intel_de_read(display, pp_stat_reg),
636
636
intel_de_read(display, pp_ctrl_reg));
637
+
return;
638
+
}
637
639
638
640
drm_dbg_kms(display->drm, "Wait complete\n");
639
641
}
+55
-54
drivers/gpu/drm/i915/display/intel_psr.c
+55
-54
drivers/gpu/drm/i915/display/intel_psr.c
···
233
233
234
234
static bool psr_global_enabled(struct intel_dp *intel_dp)
235
235
{
236
-
struct intel_display *display = to_intel_display(intel_dp);
237
236
struct intel_connector *connector = intel_dp->attached_connector;
238
237
239
238
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
240
239
case I915_PSR_DEBUG_DEFAULT:
241
-
if (display->params.enable_psr == -1)
242
-
return intel_dp_is_edp(intel_dp) ?
243
-
connector->panel.vbt.psr.enable :
244
-
true;
245
-
return display->params.enable_psr;
240
+
return intel_dp_is_edp(intel_dp) ?
241
+
connector->panel.vbt.psr.enable : true;
246
242
case I915_PSR_DEBUG_DISABLE:
247
243
return false;
248
244
default:
···
246
250
}
247
251
}
248
252
249
-
static bool psr2_global_enabled(struct intel_dp *intel_dp)
253
+
static bool sel_update_global_enabled(struct intel_dp *intel_dp)
250
254
{
251
-
struct intel_display *display = to_intel_display(intel_dp);
252
-
253
255
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
254
256
case I915_PSR_DEBUG_DISABLE:
255
257
case I915_PSR_DEBUG_FORCE_PSR1:
256
258
return false;
257
259
default:
258
-
if (display->params.enable_psr == 1)
259
-
return false;
260
260
return true;
261
261
}
262
-
}
263
-
264
-
static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp)
265
-
{
266
-
struct intel_display *display = to_intel_display(intel_dp);
267
-
268
-
if (display->params.enable_psr != -1)
269
-
return false;
270
-
271
-
return true;
272
262
}
273
263
274
264
static bool panel_replay_global_enabled(struct intel_dp *intel_dp)
275
265
{
276
266
struct intel_display *display = to_intel_display(intel_dp);
277
267
278
-
if ((display->params.enable_psr != -1) ||
279
-
(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE))
280
-
return false;
281
-
return true;
268
+
return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&
269
+
display->params.enable_panel_replay;
282
270
}
283
271
284
272
static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
···
580
600
static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
581
601
{
582
602
struct intel_display *display = to_intel_display(intel_dp);
603
+
int ret;
604
+
605
+
ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
606
+
&intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
607
+
if (ret < 0)
608
+
return;
609
+
610
+
if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
611
+
DP_PANEL_REPLAY_SUPPORT))
612
+
return;
583
613
584
614
if (intel_dp_is_edp(intel_dp)) {
585
615
if (!intel_alpm_aux_less_wake_supported(intel_dp)) {
···
621
631
static void _psr_init_dpcd(struct intel_dp *intel_dp)
622
632
{
623
633
struct intel_display *display = to_intel_display(intel_dp);
634
+
int ret;
635
+
636
+
ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
637
+
sizeof(intel_dp->psr_dpcd));
638
+
if (ret < 0)
639
+
return;
640
+
641
+
if (!intel_dp->psr_dpcd[0])
642
+
return;
624
643
625
644
drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
626
645
intel_dp->psr_dpcd[0]);
···
675
676
676
677
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
677
678
{
678
-
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
679
-
sizeof(intel_dp->psr_dpcd));
679
+
_psr_init_dpcd(intel_dp);
680
680
681
-
drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
682
-
&intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
683
-
684
-
if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
685
-
DP_PANEL_REPLAY_SUPPORT)
686
-
_panel_replay_init_dpcd(intel_dp);
687
-
688
-
if (intel_dp->psr_dpcd[0])
689
-
_psr_init_dpcd(intel_dp);
681
+
_panel_replay_init_dpcd(intel_dp);
690
682
691
683
if (intel_dp->psr.sink_psr2_support ||
692
684
intel_dp->psr.sink_panel_replay_su_support)
···
732
742
return panel_replay ?
733
743
intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
734
744
DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
735
-
intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
736
-
psr2_su_region_et_global_enabled(intel_dp);
745
+
intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
737
746
}
738
747
739
748
static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
···
925
936
/* Wa_16025596647 */
926
937
if ((DISPLAY_VER(display) == 20 ||
927
938
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
928
-
is_dc5_dc6_blocked(intel_dp))
939
+
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
929
940
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
930
941
intel_dp->psr.pipe,
931
942
true);
···
1015
1026
/* Wa_16025596647 */
1016
1027
if ((DISPLAY_VER(display) == 20 ||
1017
1028
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
1018
-
is_dc5_dc6_blocked(intel_dp))
1029
+
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
1019
1030
idle_frames = 0;
1020
1031
else
1021
1032
idle_frames = psr_compute_idle_frames(intel_dp);
···
1412
1423
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1413
1424
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
1414
1425
1415
-
if (!intel_dp->psr.sink_psr2_support)
1426
+
if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
1416
1427
return false;
1417
1428
1418
1429
/* JSL and EHL only supports eDP 1.3 */
···
1517
1528
goto unsupported;
1518
1529
}
1519
1530
1520
-
if (!psr2_global_enabled(intel_dp)) {
1531
+
if (!sel_update_global_enabled(intel_dp)) {
1521
1532
drm_dbg_kms(display->drm,
1522
1533
"Selective update disabled by flag\n");
1523
1534
goto unsupported;
···
1565
1576
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1566
1577
int entry_setup_frames;
1567
1578
1568
-
if (!CAN_PSR(intel_dp))
1579
+
if (!CAN_PSR(intel_dp) || !display->params.enable_psr)
1569
1580
return false;
1570
1581
1571
1582
/*
···
1797
1808
1798
1809
drm_WARN_ON(display->drm, intel_dp->psr.active);
1799
1810
1811
+
drm_WARN_ON(display->drm, !intel_dp->psr.enabled);
1812
+
1800
1813
lockdep_assert_held(&intel_dp->psr.lock);
1801
1814
1802
1815
/* psr1, psr2 and panel-replay are mutually exclusive.*/
···
2018
2027
intel_dp->psr.req_psr2_sdp_prior_scanline =
2019
2028
crtc_state->req_psr2_sdp_prior_scanline;
2020
2029
intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
2030
+
intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
2021
2031
2022
2032
if (!psr_interrupt_error_check(intel_dp))
2023
2033
return;
···
2095
2103
2096
2104
drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));
2097
2105
} else {
2098
-
if (DISPLAY_VER(display) == 20 ||
2099
-
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
2106
+
if ((DISPLAY_VER(display) == 20 ||
2107
+
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
2108
+
intel_dp->psr.pkg_c_latency_used)
2100
2109
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
2101
2110
intel_dp->psr.pipe,
2102
2111
false);
···
2200
2207
intel_dp->psr.su_region_et_enabled = false;
2201
2208
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2202
2209
intel_dp->psr.active_non_psr_pipes = 0;
2210
+
intel_dp->psr.pkg_c_latency_used = 0;
2203
2211
}
2204
2212
2205
2213
/**
···
3093
3099
3094
3100
/* After the unlocked wait, verify that PSR is still wanted! */
3095
3101
mutex_lock(&intel_dp->psr.lock);
3096
-
return err == 0 && intel_dp->psr.enabled;
3102
+
return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;
3097
3103
}
3098
3104
3099
3105
static int intel_psr_fastset_force(struct intel_display *display)
···
3222
3228
if (!intel_dp->psr.enabled)
3223
3229
goto unlock;
3224
3230
3225
-
if (READ_ONCE(intel_dp->psr.irq_aux_error))
3231
+
if (READ_ONCE(intel_dp->psr.irq_aux_error)) {
3226
3232
intel_psr_handle_irq(intel_dp);
3233
+
goto unlock;
3234
+
}
3235
+
3236
+
if (intel_dp->psr.pause_counter)
3237
+
goto unlock;
3227
3238
3228
3239
/*
3229
3240
* We have to make sure PSR is ready for re-enable
···
3722
3723
struct intel_display *display = to_intel_display(intel_dp);
3723
3724
bool dc5_dc6_blocked;
3724
3725
3725
-
if (!intel_dp->psr.active)
3726
+
if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)
3726
3727
return;
3727
3728
3728
3729
dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);
···
3747
3748
3748
3749
mutex_lock(&intel_dp->psr.lock);
3749
3750
3750
-
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled)
3751
+
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&
3752
+
!intel_dp->psr.pkg_c_latency_used)
3751
3753
intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
3752
3754
3753
3755
mutex_unlock(&intel_dp->psr.lock);
···
3826
3826
goto unlock;
3827
3827
3828
3828
if ((enable && intel_dp->psr.active_non_psr_pipes) ||
3829
-
(!enable && !intel_dp->psr.active_non_psr_pipes)) {
3829
+
(!enable && !intel_dp->psr.active_non_psr_pipes) ||
3830
+
!intel_dp->psr.pkg_c_latency_used) {
3830
3831
intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
3831
3832
goto unlock;
3832
3833
}
···
3862
3861
break;
3863
3862
}
3864
3863
3865
-
if (intel_dp->psr.enabled)
3864
+
if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used)
3866
3865
intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
3867
3866
3868
3867
mutex_unlock(&intel_dp->psr.lock);
···
4158
4157
4159
4158
void intel_psr_debugfs_register(struct intel_display *display)
4160
4159
{
4161
-
struct drm_minor *minor = display->drm->primary;
4160
+
struct dentry *debugfs_root = display->drm->debugfs_root;
4162
4161
4163
-
debugfs_create_file("i915_edp_psr_debug", 0644, minor->debugfs_root,
4162
+
debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root,
4164
4163
display, &i915_edp_psr_debug_fops);
4165
4164
4166
-
debugfs_create_file("i915_edp_psr_status", 0444, minor->debugfs_root,
4165
+
debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root,
4167
4166
display, &i915_edp_psr_status_fops);
4168
4167
}
4169
4168
+9
drivers/gpu/drm/i915/display/intel_quirks.c
+9
drivers/gpu/drm/i915/display/intel_quirks.c
···
80
80
drm_info(display->drm, "Applying Fast Wake sync pulse count quirk\n");
81
81
}
82
82
83
+
static void quirk_edp_limit_rate_hbr2(struct intel_display *display)
84
+
{
85
+
intel_set_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2);
86
+
drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");
87
+
}
88
+
83
89
struct intel_quirk {
84
90
int device;
85
91
int subsystem_vendor;
···
237
231
{ 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
238
232
/* HP Notebook - 14-r206nv */
239
233
{ 0x0f31, 0x103c, 0x220f, quirk_invert_brightness },
234
+
235
+
/* Dell XPS 13 7390 2-in-1 */
236
+
{ 0x8a12, 0x1028, 0x08b0, quirk_edp_limit_rate_hbr2 },
240
237
};
241
238
242
239
static const struct intel_dpcd_quirk intel_dpcd_quirks[] = {
+1
drivers/gpu/drm/i915/display/intel_quirks.h
+1
drivers/gpu/drm/i915/display/intel_quirks.h
+6
-4
drivers/gpu/drm/i915/display/intel_sdvo.c
+6
-4
drivers/gpu/drm/i915/display/intel_sdvo.c
···
47
47
#include "intel_display_driver.h"
48
48
#include "intel_display_regs.h"
49
49
#include "intel_display_types.h"
50
-
#include "intel_fdi.h"
51
50
#include "intel_fifo_underrun.h"
52
51
#include "intel_gmbus.h"
53
52
#include "intel_hdmi.h"
54
53
#include "intel_hotplug.h"
54
+
#include "intel_link_bw.h"
55
55
#include "intel_panel.h"
56
56
#include "intel_sdvo.h"
57
57
#include "intel_sdvo_regs.h"
···
1367
1367
1368
1368
if (HAS_PCH_SPLIT(display)) {
1369
1369
pipe_config->has_pch_encoder = true;
1370
-
if (!intel_fdi_compute_pipe_bpp(pipe_config))
1370
+
if (!intel_link_bw_compute_pipe_bpp(pipe_config))
1371
1371
return -EINVAL;
1372
1372
}
1373
1373
···
2052
2052
{
2053
2053
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2054
2054
2055
-
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
2056
-
&intel_sdvo->hotplug_active, 2);
2055
+
if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
2056
+
&intel_sdvo->hotplug_active, 2))
2057
+
drm_warn(intel_sdvo->base.base.dev,
2058
+
"Failed to enable hotplug on SDVO encoder\n");
2057
2059
}
2058
2060
2059
2061
static enum intel_hotplug_state
+21
-30
drivers/gpu/drm/i915/display/intel_sprite.c
+21
-30
drivers/gpu/drm/i915/display/intel_sprite.c
···
264
264
return sprctl;
265
265
}
266
266
267
-
static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
268
-
const struct intel_plane_state *plane_state)
267
+
static u32 vlv_sprite_ctl(const struct intel_plane_state *plane_state)
269
268
{
270
269
const struct drm_framebuffer *fb = plane_state->hw.fb;
271
270
unsigned int rotation = plane_state->hw.rotation;
···
394
395
enum pipe pipe = plane->pipe;
395
396
enum plane_id plane_id = plane->id;
396
397
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
397
-
u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
398
398
u32 x = plane_state->view.color_plane[0].x;
399
399
u32 y = plane_state->view.color_plane[0].y;
400
-
u32 sprctl, linear_offset;
400
+
u32 sprctl;
401
401
402
402
sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
403
-
404
-
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
405
403
406
404
if (display->platform.cherryview && pipe == PIPE_B)
407
405
chv_sprite_update_csc(plane_state);
···
414
418
415
419
intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);
416
420
417
-
intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset);
421
+
intel_de_write_fw(display, SPLINOFF(pipe, plane_id),
422
+
intel_fb_xy_to_linear(x, y, plane_state, 0));
418
423
intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),
419
424
SP_OFFSET_Y(y) | SP_OFFSET_X(x));
420
425
···
425
428
* the control register just before the surface register.
426
429
*/
427
430
intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);
428
-
intel_de_write_fw(display, SPSURF(pipe, plane_id),
429
-
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
431
+
intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf);
430
432
431
433
vlv_sprite_update_clrc(plane_state);
432
434
vlv_sprite_update_gamma(plane_state);
···
659
663
(display->platform.ivybridge || display->platform.haswell);
660
664
}
661
665
662
-
static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
663
-
const struct intel_plane_state *plane_state)
666
+
static u32 ivb_sprite_ctl(const struct intel_plane_state *plane_state)
664
667
{
665
668
struct intel_display *display = to_intel_display(plane_state);
666
669
const struct drm_framebuffer *fb = plane_state->hw.fb;
···
825
830
struct intel_display *display = to_intel_display(plane);
826
831
enum pipe pipe = plane->pipe;
827
832
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
828
-
u32 sprsurf_offset = plane_state->view.color_plane[0].offset;
829
833
u32 x = plane_state->view.color_plane[0].x;
830
834
u32 y = plane_state->view.color_plane[0].y;
831
-
u32 sprctl, linear_offset;
835
+
u32 sprctl;
832
836
833
837
sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
834
-
835
-
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
836
838
837
839
if (key->flags) {
838
840
intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);
···
844
852
intel_de_write_fw(display, SPROFFSET(pipe),
845
853
SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
846
854
} else {
847
-
intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset);
855
+
intel_de_write_fw(display, SPRLINOFF(pipe),
856
+
intel_fb_xy_to_linear(x, y, plane_state, 0));
848
857
intel_de_write_fw(display, SPRTILEOFF(pipe),
849
858
SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
850
859
}
···
856
863
* the control register just before the surface register.
857
864
*/
858
865
intel_de_write_fw(display, SPRCTL(pipe), sprctl);
859
-
intel_de_write_fw(display, SPRSURF(pipe),
860
-
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
866
+
intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf);
861
867
862
868
ivb_sprite_update_gamma(plane_state);
863
869
}
···
1008
1016
return dvscntr;
1009
1017
}
1010
1018
1011
-
static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1012
-
const struct intel_plane_state *plane_state)
1019
+
static u32 g4x_sprite_ctl(const struct intel_plane_state *plane_state)
1013
1020
{
1014
1021
struct intel_display *display = to_intel_display(plane_state);
1015
1022
const struct drm_framebuffer *fb = plane_state->hw.fb;
···
1172
1181
struct intel_display *display = to_intel_display(plane);
1173
1182
enum pipe pipe = plane->pipe;
1174
1183
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1175
-
u32 dvssurf_offset = plane_state->view.color_plane[0].offset;
1176
1184
u32 x = plane_state->view.color_plane[0].x;
1177
1185
u32 y = plane_state->view.color_plane[0].y;
1178
-
u32 dvscntr, linear_offset;
1186
+
u32 dvscntr;
1179
1187
1180
1188
dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
1181
-
1182
-
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1183
1189
1184
1190
if (key->flags) {
1185
1191
intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);
···
1185
1197
intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);
1186
1198
}
1187
1199
1188
-
intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset);
1200
+
intel_de_write_fw(display, DVSLINOFF(pipe),
1201
+
intel_fb_xy_to_linear(x, y, plane_state, 0));
1189
1202
intel_de_write_fw(display, DVSTILEOFF(pipe),
1190
1203
DVS_OFFSET_Y(y) | DVS_OFFSET_X(x));
1191
1204
···
1196
1207
* the control register just before the surface register.
1197
1208
*/
1198
1209
intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);
1199
-
intel_de_write_fw(display, DVSSURF(pipe),
1200
-
intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1210
+
intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf);
1201
1211
1202
1212
if (display->platform.g4x)
1203
1213
g4x_sprite_update_gamma(plane_state);
···
1375
1387
return ret;
1376
1388
1377
1389
if (DISPLAY_VER(display) >= 7)
1378
-
plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1390
+
plane_state->ctl = ivb_sprite_ctl(plane_state);
1379
1391
else
1380
-
plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1392
+
plane_state->ctl = g4x_sprite_ctl(plane_state);
1381
1393
1382
1394
return 0;
1383
1395
}
···
1427
1439
if (ret)
1428
1440
return ret;
1429
1441
1430
-
plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1442
+
plane_state->ctl = vlv_sprite_ctl(plane_state);
1431
1443
1432
1444
return 0;
1433
1445
}
···
1612
1624
plane->capture_error = vlv_sprite_capture_error;
1613
1625
plane->get_hw_state = vlv_sprite_get_hw_state;
1614
1626
plane->check_plane = vlv_sprite_check;
1627
+
plane->surf_offset = i965_plane_surf_offset;
1615
1628
plane->max_stride = i965_plane_max_stride;
1616
1629
plane->min_alignment = vlv_plane_min_alignment;
1617
1630
plane->min_cdclk = vlv_plane_min_cdclk;
···
1637
1648
plane->capture_error = ivb_sprite_capture_error;
1638
1649
plane->get_hw_state = ivb_sprite_get_hw_state;
1639
1650
plane->check_plane = g4x_sprite_check;
1651
+
plane->surf_offset = i965_plane_surf_offset;
1640
1652
1641
1653
if (display->platform.broadwell || display->platform.haswell) {
1642
1654
plane->max_stride = hsw_sprite_max_stride;
···
1663
1673
plane->capture_error = g4x_sprite_capture_error;
1664
1674
plane->get_hw_state = g4x_sprite_get_hw_state;
1665
1675
plane->check_plane = g4x_sprite_check;
1676
+
plane->surf_offset = i965_plane_surf_offset;
1666
1677
plane->max_stride = g4x_sprite_max_stride;
1667
1678
plane->min_alignment = g4x_sprite_min_alignment;
1668
1679
plane->min_cdclk = g4x_sprite_min_cdclk;
+172
-86
drivers/gpu/drm/i915/display/intel_tc.c
+172
-86
drivers/gpu/drm/i915/display/intel_tc.c
···
3
3
* Copyright © 2019 Intel Corporation
4
4
*/
5
5
6
+
#include <linux/iopoll.h>
7
+
6
8
#include <drm/drm_print.h>
7
9
8
10
#include "i915_reg.h"
···
24
22
#include "intel_mg_phy_regs.h"
25
23
#include "intel_modeset_lock.h"
26
24
#include "intel_tc.h"
27
-
28
-
#define DP_PIN_ASSIGNMENT_C 0x3
29
-
#define DP_PIN_ASSIGNMENT_D 0x4
30
-
#define DP_PIN_ASSIGNMENT_E 0x5
31
25
32
26
enum tc_port_mode {
33
27
TC_PORT_DISCONNECTED,
···
63
65
enum tc_port_mode mode;
64
66
enum tc_port_mode init_mode;
65
67
enum phy_fia phy_fia;
68
+
enum intel_tc_pin_assignment pin_assignment;
66
69
u8 phy_fia_idx;
70
+
u8 max_lane_count;
67
71
};
68
72
69
73
static enum intel_display_power_domain
···
251
251
{
252
252
enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
253
253
254
+
if (tc_port == TC_PORT_NONE)
255
+
return POWER_DOMAIN_INVALID;
256
+
254
257
return POWER_DOMAIN_PORT_DDI_LANES_TC1 + tc_port - TC_PORT_1;
255
258
}
256
259
···
266
263
!intel_display_power_is_enabled(display, tc_port_power_domain(tc)));
267
264
}
268
265
269
-
static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
266
+
static u32 get_lane_mask(struct intel_tc_port *tc)
270
267
{
271
-
struct intel_display *display = to_intel_display(dig_port);
272
-
struct intel_tc_port *tc = to_tc_port(dig_port);
268
+
struct intel_display *display = to_intel_display(tc->dig_port);
269
+
intel_wakeref_t wakeref;
273
270
u32 lane_mask;
274
271
275
-
lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));
272
+
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
273
+
lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));
276
274
277
275
drm_WARN_ON(display->drm, lane_mask == 0xffffffff);
278
276
assert_tc_cold_blocked(tc);
···
282
278
return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
283
279
}
284
280
285
-
u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
281
+
static char pin_assignment_name(enum intel_tc_pin_assignment pin_assignment)
286
282
{
287
-
struct intel_display *display = to_intel_display(dig_port);
288
-
struct intel_tc_port *tc = to_tc_port(dig_port);
289
-
u32 pin_mask;
283
+
if (pin_assignment == INTEL_TC_PIN_ASSIGNMENT_NONE)
284
+
return '-';
290
285
291
-
pin_mask = intel_de_read(display, PORT_TX_DFLEXPA1(tc->phy_fia));
292
-
293
-
drm_WARN_ON(display->drm, pin_mask == 0xffffffff);
294
-
assert_tc_cold_blocked(tc);
295
-
296
-
return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx)) >>
297
-
DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
286
+
return 'A' + pin_assignment - INTEL_TC_PIN_ASSIGNMENT_A;
298
287
}
299
288
300
-
static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
289
+
static enum intel_tc_pin_assignment
290
+
get_pin_assignment(struct intel_tc_port *tc)
301
291
{
302
-
struct intel_display *display = to_intel_display(dig_port);
303
-
enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
292
+
struct intel_display *display = to_intel_display(tc->dig_port);
293
+
enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
294
+
enum intel_tc_pin_assignment pin_assignment;
304
295
intel_wakeref_t wakeref;
305
-
u32 val, pin_assignment;
296
+
i915_reg_t reg;
297
+
u32 mask;
298
+
u32 val;
299
+
300
+
if (tc->mode == TC_PORT_TBT_ALT)
301
+
return INTEL_TC_PIN_ASSIGNMENT_NONE;
302
+
303
+
if (DISPLAY_VER(display) >= 20) {
304
+
reg = TCSS_DDI_STATUS(tc_port);
305
+
mask = TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK;
306
+
} else {
307
+
reg = PORT_TX_DFLEXPA1(tc->phy_fia);
308
+
mask = DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx);
309
+
}
306
310
307
311
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
308
-
val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));
312
+
val = intel_de_read(display, reg);
309
313
310
-
pin_assignment =
311
-
REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
314
+
drm_WARN_ON(display->drm, val == 0xffffffff);
315
+
assert_tc_cold_blocked(tc);
316
+
317
+
pin_assignment = (val & mask) >> (ffs(mask) - 1);
312
318
313
319
switch (pin_assignment) {
320
+
case INTEL_TC_PIN_ASSIGNMENT_A:
321
+
case INTEL_TC_PIN_ASSIGNMENT_B:
322
+
case INTEL_TC_PIN_ASSIGNMENT_F:
323
+
drm_WARN_ON(display->drm, DISPLAY_VER(display) > 11);
324
+
break;
325
+
case INTEL_TC_PIN_ASSIGNMENT_NONE:
326
+
case INTEL_TC_PIN_ASSIGNMENT_C:
327
+
case INTEL_TC_PIN_ASSIGNMENT_D:
328
+
case INTEL_TC_PIN_ASSIGNMENT_E:
329
+
break;
330
+
default:
331
+
MISSING_CASE(pin_assignment);
332
+
}
333
+
334
+
return pin_assignment;
335
+
}
336
+
337
+
static int mtl_get_max_lane_count(struct intel_tc_port *tc)
338
+
{
339
+
enum intel_tc_pin_assignment pin_assignment;
340
+
341
+
pin_assignment = get_pin_assignment(tc);
342
+
343
+
switch (pin_assignment) {
344
+
case INTEL_TC_PIN_ASSIGNMENT_NONE:
345
+
return 0;
314
346
default:
315
347
MISSING_CASE(pin_assignment);
316
348
fallthrough;
317
-
case DP_PIN_ASSIGNMENT_D:
349
+
case INTEL_TC_PIN_ASSIGNMENT_D:
318
350
return 2;
319
-
case DP_PIN_ASSIGNMENT_C:
320
-
case DP_PIN_ASSIGNMENT_E:
351
+
case INTEL_TC_PIN_ASSIGNMENT_C:
352
+
case INTEL_TC_PIN_ASSIGNMENT_E:
321
353
return 4;
322
354
}
323
355
}
324
356
325
-
static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
357
+
static int icl_get_max_lane_count(struct intel_tc_port *tc)
326
358
{
327
-
struct intel_display *display = to_intel_display(dig_port);
328
-
intel_wakeref_t wakeref;
329
-
u32 pin_mask;
330
-
331
-
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
332
-
pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
333
-
334
-
switch (pin_mask) {
335
-
default:
336
-
MISSING_CASE(pin_mask);
337
-
fallthrough;
338
-
case DP_PIN_ASSIGNMENT_D:
339
-
return 2;
340
-
case DP_PIN_ASSIGNMENT_C:
341
-
case DP_PIN_ASSIGNMENT_E:
342
-
return 4;
343
-
}
344
-
}
345
-
346
-
static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
347
-
{
348
-
struct intel_display *display = to_intel_display(dig_port);
349
-
intel_wakeref_t wakeref;
350
359
u32 lane_mask = 0;
351
360
352
-
with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
353
-
lane_mask = intel_tc_port_get_lane_mask(dig_port);
361
+
lane_mask = get_lane_mask(tc);
354
362
355
363
switch (lane_mask) {
356
364
default:
···
381
365
}
382
366
}
383
367
384
-
int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
368
+
static int get_max_lane_count(struct intel_tc_port *tc)
385
369
{
386
-
struct intel_display *display = to_intel_display(dig_port);
387
-
struct intel_tc_port *tc = to_tc_port(dig_port);
370
+
struct intel_display *display = to_intel_display(tc->dig_port);
388
371
389
-
if (!intel_encoder_is_tc(&dig_port->base) || tc->mode != TC_PORT_DP_ALT)
372
+
if (tc->mode != TC_PORT_DP_ALT)
390
373
return 4;
391
374
392
-
assert_tc_cold_blocked(tc);
393
-
394
-
if (DISPLAY_VER(display) >= 20)
395
-
return lnl_tc_port_get_max_lane_count(dig_port);
396
-
397
375
if (DISPLAY_VER(display) >= 14)
398
-
return mtl_tc_port_get_max_lane_count(dig_port);
376
+
return mtl_get_max_lane_count(tc);
399
377
400
-
return intel_tc_port_get_max_lane_count(dig_port);
378
+
return icl_get_max_lane_count(tc);
379
+
}
380
+
381
+
static void read_pin_configuration(struct intel_tc_port *tc)
382
+
{
383
+
tc->pin_assignment = get_pin_assignment(tc);
384
+
tc->max_lane_count = get_max_lane_count(tc);
385
+
}
386
+
387
+
int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
388
+
{
389
+
struct intel_tc_port *tc = to_tc_port(dig_port);
390
+
391
+
if (!intel_encoder_is_tc(&dig_port->base))
392
+
return 4;
393
+
394
+
return tc->max_lane_count;
395
+
}
396
+
397
+
enum intel_tc_pin_assignment
398
+
intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port)
399
+
{
400
+
struct intel_tc_port *tc = to_tc_port(dig_port);
401
+
402
+
if (!intel_encoder_is_tc(&dig_port->base))
403
+
return INTEL_TC_PIN_ASSIGNMENT_NONE;
404
+
405
+
return tc->pin_assignment;
401
406
}
402
407
403
408
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
···
633
596
tc_cold_wref = __tc_cold_block(tc, &domain);
634
597
635
598
tc->mode = tc_phy_get_current_mode(tc);
636
-
if (tc->mode != TC_PORT_DISCONNECTED)
599
+
if (tc->mode != TC_PORT_DISCONNECTED) {
637
600
tc->lock_wakeref = tc_cold_block(tc);
601
+
602
+
read_pin_configuration(tc);
603
+
}
638
604
639
605
__tc_cold_unblock(tc, domain, tc_cold_wref);
640
606
}
···
696
656
697
657
tc->lock_wakeref = tc_cold_block(tc);
698
658
699
-
if (tc->mode == TC_PORT_TBT_ALT)
659
+
if (tc->mode == TC_PORT_TBT_ALT) {
660
+
read_pin_configuration(tc);
661
+
700
662
return true;
663
+
}
701
664
702
665
if ((!tc_phy_is_ready(tc) ||
703
666
!icl_tc_phy_take_ownership(tc, true)) &&
···
711
668
goto out_unblock_tc_cold;
712
669
}
713
670
671
+
read_pin_configuration(tc);
714
672
715
673
if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
716
674
goto out_release_phy;
···
902
858
port_wakeref = intel_display_power_get(display, port_power_domain);
903
859
904
860
tc->mode = tc_phy_get_current_mode(tc);
905
-
if (tc->mode != TC_PORT_DISCONNECTED)
861
+
if (tc->mode != TC_PORT_DISCONNECTED) {
906
862
tc->lock_wakeref = tc_cold_block(tc);
863
+
864
+
read_pin_configuration(tc);
865
+
}
907
866
908
867
intel_display_power_put(display, port_power_domain, port_wakeref);
909
868
}
···
920
873
921
874
if (tc->mode == TC_PORT_TBT_ALT) {
922
875
tc->lock_wakeref = tc_cold_block(tc);
876
+
877
+
read_pin_configuration(tc);
878
+
923
879
return true;
924
880
}
925
881
···
943
893
}
944
894
945
895
tc->lock_wakeref = tc_cold_block(tc);
896
+
897
+
read_pin_configuration(tc);
946
898
947
899
if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
948
900
goto out_unblock_tc_cold;
···
1052
1000
xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled)
1053
1001
{
1054
1002
struct intel_display *display = to_intel_display(tc->dig_port);
1003
+
bool is_enabled;
1004
+
int ret;
1055
1005
1056
-
if (wait_for(xelpdp_tc_phy_tcss_power_is_enabled(tc) == enabled, 5)) {
1006
+
ret = poll_timeout_us(is_enabled = xelpdp_tc_phy_tcss_power_is_enabled(tc),
1007
+
is_enabled == enabled,
1008
+
200, 5000, false);
1009
+
if (ret) {
1057
1010
drm_dbg_kms(display->drm,
1058
1011
"Port %s: timeout waiting for TCSS power to get %s\n",
1059
1012
str_enabled_disabled(enabled),
···
1181
1124
tc_cold_wref = __tc_cold_block(tc, &domain);
1182
1125
1183
1126
tc->mode = tc_phy_get_current_mode(tc);
1184
-
if (tc->mode != TC_PORT_DISCONNECTED)
1127
+
if (tc->mode != TC_PORT_DISCONNECTED) {
1185
1128
tc->lock_wakeref = tc_cold_block(tc);
1129
+
1130
+
read_pin_configuration(tc);
1131
+
/*
1132
+
* Set a valid lane count value for a DP-alt sink which got
1133
+
* disconnected. The driver can only disable the output on this PHY.
1134
+
*/
1135
+
if (tc->max_lane_count == 0)
1136
+
tc->max_lane_count = 4;
1137
+
}
1186
1138
1187
1139
drm_WARN_ON(display->drm,
1188
1140
(tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) &&
···
1204
1138
{
1205
1139
tc->lock_wakeref = tc_cold_block(tc);
1206
1140
1207
-
if (tc->mode == TC_PORT_TBT_ALT)
1141
+
if (tc->mode == TC_PORT_TBT_ALT) {
1142
+
read_pin_configuration(tc);
1143
+
1208
1144
return true;
1145
+
}
1209
1146
1210
1147
if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
1211
1148
goto out_unblock_tccold;
1212
1149
1213
1150
xelpdp_tc_phy_take_ownership(tc, true);
1151
+
1152
+
read_pin_configuration(tc);
1214
1153
1215
1154
if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
1216
1155
goto out_release_phy;
···
1297
1226
tc->phy_ops->get_hw_state(tc);
1298
1227
}
1299
1228
1300
-
static bool tc_phy_is_ready_and_owned(struct intel_tc_port *tc,
1301
-
bool phy_is_ready, bool phy_is_owned)
1229
+
/* Is the PHY owned by display i.e. is it in legacy or DP-alt mode? */
1230
+
static bool tc_phy_owned_by_display(struct intel_tc_port *tc,
1231
+
bool phy_is_ready, bool phy_is_owned)
1302
1232
{
1303
1233
struct intel_display *display = to_intel_display(tc->dig_port);
1304
1234
1305
-
drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);
1235
+
if (DISPLAY_VER(display) < 20) {
1236
+
drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);
1306
1237
1307
-
return phy_is_ready && phy_is_owned;
1238
+
return phy_is_ready && phy_is_owned;
1239
+
} else {
1240
+
return phy_is_owned;
1241
+
}
1308
1242
}
1309
1243
1310
1244
static bool tc_phy_is_connected(struct intel_tc_port *tc,
···
1320
1244
bool phy_is_owned = tc_phy_is_owned(tc);
1321
1245
bool is_connected;
1322
1246
1323
-
if (tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned))
1247
+
if (tc_phy_owned_by_display(tc, phy_is_ready, phy_is_owned))
1324
1248
is_connected = port_pll_type == ICL_PORT_DPLL_MG_PHY;
1325
1249
else
1326
1250
is_connected = port_pll_type == ICL_PORT_DPLL_DEFAULT;
···
1339
1263
static bool tc_phy_wait_for_ready(struct intel_tc_port *tc)
1340
1264
{
1341
1265
struct intel_display *display = to_intel_display(tc->dig_port);
1266
+
bool is_ready;
1267
+
int ret;
1342
1268
1343
-
if (wait_for(tc_phy_is_ready(tc), 500)) {
1269
+
ret = poll_timeout_us(is_ready = tc_phy_is_ready(tc),
1270
+
is_ready,
1271
+
1000, 500 * 1000, false);
1272
+
if (ret) {
1344
1273
drm_err(display->drm, "Port %s: timeout waiting for PHY ready\n",
1345
1274
tc->port_name);
1346
1275
···
1433
1352
phy_is_ready = tc_phy_is_ready(tc);
1434
1353
phy_is_owned = tc_phy_is_owned(tc);
1435
1354
1436
-
if (!tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned)) {
1355
+
if (!tc_phy_owned_by_display(tc, phy_is_ready, phy_is_owned)) {
1437
1356
mode = get_tc_mode_in_phy_not_owned_state(tc, live_mode);
1438
1357
} else {
1439
1358
drm_WARN_ON(display->drm, live_mode == TC_PORT_TBT_ALT);
···
1522
1441
intel_display_power_flush_work(display);
1523
1442
if (!intel_tc_cold_requires_aux_pw(dig_port)) {
1524
1443
enum intel_display_power_domain aux_domain;
1525
-
bool aux_powered;
1526
1444
1527
1445
aux_domain = intel_aux_power_domain(dig_port);
1528
-
aux_powered = intel_display_power_is_enabled(display, aux_domain);
1529
-
drm_WARN_ON(display->drm, aux_powered);
1446
+
if (intel_display_power_is_enabled(display, aux_domain))
1447
+
drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n",
1448
+
tc->port_name);
1530
1449
}
1531
1450
1532
1451
tc_phy_disconnect(tc);
1533
1452
if (!force_disconnect)
1534
1453
tc_phy_connect(tc, required_lanes);
1535
1454
1536
-
drm_dbg_kms(display->drm, "Port %s: TC port mode reset (%s -> %s)\n",
1455
+
drm_dbg_kms(display->drm,
1456
+
"Port %s: TC port mode reset (%s -> %s) pin assignment: %c max lanes: %d\n",
1537
1457
tc->port_name,
1538
1458
tc_port_mode_name(old_tc_mode),
1539
-
tc_port_mode_name(tc->mode));
1459
+
tc_port_mode_name(tc->mode),
1460
+
pin_assignment_name(tc->pin_assignment),
1461
+
tc->max_lane_count);
1540
1462
}
1541
1463
1542
1464
static bool intel_tc_port_needs_reset(struct intel_tc_port *tc)
···
1694
1610
__intel_tc_port_put_link(tc);
1695
1611
}
1696
1612
1697
-
drm_dbg_kms(display->drm, "Port %s: sanitize mode (%s)\n",
1613
+
drm_dbg_kms(display->drm, "Port %s: sanitize mode (%s) pin assignment: %c max lanes: %d\n",
1698
1614
tc->port_name,
1699
-
tc_port_mode_name(tc->mode));
1615
+
tc_port_mode_name(tc->mode),
1616
+
pin_assignment_name(tc->pin_assignment),
1617
+
tc->max_lane_count);
1700
1618
1701
1619
mutex_unlock(&tc->lock);
1702
1620
}
+71
-1
drivers/gpu/drm/i915/display/intel_tc.h
+71
-1
drivers/gpu/drm/i915/display/intel_tc.h
···
12
12
struct intel_digital_port;
13
13
struct intel_encoder;
14
14
15
+
/*
16
+
* The following enum values must stay fixed, as they match the corresponding
17
+
* pin assignment fields in the PORT_TX_DFLEXPA1 and TCSS_DDI_STATUS registers.
18
+
*/
19
+
enum intel_tc_pin_assignment { /* Lanes (a) Signal/ Cable Notes */
20
+
/* DP USB Rate (b) type */
21
+
INTEL_TC_PIN_ASSIGNMENT_NONE = 0, /* 4 - - - (c) */
22
+
INTEL_TC_PIN_ASSIGNMENT_A, /* 2/4 0 GEN2 TC->TC (d,e) */
23
+
INTEL_TC_PIN_ASSIGNMENT_B, /* 1/2 1 GEN2 TC->TC (d,f,g) */
24
+
INTEL_TC_PIN_ASSIGNMENT_C, /* 4 0 DP2 TC->TC (h) */
25
+
INTEL_TC_PIN_ASSIGNMENT_D, /* 2 1 DP2 TC->TC (h,g) */
26
+
INTEL_TC_PIN_ASSIGNMENT_E, /* 4 0 DP2 TC->DP */
27
+
INTEL_TC_PIN_ASSIGNMENT_F, /* 2 1 GEN1/DP1 TC->DP (d,g,i) */
28
+
/*
29
+
* (a) - DP unidirectional lanes, each lane using 1 differential signal
30
+
* pair.
31
+
* - USB SuperSpeed bidirectional lane, using 2 differential (TX and
32
+
* RX) signal pairs.
33
+
* - USB 2.0 (HighSpeed) unidirectional lane, using 1 differential
34
+
* signal pair. Not indicated, this lane is always present on pin
35
+
* assignments A-D and never present on pin assignments E/F.
36
+
* (b) - GEN1: USB 3.1 GEN1 bit rate (5 Gbps) and signaling. This
37
+
* is used for transferring only a USB stream.
38
+
* - GEN2: USB 3.1 GEN2 bit rate (10 Gbps) and signaling. This
39
+
* allows transferring an HBR3 (8.1 Gbps) DP stream.
40
+
* - DP1: Display Port signaling defined by the DP v1.3 Standard,
41
+
* with a maximum bit rate of HBR3.
42
+
* - DP2: Display Port signaling defined by the DP v2.1 Standard,
43
+
* with a maximum bit rate defined by the DP Alt Mode
44
+
* v2.1a Standard depending on the cable type as follows:
45
+
* - Passive (Full-Featured) USB 3.2 GEN1
46
+
* TC->TC cables (CC3G1-X) : UHBR10
47
+
* - Passive (Full-Featured) USB 3.2/4 GEN2 and
48
+
* Thunderbolt Alt Mode GEN2
49
+
* TC->TC cables (CC3G2-X) all : UHBR10
50
+
* DP54 logo : UHBR13.5
51
+
* - Passive (Full-Featured) USB4 GEN3+ and
52
+
* Thunderbolt Alt Mode GEN3+
53
+
* TC->TC cables (CC4G3-X) all : UHBR13.5
54
+
* DP80 logo : UHBR20
55
+
* - Active Re-Timed or
56
+
* Active Linear Re-driven (LRD)
57
+
* USB3.2 GEN1/2 and USB4 GEN2+
58
+
* TC->TC cables all : HBR3
59
+
* with DP_BR CTS : UHBR10
60
+
* DP54 logo : UHBR13.5
61
+
* DP80 logo : UHBR20
62
+
* - Passive/Active Re-Timed or
63
+
* Active Linear Re-driven (LRD)
64
+
* TC->DP cables with DP_BR CTS/DP8K logo : HBR3
65
+
* with DP_BR CTS : UHBR10
66
+
* DP54 logo : UHBR13.5
67
+
* DP80 logo : UHBR20
68
+
* (c) Used in TBT-alt/legacy modes and on LNL+ after the sink
69
+
* disconnected in DP-alt mode.
70
+
* (d) Only defined by the DP Alt Standard v1.0a, deprecated by v1.0b,
71
+
* only supported on ICL.
72
+
* (e) GEN2 passive 1 m cable: 4 DP lanes, GEN2 active cable: 2 DP lanes.
73
+
* (f) GEN2 passive 1 m cable: 2 DP lanes, GEN2 active cable: 1 DP lane.
74
+
* (g) These pin assignments are also referred to as (USB/DP)
75
+
* multifunction or Multifunction Display Port (MFD) modes.
76
+
* (h) Also used where one end of the cable is a captive connector,
77
+
* attached to a DP->HDMI/DVI/VGA converter.
78
+
* (i) The DP end of the cable is a captive connector attached to a
79
+
* (DP/USB) multifunction dock as defined by the DockPort v1.0a
80
+
* specification.
81
+
*/
82
+
};
83
+
15
84
bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port);
16
85
bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port);
17
86
bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);
···
88
19
89
20
bool intel_tc_port_connected(struct intel_encoder *encoder);
90
21
91
-
u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
22
+
enum intel_tc_pin_assignment
23
+
intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port);
92
24
int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
93
25
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
94
26
int required_lanes);
+12
-4
drivers/gpu/drm/i915/display/intel_vblank.c
+12
-4
drivers/gpu/drm/i915/display/intel_vblank.c
···
3
3
* Copyright © 2022-2023 Intel Corporation
4
4
*/
5
5
6
+
#include <linux/iopoll.h>
7
+
6
8
#include <drm/drm_vblank.h>
7
9
8
10
#include "i915_drv.h"
11
+
#include "i915_utils.h"
9
12
#include "intel_color.h"
10
13
#include "intel_crtc.h"
11
14
#include "intel_de.h"
···
495
492
{
496
493
struct intel_display *display = to_intel_display(crtc);
497
494
enum pipe pipe = crtc->pipe;
495
+
bool is_moving;
496
+
int ret;
498
497
499
498
/* Wait for the display line to settle/start moving */
500
-
if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100))
499
+
ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),
500
+
is_moving == state,
501
+
500, 100 * 1000, false);
502
+
if (ret)
501
503
drm_err(display->drm,
502
504
"pipe %c scanline %s wait timed out\n",
503
505
pipe_name(pipe), str_on_off(state));
···
732
724
break;
733
725
734
726
if (!timeout) {
735
-
drm_err(display->drm,
736
-
"Potential atomic update failure on pipe %c\n",
737
-
pipe_name(crtc->pipe));
727
+
drm_dbg_kms(display->drm,
728
+
"Potential atomic update failure on pipe %c\n",
729
+
pipe_name(crtc->pipe));
738
730
break;
739
731
}
740
732
+19
-1
drivers/gpu/drm/i915/display/intel_vbt_defs.h
+19
-1
drivers/gpu/drm/i915/display/intel_vbt_defs.h
···
37
37
#ifndef _INTEL_VBT_DEFS_H_
38
38
#define _INTEL_VBT_DEFS_H_
39
39
40
-
#include "intel_bios.h"
40
+
#include "intel_dsi_vbt_defs.h"
41
41
42
42
/* EDID derived structures */
43
43
struct bdb_edid_pnp_id {
···
437
437
#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6
438
438
#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7
439
439
440
+
/* EDP link rate 263+ */
441
+
#define BDB_263_VBT_EDP_LINK_RATE_1_62 BIT_U32(0)
442
+
#define BDB_263_VBT_EDP_LINK_RATE_2_16 BIT_U32(1)
443
+
#define BDB_263_VBT_EDP_LINK_RATE_2_43 BIT_U32(2)
444
+
#define BDB_263_VBT_EDP_LINK_RATE_2_7 BIT_U32(3)
445
+
#define BDB_263_VBT_EDP_LINK_RATE_3_24 BIT_U32(4)
446
+
#define BDB_263_VBT_EDP_LINK_RATE_4_32 BIT_U32(5)
447
+
#define BDB_263_VBT_EDP_LINK_RATE_5_4 BIT_U32(6)
448
+
#define BDB_263_VBT_EDP_LINK_RATE_6_75 BIT_U32(7)
449
+
#define BDB_263_VBT_EDP_LINK_RATE_8_1 BIT_U32(8)
450
+
#define BDB_263_VBT_EDP_LINK_RATE_10 BIT_U32(9)
451
+
#define BDB_263_VBT_EDP_LINK_RATE_13_5 BIT_U32(10)
452
+
#define BDB_263_VBT_EDP_LINK_RATE_20 BIT_U32(11)
453
+
#define BDB_263_VBT_EDP_NUM_RATES 12
454
+
#define BDB_263_VBT_EDP_RATES_MASK GENMASK(BDB_263_VBT_EDP_NUM_RATES - 1, 0)
455
+
440
456
/*
441
457
* The child device config, aka the display device data structure, provides a
442
458
* description of a port and its configuration on the platform.
···
563
547
u8 dp_max_link_rate:3; /* 216+ */
564
548
u8 dp_max_link_rate_reserved:5; /* 216+ */
565
549
u8 efp_index; /* 256+ */
550
+
u32 edp_data_rate_override:12; /* 263+ */
551
+
u32 edp_data_rate_override_reserved:20; /* 263+ */
566
552
} __packed;
567
553
568
554
struct bdb_general_definitions {
+4
-5
drivers/gpu/drm/i915/display/intel_wm.c
+4
-5
drivers/gpu/drm/i915/display/intel_wm.c
···
5
5
6
6
#include <linux/debugfs.h>
7
7
8
-
#include <drm/drm_file.h>
9
8
#include <drm/drm_print.h>
10
9
11
10
#include "i9xx_wm.h"
···
389
390
390
391
void intel_wm_debugfs_register(struct intel_display *display)
391
392
{
392
-
struct drm_minor *minor = display->drm->primary;
393
+
struct dentry *debugfs_root = display->drm->debugfs_root;
393
394
394
-
debugfs_create_file("i915_pri_wm_latency", 0644, minor->debugfs_root,
395
+
debugfs_create_file("i915_pri_wm_latency", 0644, debugfs_root,
395
396
display, &i915_pri_wm_latency_fops);
396
397
397
-
debugfs_create_file("i915_spr_wm_latency", 0644, minor->debugfs_root,
398
+
debugfs_create_file("i915_spr_wm_latency", 0644, debugfs_root,
398
399
display, &i915_spr_wm_latency_fops);
399
400
400
-
debugfs_create_file("i915_cur_wm_latency", 0644, minor->debugfs_root,
401
+
debugfs_create_file("i915_cur_wm_latency", 0644, debugfs_root,
401
402
display, &i915_cur_wm_latency_fops);
402
403
403
404
skl_watermark_debugfs_register(display);
+49
-4
drivers/gpu/drm/i915/display/skl_scaler.c
+49
-4
drivers/gpu/drm/i915/display/skl_scaler.c
···
10
10
#include "intel_display_regs.h"
11
11
#include "intel_display_trace.h"
12
12
#include "intel_display_types.h"
13
+
#include "intel_display_wa.h"
13
14
#include "intel_fb.h"
14
15
#include "skl_scaler.h"
15
16
#include "skl_universal_plane.h"
···
92
91
}
93
92
}
94
93
95
-
static void skl_scaler_max_src_size(struct intel_crtc *crtc,
94
+
static void skl_scaler_max_src_size(struct intel_display *display,
96
95
int *max_w, int *max_h)
97
96
{
98
-
struct intel_display *display = to_intel_display(crtc);
99
-
100
97
if (DISPLAY_VER(display) >= 14) {
101
98
*max_w = 4096;
102
99
*max_h = 8192;
···
131
132
*max_w = 4096;
132
133
*max_h = 4096;
133
134
}
135
+
}
136
+
137
+
enum drm_mode_status
138
+
skl_scaler_mode_valid(struct intel_display *display,
139
+
const struct drm_display_mode *mode,
140
+
enum intel_output_format output_format,
141
+
int num_joined_pipes)
142
+
{
143
+
int max_h, max_w;
144
+
145
+
if (num_joined_pipes < 2 && output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
146
+
skl_scaler_max_src_size(display, &max_w, &max_h);
147
+
if (mode->hdisplay > max_h)
148
+
return MODE_NO_420;
149
+
}
150
+
151
+
return MODE_OK;
134
152
}
135
153
136
154
static int
···
217
201
}
218
202
219
203
skl_scaler_min_src_size(format, modifier, &min_src_w, &min_src_h);
220
-
skl_scaler_max_src_size(crtc, &max_src_w, &max_src_h);
204
+
skl_scaler_max_src_size(display, &max_src_w, &max_src_h);
221
205
222
206
skl_scaler_min_dst_size(&min_dst_w, &min_dst_h);
223
207
skl_scaler_max_dst_size(crtc, &max_dst_w, &max_dst_h);
···
763
747
crtc_state->scaler_state.scaler_id < 0))
764
748
return;
765
749
750
+
if (intel_display_wa(display, 14011503117))
751
+
adl_scaler_ecc_mask(crtc_state);
752
+
766
753
drm_rect_init(&src, 0, 0,
767
754
drm_rect_width(&crtc_state->pipe_src) << 16,
768
755
drm_rect_height(&crtc_state->pipe_src) << 16);
···
941
922
scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
942
923
else
943
924
scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
925
+
}
926
+
927
+
void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state)
928
+
{
929
+
struct intel_display *display = to_intel_display(crtc_state);
930
+
931
+
if (!crtc_state->pch_pfit.enabled)
932
+
return;
933
+
934
+
intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
935
+
}
936
+
937
+
void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
938
+
{
939
+
struct intel_display *display = to_intel_display(crtc_state);
940
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
941
+
const struct intel_crtc_scaler_state *scaler_state =
942
+
&crtc_state->scaler_state;
943
+
944
+
if (scaler_state->scaler_id < 0)
945
+
return;
946
+
947
+
intel_de_write_fw(display,
948
+
SKL_PS_ECC_STAT(crtc->pipe, scaler_state->scaler_id),
949
+
1);
950
+
intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
944
951
}
+13
drivers/gpu/drm/i915/display/skl_scaler.h
+13
drivers/gpu/drm/i915/display/skl_scaler.h
···
5
5
#ifndef INTEL_SCALER_H
6
6
#define INTEL_SCALER_H
7
7
8
+
enum drm_mode_status;
9
+
struct drm_display_mode;
8
10
struct intel_atomic_state;
9
11
struct intel_crtc;
10
12
struct intel_crtc_state;
13
+
struct intel_display;
11
14
struct intel_dsb;
15
+
enum intel_output_format;
12
16
struct intel_plane;
13
17
struct intel_plane_state;
14
18
···
36
32
37
33
void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
38
34
35
+
enum drm_mode_status
36
+
skl_scaler_mode_valid(struct intel_display *display,
37
+
const struct drm_display_mode *mode,
38
+
enum intel_output_format output_format,
39
+
int num_joined_pipes);
40
+
41
+
void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
42
+
43
+
void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
39
44
#endif
+25
-36
drivers/gpu/drm/i915/display/skl_universal_plane.c
+25
-36
drivers/gpu/drm/i915/display/skl_universal_plane.c
···
10
10
11
11
#include "pxp/intel_pxp.h"
12
12
#include "i915_drv.h"
13
+
#include "i915_utils.h"
13
14
#include "intel_bo.h"
14
15
#include "intel_de.h"
15
16
#include "intel_display_irq.h"
···
1167
1166
return plane_ctl;
1168
1167
}
1169
1168
1170
-
static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1171
-
const struct intel_plane_state *plane_state)
1169
+
static u32 skl_plane_ctl(const struct intel_plane_state *plane_state)
1172
1170
{
1173
1171
struct intel_display *display = to_intel_display(plane_state);
1174
1172
const struct drm_framebuffer *fb = plane_state->hw.fb;
···
1225
1225
return plane_color_ctl;
1226
1226
}
1227
1227
1228
-
static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1229
-
const struct intel_plane_state *plane_state)
1228
+
static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state)
1230
1229
{
1231
1230
struct intel_display *display = to_intel_display(plane_state);
1232
1231
const struct drm_framebuffer *fb = plane_state->hw.fb;
···
1270
1271
u32 offset = plane_state->view.color_plane[color_plane].offset;
1271
1272
1272
1273
if (intel_fb_uses_dpt(fb)) {
1273
-
/*
1274
-
* The DPT object contains only one vma, so the VMA's offset
1275
-
* within the DPT is always 0.
1276
-
*/
1277
-
drm_WARN_ON(display->drm, plane_state->dpt_vma &&
1278
-
intel_dpt_offset(plane_state->dpt_vma));
1279
1274
drm_WARN_ON(display->drm, offset & 0x1fffff);
1280
1275
return offset >> 9;
1281
1276
} else {
···
1278
1285
}
1279
1286
}
1280
1287
1281
-
static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
1282
-
int color_plane)
1288
+
static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
1283
1289
{
1290
+
if (plane_state->planar_linked_plane && !plane_state->is_y_plane)
1291
+
return 1;
1292
+
else
1293
+
return 0;
1294
+
}
1295
+
1296
+
static u32 skl_plane_surf_offset(const struct intel_plane_state *plane_state)
1297
+
{
1298
+
int color_plane = icl_plane_color_plane(plane_state);
1284
1299
u32 plane_surf;
1285
1300
1286
-
plane_surf = intel_plane_ggtt_offset(plane_state) +
1287
-
skl_surf_address(plane_state, color_plane);
1301
+
plane_surf = skl_surf_address(plane_state, color_plane);
1288
1302
1289
1303
if (plane_state->decrypt)
1290
1304
plane_surf |= PLANE_SURF_DECRYPT;
···
1371
1371
intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
1372
1372
intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
1373
1373
intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
1374
-
}
1375
-
1376
-
static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
1377
-
{
1378
-
if (plane_state->planar_linked_plane && !plane_state->is_y_plane)
1379
-
return 1;
1380
-
else
1381
-
return 0;
1382
1374
}
1383
1375
1384
1376
static void
···
1468
1476
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
1469
1477
plane_ctl);
1470
1478
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
1471
-
skl_plane_surf(plane_state, 0));
1479
+
plane_state->surf);
1472
1480
}
1473
1481
1474
1482
static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb,
···
1624
1632
struct intel_display *display = to_intel_display(plane);
1625
1633
enum plane_id plane_id = plane->id;
1626
1634
enum pipe pipe = plane->pipe;
1627
-
int color_plane = icl_plane_color_plane(plane_state);
1628
1635
u32 plane_ctl;
1629
1636
1630
1637
plane_ctl = plane_state->ctl |
···
1649
1658
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
1650
1659
plane_ctl);
1651
1660
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
1652
-
skl_plane_surf(plane_state, color_plane));
1661
+
plane_state->surf);
1653
1662
}
1654
1663
1655
1664
static void skl_plane_capture_error(struct intel_crtc *crtc,
···
1673
1682
struct intel_display *display = to_intel_display(plane);
1674
1683
enum plane_id plane_id = plane->id;
1675
1684
enum pipe pipe = plane->pipe;
1676
-
u32 plane_ctl = plane_state->ctl, plane_surf;
1685
+
u32 plane_ctl = plane_state->ctl;
1686
+
u32 plane_surf = plane_state->surf;
1677
1687
1678
1688
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1679
-
plane_surf = skl_plane_surf(plane_state, 0);
1680
1689
1681
1690
if (async_flip) {
1682
1691
if (DISPLAY_VER(display) >= 30)
···
2354
2363
plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
2355
2364
}
2356
2365
2357
-
plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
2366
+
plane_state->ctl = skl_plane_ctl(plane_state);
2358
2367
2359
2368
if (DISPLAY_VER(display) >= 10)
2360
-
plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
2361
-
plane_state);
2369
+
plane_state->color_ctl = glk_plane_color_ctl(plane_state);
2362
2370
2363
2371
if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2364
2372
icl_is_hdr_plane(display, plane->id))
···
2804
2814
intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl);
2805
2815
2806
2816
intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id),
2807
-
skl_plane_surf(state, 0));
2817
+
state->surf);
2808
2818
}
2809
2819
2810
2820
struct intel_plane *
···
2854
2864
plane->min_cdclk = skl_plane_min_cdclk;
2855
2865
}
2856
2866
plane->disable_tiling = skl_disable_tiling;
2867
+
2868
+
plane->surf_offset = skl_plane_surf_offset;
2857
2869
2858
2870
if (DISPLAY_VER(display) >= 13)
2859
2871
plane->max_stride = adl_plane_max_stride;
···
3183
3191
to_intel_plane_state(plane->base.state);
3184
3192
enum plane_id plane_id = plane->id;
3185
3193
enum pipe pipe = crtc->pipe;
3186
-
u32 base;
3187
3194
3188
3195
if (!plane_state->uapi.visible)
3189
3196
return false;
3190
-
3191
-
base = intel_plane_ggtt_offset(plane_state);
3192
3197
3193
3198
/*
3194
3199
* We may have moved the surface to a different
3195
3200
* part of ggtt, make the plane aware of that.
3196
3201
*/
3197
-
if (plane_config->base == base)
3202
+
if (plane_config->base == plane_state->surf)
3198
3203
return false;
3199
3204
3200
-
intel_de_write(display, PLANE_SURF(pipe, plane_id), base);
3205
+
intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf);
3201
3206
3202
3207
return true;
3203
3208
}
+12
-8
drivers/gpu/drm/i915/display/skl_watermark.c
+12
-8
drivers/gpu/drm/i915/display/skl_watermark.c
···
6
6
#include <linux/debugfs.h>
7
7
8
8
#include <drm/drm_blend.h>
9
-
#include <drm/drm_file.h>
10
9
#include <drm/drm_print.h>
11
10
12
11
#include "soc/intel_dram.h"
···
1388
1389
{
1389
1390
u16 size, extra = 0;
1390
1391
1391
-
if (data_rate) {
1392
+
if (data_rate && iter->data_rate) {
1392
1393
extra = min_t(u16, iter->size,
1393
1394
DIV64_U64_ROUND_UP(iter->size * data_rate,
1394
1395
iter->data_rate));
···
2272
2273
return wm0_lines;
2273
2274
}
2274
2275
2276
+
/*
2277
+
* TODO: In case we use PKG_C_LATENCY to allow C-states when the delayed vblank
2278
+
* size is too small for the package C exit latency we need to notify PSR about
2279
+
* the scenario to apply Wa_16025596647.
2280
+
*/
2275
2281
static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
2276
2282
int wm0_lines)
2277
2283
{
···
3209
3205
}
3210
3206
3211
3207
/*
3212
-
* WA Level-0 adjustment for 16GB DIMMs: SKL+
3208
+
* WA Level-0 adjustment for 16Gb DIMMs: SKL+
3213
3209
* If we could not get dimm info enable this WA to prevent from
3214
-
* any underrun. If not able to get Dimm info assume 16GB dimm
3210
+
* any underrun. If not able to get DIMM info assume 16Gb DIMM
3215
3211
* to avoid any underrun.
3216
3212
*/
3217
-
if (!display->platform.dg2 && dram_info->wm_lv_0_adjust_needed)
3213
+
if (!display->platform.dg2 && dram_info->has_16gb_dimms)
3218
3214
wm[0] += 1;
3219
3215
}
3220
3216
···
4037
4033
4038
4034
void skl_watermark_debugfs_register(struct intel_display *display)
4039
4035
{
4040
-
struct drm_minor *minor = display->drm->primary;
4036
+
struct dentry *debugfs_root = display->drm->debugfs_root;
4041
4037
4042
4038
if (HAS_IPC(display))
4043
-
debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root,
4039
+
debugfs_create_file("i915_ipc_status", 0644, debugfs_root,
4044
4040
display, &skl_watermark_ipc_status_fops);
4045
4041
4046
4042
if (HAS_SAGV(display))
4047
-
debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root,
4043
+
debugfs_create_file("i915_sagv_status", 0444, debugfs_root,
4048
4044
display, &intel_sagv_status_fops);
4049
4045
}
4050
4046
+2
-2
drivers/gpu/drm/i915/display/vlv_dsi.c
+2
-2
drivers/gpu/drm/i915/display/vlv_dsi.c
···
761
761
762
762
if (display->platform.valleyview || display->platform.cherryview) {
763
763
/* Disable DPOunit clock gating, can stall pipe */
764
-
intel_de_rmw(display, DSPCLK_GATE_D(display),
764
+
intel_de_rmw(display, VLV_DSPCLK_GATE_D,
765
765
0, DPOUNIT_CLOCK_GATE_DISABLE);
766
766
}
767
767
···
918
918
} else {
919
919
vlv_dsi_pll_disable(encoder);
920
920
921
-
intel_de_rmw(display, DSPCLK_GATE_D(display),
921
+
intel_de_rmw(display, VLV_DSPCLK_GATE_D,
922
922
DPOUNIT_CLOCK_GATE_DISABLE, 0);
923
923
}
924
924
+21
-11
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+21
-11
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
···
25
25
* Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
26
26
*/
27
27
28
+
#include <linux/iopoll.h>
28
29
#include <linux/kernel.h>
29
30
#include <linux/string_helpers.h>
30
31
31
32
#include <drm/drm_print.h>
32
33
33
-
#include "i915_utils.h"
34
34
#include "intel_de.h"
35
35
#include "intel_display_types.h"
36
36
#include "intel_dsi.h"
···
142
142
pll_div &= DSI_PLL_M1_DIV_MASK;
143
143
pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
144
144
145
-
while (pll_ctl) {
146
-
pll_ctl = pll_ctl >> 1;
147
-
p++;
148
-
}
149
-
p--;
145
+
p = fls(pll_ctl);
146
+
if (p)
147
+
p--;
150
148
151
149
if (!p) {
152
150
drm_err(display->drm, "wrong P1 divisor\n");
···
214
216
const struct intel_crtc_state *config)
215
217
{
216
218
struct intel_display *display = to_intel_display(encoder);
219
+
u32 val;
220
+
int ret;
217
221
218
222
drm_dbg_kms(display->drm, "\n");
219
223
···
233
233
234
234
vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
235
235
236
-
if (wait_for(vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) &
237
-
DSI_PLL_LOCK, 20)) {
238
-
236
+
ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL),
237
+
val & DSI_PLL_LOCK,
238
+
500, 20 * 1000, false);
239
+
if (ret) {
239
240
vlv_cck_put(display->drm);
240
241
drm_err(display->drm, "DSI PLL lock failed\n");
241
242
return;
···
263
262
vlv_cck_put(display->drm);
264
263
}
265
264
265
+
static bool has_dsic_clock(struct intel_display *display)
266
+
{
267
+
return display->platform.broxton;
268
+
}
269
+
266
270
bool bxt_dsi_pll_is_enabled(struct intel_display *display)
267
271
{
268
272
bool enabled;
···
290
284
* causes a system hang.
291
285
*/
292
286
val = intel_de_read(display, BXT_DSI_PLL_CTL);
293
-
if (display->platform.geminilake) {
287
+
if (!has_dsic_clock(display)) {
294
288
if (!(val & BXT_DSIA_16X_MASK)) {
295
289
drm_dbg_kms(display->drm,
296
290
"Invalid PLL divider (%08x)\n", val);
···
364
358
u32 pclk;
365
359
366
360
config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);
361
+
if (!has_dsic_clock(display))
362
+
config->dsi_pll.ctrl &= ~BXT_DSIC_16X_MASK;
367
363
368
364
pclk = bxt_dsi_pclk(encoder, config);
369
365
···
522
514
* Spec says both have to be programmed, even if one is not getting
523
515
* used. Configure MIPI_CLOCK_CTL dividers in modeset
524
516
*/
525
-
config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
517
+
config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2;
518
+
if (has_dsic_clock(display))
519
+
config->dsi_pll.ctrl |= BXT_DSIC_16X_BY2;
526
520
527
521
/* As per recommendation from hardware team,
528
522
* Prog PVD ratio =1 if dsi ratio <= 50
+2
-1
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+2
-1
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
···
110
110
111
111
static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
112
112
{
113
+
struct intel_display *display = i915->display;
113
114
int gen = GRAPHICS_VER(i915);
114
115
115
116
/* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */
···
122
121
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
123
122
return false;
124
123
125
-
return HAS_DISPLAY(i915);
124
+
return HAS_DISPLAY(display);
126
125
}
127
126
128
127
static bool fast_blit_ok(const struct blit_buffer *buf)
+1
-1
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+1
-1
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
···
148
148
*
149
149
* Testing on actual hardware has shown there is no /16.
150
150
*/
151
-
return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000;
151
+
return DIV_ROUND_CLOSEST(intel_fsb_freq(uncore->i915), 4) * 1000;
152
152
}
153
153
154
154
static u32 read_clock_frequency(struct intel_uncore *uncore)
+3
-2
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+3
-2
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
···
82
82
83
83
void intel_gt_debugfs_register(struct intel_gt *gt)
84
84
{
85
+
struct dentry *debugfs_root = gt->i915->drm.debugfs_root;
85
86
struct dentry *root;
86
87
char gtname[4];
87
88
88
-
if (!gt->i915->drm.primary->debugfs_root)
89
+
if (!debugfs_root)
89
90
return;
90
91
91
92
snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
92
-
root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
93
+
root = debugfs_create_dir(gtname, debugfs_root);
93
94
if (IS_ERR(root))
94
95
return;
95
96
+8
-3
drivers/gpu/drm/i915/gt/intel_rps.c
+8
-3
drivers/gpu/drm/i915/gt/intel_rps.c
···
9
9
10
10
#include "display/intel_display.h"
11
11
#include "display/intel_display_rps.h"
12
+
#include "soc/intel_dram.h"
12
13
#include "i915_drv.h"
13
14
#include "i915_irq.h"
14
15
#include "i915_reg.h"
···
277
276
{
278
277
struct drm_i915_private *i915 = rps_to_i915(rps);
279
278
struct intel_uncore *uncore = rps_to_uncore(rps);
279
+
unsigned int fsb_freq, mem_freq;
280
280
u8 fmax, fmin, fstart;
281
281
u32 rgvmodectl;
282
282
int c_m, i;
283
283
284
-
if (i915->fsb_freq <= 3200000)
284
+
fsb_freq = intel_fsb_freq(i915);
285
+
mem_freq = intel_mem_freq(i915);
286
+
287
+
if (fsb_freq <= 3200000)
285
288
c_m = 0;
286
-
else if (i915->fsb_freq <= 4800000)
289
+
else if (fsb_freq <= 4800000)
287
290
c_m = 1;
288
291
else
289
292
c_m = 2;
290
293
291
294
for (i = 0; i < ARRAY_SIZE(cparams); i++) {
292
295
if (cparams[i].i == c_m &&
293
-
cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) {
296
+
cparams[i].t == DIV_ROUND_CLOSEST(mem_freq, 1000)) {
294
297
rps->ips.m = cparams[i].m;
295
298
rps->ips.c = cparams[i].c;
296
299
break;
+6
-6
drivers/gpu/drm/i915/gvt/debugfs.c
+6
-6
drivers/gpu/drm/i915/gvt/debugfs.c
···
194
194
void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu)
195
195
{
196
196
struct intel_gvt *gvt = vgpu->gvt;
197
-
struct drm_minor *minor = gvt->gt->i915->drm.primary;
197
+
struct dentry *debugfs_root = gvt->gt->i915->drm.debugfs_root;
198
198
199
-
if (minor->debugfs_root && gvt->debugfs_root) {
199
+
if (debugfs_root && gvt->debugfs_root) {
200
200
debugfs_remove_recursive(vgpu->debugfs);
201
201
vgpu->debugfs = NULL;
202
202
}
···
208
208
*/
209
209
void intel_gvt_debugfs_init(struct intel_gvt *gvt)
210
210
{
211
-
struct drm_minor *minor = gvt->gt->i915->drm.primary;
211
+
struct dentry *debugfs_root = gvt->gt->i915->drm.debugfs_root;
212
212
213
-
gvt->debugfs_root = debugfs_create_dir("gvt", minor->debugfs_root);
213
+
gvt->debugfs_root = debugfs_create_dir("gvt", debugfs_root);
214
214
215
215
debugfs_create_ulong("num_tracked_mmio", 0444, gvt->debugfs_root,
216
216
&gvt->mmio.num_tracked_mmio);
···
222
222
*/
223
223
void intel_gvt_debugfs_clean(struct intel_gvt *gvt)
224
224
{
225
-
struct drm_minor *minor = gvt->gt->i915->drm.primary;
225
+
struct dentry *debugfs_root = gvt->gt->i915->drm.debugfs_root;
226
226
227
-
if (minor->debugfs_root) {
227
+
if (debugfs_root) {
228
228
debugfs_remove_recursive(gvt->debugfs_root);
229
229
gvt->debugfs_root = NULL;
230
230
}
+9
-11
drivers/gpu/drm/i915/i915_debugfs.c
+9
-11
drivers/gpu/drm/i915/i915_debugfs.c
···
720
720
{"i915_gem_drop_caches", &i915_drop_caches_fops},
721
721
};
722
722
723
-
void i915_debugfs_register(struct drm_i915_private *dev_priv)
723
+
void i915_debugfs_register(struct drm_i915_private *i915)
724
724
{
725
-
struct drm_minor *minor = dev_priv->drm.primary;
725
+
struct dentry *debugfs_root = i915->drm.debugfs_root;
726
726
int i;
727
727
728
-
i915_debugfs_params(dev_priv);
728
+
i915_debugfs_params(i915);
729
729
730
-
debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
731
-
to_i915(minor->dev), &i915_forcewake_fops);
730
+
debugfs_create_file("i915_forcewake_user", S_IRUSR, debugfs_root,
731
+
i915, &i915_forcewake_fops);
732
732
for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
733
-
debugfs_create_file(i915_debugfs_files[i].name,
734
-
S_IRUGO | S_IWUSR,
735
-
minor->debugfs_root,
736
-
to_i915(minor->dev),
733
+
debugfs_create_file(i915_debugfs_files[i].name, S_IRUGO | S_IWUSR,
734
+
debugfs_root, i915,
737
735
i915_debugfs_files[i].fops);
738
736
}
739
737
740
738
drm_debugfs_create_files(i915_debugfs_list,
741
739
ARRAY_SIZE(i915_debugfs_list),
742
-
minor->debugfs_root, minor);
740
+
debugfs_root, i915->drm.primary);
743
741
744
-
i915_gpu_error_debugfs_register(dev_priv);
742
+
i915_gpu_error_debugfs_register(i915);
745
743
}
+2
-2
drivers/gpu/drm/i915/i915_debugfs_params.c
+2
-2
drivers/gpu/drm/i915/i915_debugfs_params.c
···
248
248
/* add a subdirectory with files for each i915 param */
249
249
struct dentry *i915_debugfs_params(struct drm_i915_private *i915)
250
250
{
251
-
struct drm_minor *minor = i915->drm.primary;
251
+
struct dentry *debugfs_root = i915->drm.debugfs_root;
252
252
struct i915_params *params = &i915->params;
253
253
struct dentry *dir;
254
254
255
-
dir = debugfs_create_dir("i915_params", minor->debugfs_root);
255
+
dir = debugfs_create_dir("i915_params", debugfs_root);
256
256
if (IS_ERR(dir))
257
257
return dir;
258
258
+7
-7
drivers/gpu/drm/i915/i915_driver.c
+7
-7
drivers/gpu/drm/i915/i915_driver.c
···
977
977
intel_power_domains_disable(display);
978
978
979
979
drm_client_dev_suspend(&i915->drm, false);
980
-
if (HAS_DISPLAY(i915)) {
980
+
if (HAS_DISPLAY(display)) {
981
981
drm_kms_helper_poll_disable(&i915->drm);
982
982
intel_display_driver_disable_user_access(display);
983
983
···
989
989
intel_irq_suspend(i915);
990
990
intel_hpd_cancel_work(display);
991
991
992
-
if (HAS_DISPLAY(i915))
992
+
if (HAS_DISPLAY(display))
993
993
intel_display_driver_suspend_access(display);
994
994
995
995
intel_encoder_suspend_all(display);
···
1060
1060
* properly. */
1061
1061
intel_power_domains_disable(display);
1062
1062
drm_client_dev_suspend(dev, false);
1063
-
if (HAS_DISPLAY(dev_priv)) {
1063
+
if (HAS_DISPLAY(display)) {
1064
1064
drm_kms_helper_poll_disable(dev);
1065
1065
intel_display_driver_disable_user_access(display);
1066
1066
}
···
1072
1072
intel_irq_suspend(dev_priv);
1073
1073
intel_hpd_cancel_work(display);
1074
1074
1075
-
if (HAS_DISPLAY(dev_priv))
1075
+
if (HAS_DISPLAY(display))
1076
1076
intel_display_driver_suspend_access(display);
1077
1077
1078
1078
intel_encoder_suspend_all(display);
···
1219
1219
*/
1220
1220
intel_irq_resume(dev_priv);
1221
1221
1222
-
if (HAS_DISPLAY(dev_priv))
1222
+
if (HAS_DISPLAY(display))
1223
1223
drm_mode_config_reset(dev);
1224
1224
1225
1225
i915_gem_resume(dev_priv);
···
1228
1228
1229
1229
intel_clock_gating_init(dev_priv);
1230
1230
1231
-
if (HAS_DISPLAY(dev_priv))
1231
+
if (HAS_DISPLAY(display))
1232
1232
intel_display_driver_resume_access(display);
1233
1233
1234
1234
intel_hpd_init(display);
1235
1235
1236
1236
intel_display_driver_resume(display);
1237
1237
1238
-
if (HAS_DISPLAY(dev_priv)) {
1238
+
if (HAS_DISPLAY(display)) {
1239
1239
intel_display_driver_enable_user_access(display);
1240
1240
drm_kms_helper_poll_enable(dev);
1241
1241
}
-2
drivers/gpu/drm/i915/i915_drv.h
-2
drivers/gpu/drm/i915/i915_drv.h
+3
-3
drivers/gpu/drm/i915/i915_gpu_error.c
+3
-3
drivers/gpu/drm/i915/i915_gpu_error.c
···
2445
2445
2446
2446
void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
2447
2447
{
2448
-
struct drm_minor *minor = i915->drm.primary;
2448
+
struct dentry *debugfs_root = i915->drm.debugfs_root;
2449
2449
2450
-
debugfs_create_file("i915_error_state", 0644, minor->debugfs_root, i915,
2450
+
debugfs_create_file("i915_error_state", 0644, debugfs_root, i915,
2451
2451
&i915_error_state_fops);
2452
-
debugfs_create_file("i915_gpu_info", 0644, minor->debugfs_root, i915,
2452
+
debugfs_create_file("i915_gpu_info", 0644, debugfs_root, i915,
2453
2453
&i915_gpu_info_fops);
2454
2454
}
2455
2455
+7
-6
drivers/gpu/drm/i915/i915_irq.c
+7
-6
drivers/gpu/drm/i915/i915_irq.c
···
439
439
* able to process them after we restore SDEIER (as soon as we restore
440
440
* it, we'll get an interrupt if SDEIIR still has something to process
441
441
* due to its back queue). */
442
-
if (!HAS_PCH_NOP(i915)) {
442
+
if (!HAS_PCH_NOP(display)) {
443
443
sde_ier = raw_reg_read(regs, SDEIER);
444
444
raw_reg_write(regs, SDEIER, 0);
445
445
}
···
459
459
de_iir = raw_reg_read(regs, DEIIR);
460
460
if (de_iir) {
461
461
raw_reg_write(regs, DEIIR, de_iir);
462
-
if (DISPLAY_VER(i915) >= 7)
462
+
if (DISPLAY_VER(display) >= 7)
463
463
ivb_display_irq_handler(display, de_iir);
464
464
else
465
465
ilk_display_irq_handler(display, de_iir);
···
834
834
835
835
static u32 i9xx_error_mask(struct drm_i915_private *i915)
836
836
{
837
+
struct intel_display *display = i915->display;
837
838
/*
838
839
* On gen2/3 FBC generates (seemingly spurious)
839
840
* display INVALID_GTT/INVALID_GTT_PTE table errors.
···
847
846
* Unfortunately we can't mask off individual PGTBL_ER bits,
848
847
* so we just have to mask off all page table errors via EMR.
849
848
*/
850
-
if (HAS_FBC(i915))
849
+
if (HAS_FBC(display))
851
850
return I915_ERROR_MEMORY_REFRESH;
852
851
else
853
852
return I915_ERROR_PAGE_TABLE |
···
925
924
I915_MASTER_ERROR_INTERRUPT |
926
925
I915_USER_INTERRUPT;
927
926
928
-
if (DISPLAY_VER(dev_priv) >= 3) {
927
+
if (DISPLAY_VER(display) >= 3) {
929
928
dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT;
930
929
enable_mask |= I915_ASLE_INTERRUPT;
931
930
}
932
931
933
-
if (HAS_HOTPLUG(dev_priv)) {
932
+
if (HAS_HOTPLUG(display)) {
934
933
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
935
934
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
936
935
}
···
964
963
965
964
ret = IRQ_HANDLED;
966
965
967
-
if (HAS_HOTPLUG(dev_priv) &&
966
+
if (HAS_HOTPLUG(display) &&
968
967
iir & I915_DISPLAY_PORT_INTERRUPT)
969
968
hotplug_status = i9xx_hpd_irq_ack(display);
970
969
+5
-4
drivers/gpu/drm/i915/i915_reg.h
+5
-4
drivers/gpu/drm/i915/i915_reg.h
···
412
412
#define FW_BLC _MMIO(0x20d8)
413
413
#define FW_BLC2 _MMIO(0x20dc)
414
414
#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
415
-
#define FW_BLC_SELF_EN_MASK (1 << 31)
416
-
#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
417
-
#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
415
+
#define FW_BLC_SELF_EN_MASK REG_BIT(31)
416
+
#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
417
+
#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
418
418
#define MM_BURST_LENGTH 0x00700000
419
419
#define MM_FIFO_WATERMARK 0x0001F000
420
420
#define LM_BURST_LENGTH 0x00000700
···
613
613
#define DSTATE_GFX_CLOCK_GATING (1 << 1)
614
614
#define DSTATE_DOT_CLOCK_GATING (1 << 0)
615
615
616
-
#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
616
+
#define DSPCLK_GATE_D _MMIO(0x6200)
617
+
#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
617
618
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
618
619
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
619
620
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
+4
-2
drivers/gpu/drm/i915/i915_switcheroo.c
+4
-2
drivers/gpu/drm/i915/i915_switcheroo.c
···
15
15
enum vga_switcheroo_state state)
16
16
{
17
17
struct drm_i915_private *i915 = pdev_to_i915(pdev);
18
+
struct intel_display *display = i915 ? i915->display : NULL;
18
19
pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
19
20
20
21
if (!i915) {
21
22
dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
22
23
return;
23
24
}
24
-
if (!HAS_DISPLAY(i915)) {
25
+
if (!HAS_DISPLAY(display)) {
25
26
dev_err(&pdev->dev, "Device state not initialized, aborting switch.\n");
26
27
return;
27
28
}
···
45
44
static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
46
45
{
47
46
struct drm_i915_private *i915 = pdev_to_i915(pdev);
47
+
struct intel_display *display = i915 ? i915->display : NULL;
48
48
49
49
/*
50
50
* FIXME: open_count is protected by drm_global_mutex but that would lead to
51
51
* locking inversion with the driver load path. And the access here is
52
52
* completely racy anyway. So don't bother with locking for now.
53
53
*/
54
-
return i915 && HAS_DISPLAY(i915) && atomic_read(&i915->drm.open_count) == 0;
54
+
return i915 && HAS_DISPLAY(display) && atomic_read(&i915->drm.open_count) == 0;
55
55
}
56
56
57
57
static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
+7
-2
drivers/gpu/drm/i915/i915_utils.h
+7
-2
drivers/gpu/drm/i915/i915_utils.h
···
267
267
(Wmax))
268
268
#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
269
269
270
-
/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
271
-
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG) && IS_ENABLED(CONFIG_PREEMPT_COUNT)
270
+
/*
271
+
* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false.
272
+
* On PREEMPT_RT the context isn't becoming atomic because it is used in an
273
+
* interrupt handler or because a spinlock_t is acquired. This leads to
274
+
* warnings which don't occur otherwise and therefore the check is disabled.
275
+
*/
276
+
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG) && IS_ENABLED(CONFIG_PREEMPT_COUNT) && !defined(CONFIG_PREEMPT_RT)
272
277
# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
273
278
#else
274
279
# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
+22
-13
drivers/gpu/drm/i915/intel_clock_gating.c
+22
-13
drivers/gpu/drm/i915/intel_clock_gating.c
···
132
132
133
133
static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
134
134
{
135
+
struct intel_display *display = dev_priv->display;
135
136
enum pipe pipe;
136
137
137
-
for_each_pipe(dev_priv, pipe) {
138
-
intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe),
138
+
for_each_pipe(display, pipe) {
139
+
intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
139
140
0, DISP_TRICKLE_FEED_DISABLE);
140
141
141
-
intel_uncore_rmw(&dev_priv->uncore, DSPSURF(dev_priv, pipe),
142
+
intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
142
143
0, 0);
143
144
intel_uncore_posting_read(&dev_priv->uncore,
144
-
DSPSURF(dev_priv, pipe));
145
+
DSPSURF(display, pipe));
145
146
}
146
147
}
147
148
···
219
218
/* The below fixes the weird display corruption, a few pixels shifted
220
219
* downward, on (only) LVDS of some HP laptops with IVY.
221
220
*/
222
-
for_each_pipe(i915, pipe) {
221
+
for_each_pipe(display, pipe) {
223
222
val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
224
223
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
225
224
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
···
230
229
intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
231
230
}
232
231
/* WADP0ClockGatingDisable */
233
-
for_each_pipe(i915, pipe) {
232
+
for_each_pipe(display, pipe) {
234
233
intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
235
234
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
236
235
}
···
308
307
309
308
static void lpt_init_clock_gating(struct drm_i915_private *i915)
310
309
{
310
+
struct intel_display *display = i915->display;
311
+
311
312
/*
312
313
* TODO: this bit should only be enabled when really needed, then
313
314
* disabled when not needed anymore in order to save power.
314
315
*/
315
-
if (HAS_PCH_LPT_LP(i915))
316
+
if (HAS_PCH_LPT_LP(display))
316
317
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
317
318
0, PCH_LP_PARTITION_LEVEL_DISABLE);
318
319
···
358
355
359
356
static void cnp_init_clock_gating(struct drm_i915_private *i915)
360
357
{
361
-
if (!HAS_PCH_CNP(i915))
358
+
struct intel_display *display = i915->display;
359
+
360
+
if (!HAS_PCH_CNP(display))
362
361
return;
363
362
364
363
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
···
426
421
427
422
static void bdw_init_clock_gating(struct drm_i915_private *i915)
428
423
{
424
+
struct intel_display *display = i915->display;
429
425
enum pipe pipe;
430
426
431
427
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
···
438
432
/* WaPsrDPAMaskVBlankInSRD:bdw */
439
433
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
440
434
441
-
for_each_pipe(i915, pipe) {
435
+
for_each_pipe(display, pipe) {
442
436
/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
443
437
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
444
438
0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
···
474
468
475
469
static void hsw_init_clock_gating(struct drm_i915_private *i915)
476
470
{
471
+
struct intel_display *display = i915->display;
477
472
enum pipe pipe;
478
473
479
474
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
···
483
476
/* WaPsrDPAMaskVBlankInSRD:hsw */
484
477
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
485
478
486
-
for_each_pipe(i915, pipe) {
479
+
for_each_pipe(display, pipe) {
487
480
/* WaPsrDPRSUnmaskVBlankInSRD:hsw */
488
481
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
489
482
0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
···
501
494
502
495
static void ivb_init_clock_gating(struct drm_i915_private *i915)
503
496
{
497
+
struct intel_display *display = i915->display;
498
+
504
499
intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
505
500
506
501
/* WaFbcAsynchFlipDisableFbcQueue:ivb */
···
540
531
intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
541
532
GEN6_MBC_SNPCR_MED);
542
533
543
-
if (!HAS_PCH_NOP(i915))
534
+
if (!HAS_PCH_NOP(display))
544
535
cpt_init_clock_gating(i915);
545
536
546
537
gen6_check_mch_setup(i915);
···
620
611
OVCUNIT_CLOCK_GATE_DISABLE;
621
612
if (IS_GM45(i915))
622
613
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
623
-
intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate);
614
+
intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
624
615
625
616
g4x_disable_trickle_feed(i915);
626
617
}
···
631
622
632
623
intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
633
624
intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
634
-
intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0);
625
+
intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
635
626
intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
636
627
intel_uncore_write16(uncore, DEUC, 0);
637
628
intel_uncore_write(uncore,
+134
-132
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+134
-132
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
···
62
62
static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
63
63
{
64
64
struct drm_i915_private *dev_priv = iter->i915;
65
+
struct intel_display *display = dev_priv->display;
65
66
66
67
MMIO_RING_D(RING_IMR);
67
68
MMIO_D(SDEIMR);
···
134
133
MMIO_D(_MMIO(0x650b4));
135
134
MMIO_D(_MMIO(0xc4040));
136
135
MMIO_D(DERRMR);
137
-
MMIO_D(PIPEDSL(dev_priv, PIPE_A));
138
-
MMIO_D(PIPEDSL(dev_priv, PIPE_B));
139
-
MMIO_D(PIPEDSL(dev_priv, PIPE_C));
140
-
MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP));
141
-
MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
142
-
MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
143
-
MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
144
-
MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
145
-
MMIO_D(PIPESTAT(dev_priv, PIPE_A));
146
-
MMIO_D(PIPESTAT(dev_priv, PIPE_B));
147
-
MMIO_D(PIPESTAT(dev_priv, PIPE_C));
148
-
MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
149
-
MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A));
150
-
MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_B));
151
-
MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C));
152
-
MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, _PIPE_EDP));
153
-
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
154
-
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
155
-
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
156
-
MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP));
157
-
MMIO_D(CURCNTR(dev_priv, PIPE_A));
158
-
MMIO_D(CURCNTR(dev_priv, PIPE_B));
159
-
MMIO_D(CURCNTR(dev_priv, PIPE_C));
160
-
MMIO_D(CURPOS(dev_priv, PIPE_A));
161
-
MMIO_D(CURPOS(dev_priv, PIPE_B));
162
-
MMIO_D(CURPOS(dev_priv, PIPE_C));
163
-
MMIO_D(CURBASE(dev_priv, PIPE_A));
164
-
MMIO_D(CURBASE(dev_priv, PIPE_B));
165
-
MMIO_D(CURBASE(dev_priv, PIPE_C));
166
-
MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_A));
167
-
MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_B));
168
-
MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_C));
136
+
MMIO_D(PIPEDSL(display, PIPE_A));
137
+
MMIO_D(PIPEDSL(display, PIPE_B));
138
+
MMIO_D(PIPEDSL(display, PIPE_C));
139
+
MMIO_D(PIPEDSL(display, _PIPE_EDP));
140
+
MMIO_D(TRANSCONF(display, TRANSCODER_A));
141
+
MMIO_D(TRANSCONF(display, TRANSCODER_B));
142
+
MMIO_D(TRANSCONF(display, TRANSCODER_C));
143
+
MMIO_D(TRANSCONF(display, TRANSCODER_EDP));
144
+
MMIO_D(PIPESTAT(display, PIPE_A));
145
+
MMIO_D(PIPESTAT(display, PIPE_B));
146
+
MMIO_D(PIPESTAT(display, PIPE_C));
147
+
MMIO_D(PIPESTAT(display, _PIPE_EDP));
148
+
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));
149
+
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_B));
150
+
MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_C));
151
+
MMIO_D(PIPE_FLIPCOUNT_G4X(display, _PIPE_EDP));
152
+
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));
153
+
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_B));
154
+
MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_C));
155
+
MMIO_D(PIPE_FRMCOUNT_G4X(display, _PIPE_EDP));
156
+
MMIO_D(CURCNTR(display, PIPE_A));
157
+
MMIO_D(CURCNTR(display, PIPE_B));
158
+
MMIO_D(CURCNTR(display, PIPE_C));
159
+
MMIO_D(CURPOS(display, PIPE_A));
160
+
MMIO_D(CURPOS(display, PIPE_B));
161
+
MMIO_D(CURPOS(display, PIPE_C));
162
+
MMIO_D(CURBASE(display, PIPE_A));
163
+
MMIO_D(CURBASE(display, PIPE_B));
164
+
MMIO_D(CURBASE(display, PIPE_C));
165
+
MMIO_D(CUR_FBC_CTL(display, PIPE_A));
166
+
MMIO_D(CUR_FBC_CTL(display, PIPE_B));
167
+
MMIO_D(CUR_FBC_CTL(display, PIPE_C));
169
168
MMIO_D(_MMIO(0x700ac));
170
169
MMIO_D(_MMIO(0x710ac));
171
170
MMIO_D(_MMIO(0x720ac));
···
173
172
MMIO_D(_MMIO(0x70094));
174
173
MMIO_D(_MMIO(0x70098));
175
174
MMIO_D(_MMIO(0x7009c));
176
-
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
177
-
MMIO_D(DSPADDR(dev_priv, PIPE_A));
178
-
MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
179
-
MMIO_D(DSPPOS(dev_priv, PIPE_A));
180
-
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
181
-
MMIO_D(DSPSURF(dev_priv, PIPE_A));
182
-
MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
183
-
MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));
175
+
MMIO_D(DSPCNTR(display, PIPE_A));
176
+
MMIO_D(DSPADDR(display, PIPE_A));
177
+
MMIO_D(DSPSTRIDE(display, PIPE_A));
178
+
MMIO_D(DSPPOS(display, PIPE_A));
179
+
MMIO_D(DSPSIZE(display, PIPE_A));
180
+
MMIO_D(DSPSURF(display, PIPE_A));
181
+
MMIO_D(DSPOFFSET(display, PIPE_A));
182
+
MMIO_D(DSPSURFLIVE(display, PIPE_A));
184
183
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
185
-
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
186
-
MMIO_D(DSPADDR(dev_priv, PIPE_B));
187
-
MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
188
-
MMIO_D(DSPPOS(dev_priv, PIPE_B));
189
-
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
190
-
MMIO_D(DSPSURF(dev_priv, PIPE_B));
191
-
MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
192
-
MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));
184
+
MMIO_D(DSPCNTR(display, PIPE_B));
185
+
MMIO_D(DSPADDR(display, PIPE_B));
186
+
MMIO_D(DSPSTRIDE(display, PIPE_B));
187
+
MMIO_D(DSPPOS(display, PIPE_B));
188
+
MMIO_D(DSPSIZE(display, PIPE_B));
189
+
MMIO_D(DSPSURF(display, PIPE_B));
190
+
MMIO_D(DSPOFFSET(display, PIPE_B));
191
+
MMIO_D(DSPSURFLIVE(display, PIPE_B));
193
192
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
194
-
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
195
-
MMIO_D(DSPADDR(dev_priv, PIPE_C));
196
-
MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
197
-
MMIO_D(DSPPOS(dev_priv, PIPE_C));
198
-
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
199
-
MMIO_D(DSPSURF(dev_priv, PIPE_C));
200
-
MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
201
-
MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));
193
+
MMIO_D(DSPCNTR(display, PIPE_C));
194
+
MMIO_D(DSPADDR(display, PIPE_C));
195
+
MMIO_D(DSPSTRIDE(display, PIPE_C));
196
+
MMIO_D(DSPPOS(display, PIPE_C));
197
+
MMIO_D(DSPSIZE(display, PIPE_C));
198
+
MMIO_D(DSPSURF(display, PIPE_C));
199
+
MMIO_D(DSPOFFSET(display, PIPE_C));
200
+
MMIO_D(DSPSURFLIVE(display, PIPE_C));
202
201
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
203
202
MMIO_D(SPRCTL(PIPE_A));
204
203
MMIO_D(SPRLINOFF(PIPE_A));
···
239
238
MMIO_D(SPRSCALE(PIPE_C));
240
239
MMIO_D(SPRSURFLIVE(PIPE_C));
241
240
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
242
-
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
243
-
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
244
-
MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
245
-
MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
246
-
MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
247
-
MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
248
-
MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
249
-
MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
250
-
MMIO_D(PIPESRC(dev_priv, TRANSCODER_A));
251
-
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
252
-
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
253
-
MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
254
-
MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
255
-
MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
256
-
MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
257
-
MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
258
-
MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
259
-
MMIO_D(PIPESRC(dev_priv, TRANSCODER_B));
260
-
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
261
-
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
262
-
MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
263
-
MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
264
-
MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
265
-
MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
266
-
MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
267
-
MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
268
-
MMIO_D(PIPESRC(dev_priv, TRANSCODER_C));
269
-
MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
270
-
MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
271
-
MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
272
-
MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
273
-
MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
274
-
MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
275
-
MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
276
-
MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
277
-
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
278
-
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
279
-
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
280
-
MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
281
-
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
282
-
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
283
-
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
284
-
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A));
285
-
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
286
-
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
287
-
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
288
-
MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
289
-
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
290
-
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
291
-
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
292
-
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B));
293
-
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
294
-
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
295
-
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
296
-
MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
297
-
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
298
-
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
299
-
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
300
-
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C));
301
-
MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
302
-
MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
303
-
MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
304
-
MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
305
-
MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
306
-
MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
307
-
MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
308
-
MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP));
241
+
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_A));
242
+
MMIO_D(TRANS_HBLANK(display, TRANSCODER_A));
243
+
MMIO_D(TRANS_HSYNC(display, TRANSCODER_A));
244
+
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_A));
245
+
MMIO_D(TRANS_VBLANK(display, TRANSCODER_A));
246
+
MMIO_D(TRANS_VSYNC(display, TRANSCODER_A));
247
+
MMIO_D(BCLRPAT(display, TRANSCODER_A));
248
+
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_A));
249
+
MMIO_D(PIPESRC(display, TRANSCODER_A));
250
+
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_B));
251
+
MMIO_D(TRANS_HBLANK(display, TRANSCODER_B));
252
+
MMIO_D(TRANS_HSYNC(display, TRANSCODER_B));
253
+
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_B));
254
+
MMIO_D(TRANS_VBLANK(display, TRANSCODER_B));
255
+
MMIO_D(TRANS_VSYNC(display, TRANSCODER_B));
256
+
MMIO_D(BCLRPAT(display, TRANSCODER_B));
257
+
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_B));
258
+
MMIO_D(PIPESRC(display, TRANSCODER_B));
259
+
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_C));
260
+
MMIO_D(TRANS_HBLANK(display, TRANSCODER_C));
261
+
MMIO_D(TRANS_HSYNC(display, TRANSCODER_C));
262
+
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_C));
263
+
MMIO_D(TRANS_VBLANK(display, TRANSCODER_C));
264
+
MMIO_D(TRANS_VSYNC(display, TRANSCODER_C));
265
+
MMIO_D(BCLRPAT(display, TRANSCODER_C));
266
+
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_C));
267
+
MMIO_D(PIPESRC(display, TRANSCODER_C));
268
+
MMIO_D(TRANS_HTOTAL(display, TRANSCODER_EDP));
269
+
MMIO_D(TRANS_HBLANK(display, TRANSCODER_EDP));
270
+
MMIO_D(TRANS_HSYNC(display, TRANSCODER_EDP));
271
+
MMIO_D(TRANS_VTOTAL(display, TRANSCODER_EDP));
272
+
MMIO_D(TRANS_VBLANK(display, TRANSCODER_EDP));
273
+
MMIO_D(TRANS_VSYNC(display, TRANSCODER_EDP));
274
+
MMIO_D(BCLRPAT(display, TRANSCODER_EDP));
275
+
MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_EDP));
276
+
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_A));
277
+
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_A));
278
+
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_A));
279
+
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_A));
280
+
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_A));
281
+
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_A));
282
+
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_A));
283
+
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_A));
284
+
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_B));
285
+
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_B));
286
+
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_B));
287
+
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_B));
288
+
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_B));
289
+
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_B));
290
+
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_B));
291
+
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_B));
292
+
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_C));
293
+
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_C));
294
+
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_C));
295
+
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_C));
296
+
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_C));
297
+
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_C));
298
+
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_C));
299
+
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_C));
300
+
MMIO_D(PIPE_DATA_M1(display, TRANSCODER_EDP));
301
+
MMIO_D(PIPE_DATA_N1(display, TRANSCODER_EDP));
302
+
MMIO_D(PIPE_DATA_M2(display, TRANSCODER_EDP));
303
+
MMIO_D(PIPE_DATA_N2(display, TRANSCODER_EDP));
304
+
MMIO_D(PIPE_LINK_M1(display, TRANSCODER_EDP));
305
+
MMIO_D(PIPE_LINK_N1(display, TRANSCODER_EDP));
306
+
MMIO_D(PIPE_LINK_M2(display, TRANSCODER_EDP));
307
+
MMIO_D(PIPE_LINK_N2(display, TRANSCODER_EDP));
309
308
MMIO_D(PF_CTL(PIPE_A));
310
309
MMIO_D(PF_WIN_SZ(PIPE_A));
311
310
MMIO_D(PF_WIN_POS(PIPE_A));
···
514
513
MMIO_D(GAMMA_MODE(PIPE_A));
515
514
MMIO_D(GAMMA_MODE(PIPE_B));
516
515
MMIO_D(GAMMA_MODE(PIPE_C));
517
-
MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A));
518
-
MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B));
519
-
MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C));
520
-
MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A));
521
-
MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B));
522
-
MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C));
516
+
MMIO_D(TRANS_MULT(display, TRANSCODER_A));
517
+
MMIO_D(TRANS_MULT(display, TRANSCODER_B));
518
+
MMIO_D(TRANS_MULT(display, TRANSCODER_C));
519
+
MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_A));
520
+
MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_B));
521
+
MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_C));
523
522
MMIO_D(SFUSE_STRAP);
524
523
MMIO_D(SBI_ADDR);
525
524
MMIO_D(SBI_DATA);
···
1112
1111
static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
1113
1112
{
1114
1113
struct drm_i915_private *dev_priv = iter->i915;
1114
+
struct intel_display *display = dev_priv->display;
1115
1115
1116
1116
MMIO_F(_MMIO(0x80000), 0x3000);
1117
1117
MMIO_D(GEN7_SAMPLER_INSTDONE);
···
1244
1242
MMIO_D(BXT_DSI_PLL_ENABLE);
1245
1243
MMIO_D(GEN9_CLKGATE_DIS_0);
1246
1244
MMIO_D(GEN9_CLKGATE_DIS_4);
1247
-
MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_A));
1248
-
MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_B));
1249
-
MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_C));
1245
+
MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_A));
1246
+
MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_B));
1247
+
MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_C));
1250
1248
MMIO_D(RC6_CTX_BASE);
1251
1249
MMIO_D(GEN8_PUSHBUS_CONTROL);
1252
1250
MMIO_D(GEN8_PUSHBUS_ENABLE);
+2
-1
drivers/gpu/drm/i915/intel_uncore.c
+2
-1
drivers/gpu/drm/i915/intel_uncore.c
···
2502
2502
int intel_uncore_init_mmio(struct intel_uncore *uncore)
2503
2503
{
2504
2504
struct drm_i915_private *i915 = uncore->i915;
2505
+
struct intel_display *display = i915->display;
2505
2506
int ret;
2506
2507
2507
2508
ret = sanity_check_mmio_access(uncore);
···
2537
2536
GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
2538
2537
GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
2539
2538
2540
-
if (HAS_FPGA_DBG_UNCLAIMED(i915))
2539
+
if (HAS_FPGA_DBG_UNCLAIMED(display))
2541
2540
uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
2542
2541
2543
2542
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+4
-4
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
+4
-4
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
···
69
69
70
70
void intel_pxp_debugfs_register(struct intel_pxp *pxp)
71
71
{
72
-
struct drm_minor *minor;
72
+
struct dentry *debugfs_root;
73
73
struct dentry *pxproot;
74
74
75
75
if (!intel_pxp_is_supported(pxp))
76
76
return;
77
77
78
-
minor = pxp->ctrl_gt->i915->drm.primary;
79
-
if (!minor->debugfs_root)
78
+
debugfs_root = pxp->ctrl_gt->i915->drm.debugfs_root;
79
+
if (!debugfs_root)
80
80
return;
81
81
82
-
pxproot = debugfs_create_dir("pxp", minor->debugfs_root);
82
+
pxproot = debugfs_create_dir("pxp", debugfs_root);
83
83
if (IS_ERR(pxproot))
84
84
return;
85
85
+5
-3
drivers/gpu/drm/i915/selftests/intel_uncore.c
+5
-3
drivers/gpu/drm/i915/selftests/intel_uncore.c
···
277
277
#define FW_RANGE 0x40000
278
278
struct intel_gt *gt = arg;
279
279
struct intel_uncore *uncore = gt->uncore;
280
+
struct drm_i915_private *i915 = gt->i915;
281
+
struct intel_display *display = i915->display;
280
282
unsigned long *valid;
281
283
u32 offset;
282
284
int err;
283
285
284
-
if (!HAS_FPGA_DBG_UNCLAIMED(gt->i915) &&
285
-
!IS_VALLEYVIEW(gt->i915) &&
286
-
!IS_CHERRYVIEW(gt->i915))
286
+
if (!HAS_FPGA_DBG_UNCLAIMED(display) &&
287
+
!IS_VALLEYVIEW(i915) &&
288
+
!IS_CHERRYVIEW(i915))
287
289
return 0;
288
290
289
291
/*
+54
-43
drivers/gpu/drm/i915/soc/intel_dram.c
+54
-43
drivers/gpu/drm/i915/soc/intel_dram.c
···
11
11
12
12
#include "i915_drv.h"
13
13
#include "i915_reg.h"
14
+
#include "i915_utils.h"
14
15
#include "intel_dram.h"
15
16
#include "intel_mchbar_regs.h"
16
17
#include "intel_pcode.h"
···
31
30
32
31
#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
33
32
34
-
static const char *intel_dram_type_str(enum intel_dram_type type)
33
+
const char *intel_dram_type_str(enum intel_dram_type type)
35
34
{
36
35
static const char * const str[] = {
37
36
DRAM_TYPE_STR(UNKNOWN),
37
+
DRAM_TYPE_STR(DDR2),
38
38
DRAM_TYPE_STR(DDR3),
39
39
DRAM_TYPE_STR(DDR4),
40
40
DRAM_TYPE_STR(LPDDR3),
···
56
54
57
55
#undef DRAM_TYPE_STR
58
56
59
-
static bool pnv_is_ddr3(struct drm_i915_private *i915)
57
+
static enum intel_dram_type pnv_dram_type(struct drm_i915_private *i915)
60
58
{
61
-
return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
59
+
return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ?
60
+
INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2;
62
61
}
63
62
64
63
static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
···
138
135
return 0;
139
136
}
140
137
141
-
static void detect_mem_freq(struct drm_i915_private *i915)
138
+
unsigned int intel_mem_freq(struct drm_i915_private *i915)
142
139
{
143
140
if (IS_PINEVIEW(i915))
144
-
i915->mem_freq = pnv_mem_freq(i915);
141
+
return pnv_mem_freq(i915);
145
142
else if (GRAPHICS_VER(i915) == 5)
146
-
i915->mem_freq = ilk_mem_freq(i915);
143
+
return ilk_mem_freq(i915);
147
144
else if (IS_CHERRYVIEW(i915))
148
-
i915->mem_freq = chv_mem_freq(i915);
145
+
return chv_mem_freq(i915);
149
146
else if (IS_VALLEYVIEW(i915))
150
-
i915->mem_freq = vlv_mem_freq(i915);
151
-
152
-
if (IS_PINEVIEW(i915))
153
-
i915->is_ddr3 = pnv_is_ddr3(i915);
154
-
155
-
if (i915->mem_freq)
156
-
drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
147
+
return vlv_mem_freq(i915);
148
+
else
149
+
return 0;
157
150
}
158
151
159
-
unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
152
+
static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
160
153
{
161
154
u32 fsb;
162
155
···
234
235
}
235
236
}
236
237
237
-
static void detect_fsb_freq(struct drm_i915_private *i915)
238
+
unsigned int intel_fsb_freq(struct drm_i915_private *i915)
238
239
{
239
240
if (GRAPHICS_VER(i915) == 5)
240
-
i915->fsb_freq = ilk_fsb_freq(i915);
241
+
return ilk_fsb_freq(i915);
241
242
else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
242
-
i915->fsb_freq = i9xx_fsb_freq(i915);
243
+
return i9xx_fsb_freq(i915);
244
+
else
245
+
return 0;
246
+
}
243
247
244
-
if (i915->fsb_freq)
245
-
drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
248
+
static int i915_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
249
+
{
250
+
dram_info->fsb_freq = intel_fsb_freq(i915);
251
+
if (dram_info->fsb_freq)
252
+
drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq);
253
+
254
+
dram_info->mem_freq = intel_mem_freq(i915);
255
+
if (dram_info->mem_freq)
256
+
drm_dbg(&i915->drm, "DDR speed: %d kHz\n", dram_info->mem_freq);
257
+
258
+
if (IS_PINEVIEW(i915))
259
+
dram_info->type = pnv_dram_type(i915);
260
+
261
+
return 0;
246
262
}
247
263
248
264
static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
···
406
392
u32 val;
407
393
int ret;
408
394
395
+
/* Assume 16Gb DIMMs are present until proven otherwise */
396
+
dram_info->has_16gb_dimms = true;
397
+
409
398
val = intel_uncore_read(&i915->uncore,
410
399
SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
411
400
ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
···
431
414
return -EINVAL;
432
415
}
433
416
434
-
dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
417
+
dram_info->has_16gb_dimms = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
435
418
436
419
dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
437
420
438
421
drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
439
422
str_yes_no(dram_info->symmetric_memory));
423
+
424
+
drm_dbg_kms(&i915->drm, "16Gb DIMMs: %s\n",
425
+
str_yes_no(dram_info->has_16gb_dimms));
440
426
441
427
return 0;
442
428
}
···
669
649
670
650
static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
671
651
{
672
-
int ret = skl_get_dram_info(i915, dram_info);
652
+
int ret;
673
653
654
+
ret = skl_dram_get_channels_info(i915, dram_info);
674
655
if (ret)
675
656
return ret;
676
657
···
680
659
681
660
static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
682
661
{
683
-
dram_info->wm_lv_0_adjust_needed = false;
684
-
685
662
return icl_pcode_read_mem_global_info(i915, dram_info);
686
663
}
687
664
···
728
709
729
710
int intel_dram_detect(struct drm_i915_private *i915)
730
711
{
712
+
struct intel_display *display = i915->display;
731
713
struct dram_info *dram_info;
732
714
int ret;
733
715
734
-
detect_fsb_freq(i915);
735
-
detect_mem_freq(i915);
736
-
737
-
if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
716
+
if (IS_DG2(i915) || !HAS_DISPLAY(display))
738
717
return 0;
739
718
740
719
dram_info = drmm_kzalloc(&i915->drm, sizeof(*dram_info), GFP_KERNEL);
···
741
724
742
725
i915->dram_info = dram_info;
743
726
744
-
/*
745
-
* Assume level 0 watermark latency adjustment is needed until proven
746
-
* otherwise, this w/a is not needed by bxt/glk.
747
-
*/
748
-
dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);
749
-
750
-
if (DISPLAY_VER(i915) >= 14)
727
+
if (DISPLAY_VER(display) >= 14)
751
728
ret = xelpdp_get_dram_info(i915, dram_info);
752
729
else if (GRAPHICS_VER(i915) >= 12)
753
730
ret = gen12_get_dram_info(i915, dram_info);
···
749
738
ret = gen11_get_dram_info(i915, dram_info);
750
739
else if (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
751
740
ret = bxt_get_dram_info(i915, dram_info);
752
-
else
741
+
else if (GRAPHICS_VER(i915) >= 9)
753
742
ret = skl_get_dram_info(i915, dram_info);
743
+
else
744
+
ret = i915_get_dram_info(i915, dram_info);
754
745
755
746
drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
756
747
intel_dram_type_str(dram_info->type));
757
748
749
+
drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
750
+
751
+
drm_dbg_kms(&i915->drm, "Num QGV points %u\n", dram_info->num_qgv_points);
752
+
drm_dbg_kms(&i915->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points);
753
+
758
754
/* TODO: Do we want to abort probe on dram detection failures? */
759
755
if (ret)
760
756
return 0;
761
-
762
-
drm_dbg_kms(&i915->drm, "Num qgv points %u\n", dram_info->num_qgv_points);
763
-
764
-
drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
765
-
766
-
drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
767
-
str_yes_no(dram_info->wm_lv_0_adjust_needed));
768
757
769
758
return 0;
770
759
}
+9
-4
drivers/gpu/drm/i915/soc/intel_dram.h
+9
-4
drivers/gpu/drm/i915/soc/intel_dram.h
···
12
12
struct drm_device;
13
13
14
14
struct dram_info {
15
-
bool wm_lv_0_adjust_needed;
16
-
u8 num_channels;
17
-
bool symmetric_memory;
18
15
enum intel_dram_type {
19
16
INTEL_DRAM_UNKNOWN,
17
+
INTEL_DRAM_DDR2,
20
18
INTEL_DRAM_DDR3,
21
19
INTEL_DRAM_DDR4,
22
20
INTEL_DRAM_LPDDR3,
···
25
27
INTEL_DRAM_GDDR_ECC,
26
28
__INTEL_DRAM_TYPE_MAX,
27
29
} type;
30
+
unsigned int fsb_freq;
31
+
unsigned int mem_freq;
32
+
u8 num_channels;
28
33
u8 num_qgv_points;
29
34
u8 num_psf_gv_points;
35
+
bool symmetric_memory;
36
+
bool has_16gb_dimms;
30
37
};
31
38
32
39
void intel_dram_edram_detect(struct drm_i915_private *i915);
33
40
int intel_dram_detect(struct drm_i915_private *i915);
34
-
unsigned int i9xx_fsb_freq(struct drm_i915_private *i915);
41
+
unsigned int intel_fsb_freq(struct drm_i915_private *i915);
42
+
unsigned int intel_mem_freq(struct drm_i915_private *i915);
35
43
const struct dram_info *intel_dram_info(struct drm_device *drm);
44
+
const char *intel_dram_type_str(enum intel_dram_type type);
36
45
37
46
#endif /* __INTEL_DRAM_H__ */
+2
-1
drivers/gpu/drm/i915/soc/intel_gmch.c
+2
-1
drivers/gpu/drm/i915/soc/intel_gmch.c
···
148
148
149
149
int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
150
150
{
151
-
unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
151
+
struct intel_display *display = i915->display;
152
+
unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
152
153
u16 gmch_ctrl;
153
154
154
155
if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
-22
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
-22
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
···
12
12
13
13
#include <drm/drm_drv.h>
14
14
15
-
#include "i915_utils.h"
16
15
#include "xe_device.h" /* for xe_device_has_flat_ccs() */
17
16
#include "xe_device_types.h"
18
17
···
25
26
#define IS_I915G(dev_priv) (dev_priv && 0)
26
27
#define IS_I915GM(dev_priv) (dev_priv && 0)
27
28
#define IS_PINEVIEW(dev_priv) (dev_priv && 0)
28
-
#define IS_IVYBRIDGE(dev_priv) (dev_priv && 0)
29
29
#define IS_VALLEYVIEW(dev_priv) (dev_priv && 0)
30
30
#define IS_CHERRYVIEW(dev_priv) (dev_priv && 0)
31
31
#define IS_HASWELL(dev_priv) (dev_priv && 0)
32
32
#define IS_BROADWELL(dev_priv) (dev_priv && 0)
33
-
#define IS_SKYLAKE(dev_priv) (dev_priv && 0)
34
33
#define IS_BROXTON(dev_priv) (dev_priv && 0)
35
-
#define IS_KABYLAKE(dev_priv) (dev_priv && 0)
36
34
#define IS_GEMINILAKE(dev_priv) (dev_priv && 0)
37
-
#define IS_COFFEELAKE(dev_priv) (dev_priv && 0)
38
-
#define IS_COMETLAKE(dev_priv) (dev_priv && 0)
39
-
#define IS_ICELAKE(dev_priv) (dev_priv && 0)
40
-
#define IS_JASPERLAKE(dev_priv) (dev_priv && 0)
41
-
#define IS_ELKHARTLAKE(dev_priv) (dev_priv && 0)
42
-
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_TIGERLAKE)
43
-
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE)
44
-
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
45
-
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
46
-
#define IS_ALDERLAKE_P(dev_priv) (IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) || \
47
-
IS_PLATFORM(dev_priv, XE_ALDERLAKE_N))
48
35
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
49
-
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
50
-
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
51
-
#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE)
52
-
#define IS_PANTHERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_PANTHERLAKE)
53
-
54
-
#define IS_HASWELL_ULT(dev_priv) (dev_priv && 0)
55
-
#define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)
56
36
57
37
#define IS_MOBILE(xe) (xe && 0)
58
38
+1
drivers/gpu/drm/xe/display/ext/i915_utils.c
+1
drivers/gpu/drm/xe/display/ext/i915_utils.c
+6
drivers/gpu/drm/xe/display/xe_display.c
+6
drivers/gpu/drm/xe/display/xe_display.c
···
96
96
if (!xe->info.probe_display)
97
97
return;
98
98
99
+
intel_hpd_cancel_work(display);
99
100
intel_display_driver_remove_nogem(display);
100
101
intel_display_driver_remove_noirq(display);
101
102
intel_opregion_cleanup(display);
···
341
340
342
341
xe_display_flush_cleanup_work(xe);
343
342
343
+
intel_encoder_block_all_hpds(display);
344
+
344
345
intel_hpd_cancel_work(display);
345
346
346
347
if (has_display(xe)) {
···
373
370
374
371
xe_display_flush_cleanup_work(xe);
375
372
intel_dp_mst_suspend(display);
373
+
intel_encoder_block_all_hpds(display);
376
374
intel_hpd_cancel_work(display);
377
375
378
376
if (has_display(xe))
···
474
470
intel_display_driver_resume_access(display);
475
471
476
472
intel_hpd_init(display);
473
+
474
+
intel_encoder_unblock_all_hpds(display);
477
475
478
476
if (has_display(xe)) {
479
477
intel_display_driver_resume(display);
+9
drivers/gpu/drm/xe/display/xe_fb_pin.c
+9
drivers/gpu/drm/xe/display/xe_fb_pin.c
···
383
383
const struct intel_plane_state *old_plane_state)
384
384
{
385
385
struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb);
386
+
struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
386
387
struct xe_device *xe = to_xe_device(fb->base.dev);
387
388
struct intel_display *display = xe->display;
388
389
struct i915_vma *vma;
···
407
406
found:
408
407
refcount_inc(&vma->ref);
409
408
new_plane_state->ggtt_vma = vma;
409
+
410
+
new_plane_state->surf = i915_ggtt_offset(new_plane_state->ggtt_vma) +
411
+
plane->surf_offset(new_plane_state);
412
+
410
413
return true;
411
414
}
412
415
···
437
432
return PTR_ERR(vma);
438
433
439
434
new_plane_state->ggtt_vma = vma;
435
+
436
+
new_plane_state->surf = i915_ggtt_offset(new_plane_state->ggtt_vma) +
437
+
plane->surf_offset(new_plane_state);
438
+
440
439
return 0;
441
440
}
442
441
+4
drivers/gpu/drm/xe/display/xe_plane_initial.c
+4
drivers/gpu/drm/xe/display/xe_plane_initial.c
···
10
10
#include "xe_ggtt.h"
11
11
#include "xe_mmio.h"
12
12
13
+
#include "i915_vma.h"
13
14
#include "intel_crtc.h"
14
15
#include "intel_display.h"
15
16
#include "intel_display_core.h"
···
236
235
goto nofb;
237
236
238
237
plane_state->ggtt_vma = vma;
238
+
239
+
plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma);
240
+
239
241
plane_state->uapi.src_x = 0;
240
242
plane_state->uapi.src_y = 0;
241
243
plane_state->uapi.src_w = fb->width << 16;
+1
-2
drivers/gpu/drm/xe/xe_device_types.h
+1
-2
drivers/gpu/drm/xe/xe_device_types.h
···
430
430
/** @ordered_wq: used to serialize compute mode resume */
431
431
struct workqueue_struct *ordered_wq;
432
432
433
-
/** @unordered_wq: used to serialize unordered work, mostly display */
433
+
/** @unordered_wq: used to serialize unordered work */
434
434
struct workqueue_struct *unordered_wq;
435
435
436
436
/** @destroy_wq: used to serialize user destroy work, like queue */
···
622
622
struct {
623
623
unsigned int hpll_freq;
624
624
unsigned int czclk_freq;
625
-
unsigned int fsb_freq, mem_freq, is_ddr3;
626
625
};
627
626
#endif
628
627
};
+114
-56
include/linux/iopoll.h
+114
-56
include/linux/iopoll.h
···
14
14
#include <linux/io.h>
15
15
16
16
/**
17
+
* poll_timeout_us - Periodically poll and perform an operation until
18
+
* a condition is met or a timeout occurs
19
+
*
20
+
* @op: Operation
21
+
* @cond: Break condition
22
+
* @sleep_us: Maximum time to sleep between operations in us (0 tight-loops).
23
+
* Please read usleep_range() function description for details and
24
+
* limitations.
25
+
* @timeout_us: Timeout in us, 0 means never timeout
26
+
* @sleep_before_op: if it is true, sleep @sleep_us before operation.
27
+
*
28
+
* When available, you'll probably want to use one of the specialized
29
+
* macros defined below rather than this macro directly.
30
+
*
31
+
* Returns: 0 on success and -ETIMEDOUT upon a timeout. Must not
32
+
* be called from atomic context if sleep_us or timeout_us are used.
33
+
*/
34
+
#define poll_timeout_us(op, cond, sleep_us, timeout_us, sleep_before_op) \
35
+
({ \
36
+
u64 __timeout_us = (timeout_us); \
37
+
unsigned long __sleep_us = (sleep_us); \
38
+
ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
39
+
int ___ret; \
40
+
might_sleep_if((__sleep_us) != 0); \
41
+
if ((sleep_before_op) && __sleep_us) \
42
+
usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
43
+
for (;;) { \
44
+
bool __expired = __timeout_us && \
45
+
ktime_compare(ktime_get(), __timeout) > 0; \
46
+
/* guarantee 'op' and 'cond' are evaluated after timeout expired */ \
47
+
barrier(); \
48
+
op; \
49
+
if (cond) { \
50
+
___ret = 0; \
51
+
break; \
52
+
} \
53
+
if (__expired) { \
54
+
___ret = -ETIMEDOUT; \
55
+
break; \
56
+
} \
57
+
if (__sleep_us) \
58
+
usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
59
+
cpu_relax(); \
60
+
} \
61
+
___ret; \
62
+
})
63
+
64
+
/**
65
+
* poll_timeout_us_atomic - Periodically poll and perform an operation until
66
+
* a condition is met or a timeout occurs
67
+
*
68
+
* @op: Operation
69
+
* @cond: Break condition
70
+
* @delay_us: Time to udelay between operations in us (0 tight-loops).
71
+
* Please read udelay() function description for details and
72
+
* limitations.
73
+
* @timeout_us: Timeout in us, 0 means never timeout
74
+
* @delay_before_op: if it is true, delay @delay_us before operation.
75
+
*
76
+
* This macro does not rely on timekeeping. Hence it is safe to call even when
77
+
* timekeeping is suspended, at the expense of an underestimation of wall clock
78
+
* time, which is rather minimal with a non-zero delay_us.
79
+
*
80
+
* When available, you'll probably want to use one of the specialized
81
+
* macros defined below rather than this macro directly.
82
+
*
83
+
* Returns: 0 on success and -ETIMEDOUT upon a timeout.
84
+
*/
85
+
#define poll_timeout_us_atomic(op, cond, delay_us, timeout_us, \
86
+
delay_before_op) \
87
+
({ \
88
+
u64 __timeout_us = (timeout_us); \
89
+
s64 __left_ns = __timeout_us * NSEC_PER_USEC; \
90
+
unsigned long __delay_us = (delay_us); \
91
+
u64 __delay_ns = __delay_us * NSEC_PER_USEC; \
92
+
int ___ret; \
93
+
if ((delay_before_op) && __delay_us) { \
94
+
udelay(__delay_us); \
95
+
if (__timeout_us) \
96
+
__left_ns -= __delay_ns; \
97
+
} \
98
+
for (;;) { \
99
+
bool __expired = __timeout_us && __left_ns < 0; \
100
+
/* guarantee 'op' and 'cond' are evaluated after timeout expired */ \
101
+
barrier(); \
102
+
op; \
103
+
if (cond) { \
104
+
___ret = 0; \
105
+
break; \
106
+
} \
107
+
if (__expired) { \
108
+
___ret = -ETIMEDOUT; \
109
+
break; \
110
+
} \
111
+
if (__delay_us) { \
112
+
udelay(__delay_us); \
113
+
if (__timeout_us) \
114
+
__left_ns -= __delay_ns; \
115
+
} \
116
+
cpu_relax(); \
117
+
if (__timeout_us) \
118
+
__left_ns--; \
119
+
} \
120
+
___ret; \
121
+
})
122
+
123
+
/**
17
124
* read_poll_timeout - Periodically poll an address until a condition is
18
-
* met or a timeout occurs
125
+
* met or a timeout occurs
19
126
* @op: accessor function (takes @args as its arguments)
20
127
* @val: Variable to read the value into
21
128
* @cond: Break condition (usually involving @val)
···
141
34
* be called from atomic context if sleep_us or timeout_us are used.
142
35
*/
143
36
#define read_poll_timeout(op, val, cond, sleep_us, timeout_us, \
144
-
sleep_before_read, args...) \
145
-
({ \
146
-
u64 __timeout_us = (timeout_us); \
147
-
unsigned long __sleep_us = (sleep_us); \
148
-
ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
149
-
might_sleep_if((__sleep_us) != 0); \
150
-
if (sleep_before_read && __sleep_us) \
151
-
usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
152
-
for (;;) { \
153
-
(val) = op(args); \
154
-
if (cond) \
155
-
break; \
156
-
if (__timeout_us && \
157
-
ktime_compare(ktime_get(), __timeout) > 0) { \
158
-
(val) = op(args); \
159
-
break; \
160
-
} \
161
-
if (__sleep_us) \
162
-
usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
163
-
cpu_relax(); \
164
-
} \
165
-
(cond) ? 0 : -ETIMEDOUT; \
166
-
})
37
+
sleep_before_read, args...) \
38
+
poll_timeout_us((val) = op(args), cond, sleep_us, timeout_us, sleep_before_read)
167
39
168
40
/**
169
41
* read_poll_timeout_atomic - Periodically poll an address until a condition is
170
-
* met or a timeout occurs
42
+
* met or a timeout occurs
171
43
* @op: accessor function (takes @args as its arguments)
172
44
* @val: Variable to read the value into
173
45
* @cond: Break condition (usually involving @val)
···
167
81
* Returns: 0 on success and -ETIMEDOUT upon a timeout. In either
168
82
* case, the last read value at @args is stored in @val.
169
83
*/
170
-
#define read_poll_timeout_atomic(op, val, cond, delay_us, timeout_us, \
171
-
delay_before_read, args...) \
172
-
({ \
173
-
u64 __timeout_us = (timeout_us); \
174
-
s64 __left_ns = __timeout_us * NSEC_PER_USEC; \
175
-
unsigned long __delay_us = (delay_us); \
176
-
u64 __delay_ns = __delay_us * NSEC_PER_USEC; \
177
-
if (delay_before_read && __delay_us) { \
178
-
udelay(__delay_us); \
179
-
if (__timeout_us) \
180
-
__left_ns -= __delay_ns; \
181
-
} \
182
-
for (;;) { \
183
-
(val) = op(args); \
184
-
if (cond) \
185
-
break; \
186
-
if (__timeout_us && __left_ns < 0) { \
187
-
(val) = op(args); \
188
-
break; \
189
-
} \
190
-
if (__delay_us) { \
191
-
udelay(__delay_us); \
192
-
if (__timeout_us) \
193
-
__left_ns -= __delay_ns; \
194
-
} \
195
-
cpu_relax(); \
196
-
if (__timeout_us) \
197
-
__left_ns--; \
198
-
} \
199
-
(cond) ? 0 : -ETIMEDOUT; \
200
-
})
84
+
#define read_poll_timeout_atomic(op, val, cond, sleep_us, timeout_us, \
85
+
sleep_before_read, args...) \
86
+
poll_timeout_us_atomic((val) = op(args), cond, sleep_us, timeout_us, sleep_before_read)
201
87
202
88
/**
203
89
* readx_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs