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drm/i915/dp: Use the effective data rate for DP BW calculation

Use intel_dp_effective_data_rate() to calculate the required link BW for
eDP, DP-SST and MST links. This ensures that the BW is calculated the
same way for all DP output types, during mode validation as well as
during state computation. This approach also allows for accounting with
BW overheads due to the SSC, DSC, FEC being enabled on a link, as well
as due to the MST symbol alignment on the link. Accounting for these
overheads will be added by follow-up changes.

This way also computes the stream BW on a UHBR link correctly, using the
corresponding symbol size to effective data size ratio (i.e. ~97% link
BW utilization for UHBR vs. only ~80% for non-UHBR).

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-9-imre.deak@intel.com

Imre Deak b1ec2916 3999f6d7

+33 -19
+24 -16
drivers/gpu/drm/i915/display/intel_dp.c
··· 453 453 /* 454 454 * The required data bandwidth for a mode with given pixel clock and bpp. This 455 455 * is the required net bandwidth independent of the data bandwidth efficiency. 456 - * 457 - * TODO: check if callers of this functions should use 458 - * intel_dp_effective_data_rate() instead. 459 456 */ 460 - int 461 - intel_dp_link_required(int pixel_clock, int bpp) 457 + int intel_dp_link_required(int link_clock, int lane_count, 458 + int mode_clock, int mode_hdisplay, 459 + int link_bpp_x16, unsigned long bw_overhead_flags) 462 460 { 463 - /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 464 - return DIV_ROUND_UP(pixel_clock * bpp, 8); 461 + int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdisplay, 462 + 0, link_bpp_x16, bw_overhead_flags); 463 + 464 + return intel_dp_effective_data_rate(mode_clock, link_bpp_x16, bw_overhead); 465 465 } 466 466 467 467 /** ··· 1532 1532 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1533 1533 1534 1534 link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); 1535 - mode_rate = intel_dp_link_required(target_clock, fxp_q4_to_int_roundup(link_bpp_x16)); 1535 + mode_rate = intel_dp_link_required(max_link_clock, max_lanes, 1536 + target_clock, mode->hdisplay, 1537 + link_bpp_x16, 0); 1536 1538 1537 1539 if (intel_dp_has_dsc(connector)) { 1538 1540 int pipe_bpp; ··· 1841 1839 const struct link_config_limits *limits) 1842 1840 { 1843 1841 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1844 - int mode_rate, link_rate, link_avail; 1842 + int link_rate, link_avail; 1845 1843 1846 1844 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1847 1845 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1848 1846 bpp -= 2 * 3) { 1849 1847 int link_bpp_x16 = 1850 1848 intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); 1851 - 1852 - mode_rate = intel_dp_link_required(clock, fxp_q4_to_int_roundup(link_bpp_x16)); 1853 1849 1854 1850 for (i = 0; i < intel_dp->num_common_rates; i++) { 1855 1851 link_rate = intel_dp_common_rate(intel_dp, i); ··· 1858 1858 for (lane_count = limits->min_lane_count; 1859 1859 lane_count <= limits->max_lane_count; 1860 1860 lane_count <<= 1) { 1861 + const struct drm_display_mode *adjusted_mode = 1862 + &pipe_config->hw.adjusted_mode; 1863 + int mode_rate = 1864 + intel_dp_link_required(link_rate, lane_count, 1865 + clock, adjusted_mode->hdisplay, 1866 + link_bpp_x16, 0); 1867 + 1861 1868 link_avail = intel_dp_max_link_data_rate(intel_dp, 1862 1869 link_rate, 1863 1870 lane_count); 1864 - 1865 1871 1866 1872 if (mode_rate <= link_avail) { 1867 1873 pipe_config->lane_count = lane_count; ··· 2731 2725 { 2732 2726 const struct drm_display_mode *adjusted_mode = 2733 2727 &crtc_state->hw.adjusted_mode; 2734 - int bpp = crtc_state->dsc.compression_enable ? 2735 - fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2736 - crtc_state->pipe_bpp; 2728 + int link_bpp_x16 = crtc_state->dsc.compression_enable ? 2729 + crtc_state->dsc.compressed_bpp_x16 : 2730 + fxp_q4_from_int(crtc_state->pipe_bpp); 2737 2731 2738 - return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2732 + return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count, 2733 + adjusted_mode->crtc_clock, adjusted_mode->hdisplay, 2734 + link_bpp_x16, 0); 2739 2735 } 2740 2736 2741 2737 bool intel_dp_joiner_needs_dsc(struct intel_display *display,
+3 -1
drivers/gpu/drm/i915/display/intel_dp.h
··· 119 119 120 120 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 121 121 int dsc_slice_count, int bpp_x16, unsigned long flags); 122 - int intel_dp_link_required(int pixel_clock, int bpp); 122 + int intel_dp_link_required(int link_clock, int lane_count, 123 + int mode_clock, int mode_hdisplay, 124 + int link_bpp_x16, unsigned long bw_overhead_flags); 123 125 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 124 126 int bw_overhead); 125 127 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
+3 -1
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 1489 1489 1490 1490 max_rate = intel_dp_max_link_data_rate(intel_dp, 1491 1491 max_link_clock, max_lanes); 1492 - mode_rate = intel_dp_link_required(mode->clock, min_bpp); 1492 + mode_rate = intel_dp_link_required(max_link_clock, max_lanes, 1493 + mode->clock, mode->hdisplay, 1494 + fxp_q4_from_int(min_bpp), 0); 1493 1495 1494 1496 /* 1495 1497 * TODO: