tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
"Another round of MIPS fixes:

- compressed boot: Ignore a generated .c file

- VDSO: Fix a register clobber list

- DECstation: Fix an int-handler.S CPU_DADDI_WORKAROUNDS regression

- Octeon: Fix recent cleanups that cleaned away a bit too much thus
breaking the arch side of the EDAC and USB drivers.

- uasm: Fix duplicate const in "const struct foo const bar[]" which
GCC 7.1 no longer accepts.

- Fix race on setting and getting cpu_online_mask

- Fix preemption issue. To do so cleanly introduce macro to get the
size of L3 cache line.

- Revert include cleanup that sometimes results in build error

- MicroMIPS uses bit 0 of the PC to indicate microMIPS mode. Make
sure this bit is set for kernel entry as well.

- Prevent configuring the kernel for both microMIPS and MT. There are
no such CPUs currently and thus the combination is unsupported and
results in build errors.

This has been sitting in linux-next for a few days and has survived
automated testing by Imagination's test farm. No known regressions
pending except a number of issues that crept up due to lots of people
switching to GCC 7.1"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Set ISA bit in entry-y for microMIPS kernels
MIPS: Prevent building MT support for microMIPS kernels
MIPS: PCI: Fix smp_processor_id() in preemptible
MIPS: Introduce cpu_tcache_line_size
MIPS: DEC: Fix an int-handler.S CPU_DADDI_WORKAROUNDS regression
MIPS: VDSO: Fix clobber lists in fallback code paths
Revert "MIPS: Don't unnecessarily include kmalloc.h into <asm/cache.h>."
MIPS: OCTEON: Fix USB platform code breakage.
MIPS: Octeon: Fix broken EDAC driver.
MIPS: gitignore: ignore generated .c files
MIPS: Fix race on setting and getting cpu_online_mask
MIPS: mm: remove duplicate "const" qualifier on insn_table

Linus Torvalds b2298fc9 c9dc281d

+137 -42
+1 -1
arch/mips/Kconfig
··· 2260 2260 2261 2261 config MIPS_MT_SMP 2262 2262 bool "MIPS MT SMP support (1 TC on each available VPE)" 2263 - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 2263 + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS 2264 2264 select CPU_MIPSR2_IRQ_VI 2265 2265 select CPU_MIPSR2_IRQ_EI 2266 2266 select SYNC_R4K
+14 -1
arch/mips/Makefile
··· 243 243 ifdef CONFIG_PHYSICAL_START 244 244 load-y = $(CONFIG_PHYSICAL_START) 245 245 endif 246 - entry-y = 0x$(shell $(NM) vmlinux 2>/dev/null \ 246 + 247 + entry-noisa-y = 0x$(shell $(NM) vmlinux 2>/dev/null \ 247 248 | grep "\bkernel_entry\b" | cut -f1 -d \ ) 249 + ifdef CONFIG_CPU_MICROMIPS 250 + # 251 + # Set the ISA bit, since the kernel_entry symbol in the ELF will have it 252 + # clear which would lead to images containing addresses which bootloaders may 253 + # jump to as MIPS32 code. 254 + # 255 + entry-y = $(patsubst %0,%1,$(patsubst %2,%3,$(patsubst %4,%5, \ 256 + $(patsubst %6,%7,$(patsubst %8,%9,$(patsubst %a,%b, \ 257 + $(patsubst %c,%d,$(patsubst %e,%f,$(entry-noisa-y))))))))) 258 + else 259 + entry-y = $(entry-noisa-y) 260 + endif 248 261 249 262 cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 250 263 drivers-$(CONFIG_PCI) += arch/mips/pci/
+2
arch/mips/boot/compressed/.gitignore
··· 1 + ashldi3.c 2 + bswapsi.c
+1 -1
arch/mips/cavium-octeon/octeon-usb.c
··· 13 13 #include <linux/mutex.h> 14 14 #include <linux/delay.h> 15 15 #include <linux/of_platform.h> 16 + #include <linux/io.h> 16 17 17 18 #include <asm/octeon/octeon.h> 18 - #include <asm/octeon/cvmx-gpio-defs.h> 19 19 20 20 /* USB Control Register */ 21 21 union cvm_usbdrd_uctl_ctl {
+6 -28
arch/mips/dec/int-handler.S
··· 147 147 * Find irq with highest priority 148 148 */ 149 149 # open coded PTR_LA t1, cpu_mask_nr_tbl 150 - #if (_MIPS_SZPTR == 32) 150 + #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 151 151 # open coded la t1, cpu_mask_nr_tbl 152 152 lui t1, %hi(cpu_mask_nr_tbl) 153 153 addiu t1, %lo(cpu_mask_nr_tbl) 154 - 155 - #endif 156 - #if (_MIPS_SZPTR == 64) 157 - # open coded dla t1, cpu_mask_nr_tbl 158 - .set push 159 - .set noat 160 - lui t1, %highest(cpu_mask_nr_tbl) 161 - lui AT, %hi(cpu_mask_nr_tbl) 162 - daddiu t1, t1, %higher(cpu_mask_nr_tbl) 163 - daddiu AT, AT, %lo(cpu_mask_nr_tbl) 164 - dsll t1, 32 165 - daddu t1, t1, AT 166 - .set pop 154 + #else 155 + #error GCC `-msym32' option required for 64-bit DECstation builds 167 156 #endif 168 157 1: lw t2,(t1) 169 158 nop ··· 203 214 * Find irq with highest priority 204 215 */ 205 216 # open coded PTR_LA t1,asic_mask_nr_tbl 206 - #if (_MIPS_SZPTR == 32) 217 + #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 207 218 # open coded la t1, asic_mask_nr_tbl 208 219 lui t1, %hi(asic_mask_nr_tbl) 209 220 addiu t1, %lo(asic_mask_nr_tbl) 210 - 211 - #endif 212 - #if (_MIPS_SZPTR == 64) 213 - # open coded dla t1, asic_mask_nr_tbl 214 - .set push 215 - .set noat 216 - lui t1, %highest(asic_mask_nr_tbl) 217 - lui AT, %hi(asic_mask_nr_tbl) 218 - daddiu t1, t1, %higher(asic_mask_nr_tbl) 219 - daddiu AT, AT, %lo(asic_mask_nr_tbl) 220 - dsll t1, 32 221 - daddu t1, t1, AT 222 - .set pop 221 + #else 222 + #error GCC `-msym32' option required for 64-bit DECstation builds 223 223 #endif 224 224 2: lw t2,(t1) 225 225 nop
+2
arch/mips/include/asm/cache.h
··· 9 9 #ifndef _ASM_CACHE_H 10 10 #define _ASM_CACHE_H 11 11 12 + #include <kmalloc.h> 13 + 12 14 #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 13 15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 14 16
+3
arch/mips/include/asm/cpu-features.h
··· 428 428 #ifndef cpu_scache_line_size 429 429 #define cpu_scache_line_size() cpu_data[0].scache.linesz 430 430 #endif 431 + #ifndef cpu_tcache_line_size 432 + #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 433 + #endif 431 434 432 435 #ifndef cpu_hwrena_impl_bits 433 436 #define cpu_hwrena_impl_bits 0
+36 -1
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
··· 33 33 #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) 34 34 #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) 35 35 #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) 36 + #define CVMX_L2C_ERR_TDTX(block_id) \ 37 + (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) 38 + #define CVMX_L2C_ERR_TTGX(block_id) \ 39 + (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) 36 40 #define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull)) 37 41 #define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull)) 38 42 #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) ··· 70 66 ((offset) & 1) * 8) 71 67 #define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \ 72 68 ((offset) & 31) * 8) 73 - #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) 74 69 70 + 71 + union cvmx_l2c_err_tdtx { 72 + uint64_t u64; 73 + struct cvmx_l2c_err_tdtx_s { 74 + __BITFIELD_FIELD(uint64_t dbe:1, 75 + __BITFIELD_FIELD(uint64_t sbe:1, 76 + __BITFIELD_FIELD(uint64_t vdbe:1, 77 + __BITFIELD_FIELD(uint64_t vsbe:1, 78 + __BITFIELD_FIELD(uint64_t syn:10, 79 + __BITFIELD_FIELD(uint64_t reserved_22_49:28, 80 + __BITFIELD_FIELD(uint64_t wayidx:18, 81 + __BITFIELD_FIELD(uint64_t reserved_2_3:2, 82 + __BITFIELD_FIELD(uint64_t type:2, 83 + ;))))))))) 84 + } s; 85 + }; 86 + 87 + union cvmx_l2c_err_ttgx { 88 + uint64_t u64; 89 + struct cvmx_l2c_err_ttgx_s { 90 + __BITFIELD_FIELD(uint64_t dbe:1, 91 + __BITFIELD_FIELD(uint64_t sbe:1, 92 + __BITFIELD_FIELD(uint64_t noway:1, 93 + __BITFIELD_FIELD(uint64_t reserved_56_60:5, 94 + __BITFIELD_FIELD(uint64_t syn:6, 95 + __BITFIELD_FIELD(uint64_t reserved_22_49:28, 96 + __BITFIELD_FIELD(uint64_t wayidx:15, 97 + __BITFIELD_FIELD(uint64_t reserved_2_6:5, 98 + __BITFIELD_FIELD(uint64_t type:2, 99 + ;))))))))) 100 + } s; 101 + }; 75 102 76 103 union cvmx_l2c_cfg { 77 104 uint64_t u64;
+60
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
··· 1 + /***********************license start*************** 2 + * Author: Cavium Networks 3 + * 4 + * Contact: support@caviumnetworks.com 5 + * This file is part of the OCTEON SDK 6 + * 7 + * Copyright (c) 2003-2017 Cavium, Inc. 8 + * 9 + * This file is free software; you can redistribute it and/or modify 10 + * it under the terms of the GNU General Public License, Version 2, as 11 + * published by the Free Software Foundation. 12 + * 13 + * This file is distributed in the hope that it will be useful, but 14 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 + * NONINFRINGEMENT. See the GNU General Public License for more 17 + * details. 18 + * 19 + * You should have received a copy of the GNU General Public License 20 + * along with this file; if not, write to the Free Software 21 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 + * or visit http://www.gnu.org/licenses/. 23 + * 24 + * This file may also be available under a different license from Cavium. 25 + * Contact Cavium Networks for more information 26 + ***********************license end**************************************/ 27 + 28 + #ifndef __CVMX_L2D_DEFS_H__ 29 + #define __CVMX_L2D_DEFS_H__ 30 + 31 + #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull)) 32 + #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) 33 + 34 + 35 + union cvmx_l2d_err { 36 + uint64_t u64; 37 + struct cvmx_l2d_err_s { 38 + __BITFIELD_FIELD(uint64_t reserved_6_63:58, 39 + __BITFIELD_FIELD(uint64_t bmhclsel:1, 40 + __BITFIELD_FIELD(uint64_t ded_err:1, 41 + __BITFIELD_FIELD(uint64_t sec_err:1, 42 + __BITFIELD_FIELD(uint64_t ded_intena:1, 43 + __BITFIELD_FIELD(uint64_t sec_intena:1, 44 + __BITFIELD_FIELD(uint64_t ecc_ena:1, 45 + ;))))))) 46 + } s; 47 + }; 48 + 49 + union cvmx_l2d_fus3 { 50 + uint64_t u64; 51 + struct cvmx_l2d_fus3_s { 52 + __BITFIELD_FIELD(uint64_t reserved_40_63:24, 53 + __BITFIELD_FIELD(uint64_t ema_ctl:3, 54 + __BITFIELD_FIELD(uint64_t reserved_34_36:3, 55 + __BITFIELD_FIELD(uint64_t q3fus:34, 56 + ;)))) 57 + } s; 58 + }; 59 + 60 + #endif
+1
arch/mips/include/asm/octeon/cvmx.h
··· 62 62 #include <asm/octeon/cvmx-iob-defs.h> 63 63 #include <asm/octeon/cvmx-ipd-defs.h> 64 64 #include <asm/octeon/cvmx-l2c-defs.h> 65 + #include <asm/octeon/cvmx-l2d-defs.h> 65 66 #include <asm/octeon/cvmx-l2t-defs.h> 66 67 #include <asm/octeon/cvmx-led-defs.h> 67 68 #include <asm/octeon/cvmx-mio-defs.h>
+3 -3
arch/mips/kernel/smp.c
··· 376 376 cpumask_set_cpu(cpu, &cpu_coherent_mask); 377 377 notify_cpu_starting(cpu); 378 378 379 - complete(&cpu_running); 380 - synchronise_count_slave(cpu); 381 - 382 379 set_cpu_online(cpu, true); 383 380 384 381 set_cpu_sibling_map(cpu); 385 382 set_cpu_core_map(cpu); 386 383 387 384 calculate_cpu_foreign_map(); 385 + 386 + complete(&cpu_running); 387 + synchronise_count_slave(cpu); 388 388 389 389 /* 390 390 * irq will be enabled in ->smp_finish(), enabling it too early
+1 -1
arch/mips/mm/uasm-mips.c
··· 48 48 49 49 #include "uasm.c" 50 50 51 - static const struct insn const insn_table[insn_invalid] = { 51 + static const struct insn insn_table[insn_invalid] = { 52 52 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 53 53 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, 54 54 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
+3 -4
arch/mips/pci/pci.c
··· 28 28 29 29 static int __init pcibios_set_cache_line_size(void) 30 30 { 31 - struct cpuinfo_mips *c = &current_cpu_data; 32 31 unsigned int lsize; 33 32 34 33 /* 35 34 * Set PCI cacheline size to that of the highest level in the 36 35 * cache hierarchy. 37 36 */ 38 - lsize = c->dcache.linesz; 39 - lsize = c->scache.linesz ? : lsize; 40 - lsize = c->tcache.linesz ? : lsize; 37 + lsize = cpu_dcache_line_size(); 38 + lsize = cpu_scache_line_size() ? : lsize; 39 + lsize = cpu_tcache_line_size() ? : lsize; 41 40 42 41 BUG_ON(!lsize); 43 42
+4 -2
arch/mips/vdso/gettimeofday.c
··· 35 35 " syscall\n" 36 36 : "=r" (ret), "=r" (error) 37 37 : "r" (tv), "r" (tz), "r" (nr) 38 - : "memory"); 38 + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13", 39 + "$14", "$15", "$24", "$25", "hi", "lo", "memory"); 39 40 40 41 return error ? -ret : ret; 41 42 } ··· 56 55 " syscall\n" 57 56 : "=r" (ret), "=r" (error) 58 57 : "r" (clkid), "r" (ts), "r" (nr) 59 - : "memory"); 58 + : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13", 59 + "$14", "$15", "$24", "$25", "hi", "lo", "memory"); 60 60 61 61 return error ? -ret : ret; 62 62 }