Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
accel/amdxdna: Support getting last hardware error
Add new parameter DRM_AMDXDNA_HW_LAST_ASYNC_ERR to get array IOCTL. When
hardware reports an error, the driver save the error information and
timestamp. This new get array parameter retrieves the last error.
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://lore.kernel.org/r/20251014234119.628453-1-lizhi.hou@amd.com
+159
-19
+78
-17
drivers/accel/amdxdna/aie2_error.c
+78
-17
drivers/accel/amdxdna/aie2_error.c
···
13
13
14
14
#include "aie2_msg_priv.h"
15
15
#include "aie2_pci.h"
16
+
#include "amdxdna_error.h"
16
17
#include "amdxdna_mailbox.h"
17
18
#include "amdxdna_pci_drv.h"
18
19
···
47
46
AIE_MEM_MOD = 0,
48
47
AIE_CORE_MOD,
49
48
AIE_PL_MOD,
49
+
AIE_UNKNOWN_MOD,
50
50
};
51
51
52
52
enum aie_error_category {
···
145
143
EVENT_CATEGORY(74U, AIE_ERROR_LOCK),
146
144
};
147
145
146
+
static const enum amdxdna_error_num aie_cat_err_num_map[] = {
147
+
[AIE_ERROR_SATURATION] = AMDXDNA_ERROR_NUM_AIE_SATURATION,
148
+
[AIE_ERROR_FP] = AMDXDNA_ERROR_NUM_AIE_FP,
149
+
[AIE_ERROR_STREAM] = AMDXDNA_ERROR_NUM_AIE_STREAM,
150
+
[AIE_ERROR_ACCESS] = AMDXDNA_ERROR_NUM_AIE_ACCESS,
151
+
[AIE_ERROR_BUS] = AMDXDNA_ERROR_NUM_AIE_BUS,
152
+
[AIE_ERROR_INSTRUCTION] = AMDXDNA_ERROR_NUM_AIE_INSTRUCTION,
153
+
[AIE_ERROR_ECC] = AMDXDNA_ERROR_NUM_AIE_ECC,
154
+
[AIE_ERROR_LOCK] = AMDXDNA_ERROR_NUM_AIE_LOCK,
155
+
[AIE_ERROR_DMA] = AMDXDNA_ERROR_NUM_AIE_DMA,
156
+
[AIE_ERROR_MEM_PARITY] = AMDXDNA_ERROR_NUM_AIE_MEM_PARITY,
157
+
[AIE_ERROR_UNKNOWN] = AMDXDNA_ERROR_NUM_UNKNOWN,
158
+
};
159
+
160
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static_assert(ARRAY_SIZE(aie_cat_err_num_map) == AIE_ERROR_UNKNOWN + 1);
161
+
162
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static const enum amdxdna_error_module aie_err_mod_map[] = {
163
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[AIE_MEM_MOD] = AMDXDNA_ERROR_MODULE_AIE_MEMORY,
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[AIE_CORE_MOD] = AMDXDNA_ERROR_MODULE_AIE_CORE,
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[AIE_PL_MOD] = AMDXDNA_ERROR_MODULE_AIE_PL,
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[AIE_UNKNOWN_MOD] = AMDXDNA_ERROR_MODULE_UNKNOWN,
167
+
};
168
+
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+
static_assert(ARRAY_SIZE(aie_err_mod_map) == AIE_UNKNOWN_MOD + 1);
170
+
148
171
static enum aie_error_category
149
172
aie_get_error_category(u8 row, u8 event_id, enum aie_module_type mod_type)
150
173
{
···
203
176
if (event_id != lut[i].event_id)
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177
continue;
205
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+
if (lut[i].category > AIE_ERROR_UNKNOWN)
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return AIE_ERROR_UNKNOWN;
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+
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return lut[i].category;
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183
}
208
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return AIE_ERROR_UNKNOWN;
186
+
}
187
+
188
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static void aie2_update_last_async_error(struct amdxdna_dev_hdl *ndev, void *err_info, u32 num_err)
189
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{
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struct aie_error *errs = err_info;
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enum amdxdna_error_module err_mod;
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enum aie_error_category aie_err;
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enum amdxdna_error_num err_num;
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struct aie_error *last_err;
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+
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last_err = &errs[num_err - 1];
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if (last_err->mod_type >= AIE_UNKNOWN_MOD) {
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err_num = aie_cat_err_num_map[AIE_ERROR_UNKNOWN];
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err_mod = aie_err_mod_map[AIE_UNKNOWN_MOD];
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} else {
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aie_err = aie_get_error_category(last_err->row,
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last_err->event_id,
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last_err->mod_type);
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err_num = aie_cat_err_num_map[aie_err];
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err_mod = aie_err_mod_map[last_err->mod_type];
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}
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ndev->last_async_err.err_code = AMDXDNA_ERROR_ENCODE(err_num, err_mod);
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ndev->last_async_err.ts_us = ktime_to_us(ktime_get_real());
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ndev->last_async_err.ex_err_code = AMDXDNA_EXTRA_ERR_ENCODE(last_err->row, last_err->col);
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}
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static u32 aie2_error_backtrack(struct amdxdna_dev_hdl *ndev, void *err_info, u32 num_err)
···
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}
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mutex_lock(&xdna->dev_lock);
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aie2_update_last_async_error(e->ndev, info->payload, info->err_cnt);
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/* Re-sent this event to firmware */
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if (aie2_error_event_send(e))
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XDNA_WARN(xdna, "Unable to register async event");
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mutex_unlock(&xdna->dev_lock);
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-
}
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int aie2_error_async_events_send(struct amdxdna_dev_hdl *ndev)
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{
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struct amdxdna_dev *xdna = ndev->xdna;
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struct async_event *e;
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int i, ret;
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-
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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for (i = 0; i < ndev->async_events->event_cnt; i++) {
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e = &ndev->async_events->event[i];
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ret = aie2_error_event_send(e);
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if (ret)
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return ret;
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-
}
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-
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-
return 0;
343
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}
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void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev)
···
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e->size = ASYNC_BUF_SIZE;
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e->resp.status = MAX_AIE2_STATUS_CODE;
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INIT_WORK(&e->work, aie2_error_worker);
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+
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ret = aie2_error_event_send(e);
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if (ret)
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goto free_wq;
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}
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ndev->async_events = events;
···
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events->event_cnt, events->size);
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return 0;
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free_wq:
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destroy_workqueue(events->wq);
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free_buf:
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dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf,
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events->addr, DMA_FROM_DEVICE);
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free_events:
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kfree(events);
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return ret;
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}
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int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev, struct amdxdna_drm_get_array *args)
363
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{
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struct amdxdna_dev *xdna = ndev->xdna;
365
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drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
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args->num_element = 1;
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args->element_size = sizeof(ndev->last_async_err);
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if (copy_to_user(u64_to_user_ptr(args->buffer),
371
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&ndev->last_async_err, args->element_size))
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return -EFAULT;
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return 0;
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}
+3
drivers/accel/amdxdna/aie2_pci.c
+3
drivers/accel/amdxdna/aie2_pci.c
···
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case DRM_AMDXDNA_HW_CONTEXT_ALL:
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ret = aie2_query_ctx_status_array(client, args);
926
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break;
927
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case DRM_AMDXDNA_HW_LAST_ASYNC_ERR:
928
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ret = aie2_get_array_async_error(xdna->dev_handle, args);
929
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break;
927
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default:
928
931
XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
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ret = -EOPNOTSUPP;
+4
-1
drivers/accel/amdxdna/aie2_pci.h
+4
-1
drivers/accel/amdxdna/aie2_pci.h
···
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enum aie2_dev_status dev_status;
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u32 hwctx_num;
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struct amdxdna_async_error last_async_err;
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};
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#define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \
···
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/* aie2_error.c */
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int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev);
257
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void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev);
258
-
int aie2_error_async_events_send(struct amdxdna_dev_hdl *ndev);
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int aie2_error_async_msg_thread(void *data);
257
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int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev,
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struct amdxdna_drm_get_array *args);
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/* aie2_message.c */
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int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev);
+59
drivers/accel/amdxdna/amdxdna_error.h
+59
drivers/accel/amdxdna/amdxdna_error.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
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/*
3
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* Copyright (C) 2025, Advanced Micro Devices, Inc.
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+
*/
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+
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#ifndef _AMDXDNA_ERROR_H_
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+
#define _AMDXDNA_ERROR_H_
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+
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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+
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#define AMDXDNA_ERR_DRV_AIE 4
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#define AMDXDNA_ERR_SEV_CRITICAL 3
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#define AMDXDNA_ERR_CLASS_AIE 2
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+
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#define AMDXDNA_ERR_NUM_MASK GENMASK_U64(15, 0)
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#define AMDXDNA_ERR_DRV_MASK GENMASK_U64(23, 16)
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#define AMDXDNA_ERR_SEV_MASK GENMASK_U64(31, 24)
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#define AMDXDNA_ERR_MOD_MASK GENMASK_U64(39, 32)
20
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#define AMDXDNA_ERR_CLASS_MASK GENMASK_U64(47, 40)
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+
22
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enum amdxdna_error_num {
23
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AMDXDNA_ERROR_NUM_AIE_SATURATION = 3,
24
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AMDXDNA_ERROR_NUM_AIE_FP,
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AMDXDNA_ERROR_NUM_AIE_STREAM,
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AMDXDNA_ERROR_NUM_AIE_ACCESS,
27
+
AMDXDNA_ERROR_NUM_AIE_BUS,
28
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AMDXDNA_ERROR_NUM_AIE_INSTRUCTION,
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AMDXDNA_ERROR_NUM_AIE_ECC,
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AMDXDNA_ERROR_NUM_AIE_LOCK,
31
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AMDXDNA_ERROR_NUM_AIE_DMA,
32
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AMDXDNA_ERROR_NUM_AIE_MEM_PARITY,
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AMDXDNA_ERROR_NUM_UNKNOWN = 15,
34
+
};
35
+
36
+
enum amdxdna_error_module {
37
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AMDXDNA_ERROR_MODULE_AIE_CORE = 3,
38
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AMDXDNA_ERROR_MODULE_AIE_MEMORY,
39
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AMDXDNA_ERROR_MODULE_AIE_SHIM,
40
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AMDXDNA_ERROR_MODULE_AIE_NOC,
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AMDXDNA_ERROR_MODULE_AIE_PL,
42
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AMDXDNA_ERROR_MODULE_UNKNOWN = 8,
43
+
};
44
+
45
+
#define AMDXDNA_ERROR_ENCODE(err_num, err_mod) \
46
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(FIELD_PREP(AMDXDNA_ERR_NUM_MASK, err_num) | \
47
+
FIELD_PREP_CONST(AMDXDNA_ERR_DRV_MASK, AMDXDNA_ERR_DRV_AIE) | \
48
+
FIELD_PREP_CONST(AMDXDNA_ERR_SEV_MASK, AMDXDNA_ERR_SEV_CRITICAL) | \
49
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FIELD_PREP(AMDXDNA_ERR_MOD_MASK, err_mod) | \
50
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FIELD_PREP_CONST(AMDXDNA_ERR_CLASS_MASK, AMDXDNA_ERR_CLASS_AIE))
51
+
52
+
#define AMDXDNA_EXTRA_ERR_COL_MASK GENMASK_U64(7, 0)
53
+
#define AMDXDNA_EXTRA_ERR_ROW_MASK GENMASK_U64(15, 8)
54
+
55
+
#define AMDXDNA_EXTRA_ERR_ENCODE(row, col) \
56
+
(FIELD_PREP(AMDXDNA_EXTRA_ERR_COL_MASK, col) | \
57
+
FIELD_PREP(AMDXDNA_EXTRA_ERR_ROW_MASK, row))
58
+
59
+
#endif /* _AMDXDNA_ERROR_H_ */
+2
-1
drivers/accel/amdxdna/amdxdna_pci_drv.c
+2
-1
drivers/accel/amdxdna/amdxdna_pci_drv.c
···
27
27
/*
28
28
* 0.0: Initial version
29
29
* 0.1: Support getting all hardware contexts by DRM_IOCTL_AMDXDNA_GET_ARRAY
30
+
* 0.2: Support getting last error hardware error
30
31
*/
31
32
#define AMDXDNA_DRIVER_MAJOR 0
32
-
#define AMDXDNA_DRIVER_MINOR 1
33
+
#define AMDXDNA_DRIVER_MINOR 2
33
34
34
35
/*
35
36
* Bind the driver base on (vendor_id, device_id) pair and later use the
+13
include/uapi/drm/amdxdna_accel.h
+13
include/uapi/drm/amdxdna_accel.h
···
523
523
__u32 pad;
524
524
};
525
525
526
+
/**
527
+
* struct amdxdna_async_error - XDNA async error structure
528
+
*/
529
+
struct amdxdna_async_error {
530
+
/** @err_code: Error code. */
531
+
__u64 err_code;
532
+
/** @ts_us: Timestamp. */
533
+
__u64 ts_us;
534
+
/** @ex_err_code: Extra error code */
535
+
__u64 ex_err_code;
536
+
};
537
+
526
538
#define DRM_AMDXDNA_HW_CONTEXT_ALL 0
539
+
#define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2
527
540
528
541
/**
529
542
* struct amdxdna_drm_get_array - Get information array.