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iommu/amd: Always enable GCR3TRPMode when supported.

The GCR3TRPMode feature allows the DTE[GCR3TRP] field to be configured
with GPA (instead of SPA). This simplifies the implementation, and is
a pre-requisite for nested translation support.

Therefore, always enable this feature if available.

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

authored by

Suravee Suthikulpanit and committed by
Joerg Roedel b2bb0573 e05698c1

+10
+2
drivers/iommu/amd/amd_iommu_types.h
··· 108 108 109 109 /* Extended Feature 2 Bits */ 110 110 #define FEATURE_SEVSNPIO_SUP BIT_ULL(1) 111 + #define FEATURE_GCR3TRPMODE BIT_ULL(3) 111 112 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) 112 113 #define FEATURE_SNPAVICSUP_GAM(x) \ 113 114 (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) ··· 187 186 #define CONTROL_EPH_EN 45 188 187 #define CONTROL_XT_EN 50 189 188 #define CONTROL_INTCAPXT_EN 51 189 + #define CONTROL_GCR3TRPMODE 58 190 190 #define CONTROL_IRTCACHEDIS 59 191 191 #define CONTROL_SNPAVIC_EN 61 192 192
+8
drivers/iommu/amd/init.c
··· 1122 1122 return; 1123 1123 1124 1124 iommu_feature_enable(iommu, CONTROL_GT_EN); 1125 + 1126 + /* 1127 + * This feature needs to be enabled prior to a call 1128 + * to iommu_snp_enable(). Since this function is called 1129 + * in early_enable_iommu(), it is safe to enable here. 1130 + */ 1131 + if (check_feature2(FEATURE_GCR3TRPMODE)) 1132 + iommu_feature_enable(iommu, CONTROL_GCR3TRPMODE); 1125 1133 } 1126 1134 1127 1135 /* sets a specific bit in the device table entry. */