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mtd: rawnand: atmel: Fix pulse read timing for certain flash chips

Prevent PMECC errors when reading from AMD/Spansion S34ML02G1 flash on
SAM9X60 SoC, after switching to ONFI timing mode 3.

From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse must be at least tREA.

The previous approach to set this timing worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.

The approach to fix the issue was carried over from u-boot, which itself
got it from at91bootstrap. It has been successfully tested in
at91bootstrap, U-Boot and Linux on sam9x60 and sama5d2, for several
months here.

Link: https://github.com/linux4sam/at91bootstrap/issues/174
Link: https://github.com/linux4sam/at91bootstrap/commit/e2dfd8141d00613a37acee66ef5724f70f34a538
Link: https://lore.kernel.org/u-boot/20240415075755.780653-1-ada@thorsis.com/
Link: https://source.denx.de/u-boot/u-boot/-/commit/344e2f2cd4a407f847b301804f37d036e8a0a10c
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

authored by

Alexander Dahl and committed by
Miquel Raynal b2d2c2b8 dfea8f71

+9 -4
+9 -4
drivers/mtd/nand/raw/atmel/nand-controller.c
··· 1240 1240 const struct nand_interface_config *conf, 1241 1241 struct atmel_smc_cs_conf *smcconf) 1242 1242 { 1243 - u32 ncycles, totalcycles, timeps, mckperiodps; 1243 + u32 ncycles, totalcycles, timeps, mckperiodps, pulse; 1244 1244 struct atmel_nand_controller *nc; 1245 1245 int ret; 1246 1246 ··· 1366 1366 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED; 1367 1367 1368 1368 /* 1369 - * Read pulse timing directly matches tRP: 1369 + * Read pulse timing would directly match tRP, 1370 + * but some NAND flash chips (S34ML01G2 and W29N02KVxxAF) 1371 + * do not work properly in timing mode 3. 1372 + * The workaround is to extend the SMC NRD pulse to meet tREA 1373 + * timing. 1370 1374 * 1371 - * NRD_PULSE = tRP 1375 + * NRD_PULSE = max(tRP, tREA) 1372 1376 */ 1373 - ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); 1377 + pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max); 1378 + ncycles = DIV_ROUND_UP(pulse, mckperiodps); 1374 1379 totalcycles += ncycles; 1375 1380 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT, 1376 1381 ncycles);