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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late updates from Olof Johansson:
"A couple of late-merged changes that would be useful to get in this
merge window:

- Driver support for reset of audio complex on Meson platforms. The
audio driver went in this merge window, and these changes have been
in -next for a while (just not in our tree).

- Power management fixes for IOMMU on Rockchip platforms, getting
closer to kexec working on them, including Chromebooks.

- Another pass updating "arm,psci" -> "psci" for some properties that
have snuck in since last time it was done"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
iommu/rockchip: Move irq request past pm_runtime_enable
iommu/rockchip: Handle errors returned from PM framework
arm64: rockchip: Force CONFIG_PM on Rockchip systems
ARM: rockchip: Force CONFIG_PM on Rockchip systems
arm64: dts: Fix various entry-method properties to reflect documentation
reset: imx7: Fix always writing bits as 0
reset: meson: add meson audio arb driver
reset: meson: add dt-bindings for meson-axg audio arb

+257 -30
+1 -1
Documentation/devicetree/bindings/arm/cpu-capacity.txt
··· 94 94 }; 95 95 96 96 idle-states { 97 - entry-method = "arm,psci"; 97 + entry-method = "psci"; 98 98 99 99 CPU_SLEEP_0: cpu-sleep-0 { 100 100 compatible = "arm,idle-state";
+2 -2
Documentation/devicetree/bindings/arm/idle-states.txt
··· 237 237 Value type: <stringlist> 238 238 Usage and definition depend on ARM architecture version. 239 239 # On ARM v8 64-bit this property is required and must 240 - be one of: 241 - - "psci" (see bindings in [2]) 240 + be: 241 + - "psci" 242 242 # On ARM 32-bit systems this property is optional 243 243 244 244 The nodes describing the idle states (state) can only be defined within the
+21
Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
··· 1 + * Amlogic audio memory arbiter controller 2 + 3 + The Amlogic Audio ARB is a simple device which enables or 4 + disables the access of Audio FIFOs to DDR on AXG based SoC. 5 + 6 + Required properties: 7 + - compatible: 'amlogic,meson-axg-audio-arb' 8 + - reg: physical base address of the controller and length of memory 9 + mapped region. 10 + - clocks: phandle to the fifo peripheral clock provided by the audio 11 + clock controller. 12 + - #reset-cells: must be 1. 13 + 14 + Example on the A113 SoC: 15 + 16 + arb: reset-controller@280 { 17 + compatible = "amlogic,meson-axg-audio-arb"; 18 + reg = <0x0 0x280 0x0 0x4>; 19 + #reset-cells = <1>; 20 + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 21 + };
+1
arch/arm/mach-rockchip/Kconfig
··· 17 17 select ARM_GLOBAL_TIMER 18 18 select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK 19 19 select ZONE_DMA if ARM_LPAE 20 + select PM 20 21 help 21 22 Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs 22 23 containing the RK2928, RK30xx and RK31xx series.
+1
arch/arm64/Kconfig.platforms
··· 158 158 select GPIOLIB 159 159 select PINCTRL 160 160 select PINCTRL_ROCKCHIP 161 + select PM 161 162 select ROCKCHIP_TIMER 162 163 help 163 164 This enables support for the ARMv8 based Rockchip chipsets,
+1 -1
arch/arm64/boot/dts/arm/juno-r1.dts
··· 63 63 }; 64 64 65 65 idle-states { 66 - entry-method = "arm,psci"; 66 + entry-method = "psci"; 67 67 68 68 CPU_SLEEP_0: cpu-sleep-0 { 69 69 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/arm/juno-r2.dts
··· 63 63 }; 64 64 65 65 idle-states { 66 - entry-method = "arm,psci"; 66 + entry-method = "psci"; 67 67 68 68 CPU_SLEEP_0: cpu-sleep-0 { 69 69 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/arm/juno.dts
··· 62 62 }; 63 63 64 64 idle-states { 65 - entry-method = "arm,psci"; 65 + entry-method = "psci"; 66 66 67 67 CPU_SLEEP_0: cpu-sleep-0 { 68 68 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
··· 43 43 * PSCI node is not added default, U-boot will add missing 44 44 * parts if it determines to use PSCI. 45 45 */ 46 - entry-method = "arm,psci"; 46 + entry-method = "psci"; 47 47 48 48 CPU_PH20: cpu-ph20 { 49 49 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
··· 87 87 * PSCI node is not added default, U-boot will add missing 88 88 * parts if it determines to use PSCI. 89 89 */ 90 - entry-method = "arm,psci"; 90 + entry-method = "psci"; 91 91 92 92 CPU_PH20: cpu-ph20 { 93 93 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
··· 83 83 * PSCI node is not added default, U-boot will add missing 84 84 * parts if it determines to use PSCI. 85 85 */ 86 - entry-method = "arm,psci"; 86 + entry-method = "psci"; 87 87 88 88 CPU_PH20: cpu-ph20 { 89 89 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
··· 119 119 }; 120 120 121 121 idle-states { 122 - entry-method = "arm,psci"; 122 + entry-method = "psci"; 123 123 124 124 CPU_SLEEP_0: cpu-sleep-0 { 125 125 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/sprd/sc9860.dtsi
··· 114 114 }; 115 115 116 116 idle-states{ 117 - entry-method = "arm,psci"; 117 + entry-method = "psci"; 118 118 119 119 CORE_PD: core_pd { 120 120 compatible = "arm,idle-state";
+1 -1
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
··· 58 58 }; 59 59 60 60 idle-states { 61 - entry-method = "arm,psci"; 61 + entry-method = "psci"; 62 62 63 63 CPU_SLEEP_0: cpu-sleep-0 { 64 64 compatible = "arm,idle-state";
+28 -17
drivers/iommu/rockchip-iommu.c
··· 521 521 u32 int_status; 522 522 dma_addr_t iova; 523 523 irqreturn_t ret = IRQ_NONE; 524 - int i; 524 + int i, err; 525 525 526 - if (WARN_ON(!pm_runtime_get_if_in_use(iommu->dev))) 527 - return 0; 526 + err = pm_runtime_get_if_in_use(iommu->dev); 527 + if (WARN_ON_ONCE(err <= 0)) 528 + return ret; 528 529 529 530 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) 530 531 goto out; ··· 621 620 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 622 621 list_for_each(pos, &rk_domain->iommus) { 623 622 struct rk_iommu *iommu; 623 + int ret; 624 624 625 625 iommu = list_entry(pos, struct rk_iommu, node); 626 626 627 627 /* Only zap TLBs of IOMMUs that are powered on. */ 628 - if (pm_runtime_get_if_in_use(iommu->dev)) { 628 + ret = pm_runtime_get_if_in_use(iommu->dev); 629 + if (WARN_ON_ONCE(ret < 0)) 630 + continue; 631 + if (ret) { 629 632 WARN_ON(clk_bulk_enable(iommu->num_clocks, 630 633 iommu->clocks)); 631 634 rk_iommu_zap_lines(iommu, iova, size); ··· 896 891 struct rk_iommu *iommu; 897 892 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 898 893 unsigned long flags; 894 + int ret; 899 895 900 896 /* Allow 'virtual devices' (eg drm) to detach from domain */ 901 897 iommu = rk_iommu_from_dev(dev); ··· 915 909 list_del_init(&iommu->node); 916 910 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 917 911 918 - if (pm_runtime_get_if_in_use(iommu->dev)) { 912 + ret = pm_runtime_get_if_in_use(iommu->dev); 913 + WARN_ON_ONCE(ret < 0); 914 + if (ret > 0) { 919 915 rk_iommu_disable(iommu); 920 916 pm_runtime_put(iommu->dev); 921 917 } ··· 954 946 list_add_tail(&iommu->node, &rk_domain->iommus); 955 947 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 956 948 957 - if (!pm_runtime_get_if_in_use(iommu->dev)) 949 + ret = pm_runtime_get_if_in_use(iommu->dev); 950 + if (!ret || WARN_ON_ONCE(ret < 0)) 958 951 return 0; 959 952 960 953 ret = rk_iommu_enable(iommu); ··· 1160 1151 if (iommu->num_mmu == 0) 1161 1152 return PTR_ERR(iommu->bases[0]); 1162 1153 1163 - i = 0; 1164 - while ((irq = platform_get_irq(pdev, i++)) != -ENXIO) { 1165 - if (irq < 0) 1166 - return irq; 1167 - 1168 - err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1169 - IRQF_SHARED, dev_name(dev), iommu); 1170 - if (err) 1171 - return err; 1172 - } 1173 - 1174 1154 iommu->reset_disabled = device_property_read_bool(dev, 1175 1155 "rockchip,disable-mmu-reset"); 1176 1156 ··· 1215 1217 bus_set_iommu(&platform_bus_type, &rk_iommu_ops); 1216 1218 1217 1219 pm_runtime_enable(dev); 1220 + 1221 + i = 0; 1222 + while ((irq = platform_get_irq(pdev, i++)) != -ENXIO) { 1223 + if (irq < 0) 1224 + return irq; 1225 + 1226 + err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1227 + IRQF_SHARED, dev_name(dev), iommu); 1228 + if (err) { 1229 + pm_runtime_disable(dev); 1230 + goto err_remove_sysfs; 1231 + } 1232 + } 1218 1233 1219 1234 return 0; 1220 1235 err_remove_sysfs:
+7
drivers/reset/Kconfig
··· 73 73 help 74 74 This enables the reset driver for Amlogic Meson SoCs. 75 75 76 + config RESET_MESON_AUDIO_ARB 77 + tristate "Meson Audio Memory Arbiter Reset Driver" 78 + depends on ARCH_MESON || COMPILE_TEST 79 + help 80 + This enables the reset driver for Audio Memory Arbiter of 81 + Amlogic's A113 based SoCs 82 + 76 83 config RESET_OXNAS 77 84 bool 78 85
+1
drivers/reset/Makefile
··· 12 12 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o 13 13 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o 14 14 obj-$(CONFIG_RESET_MESON) += reset-meson.o 15 + obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o 15 16 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o 16 17 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o 17 18 obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
+1 -1
drivers/reset/reset-imx7.c
··· 81 81 { 82 82 struct imx7_src *imx7src = to_imx7_src(rcdev); 83 83 const struct imx7_src_signal *signal = &imx7_src_signals[id]; 84 - unsigned int value = 0; 84 + unsigned int value = assert ? signal->bit : 0; 85 85 86 86 switch (id) { 87 87 case IMX7_RESET_PCIEPHY:
+168
drivers/reset/reset-meson-audio-arb.c
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + // Copyright (c) 2018 BayLibre, SAS. 3 + // Author: Jerome Brunet <jbrunet@baylibre.com> 4 + 5 + #include <linux/clk.h> 6 + #include <linux/io.h> 7 + #include <linux/module.h> 8 + #include <linux/of_platform.h> 9 + #include <linux/reset-controller.h> 10 + #include <linux/spinlock.h> 11 + 12 + #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 13 + 14 + struct meson_audio_arb_data { 15 + struct reset_controller_dev rstc; 16 + void __iomem *regs; 17 + struct clk *clk; 18 + const unsigned int *reset_bits; 19 + spinlock_t lock; 20 + }; 21 + 22 + #define ARB_GENERAL_BIT 31 23 + 24 + static const unsigned int axg_audio_arb_reset_bits[] = { 25 + [AXG_ARB_TODDR_A] = 0, 26 + [AXG_ARB_TODDR_B] = 1, 27 + [AXG_ARB_TODDR_C] = 2, 28 + [AXG_ARB_FRDDR_A] = 4, 29 + [AXG_ARB_FRDDR_B] = 5, 30 + [AXG_ARB_FRDDR_C] = 6, 31 + }; 32 + 33 + static int meson_audio_arb_update(struct reset_controller_dev *rcdev, 34 + unsigned long id, bool assert) 35 + { 36 + u32 val; 37 + struct meson_audio_arb_data *arb = 38 + container_of(rcdev, struct meson_audio_arb_data, rstc); 39 + 40 + spin_lock(&arb->lock); 41 + val = readl(arb->regs); 42 + 43 + if (assert) 44 + val &= ~BIT(arb->reset_bits[id]); 45 + else 46 + val |= BIT(arb->reset_bits[id]); 47 + 48 + writel(val, arb->regs); 49 + spin_unlock(&arb->lock); 50 + 51 + return 0; 52 + } 53 + 54 + static int meson_audio_arb_status(struct reset_controller_dev *rcdev, 55 + unsigned long id) 56 + { 57 + u32 val; 58 + struct meson_audio_arb_data *arb = 59 + container_of(rcdev, struct meson_audio_arb_data, rstc); 60 + 61 + val = readl(arb->regs); 62 + 63 + return !(val & BIT(arb->reset_bits[id])); 64 + } 65 + 66 + static int meson_audio_arb_assert(struct reset_controller_dev *rcdev, 67 + unsigned long id) 68 + { 69 + return meson_audio_arb_update(rcdev, id, true); 70 + } 71 + 72 + static int meson_audio_arb_deassert(struct reset_controller_dev *rcdev, 73 + unsigned long id) 74 + { 75 + return meson_audio_arb_update(rcdev, id, false); 76 + } 77 + 78 + static const struct reset_control_ops meson_audio_arb_rstc_ops = { 79 + .assert = meson_audio_arb_assert, 80 + .deassert = meson_audio_arb_deassert, 81 + .status = meson_audio_arb_status, 82 + }; 83 + 84 + static const struct of_device_id meson_audio_arb_of_match[] = { 85 + { .compatible = "amlogic,meson-axg-audio-arb", }, 86 + {} 87 + }; 88 + MODULE_DEVICE_TABLE(of, meson_audio_arb_of_match); 89 + 90 + static int meson_audio_arb_remove(struct platform_device *pdev) 91 + { 92 + struct meson_audio_arb_data *arb = platform_get_drvdata(pdev); 93 + 94 + /* Disable all access */ 95 + spin_lock(&arb->lock); 96 + writel(0, arb->regs); 97 + spin_unlock(&arb->lock); 98 + 99 + clk_disable_unprepare(arb->clk); 100 + 101 + return 0; 102 + } 103 + 104 + static int meson_audio_arb_probe(struct platform_device *pdev) 105 + { 106 + struct device *dev = &pdev->dev; 107 + struct meson_audio_arb_data *arb; 108 + struct resource *res; 109 + int ret; 110 + 111 + arb = devm_kzalloc(dev, sizeof(*arb), GFP_KERNEL); 112 + if (!arb) 113 + return -ENOMEM; 114 + platform_set_drvdata(pdev, arb); 115 + 116 + arb->clk = devm_clk_get(dev, NULL); 117 + if (IS_ERR(arb->clk)) { 118 + if (PTR_ERR(arb->clk) != -EPROBE_DEFER) 119 + dev_err(dev, "failed to get clock\n"); 120 + return PTR_ERR(arb->clk); 121 + } 122 + 123 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 124 + arb->regs = devm_ioremap_resource(dev, res); 125 + if (IS_ERR(arb->regs)) 126 + return PTR_ERR(arb->regs); 127 + 128 + spin_lock_init(&arb->lock); 129 + arb->reset_bits = axg_audio_arb_reset_bits; 130 + arb->rstc.nr_resets = ARRAY_SIZE(axg_audio_arb_reset_bits); 131 + arb->rstc.ops = &meson_audio_arb_rstc_ops; 132 + arb->rstc.of_node = dev->of_node; 133 + 134 + /* 135 + * Enable general : 136 + * In the initial state, all memory interfaces are disabled 137 + * and the general bit is on 138 + */ 139 + ret = clk_prepare_enable(arb->clk); 140 + if (ret) { 141 + dev_err(dev, "failed to enable arb clock\n"); 142 + return ret; 143 + } 144 + writel(BIT(ARB_GENERAL_BIT), arb->regs); 145 + 146 + /* Register reset controller */ 147 + ret = devm_reset_controller_register(dev, &arb->rstc); 148 + if (ret) { 149 + dev_err(dev, "failed to register arb reset controller\n"); 150 + meson_audio_arb_remove(pdev); 151 + } 152 + 153 + return ret; 154 + } 155 + 156 + static struct platform_driver meson_audio_arb_pdrv = { 157 + .probe = meson_audio_arb_probe, 158 + .remove = meson_audio_arb_remove, 159 + .driver = { 160 + .name = "meson-audio-arb-reset", 161 + .of_match_table = meson_audio_arb_of_match, 162 + }, 163 + }; 164 + module_platform_driver(meson_audio_arb_pdrv); 165 + 166 + MODULE_DESCRIPTION("Amlogic A113 Audio Memory Arbiter"); 167 + MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 168 + MODULE_LICENSE("GPL v2");
+17
include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + * 3 + * Copyright (c) 2018 Baylibre SAS. 4 + * Author: Jerome Brunet <jbrunet@baylibre.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H 8 + #define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H 9 + 10 + #define AXG_ARB_TODDR_A 0 11 + #define AXG_ARB_TODDR_B 1 12 + #define AXG_ARB_TODDR_C 2 13 + #define AXG_ARB_FRDDR_A 3 14 + #define AXG_ARB_FRDDR_B 4 15 + #define AXG_ARB_FRDDR_C 5 16 + 17 + #endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */