Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.14-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Two amd fixes, one i915 core and a few i915 GVT fixes, things seem
fairly quiet"
* tag 'drm-fixes-for-v4.14-rc7' of git://people.freedesktop.org/~airlied/linux:
drm/i915/gvt: Adding ACTHD mmio read handler
drm/i915/gvt: Extract mmio_read_from_hw() common function
drm/i915/gvt: Refine MMIO_RING_F()
drm/i915/gvt: properly check per_ctx bb valid state
drm/i915/perf: fix perf enable/disable ioctls with 32bits userspace
drm/amd/amdgpu: Remove workaround check for UVD6 on APUs
drm/amd/powerplay: fix uninitialized variable
+27
-79
+5
-11
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+5
-11
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
···
225
225
if (r)
226
226
return r;
227
227
228
-
/* Skip this for APU for now */
229
-
if (!(adev->flags & AMD_IS_APU))
230
-
r = amdgpu_uvd_suspend(adev);
231
-
232
-
return r;
228
+
return amdgpu_uvd_suspend(adev);
233
229
}
234
230
235
231
static int uvd_v6_0_resume(void *handle)
···
233
237
int r;
234
238
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
235
239
236
-
/* Skip this for APU for now */
237
-
if (!(adev->flags & AMD_IS_APU)) {
238
-
r = amdgpu_uvd_resume(adev);
239
-
if (r)
240
-
return r;
241
-
}
240
+
r = amdgpu_uvd_resume(adev);
241
+
if (r)
242
+
return r;
243
+
242
244
return uvd_v6_0_hw_init(adev);
243
245
}
244
246
+3
-3
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+3
-3
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
830
830
{
831
831
uint32_t reference_clock, tmp;
832
832
struct cgs_display_info info = {0};
833
-
struct cgs_mode_info mode_info;
833
+
struct cgs_mode_info mode_info = {0};
834
834
835
835
info.mode_info = &mode_info;
836
836
···
3948
3948
uint32_t ref_clock;
3949
3949
uint32_t refresh_rate = 0;
3950
3950
struct cgs_display_info info = {0};
3951
-
struct cgs_mode_info mode_info;
3951
+
struct cgs_mode_info mode_info = {0};
3952
3952
3953
3953
info.mode_info = &mode_info;
3954
-
3955
3954
cgs_get_active_displays_info(hwmgr->device, &info);
3956
3955
num_active_displays = info.display_count;
3957
3956
···
3966
3967
frame_time_in_us = 1000000 / refresh_rate;
3967
3968
3968
3969
pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
3970
+
3969
3971
data->frame_time_x2 = frame_time_in_us * 2 / 100;
3970
3972
3971
3973
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
+3
drivers/gpu/drm/i915/gvt/cmd_parser.c
+3
drivers/gpu/drm/i915/gvt/cmd_parser.c
+1
-2
drivers/gpu/drm/i915/gvt/execlist.c
+1
-2
drivers/gpu/drm/i915/gvt/execlist.c
+10
-60
drivers/gpu/drm/i915/gvt/handlers.c
+10
-60
drivers/gpu/drm/i915/gvt/handlers.c
···
1429
1429
return 0;
1430
1430
}
1431
1431
1432
-
static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1433
-
unsigned int offset, void *p_data, unsigned int bytes)
1434
-
{
1435
-
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1436
-
1437
-
mmio_hw_access_pre(dev_priv);
1438
-
vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1439
-
mmio_hw_access_post(dev_priv);
1440
-
return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1441
-
}
1442
-
1443
-
static int instdone_mmio_read(struct intel_vgpu *vgpu,
1432
+
static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1444
1433
unsigned int offset, void *p_data, unsigned int bytes)
1445
1434
{
1446
1435
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
···
1578
1589
MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1579
1590
MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1580
1591
MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1592
+
if (HAS_BSD2(dev_priv)) \
1593
+
MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1581
1594
} while (0)
1582
1595
1583
1596
#define MMIO_RING_D(prefix, d) \
···
1626
1635
#undef RING_REG
1627
1636
1628
1637
#define RING_REG(base) (base + 0x6c)
1629
-
MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);
1630
-
MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);
1638
+
MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1631
1639
#undef RING_REG
1632
-
MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);
1640
+
MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1633
1641
1634
1642
MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1635
1643
MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
···
1638
1648
MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1639
1649
MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1640
1650
MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1641
-
MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1651
+
MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1642
1652
MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1643
1653
1644
1654
/* RING MODE */
···
1652
1662
MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1653
1663
NULL, NULL);
1654
1664
MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1655
-
ring_timestamp_mmio_read, NULL);
1665
+
mmio_read_from_hw, NULL);
1656
1666
MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1657
-
ring_timestamp_mmio_read, NULL);
1667
+
mmio_read_from_hw, NULL);
1658
1668
1659
1669
MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1660
1670
MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
···
2401
2411
struct drm_i915_private *dev_priv = gvt->dev_priv;
2402
2412
int ret;
2403
2413
2404
-
MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
2405
-
intel_vgpu_reg_imr_handler);
2406
-
2407
2414
MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2408
2415
MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2409
2416
MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
···
2463
2476
MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2464
2477
intel_vgpu_reg_master_irq_handler);
2465
2478
2466
-
MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2467
-
F_CMD_ACCESS, NULL, NULL);
2468
-
MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2469
-
2470
-
MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2471
-
NULL, NULL);
2472
-
MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2473
-
F_CMD_ACCESS, NULL, NULL);
2474
-
MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2475
-
MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2476
-
NULL, NULL);
2477
-
MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2478
-
F_CMD_ACCESS, NULL, NULL);
2479
-
MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2480
-
F_CMD_ACCESS, NULL, NULL);
2481
-
MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2482
-
ring_mode_mmio_write);
2483
-
MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2484
-
F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2485
-
MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2486
-
F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2487
-
MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2488
-
ring_timestamp_mmio_read, NULL);
2489
-
2490
-
MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2479
+
MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2480
+
mmio_read_from_hw, NULL);
2491
2481
2492
2482
#define RING_REG(base) (base + 0xd0)
2493
2483
MMIO_RING_F(RING_REG, 4, F_RO, 0,
2494
-
~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2495
-
ring_reset_ctl_write);
2496
-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
2497
2484
~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2498
2485
ring_reset_ctl_write);
2499
2486
#undef RING_REG
2500
2487
2501
2488
#define RING_REG(base) (base + 0x230)
2502
2489
MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2503
-
MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
2504
2490
#undef RING_REG
2505
2491
2506
2492
#define RING_REG(base) (base + 0x234)
2507
2493
MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2508
2494
NULL, NULL);
2509
-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
2510
-
~0LL, D_BDW_PLUS, NULL, NULL);
2511
2495
#undef RING_REG
2512
2496
2513
2497
#define RING_REG(base) (base + 0x244)
2514
2498
MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2515
-
MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2516
-
NULL, NULL);
2517
2499
#undef RING_REG
2518
2500
2519
2501
#define RING_REG(base) (base + 0x370)
2520
2502
MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2521
-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2522
-
NULL, NULL);
2523
2503
#undef RING_REG
2524
2504
2525
2505
#define RING_REG(base) (base + 0x3a0)
2526
2506
MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2527
-
MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2528
2507
#undef RING_REG
2529
2508
2530
2509
MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
···
2510
2557
2511
2558
#define RING_REG(base) (base + 0x270)
2512
2559
MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2513
-
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2514
2560
#undef RING_REG
2515
2561
2516
2562
MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2517
-
MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2518
2563
2519
2564
MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2520
2565
···
2800
2849
MMIO_D(0x65f08, D_SKL | D_KBL);
2801
2850
MMIO_D(0x320f0, D_SKL | D_KBL);
2802
2851
2803
-
MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2804
2852
MMIO_D(0x70034, D_SKL_PLUS);
2805
2853
MMIO_D(0x71034, D_SKL_PLUS);
2806
2854
MMIO_D(0x72034, D_SKL_PLUS);
-3
drivers/gpu/drm/i915/gvt/reg.h
-3
drivers/gpu/drm/i915/gvt/reg.h
···
54
54
55
55
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
56
56
57
-
#define _REG_VECS_EXCC 0x1A028
58
-
#define _REG_VCS2_EXCC 0x1c028
59
-
60
57
#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
61
58
#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
62
59
+1
drivers/gpu/drm/i915/gvt/scheduler.h
+1
drivers/gpu/drm/i915/gvt/scheduler.h
+4
drivers/gpu/drm/i915/i915_perf.c
+4
drivers/gpu/drm/i915/i915_perf.c
···
2537
2537
.poll = i915_perf_poll,
2538
2538
.read = i915_perf_read,
2539
2539
.unlocked_ioctl = i915_perf_ioctl,
2540
+
/* Our ioctl have no arguments, so it's safe to use the same function
2541
+
* to handle 32bits compatibility.
2542
+
*/
2543
+
.compat_ioctl = i915_perf_ioctl,
2540
2544
};
2541
2545
2542
2546